An internal error checking circuit and memory

Abstract

An embodiment of the present disclosure provides an internal error checking circuit and a memory, wherein the internal error checking circuit includes a clock generating circuit, an internal command generating circuit, an address generating circuit, a control logic circuit and an error correction circuit; wherein the clock generating circuit generates and outputs a self-refresh clock signal in response to a self-refresh enable signal; the internal command generating circuit counts the self-refresh clock signal when the error checking enable signal indicates that the internal error checking function is turned on, and generates and outputs an internal error checking command signal when the count value of the self-refresh clock signal is a first preset value; the address generating circuit counts the internal error checking command signal to generate and output an internal error checking address; and the control logic circuit controls the error correction circuit to sequentially perform an internal read-modify-write operation on target storage cells corresponding to the internal error checking addresses in multiple storage arrays in response to the internal error checking command signal.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to an internal error checking circuit and a memory. Background Art

[0002] With the continuous development of semiconductor technology, people have put forward higher and higher requirements for data transmission speed when manufacturing and using computers and other equipment. In order to obtain faster data transmission speed, a series of dynamic random access memory devices DRAM that can transmit data at double data rate (Double Data Rate, DDR) have emerged.

[0003] However, as the transmission speed of memory becomes faster and faster, the size of memory cell process is reduced, and row hammering and other reasons occur, the charge leakage and other problems existing in DRAM memory are becoming more and more serious, which may increase the instability and potential error rate of storage system data. Therefore, an appropriate internal error checking mechanism is required to regularly check the internal error of the memory and correct the detected errors in time to ensure the integrity of the data and the reliability of the system. Summary of the invention

[0004] Embodiments of the present disclosure provide an internal error checking circuit and a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides an internal error check circuit, comprising: a clock generation circuit, an internal command generation circuit, an address generation circuit, a control logic circuit and an error correction circuit; the clock generation circuit is configured to generate and output a self-refresh clock signal in response to a self-refresh enable signal; the internal command generation circuit is configured to receive a self-refresh clock signal and an error check enable signal, count the self-refresh clock signal when the error check enable signal indicates that the internal error check function is turned on, and generate and output an internal error check command signal when the count value of the self-refresh clock signal is a first preset value; the address generation circuit is configured to receive the internal error check command signal, and count the internal error check command signal to generate and output an internal error check address; the control logic circuit is configured to receive the internal error check command signal and the internal error check address, and in response to the internal error check command signal, control the error correction circuit to sequentially perform an internal read-modify-write operation on target storage cells corresponding to the internal error check addresses in multiple storage arrays; wherein the multiple storage arrays share the error correction circuit.

[0006] In some embodiments, the control logic circuit includes multiple storage array control circuits, and the multiple storage array control circuits correspond one-to-one to the multiple storage arrays; each of the storage array control circuits is configured to receive the internal error check command signal and the internal error check address, generate multiple groups of internal signals in sequence in response to the internal error check command signal, and when the corresponding storage array is in an enabled state, control the error correction circuit according to the corresponding group of internal signals to perform an internal read-modify-write operation on the target storage unit in the corresponding storage array; wherein each group of internal signals includes an internal read signal and an internal write signal.

[0007] In some embodiments, the error correction circuit is configured to read storage data from the target storage unit according to the internal read signal, and perform error detection and error correction on the storage data to generate correction data; the error correction circuit is also configured to write the correction data into the target storage unit according to the internal write signal.

[0008] In some embodiments, the internal command generation circuit is further configured to, in response to each pulse on the self-refresh clock signal, generate and output an internal self-refresh command signal when the error check enable signal indicates that the internal error check function is not turned on; and to generate and output an internal self-refresh command signal when the error check enable signal indicates that the internal error check function is turned on and the count value of the self-refresh clock signal is not a first preset value.

[0009] In some embodiments, the control logic circuit is further configured to, after controlling the error correction circuit to sequentially perform an internal read-modify-write operation on the target storage cells corresponding to the internal error check addresses in multiple storage arrays, control a self-refresh operation to be performed on all storage arrays.

[0010] In some embodiments, the address generation circuit includes a column address generation circuit, a first decoding circuit and a row address generation circuit; the column address generation circuit is configured to receive the internal error check command signal, count the columns of the current storage row according to the internal error check command signal, and generate and output a target column address; the first decoding circuit is configured to decode the target column address, and generate and output a column end signal when the target column address indicates that the column count of the current storage row is completed; the row address generation circuit is configured to receive the column end signal and the internal error check command signal, count the rows of the storage array according to the column end signal, and generate and output a target row address signal.

[0011] In some embodiments, the row address generation circuit includes: a row counting circuit, configured to receive the column end signal, and count the rows of the storage array according to the column end signal, generate and output a row count value; a row address sampling circuit, configured to receive the internal error check command signal and the row count value, and sample the row count value in response to the internal error check command signal, generate and output the target row address signal.

[0012] In some embodiments, the address generation circuit also includes a refresh address generation circuit, which is configured to receive the internal self-refresh command signal, and count the rows of the storage array according to the internal self-refresh command signal, generate and output a self-refresh address; the control logic circuit is also configured to perform a refresh operation on all storage arrays based on the self-refresh address control.

[0013] In some embodiments, the column address generation circuit includes N cascaded first flip-flops, where N is an integer greater than or equal to 1; the clock control end of the first stage first flip-flop serves as the input end of the column address generation circuit to receive the internal error check command signal; the inverting output end of each stage first flip-flop is connected to its own data input end; the clock control ends of other first flip-flops except the first stage first flip-flop are connected to the inverting output end of the first flip-flop of the previous stage; the positive output ends of the N first flip-flops jointly output the target column address; the first decoding circuit includes a first NAND gate, the N input ends of the first NAND gate are respectively connected to the positive output ends of the N first flip-flops, and the output end of the first NAND gate is used to output the column end signal.

[0014] In some embodiments, the row counting circuit includes M cascaded second flip-flops, where M is an integer greater than or equal to 1; the clock control end of the first-stage second flip-flop serves as the input end of the row counting circuit to receive the column end signal; the inverting output end of each stage of the second flip-flop is connected to its own data input end; the clock control ends of the other second flip-flops except the first-stage second flip-flop are connected to the inverting output end of the previous stage of the second flip-flop; the positive output ends of the M second flip-flops jointly output the row count value; the row address sampling circuit includes M third flip-flops; the clock control end of each of the third flip-flops receives the internal error check command signal; the data input ends of the M third flip-flops are connected one-to-one with the positive output ends of the M second flip-flops to receive the row count value; the positive output ends of the M third flip-flops jointly output the target row address.

[0015] In some embodiments, the storage array control circuit includes: an identification signal generating circuit, configured to receive the internal error checking command signal, and in response to the internal error checking command signal, generate and output an operation identification signal at a valid level; a read / write command generating circuit, configured to receive the operation identification signal and the internal error checking command signal, and in response to the internal error checking command signal, sequentially generate multiple groups of internal signals during the period when the operation identification signal is at a valid level; the identification signal generating circuit is also configured to receive the internal write signal, and when the count value of the internal write signal reaches a second preset value, sets the operation identification signal to an invalid level.

[0016] In some embodiments, the identification signal generating circuit includes: a command counting circuit, configured to count the inverted signal of the internal write signal to generate and output the count value of the internal write signal; a second decoding circuit, configured to receive the count value of the internal write signal, and generate and output an operation end signal when the count value of the internal write signal is a second preset value; an SR trigger, configured to receive the internal error check command signal and the operation end signal, and in response to the internal error check command signal, set the operation identification signal to a valid level, and when the count value of the internal write signal reaches a second preset value, set the operation identification signal to an invalid level.

[0017] In some embodiments, the read / write command generation circuit includes: a second NAND gate, a first input end of the second NAND gate receiving the operation identification signal, and a second input end of the second NAND gate receiving the internal error check command signal; a first NOR gate, a first input end of the first NOR gate electrically connected to an output end of the second NAND gate, and an output end of the first NOR gate is used to output the internal read signal; a second NOR gate, a first input end of the second NOR gate electrically connected to an output end of the first NOR gate, and an output end of the second NOR gate electrically connected to a second input end of the first NOR gate; a delay unit, an input end of the delay unit electrically connected to an output end of the first NOR gate; a first NOR gate, an input end of the first NOR gate electrically connected to an output end of the delay unit, and an output end of the first NOR gate electrically connected to a second input end of the second NOR gate; a second NOR gate, an input end of the second NOR gate receiving the operation identification signal; a third NOR gate, a first input end of the third NOR gate electrically connected to an output end of the second NOR gate, a second input end of the third NOR gate electrically connected to an output end of the first NOR gate, and an output end of the third NOR gate is used to output the internal write signal.

[0018] In some embodiments, the storage array control circuit also includes: a self-refresh control circuit configured to receive the operation identification signal and the self-refresh address, and when the operation identification signal flips to an invalid level, control the corresponding storage array to perform a refresh operation according to the self-refresh address.

[0019] In some embodiments, the error correction circuit is also configured to generate and output an error identification signal when an internal read-modify-write operation is performed on the target storage unit if there is an error in the storage data in the target storage unit; the internal error checking circuit also includes: an error register configured to receive the internal error checking address and the error identification signal, and store the internal error checking address in response to the error identification signal.

[0020] In a second aspect, an embodiment of the present disclosure provides a memory, which includes the internal error checking circuit as described in the first aspect.

[0021] An embodiment of the present disclosure provides an internal error checking circuit and a memory, wherein the internal command generating circuit in the internal error checking circuit can "steal" the current pulse on the self-refresh clock signal to generate an internal error checking command signal when the error checking enable signal indicates that the internal error checking function is turned on and whenever the count value of the self-refresh clock signal reaches a first preset value, and the control logic circuit can reuse the original operation circuit and path for executing the external read-modify-write command based on the internal error checking command signal, and control the error correction circuit to sequentially perform an internal read-modify-write operation on the target storage cells in the multiple storage arrays that share it, because the internal read-modify-write operation performed by the error correction circuit has the function of data error detection / correction. In this way, the memory error checking circuit can reuse the original clock generation circuit (for self-refresh operation), the operation circuit and path for executing external read-modify-write commands, without affecting the timing of the original self-refresh operation and external read-modify-write operation. Moreover, only simple improvements need to be made to the original internal command generation circuit, address generation circuit and control logic circuit to realize regular data error detection / correction operations on multiple storage arrays. On the premise of realizing the internal error checking mechanism to effectively improve the stability of stored data, the circuit design is optimized and the circuit area is saved. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the structure of an internal error checking circuit provided by an embodiment of the present disclosure;

[0023] Figure 2 A schematic diagram of the structure of a control logic circuit provided in an embodiment of the present disclosure;

[0024] Figure 3A schematic diagram of the composition structure of a storage area provided in an embodiment of the present disclosure;

[0025] Figure 4 A signal timing corresponding to an internal error checking circuit provided in an embodiment of the present disclosure Figure 1 ;

[0026] Figure 5 A schematic diagram of the structure of an address generation circuit provided in an embodiment of the present disclosure;

[0027] Figure 6 A signal timing corresponding to an internal error checking circuit provided in an embodiment of the present disclosure Figure 1 ;

[0028] Figure 7 A schematic diagram of the structure of a row address generation circuit provided in an embodiment of the present disclosure;

[0029] Figure 8 A schematic diagram of the structure of a column address generation circuit provided in an embodiment of the present disclosure;

[0030] Fig. 9 A schematic diagram of the structure of a first decoding circuit provided in an embodiment of the present disclosure;

[0031] Fig.10 A schematic diagram of the structure of a row counting circuit and a row address sampling circuit provided in an embodiment of the present disclosure;

[0032] Fig.11 A schematic diagram of the structure of a storage array control circuit provided by an embodiment of the present disclosure;

[0033] Fig.12 A schematic diagram of the structure of an identification signal generating circuit provided in an embodiment of the present disclosure;

[0034] Fig.13 A schematic diagram of the composition structure of another storage array control circuit provided by an embodiment of the present disclosure;

[0035] Fig.14 A schematic diagram of the structure of a read / write command generation circuit provided in an embodiment of the present disclosure;

[0036] Fig.15 A schematic diagram of the structure of another internal error checking circuit provided by an embodiment of the present disclosure;

[0037] Fig.16 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0040] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0041] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0042] In order to establish an appropriate internal error checking mechanism to periodically perform error detection / correction operations on multiple storage arrays (in a memory), an embodiment of the present disclosure provides an internal error checking circuit including a clock generating circuit, an internal command generating circuit, an address generating circuit, a control logic circuit and an error correction circuit; wherein the clock generating circuit is configured to generate and output a self-refresh clock signal in response to a self-refresh enable signal; the internal command generating circuit is configured to receive the self-refresh clock signal and the error checking enable signal, count the pulses of (on) the self-refresh clock signal when the error checking enable signal is at an effective level, and generate and output an internal error checking command signal when the count value of the self-refresh clock signal is a first preset value; the address generating circuit is configured to receive the internal error checking command signal, and count the internal error checking command signal to generate and output an internal error checking address; the control logic circuit is configured to receive the internal error checking command signal and the internal error checking address, and in response to the internal error checking command signal, control the error correction circuit to sequentially perform an internal read-modify-write operation on target storage cells corresponding to the internal error checking addresses in multiple storage arrays; wherein the error correction circuit is shared by multiple storage arrays. In this way, when the error check enable signal indicates that the internal error check function is turned on and each time the count value of the self-refresh clock signal reaches a first preset value, the internal command generation circuit can "steal" the current pulse on the self-refresh clock signal to generate an internal error check command signal, and the control logic circuit can also reuse the original operation circuit and path for executing external read-modify-write commands, and based on the internal error check command signal, control the error correction circuit to perform an (internal) read-modify-write operation on the target storage cells in multiple storage arrays that share it in turn, because the internal read-modify-write operation performed by the error correction circuit has the function of data error detection / correction. In this way, the memory error checking circuit can reuse the original clock generation circuit (for self-refresh operation), the operation circuit and path for executing external read-modify-write commands, without affecting the timing of the original self-refresh operation and external read-modify-write operation. Moreover, only simple improvements need to be made to the original internal command generation circuit, address generation circuit and control logic circuit to realize regular data error detection / correction operations on multiple storage arrays. On the premise of realizing the internal error checking mechanism to effectively improve the stability of stored data, the circuit design is optimized and the circuit area is saved.

[0043] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0044] In one embodiment of the present disclosure, see Figure 1 , which shows a schematic diagram of the composition structure of an internal error checking circuit 10 provided in an embodiment of the present disclosure. Figure 1As shown, the internal error checking circuit 10 includes: a clock generating circuit 11, an internal command generating circuit 12, an address generating circuit 13, a control logic circuit 14 and an error correction circuit 16, wherein:

[0045] The clock generation circuit 11 is configured to generate and output a self-refresh clock signal SR_CLK in response to a self-refresh enable signal SR_EN; wherein the self-refresh clock signal SR_CLK has a first preset period;

[0046] The internal command generation circuit 12 is configured to receive the self-refresh clock signal SR_CLK and the error check enable signal, count the pulses of the self-refresh clock signal SR_CLK when the error check enable signal indicates that the internal error check function is turned on, and generate and output an internal error check command signal IMWRAB when the count value of the self-refresh clock signal SR_CLK is a first preset value;

[0047] The address generation circuit 13 is configured to receive the internal error check command signal IMWRAB and count the internal error check command signal IMWRAB to generate and output the internal error check address IMWR_AD;

[0048] The control logic circuit 14 is configured to receive the internal error check command signal IMWRAB and the internal error check address IMWR_AD, and in response to the internal error check command signal IMWRAB, control the error correction circuit 16 to sequentially perform an internal read-modify-write operation on target storage cells corresponding to the internal error check address IMWR_AD in the plurality of storage arrays 15;

[0049] The multiple storage arrays 15 share the error correction circuit 16 .

[0050] It should be noted that the embodiments of the present disclosure relate to the overall framework design of the circuit of the internal error check and correction mechanism, and particularly to DRAM LPDDR series chips and DRAM DDR4 chips. Since the ECS function is only specified in the SPEC of the DRAM DDR4 chip, and the ECS function and related requirements are not specified in the SEPC of the LPDDR series chips and DDR4 chips, there is no way to use the ECS function to perform complete error check and clearing on such DRAM chips regularly (every 12 hours / 24 hours / 48 hours, etc.). Therefore, in order to implement an internal error check and correction mechanism similar to the ECS function in such chips, it is necessary to complete the overall framework design of the internal error check circuit without affecting the original function and timing requirements of the DRAM chip. The internal error check circuit reuses the original clock generation circuit for self-refresh operation, the path of the self-refresh command, and the operation circuit and path for executing the external read-modify-write command, which will not affect the original self-refresh operation and the function and timing of the external read-modify-write operation of the DRAM chip. It only needs to make simple improvements to the original internal command generation circuit, address generation circuit and control logic circuit to implement a regular internal error check and correction mechanism. The internal error checking circuit can be applied to DDR4 chips and LPDDR series chips, but is not limited to this scope. Other memory chips, as well as other internally generated commands, timing controls, etc. can adopt this design.

[0051] It should also be noted that, in the related art, when the external write command received by the DRAM chip is a partial write command (Masked Write, MWR), an external read-modify-write (Read-Modify-Write, RMW) operation will be performed. The external read-modify-write operation can be decomposed into three operation steps: reading, modifying, and writing back. Specifically, reading: the error correction circuit first reads the storage data from the storage array, modifying: the error correction circuit modifies the read storage data according to the partial data to be written to generate write data, and can generate new verification data based on the write data, and write back: the error correction circuit stores the write data and verification data. The internal error checking circuit 10 of the disclosed embodiment reuses the relevant circuits and paths of the original external read-modify-write operation of the DRAM chip, and performs internal read-modify-write operations on the storage data in the storage array to realize the internal error detection / correction function. The internal read-modify-write operation can be decomposed into two operation steps: read-modify and write back. Specifically, read-modify: the error correction circuit 16 reads the storage data from the storage array 15 based on the internal read signal IRD, and performs error detection and correction on the storage data based on the verification data to generate correction data; write: writes the correction data into the storage array based on the internal write signal IWR, wherein the read and modify operations are completed during the validity period of the write command signal and should belong to the same operation step. It can be seen that the internal read-modify-write operation in the embodiment of the present disclosure, although it reuses the relevant circuits (error correction circuit 16) and paths (interaction paths between the control logic circuit 14, the error correction circuit 16 and the storage array 15) of the external read-modify-write operation, there is a difference between the internal read-modify-write operation and the external read-modify-write operation. The modification in the external read-modify-write operation refers to modifying the read storage data according to part of the data to be written, while there is no external input data to be written in the internal read-modify-write operation, and its modification essentially refers to error detection and error correction operations on the read storage data. In addition, executing an internal read-modify-write operation can be considered as completing an internal error check operation, and because the error correction circuit 16 performs a read operation on the storage array based on the internal error check command, it can only read a certain number of bits of storage data of a storage address (internal error check address) each time, which can be 64 bits, 128 bits, 256 bits, etc., and therefore it is necessary to count the columns and rows of the storage array based on each internal error check command to traverse each storage address in the storage array. In this way, each internal error check command can generate an internal error check address correspondingly, thereby ensuring that the internal read-modify-write operation can be performed on the storage data in all storage cells of the storage array. After performing an internal read-modify-write operation on all storage cells of the storage array, it can be considered as completing a round of internal error check operations.

[0052] like Figure 1As shown, the clock generation circuit 11 is used to generate a self-refresh clock signal SR_CLK when the self-refresh enable signal SR_EN indicates that the memory enters a self-refresh state. When the internal error check function is not introduced, the internal command generation circuit 12 can generate a self-refresh command signal IREFAB based on each pulse on the self-refresh clock signal SR_CLK to control the execution of a self-refresh operation. After the internal error check function is introduced, the clock generation circuit 11 and the internal command generation circuit 12 can be reused, and the internal command generation circuit 12 can be simply improved, that is, the internal command generation circuit 12 can receive the error check enable signal IMWR_EN, and indicate that the internal error check function is turned on when the error check enable signal IMWR_EN is at a valid level. The internal command generation circuit 12 needs to periodically "steal" a pulse on the self-refresh clock signal SR_CLK to generate the internal error check command signal IMWRAB, that is, whenever the count value of the self-refresh clock signal SR_CLK is the first preset value, An internal error check command signal IMWRAB is generated and output, and is simultaneously sent to the address generation circuit 13 and the control logic circuit 14 to control the execution of the internal read-modify-write operation. At this time, the internal self-refresh command signal IREFAB is no longer generated based on the pulse on the "stolen" self-refresh clock signal SR_CLK; when the error check enable signal IMWR_EN is at an invalid level, indicating that the internal error check function is not turned on, the internal command generation circuit 12 generates the internal self-refresh command signal IREFAB based on the self-refresh clock signal SR_CLK to perform the relevant functions of the original self-refresh operation.

[0053] It should be noted that the count value of the self-refresh clock signal SR_CLK refers to the count value generated by counting the pulses on the self-refresh clock signal SR_CLK; and after generating the internal error check command signal IMWRAB, the internal command generation circuit 12 needs to reset the count value of the self-refresh clock signal SR_CLK to 0 to ensure that the time interval for generating the internal error check command signal IMWRAB is the same.

[0054] In some embodiments, the first preset value can be any integer greater than 1, that is, the internal command generation circuit 12 generates an internal error check command signal IMWRAB based on the self-refresh clock signal SR_CLK every first preset value of pulses; in other embodiments, the first preset value is 1, that is, each pulse on the self-refresh clock signal SR_CLK corresponds to the generation of an internal error check command signal IMWRAB. At this time, since the internal command generation circuit 12 will not generate a self-refresh command signal IREFAB based on the self-refresh clock signal SR_CLK, in order to ensure the normal execution of the self-refresh operation, it is necessary to perform a self-refresh operation immediately after each internal read-modify-write operation is completed.

[0055] In the embodiment of the present disclosure, the valid level is a high level (logic "1"), and the invalid level is a low level (logic "0"); in some other embodiments, the invalid level may also be a high level (logic "1"), and the valid level may be a low level (logic "0"), and there is no limitation on this.

[0056] In some embodiments, the clock generation circuit 11 may be an oscillator with a control end. When an external self-refresh entry command (Self-Refresh Entry, SRE) instructs the memory to enter a self-refresh state, the self-refresh enable signal SR_EN is activated. The control end of the oscillator starts to oscillate when receiving the activated self-refresh enable signal SR_EN, and generates and outputs a self-refresh clock signal SR_CLK. The period of the self-refresh clock signal may be set according to the interval time of the self-refresh command signal or the self-refresh period, and generally, the duty cycle of the self-refresh clock signal SR_CLK is less than 50%. In the disclosed embodiment, the self-refresh enable signal SR_EN is in an activated state when it is at a high level (logic "1"), and in a deactivated state when it is at a low level (logic "0"); in some other embodiments, the self-refresh enable signal SR_EN is in a deactivated state when it is at a high level (logic "1"), and in an activated state when it is at a low level (logic "0"), and there is no limitation on this.

[0057] Continue to refer Figure 1The address generation circuit 13 is used to generate a corresponding internal error check address IMWR_AD to indicate the target storage unit to perform the current internal error check operation (internal read-modify-write operation) according to the internal error check command signal IMWRAB output by the internal command generation circuit 12, so that the control logic circuit 14 can control the error correction circuit 16 to perform an internal read-modify-write operation on the target storage units in the multiple storage arrays 15 in sequence according to the internal error check command signal IMWRAB. Among them, the internal error check address IMWR_AD includes a target row address and a target column address, and the internal error check address IMWR_AD is shared by multiple storage arrays 15, that is, each storage array 15 has a target storage unit indicated by the internal error check address IMWR_AD; and the error correction circuit 16 is shared by multiple storage arrays 15 and the error correction circuit 16 can only perform an internal read-modify-write operation on a target storage unit in one storage array 15 at the same time. Therefore, based on each internal error check command signal IMWRAB and the corresponding internal error check address IMWR_AD, the error correction circuit 16 needs to perform an internal read-modify-write operation on the target storage unit in each storage array 15 in turn, that is, the error correction circuit 16 actually performs multiple internal read-modify-write operations (corresponding to multiple groups of internal signals IRD / IWR) in succession to complete the internal error check operation (internal read-modify-write operation) corresponding to the current internal error check command signal IMWRAB.

[0058] In some embodiments, the error correction circuit 16 may be an on-die ECC circuit. The error correction circuit 16 may generate check data for the write data written into the storage array 15, and may also use the storage data and check data read from the storage array 15 to check and correct errors in the storage data. The internal read-modify-write operation in the present disclosure utilizes the function of the error correction circuit 16 to check and correct errors in the storage data. In addition, the error correction circuit 16 may use encoding methods such as Hamming code, RS code, and convolutional code, which are not specifically limited here.

[0059] Furthermore, the control logic circuit 14 is composed of: Figure 2As shown, the control logic circuit 14 includes a plurality of storage array control circuits 141, and the plurality of storage array control circuits 141 correspond one to one with the plurality of storage arrays 15; each storage array control circuit 141 is configured to receive an internal error check command signal IMWRAB and an internal error check address IMWR_AD, generate a plurality of groups of internal signals IRD / IWR in response to the internal error check command signal IMWRAB, and when the corresponding storage array 15 is in an enabled state, control the error correction circuit 16 according to the corresponding group of internal signals IRD / IWR to perform an internal read-modify-write operation on the target storage unit in the corresponding storage array 15; wherein each group of internal signals includes an internal read signal IRD and an internal write signal IWR.

[0060] It should be noted that, in a DRAM chip, each memory array 15 may correspond to a memory array control circuit 141, and the memory array control circuit 141 may not only control the error correction circuit 16 to perform internal read-modify-write operations on the corresponding memory array 15, but may also control the error correction circuit 16 to perform external read-modify-write operations on the corresponding memory array 15, that is, the internal error checking circuit 10 of the disclosed embodiment implements the related circuits (memory array control circuit 141 and error correction circuit 16) and paths (interaction paths between the memory array control circuit 141, the error correction circuit 16 and the memory array 15) of the original external read-modify-write operations, and only a simple improvement is made to the memory array control circuit 141, so that the internal read-modify-write operations can be performed on the storage data in the memory array 15, so as to realize the internal error detection / correction function.

[0061] In addition, the storage array control circuit 141 can also control the corresponding storage array 15 to perform external read-modify-write operations and normal read and write operations. Specifically, the storage array control circuit 141 can control the corresponding storage cells in the storage array to perform word line opening, charge sharing, data amplification, data reading, data writing, precharging and other operations in sequence according to the activation command signal, read / write command signal, precharge signal, row address, column address and other information to achieve correct reading or writing of storage data.

[0062] Exemplarily, if four storage arrays 15 (BA0, BA1, BA2, BA3) share one error correction circuit 16, the logic control circuit 14 includes four storage array control circuits 141 (BA Logic0, BA Logic1, BA Logic2, BA Logic3), which correspond to the four storage arrays 15 one by one, and each storage array control circuit 141 generates four groups of internal signals IRD / IWR (IRD0 / IWR0, IRD1 / IWR1, IRD2 / IWR2, IRD3 / IWR3), and enables the four storage arrays BA0, BA1, BA2, BA3 in sequence to ensure that the error correction circuit 16 performs an internal read-modify-write operation on only one storage array 15 at the same time. In the first time period T0, each storage array control circuit sends the first group of internal signals IRD0 / IWR0. At this time, the storage array BA0 is enabled. In the second time period T1, each storage array control circuit sends a second group of internal signals IRD1 / IWR1. At this time, the storage array BA1 is in the enabled state, and the other storage arrays BA0, BA2, and BA3 are not enabled. The error correction circuit 16 only receives the first group of internal signals IRD0 / IWR0 sent by the corresponding storage array control circuit BALogic0 to control the target storage unit in the storage array BA0 to perform an internal read-modify-write operation. In the second time period T1, each storage array control circuit sends a second group of internal signals IRD1 / IWR1. At this time, the storage array BA1 is in the enabled state, and the other storage arrays BA0, BA2, and BA3 are not enabled. The error correction circuit 16 only receives the first group of internal signals IRD0 / IWR0 sent by the corresponding storage array control circuit BALogic0 to control the target storage unit in the storage array BA0 to perform an internal read-modify-write operation. The second group of internal signals IRD1 / IWR1 sent by Logic1 controls an internal read-modify-write operation to be performed on the target storage cells in the storage array BA1. Similarly, in the third time period T2, the error correction circuit 16 only receives the third group of internal signals IRD2 / IWR2 sent by the corresponding storage array control circuit BA Logic2, controls an internal read-modify-write operation to be performed on the target storage cells in the storage array BA2. In the third time period T3, the error correction circuit 16 only receives the fourth group of internal signals IRD3 / IWR3 sent by the corresponding storage array control circuit BA Logic3, controls an internal read-modify-write operation to be performed on the target storage cells in the storage array BA3. So far, based on a group of internal signals sent by the corresponding storage array control circuit, the error correction circuit 16 has successively performed an internal read-modify-write operation on the target storage cells in the four storage arrays BA0, BA1, BA2, and BA3.

[0063] See also Figure 3 , which shows a layout diagram of a storage array 15, a storage array control circuit 141 and an error correction circuit 16 provided by an embodiment of the present disclosure. Figure 3In the example shown, the storage area (Array region, also called Coreregion) includes 8 storage groups (Bank Group, BG): BG0-BG7. Different storage groups can operate synchronously. Each storage group corresponds to an error correction circuit 16: ECC0-ECC7. Each storage group includes 4 storage arrays 15 (also called storage body Bank, BA): BA0, BA1, BA2 and BA3. The 4 storage arrays BA0, BA1, BA2 and BA3 in each storage group share an error correction circuit 16. Each storage body in each storage group corresponds to a storage array control circuit 151 (also called storage body logic circuit Bank Logic). Taking BA3 in BG1 as an example, the storage array BA3 includes m rows (Row): ROW0-ROWm, and the storage array BA3 includes n columns (Column, Col): Col0-Coln. Figure 3 In the figure, a circle represents multiple storage cells corresponding to a storage address. Specifically, in the storage array BA3, the corresponding multiple storage cells can be located according to a storage address (including row address ROW0 and row address Col0), and each internal read-modify-write operation is for multiple storage cells corresponding to a storage address in the storage array 15.

[0064] In some embodiments, the internal command generation circuit 12 and the address generation circuit 13 are shared by all the memory arrays 15 in the memory, that is, the internal error check command signal IMWRAB generated by the internal command generation circuit 12 and the internal error check address IMWR_AD (including the target row address Row_ad and the target column address Col_ad) generated by the address generation circuit 13 are respectively sent to each memory array 15. Since different memory groups BG0-BG7 can be operated synchronously, each memory group BG needs to be set with a corresponding control logic circuit 14 and an error correction circuit 16, and multiple memory arrays 15 in each memory group BG can share a control logic circuit 14 and an error correction circuit 16. Specifically, Figure 3 As shown, the storage area includes a total of 4*8=32 storage arrays 15, and the 32 storage arrays 15 in the 8 storage groups share one internal command generation circuit 12 and address generation circuit 13. Among them, each storage group BG corresponds to one control logic circuit 14 (including four storage array control circuits 141) and one error correction circuit 16, and eight storage groups correspond to eight control logic circuits 14 (32 storage array control circuits) and eight error correction circuits 16, among which the four storage arrays 15 in each storage group BG share one error correction circuit 16, and each storage array control circuit 141 controls one storage array.

[0065] It should be noted that the storage array may be a storage body BA, or a storage group BG, or a storage block Block. Here, the storage array is taken as a storage body BA for illustration, but it does not constitute a limitation to the disclosure.

[0066] In some embodiments, Figure 1-2 As shown, the error correction circuit 16 is configured to read the storage data RD_Data from the target storage unit according to the internal read signal IRD, and perform error detection and error correction on the storage data RD_Data to generate correction data WR_Data; the error correction circuit 16 is also configured to write the correction data WR_Data into the target storage unit according to the internal write signal IWR.

[0067] It should be noted that if Figure 2 As shown, the error correction circuit 16 needs to perform an internal read-modify-write operation on multiple storage arrays 15 in sequence based on multiple groups of internal signals IRD / IWR. When the error correction circuit 16 performs an internal read-modify-write operation on each storage array 15, it needs to perform the above-mentioned read-modify function (i.e., reading the storage data RD_Data from the target storage unit according to the internal read signal IRD, and performing error detection and error correction on the storage data RD_Data to generate correction data WR_Data) and write function (i.e., writing the correction data WR_Data into the target storage unit according to the internal write signal IWR).

[0068] In some embodiments, Figure 1 As shown, the internal command generation circuit 12 is also configured to, when the error check enable signal IMWR_EN indicates that the internal error check function is not turned on, generate and output an internal self-refresh command signal IMWRAB in response to each pulse on the self-refresh clock signal SR_CLK; and when the error check enable signal IMWR_EN indicates that the internal error check function is turned on and the count value of the self-refresh clock signal SR_CLK is not a first preset value, generate and output an internal self-refresh command signal IMWRAB.

[0069] It should be noted that, as mentioned above, when the error check enable signal IMWR_EN is at a valid level, indicating that the internal error check function is turned on, the internal command generation circuit 12 needs to periodically "steal" a pulse on the self-refresh clock signal SR_CLK to generate the internal error check command signal IMWRAB; and when the count value of the self-refresh clock signal SR_CLK is not the first preset value, or when the error check enable signal IMWR_EN is at an invalid level, indicating that the internal error check function is not turned on, there is no need to "steal" a pulse on the self-refresh clock signal SR_CLK to generate the internal error check command signal IMWRAB, and the internal command generation circuit 12 continues to generate and output an internal self-refresh command signal IREFAB based on the pulses on the self-refresh clock signal SR_CLK to perform the relevant functions of the original self-refresh operation.

[0070] Combination Figure 4 The signal timing diagram shown in the figure illustrates the working principle of the internal error checking circuit 10 provided in the embodiment of the present disclosure, which is specifically as follows:

[0071] At time t0, when the external self-refresh entry command SRE instructs the memory to enter the self-refresh state, the self-refresh enable signal SR_EN is activated, that is, the self-refresh enable signal SR_EN is flipped from a low level to a high level; the clock generation circuit 11 starts to generate and output the self-refresh clock signal SR_CLK in response to the self-refresh enable signal SR_EN;

[0072] In the t0-t1 phase, the error check enable signal IMWR_EN is at an invalid level (low level), and the internal error check function is not enabled at this time. The internal command generation circuit 12 generates an internal self-refresh command signal IREFAB based on the self-refresh clock signal SR_CLK to control the storage array 15 to perform the original self-refresh operation;

[0073] At time t1, the error check enable signal IMWR_EN flips to the valid level (high level), at which time the internal error check function is turned on, and the internal command generation circuit 12 starts counting the pulses on the self-refresh clock signal SR_CLK;

[0074] At time t2, when the count value of the pulses on the self-refresh clock signal SR_CLK reaches the first preset value for the first time, a first internal error check command signal IMWRAB is generated, and the count value is reset;

[0075] In the stage t2-t3, the address generation circuit 13 counts the row / column addresses of the storage array according to the received first internal error check command signal IMWRAB, generates and outputs the target row address Row_ad=RA and the target column address Col_ad=CA+1=000000 (taking the column address as a 6-bit signal and the column address CA as the initial value 111111 for example), i.e., the internal error check address IMWR_AD; the control logic circuit 14 (or the storage array control circuit 141) sets the operation identification signal IMWR_FLAG to a valid level (high level) at time t3 according to the received internal error check command signal IMWRAB; here, the internal error check command signal IMWRAB actually refers to the pulse on the internal error check command signal;

[0076] It should be noted that Figure 4 In the timing diagram shown, the transmission delay between circuits and the delay of the circuit devices themselves have been taken into account, so the change moments of some related signals are not completely aligned. Specifically, the internal error check command signal IMWRAB is generated at time t2, and the operation identification signal IMWR_FLAG associated with it is flipped from the invalid level to the valid level at time t3 after time t2;

[0077] In the stage t3-t7, the operation identification signal IMWR_FLAG is at the valid level, and the control logic circuit 14 (or the storage array control circuit 141) generates four groups of internal signals in sequence, that is, alternately generates four internal read signals IRD and four internal write signals IWR, so as to control the error correction circuit 16 to perform an internal read-modify-write operation on the four storage arrays 15 in sequence; here, the example of four storage arrays 15 (BA0-BA3) sharing one error correction circuit 16 is used for illustration, which does not constitute a limitation;

[0078] Specifically, in the t3-t4 stage, the count value IWR_cnt of the internal write signal is an initial value 00, at which time the storage array BA0 is in an enabled state, and the storage arrays BA1-BA3 are not enabled, and the error correction circuit 16 receives the first group of internal signals sent by the control logic circuit 14 (or only receives the corresponding storage array control circuit 141), that is, the internal read signal IRD and the internal write signal IWR sent in the t3-t4 stage, and the error correction circuit 16 performs an internal read-modify-write operation on the storage array BA0 based on the first group of internal signals; at time t4, based on the first rising edge of the inverted signal IWRB of the internal write signal, the count value IWR_cnt of the internal write signal is From 00 to 01, at this time, the storage array BA1 is switched to the enabled state, and other storage arrays are not enabled. During t4-t5, the error correction circuit 16 receives the second group of internal signals sent by the control logic circuit 14 (or only receives the corresponding storage array control circuit 141), and the error correction circuit 16 performs an internal read-modify-write operation on the storage array BA1 based on the second group of internal signals; and so on, during t5-t6, the error correction circuit 16 performs an internal read-modify-write operation on the storage array BA2 based on the third group of internal signals, and during t6-t7, the error correction circuit 16 performs an internal read-modify-write operation on the storage array BA3 based on the fourth group of internal signals;

[0079] Until time t8, based on the last rising edge of the inverted signal IWRB of the internal write signal, the count value IWR_cnt of the internal write signal changes from 11 to 00, and the operation end signal IMWR_END generates a rising edge, that is, it flips from the invalid level (low level, logic "0") to the valid level (high level, logic "1"); based on the rising edge of the operation end signal IMWR_END, the operation identification signal IMWR_FLAG flips from the valid level to the invalid level. At this point, the internal read-modify-write operation is completed.

[0080] At time t9, when the count value of the pulses on the self-refresh clock signal SR_CLK reaches the first preset value again, a second internal error check command signal IMWRAB is generated, and the count value is reset; the address generation circuit 13 counts the row / column addresses of the storage array according to the second internal error check command signal IMWRAB, specifically, the column address is "+1", and the target column address Col_ad=CA+2=000001 is generated and output, and the target row address Row_ad=RA remains unchanged;

[0081] Until time t10, when the count value of the pulses on the self-refresh clock signal SR_CLK reaches the first preset value for the nth time, the nth internal error check command signal IMWRAB is generated. Assuming that n is 64, the address generation circuit 13 performs the 64th "+1" operation on the column address, generates and outputs the target column address Col_ad=111111, and the target row address Row_ad=RA remains unchanged. At this time, it indicates that the address generation circuit 13 has traversed all column addresses (Col_ad=000000 to Col_ad=111111) of the RAth row in the storage array 15, and the error correction circuit 16 will perform an internal read-modify-write operation on the storage cell corresponding to the last column address CA=111111 of the RAth row;

[0082] It should be noted that the address generation circuit 13 needs to synchronously sample and output the target row address Row_ad and the target column address Col_ad based on the internal error check command signal IMWRAB each time, and the row count value Row_cnt will change based on the currently generated target column address Col_ad, that is, the target row address Row_ad sampled and output by the address generation circuit 13 each time corresponds to the previous target column address Col_ad, and because the next internal error check command signal IMWRAB will instruct the error correction circuit 16 to perform an internal read-modify-write operation on the storage cell corresponding to the first column address Col_ad=000000 of the next row RA+1 of the storage array 15, therefore, when the currently generated target column address Col_ad=111111, the row count value Row_cnt needs to be set to RA+1, so that when the next internal error check command signal IMWRAB is received, the address generation circuit 13 can synchronously sample and output the correct target row address Row_ad=RA+1 and target column address Col_ad=000000.

[0083] In some embodiments, Figure 1 As shown, the control logic circuit 14 is further configured to control a self-refresh operation to be performed on all storage arrays 15 after controlling the error correction circuit 16 to sequentially perform an internal read-modify-write operation on target storage cells corresponding to the internal error check addresses IMWR_AD in multiple storage arrays 15.

[0084] It should be noted that when the error check enable signal IMWR_EN indicates that the internal error check function is turned on, the internal command generation circuit 12 needs to periodically "steal" a pulse on the self-refresh clock signal SR_CLK to generate the internal error check command signal IMWRAB. At this time, the internal self-refresh command signal IREFAB is no longer generated based on the pulse on the "stolen" self-refresh clock signal SR_CLK. At this time, the control logic circuit 14 can no longer perform a self-refresh operation based on the internal self-refresh command signal IREFAB, which is equivalent to performing one less self-refresh operation. In order to ensure that the original self-refresh function is not affected after the introduction of the internal error check function, the control logic circuit 14 can perform a self-refresh operation on all storage arrays 141 immediately after each internal read-modify-write operation is executed based on the internal error check command signal IMWRAB (without waiting for the next pulse of the self-refresh clock signal SR_CLK), which is equivalent to compensating for the impact of the internal error check operation on the original self-refresh function.

[0085] In some embodiments, Figure 5 As shown, the address generation circuit 13 includes a column address generation circuit 131, a first decoding circuit 132 and a row address generation circuit 133;

[0086] The column address generation circuit 131 is configured to receive the internal error check command signal IMWRAB, perform column counting on the current storage row according to the internal error check command signal IMWRAB, and generate and output a target column address Col_ad;

[0087] The first decoding circuit 132 is configured to decode the target column address Col_ad, and generate and output a column end signal Col_End when the target column address Col_ad indicates that the column count of the current storage row is completed;

[0088] The row address generation circuit 133 is configured to receive the column end signal Col_End and the internal error check command signal IMWRAB, count rows of the memory array according to the column end signal Col_End, and generate and output a target row address signal Row_ad.

[0089] by Figure 3 The storage area shown is an example, combined with Figure 4 and Figure 5The working principle of the address generation circuit 13 is described. The column address generation circuit 131 can sequentially traverse all column addresses (Col_ad=000000 to Col_ad=111111) of each row in the storage array 15, and each time perform a "+1" count on the current column address based on the internal error check command signal IMWRAB to generate and output the target column address Col_ad, until the currently generated target row address Row_ad=RA and the target column address Col_ad=111111, as shown in FIG. Figure 4 The time t10 shown indicates that the column address generation circuit 131 has completed the traversal count of all column addresses (Col_ad=000000 to Col_ad=111111) of the current row RA in the storage array 15. At this time, the first decoding circuit 132 decodes the current target column address Col_ad=111111 and outputs the column end signal Col_End to instruct the row address generation circuit 133 to perform a "+1" count on the current row address to generate and output a new target row address RA+1. At the same time, the column address generation circuit 131 will still perform a "+1" count on the target column address Col_ad=111111 next time to obtain a new target column address Col_ad=000000 to indicate that a content read-modify-write operation is performed on the storage cell corresponding to the first column address of the next row RA+1.

[0090] Combination Figure 1 , Figure 5 and Figure 6 , the working principle of the internal error checking circuit 10 in the embodiment of the present disclosure to continue to perform a self-refresh operation after controlling the execution of the internal read-modify-write operation is described as follows:

[0091] At time t11, Figure 4 Similarly, when the external self-refresh entry command SRE instructs the memory to enter the self-refresh state, the self-refresh enable signal SR_EN is activated, and the clock generation circuit 11 starts to generate and output the self-refresh clock signal SR_CLK;

[0092] In the stage t11-t13, the error check enable signal IMWR_EN is at an invalid level, and the internal error check function is not turned on at this time. The internal command generation circuit 12 generates an internal self-refresh command signal IREFAB based on each pulse on the self-refresh clock signal SR_CLK to control the storage array 15 to perform a self-refresh operation. Specifically, at time t13, the internal command generation circuit 12 generates an internal self-refresh command signal IREFAB based on the self-refresh clock signal SR_CLK. At the same time, the address generation circuit 13 (or the refresh address generation circuit 136) also counts the rows of the storage array based on the internal self-refresh command signal IREFAB, generates and outputs the self-refresh address S_RA, and the control logic circuit 14 (or the storage array control circuit 141) controls the self-refresh operation of the storage rows corresponding to the self-refresh address S_RA in all storage arrays 15.

[0093] At time t13, the error check enable signal IMWR_EN flips to the valid level, at which time the internal error check function is turned on, and the internal command generation circuit 12 starts counting the pulses on the self-refresh clock signal SR_CLK;

[0094] In the t14-t16 phase, when the count value of the pulses on the self-refresh clock signal SR_CLK reaches the first preset value for the first time (the first preset value is taken as m for example), after the internal command generation circuit 12 generates the internal error check command signal IMWRAB, the address generation circuit 13 and the control logic circuit 14 (or the storage array control circuit 141) control the error correction circuit 16 to sequentially perform an internal read-modify-write operation on the plurality of storage arrays 15, Figure 4 The same as shown, please refer to the above content, no further details will be given here;

[0095] It should be noted that, in the t13-t14 phase, before the internal read-modify-write operation is performed (i.e., before the count value of the pulses on the self-refresh clock signal SR_CLK reaches the first preset value m for the first time), the internal command generation circuit 12 has generated m-1 self-refresh command signals IREFAB, and accordingly, the address generation circuit 13 (or the refresh address generation circuit 136) has also performed m-1 "+1" counts on the self-refresh address SREF_Row based on the m-1 self-refresh command signals IREFAB, and the self-refresh row address SREF_Row becomes S_RA+m-1; when a self-refresh operation is continued after the internal read-modify-write operation is performed, in order to avoid this self-refresh The operation repeats the self-refresh operation on the last self-refresh address S_RA+m-1, and the address generation circuit 13 (or the refresh address generation circuit 136) also needs to count the self-refresh row address SREF_Row by "+1" to output the self-refresh address SREF_Row corresponding to the self-refresh operation. However, since the internal command generation circuit 12 does not generate the self-refresh command signal IREFAB, at time t14, the address generation circuit 13 (or the refresh address generation circuit 136) can count the self-refresh row address SREF_Row by "+1" based on the internal error check command signal IMWRAB, and output a new self-refresh address SREF_Row=S_RA+m;

[0096] At time t16, the operation identification signal IMWR_FLAG flips from a valid level to an invalid level, indicating that all storage arrays 15 have completed the internal read-modify-write operation. At this time, in response to the falling edge of the operation identification signal IMWR_FLAG, the control logic circuit 14 (specifically, it can be the self-refresh control circuit 147 in the storage array control circuit 141) flips the self-refresh window signal SREF_WIN from an invalid level (low level, logic "0") to a valid level (high level, logic "1"). Based on the self-refresh window signal SREF_WIN at the valid level and the received self-refresh address S_RA+m, the control logic circuit 14 (specifically, it can be the self-refresh control circuit 147 in the storage array control circuit 141) controls the storage array 15 to perform a self-refresh operation.

[0097] In some embodiments, Figure 7As shown, the row address generation circuit 133 includes: a row counting circuit 134, configured to receive a column end signal Col_End, and perform row counting on the storage array 15 according to the column end signal Col_End, and generate and output a row count value Row_cnt; a row address sampling circuit 135, configured to receive an internal error check command signal IMWRAB and a row count value Row_cnt, and sample the row count value Row_cnt in response to the internal error check command signal IMWRAB, and generate and output a target row address signal Row_ad.

[0098] It should be noted that after the control logic circuit 14 (or the storage array control circuit 141) receives the internal error check command signal IMWRAB, it is still necessary to wait for the corresponding internal error check address (i.e., the target row address Row_ad and the target column address Col_ad) before it can control the error correction circuit 16 to perform an internal read-modify-write operation. In order not to affect the original external read-modify-write operation timing requirements of the memory, the column address generation circuit 131 and the row address generation circuit 133 need to synchronously sample and output the target row address Row_ad and the target column address Col_ad based on the internal error check command signal IMWRAB each time. This ensures that the time for outputting the target row address Row_ad and the target column address Col_ad is less delayed than the internal error check command signal IMWRAB.

[0099] It should also be noted that the row counting circuit 134 counts the column end signal Col_End to generate a row count value Row_cnt. The row count value Row_cnt changes based on the currently generated target column address Col_ad, and the target column address Col_ad changes based on the internal error check command signal IMWRAB. Therefore, before the row count value Row_cnt changes, the row address sampling circuit 135 has completed sampling the row count value Row_cnt based on the internal error check command signal IMWRAB and outputs the target row address Row_ad, that is, the target row address Row_ad sampled and output by the row address sampling circuit 135 each time corresponds to the previous target column address Col_ad output by the row address generation circuit 131.

[0100] In some embodiments, Figure 5 As shown, the address generation circuit 13 also includes a refresh address generation circuit 136, which is configured to receive an internal self-refresh command signal IREFAB, and count the rows of the storage array 15 according to the internal self-refresh command signal IREFAB, generate and output a self-refresh address SREF_Row; the control logic circuit 14 is also configured to control a refresh operation on all storage arrays based on the self-refresh address SREF_Row.

[0101] It should be noted that the refresh is performed on one or more rows of the storage array 15. Therefore, the refresh address generation circuit 136 does not need to perform traversal counting on the column address, but only needs to complete the traversal counting on the row address. The self-refresh address SREF_Row only includes the row address information.

[0102] In some embodiments, continue to refer to Figure 5 , wherein the address generation circuit 13 further includes a refresh address generation circuit 136, which is configured to receive an internal self-refresh command signal IREFAB or an internal error check command signal IMWRAB, and count rows of the storage array 15 according to the internal self-refresh command signal IREFAB or the internal error check command signal IMWRAB, and generate and output a self-refresh address SREF_Row.

[0103] refer to Figure 6 At time t16, when the control logic circuit 14 controls to continue to perform a self-refresh operation after completing the internal read-modify-write operation, the refresh address generation circuit 136 included in the address generation circuit 13 also needs to synchronously output the self-refresh address SREF_Row corresponding to the self-refresh operation to the control logic circuit 14. If the refresh address generation circuit 136 only counts the rows of the storage array based on the internal self-refresh command signal IREFAB, but because the current pulse of the self-refresh clock signal SR_CLK is "stolen" to generate the internal error check command signal IMWRAB, and the internal self-refresh command signal IREFAB is not generated, at this time, the refresh address generation circuit 136 cannot count the rows of the storage array based on the internal self-refresh command signal IREFAB to generate a new self-refresh address, and will still output the self-refresh address S_RA corresponding to the last self-refresh operation (the refresh operation before time t10), resulting in repeated refresh of the storage unit with the same row address twice. Therefore, in this case, the refresh address generation circuit 136 can be configured to simultaneously receive the internal error check command signal IMWRAB and the internal self-refresh command signal IREFAB, and perform row counts on the storage array according to the internal error check command signal IMWRAB or the internal self-refresh command signal IREFAB, and generate and output a self-refresh address SREF_Row. That is, regardless of whether the internal command address generation circuit 12 generates the internal error check command signal IMWRAB or the internal self-refresh command signal IREFAB, the refresh address generation circuit 136 can perform a row count on the storage array. For example, at time t10, the refresh address generation circuit 136 can generate a new self-refresh address S_RA+m based on the internal error check command signal IMWRAB to ensure that at time t16, a self-refresh operation can be continued on the new self-refresh address S_RA+m after the internal read-modify-write operation, thereby avoiding performing two self-refresh operations on the same row address at time t15.

[0104] In some embodiments, the memory array control circuit 141 can control the multiple memory rows of the memory array 15 to perform a refresh operation at the same time. At this time, the refresh address generation circuit 136 can output multiple self-refresh addresses at the same time. The memory array row count is performed each time according to the internal error check command signal IMWRAB or the internal self-refresh command signal IREFAB, and the +1 count may not be performed. Exemplarily, based on the parameter configuration in the mode register, the memory array control circuit 141 can perform a refresh operation on 4 memory rows at the same time. The refresh address generation circuit 136 performs a +4 row count on the memory array each time according to the internal error check command signal IMWRAB or the internal self-refresh command signal IREFAB. If the 4 self-refresh addresses corresponding to the last self-refresh operation are S_RA, S_RA+1, S_RA+2, and S_RA+3, the 4 self-refresh addresses output this time are S_RA+4, S_RA+5, S_RA+6, and S_RA+7. Of course, if the storage rows of the storage array are divided into 4 groups, with P storage rows in each group, the refresh address generation circuit 136 can also perform a row count of +1 each time. When the 4 self-refresh addresses corresponding to the last self-refresh operation are S_RA, S_RA+P, S_RA+2P, and S_RA+3P, the 4 self-refresh addresses output this time are S_RA+1, S_RA+P+1, S_RA+2P+1, and S_RA+3P+1.

[0105] In some embodiments, Figure 8-Figure 9 As shown, the column address generation circuit 131 includes N cascaded first triggers DFF1, N is an integer greater than or equal to 1; the clock control end of the first-stage first trigger DFF1 serves as the input end of the column address generation circuit 131, and receives the internal error check command signal IMWRAB; the inverting output end of each stage of the first trigger DFF1 is connected to its own data input end; the clock control ends of the other first triggers DFF1 except the first-stage first trigger DFF1 are all connected to the inverting output end of the first trigger DFF1 of the previous stage; the positive output ends of the N first triggers DFF1 jointly output the target column address Col_ad; the first decoding circuit includes a first NAND gate, the N input ends of the first NAND gate are respectively connected to the positive output ends of the N first triggers DFF1, and the output end of the first NAND gate is used to output a column end signal.

[0106] Figure 8 and Fig. 9 In the example, N=6 is used for explanation, that is, the target column address Col_ad<5:0> includes 6 bits of information, but this does not constitute a limitation to the present disclosure.

[0107] It should be noted that Figure 8The column address generation circuit 131 shown in FIG. 1 is a synchronous binary counter. In some other embodiments, the column address generation circuit 131 may also be implemented by an asynchronous binary counter, which is not specifically limited here. Fig. 9 The first decoding circuit 132 shown in the figure outputs the column count signal Col_End when Col_ad<5:0> is 111111, that is, the target column address Col_ad<5:0> is traversed and counted in the order of CA=000000 to CA=111111. In some other embodiments, the traversal and count may also be performed in other orders. Specifically, the target column address Col_ad<5:0> may be traversed and counted in the order of CA=100000 to CA=011111. At this time, the first decoding circuit 132 outputs the column count signal Col_End when Col_ad<5:0> is 011111.

[0108] In some embodiments, Fig.10 As shown, the row counting circuit 134 includes M cascaded second flip-flops DFF2, where M is an integer greater than or equal to 1; the clock control end of the first-stage second flip-flop DFF2 serves as the input end of the row counting circuit 134 to receive the column end signal Col_End; the inverting output end of each stage of the second flip-flop DFF2 is connected to its own data input end; the clock control ends of the other second flip-flops DFF2 except the first-stage second flip-flop DFF2 are connected to the inverting output end of the previous stage of the second flip-flop DFF2; the positive output ends of the M second flip-flops DFF2 jointly output the row count value Row_cnt; the row address sampling circuit 135 includes M third flip-flops DFF3; the clock control end of each third flip-flop DFF3 receives the internal error check command signal IMWRAB; the data input ends of the M third flip-flops DFF3 are connected to the positive output ends of the M second flip-flops DFF2 in a one-to-one correspondence to receive the row count value Row_cnt; the positive output ends of the M third flip-flops DFF3 jointly output the target row address Row_ad.

[0109] It should be noted that Fig.10 In the example, M=15 is used for explanation, that is, the row count value Row_cnt<14:0> and the target row address Row_ad<14:0> both include 15 bits of information, but this does not constitute a limitation to the present disclosure; Fig.10 The row counting circuit 134 shown in FIG. 1 is a synchronous binary counter. In some other embodiments, the row counting circuit 134 may also be implemented by an asynchronous binary counter, which is not specifically limited here.

[0110] In some embodiments, Fig.11As shown, the storage array control circuit 141 includes: an identification signal generating circuit 142, configured to receive an internal error checking command signal IMWRAB, and in response to the internal error checking command signal IMWRAB, generate and output an operation identification signal IMWR_FLAG at a valid level; a read / write command generating circuit 143, configured to receive the operation identification signal IMWR_FLAG and the internal error checking command signal IMWRAB, and in response to the internal error checking command signal IMWRAB, sequentially generate a plurality of groups of internal signals during a period in which the operation identification signal IMWR_FLAG is at a valid level; the identification signal generating circuit 142 is also configured to receive an internal write signal IWR, and when the count value of the internal write signal IWR reaches a second preset value, sets the operation identification signal IMWR_FLAG to an invalid level.

[0111] It should be noted that the second preset value is associated with the number of multiple storage arrays 15 that share the error correction circuit 16 in each storage group BG, that is, it ensures that the multiple groups of internal signals (internal read signal IRD and internal write signal IWR) generated and output by the read / write command generation circuit 143 can control the error correction circuit 16 to perform one internal read-modify-write operation on the multiple storage arrays 15 in turn.

[0112] In some embodiments, Fig.12 As shown, the identification signal generating circuit 142 includes: a command counting circuit 144, configured to count the inverted signal of the internal write signal IWR to generate and output the count value of the internal write signal IWR; a second decoding circuit 145, configured to receive the count value of the internal write signal IWR, and when the count value of the internal write signal IWR is a second preset value, generate and output the operation end signal IMWR_END; an SR trigger 146, configured to receive the internal error check command signal IMWRAB and the operation end signal IMWR_END, and in response to the internal error check command signal IMWRAB, set the operation identification signal IMWR_FLAG to a valid level, and when the count value of the internal write signal IWR reaches the second preset value, set the operation identification signal IMWR_FLAG to an invalid level.

[0113] For example, Figure 3 and Figure 4As shown, if each storage group BG includes 1 error correction circuit 16 and 4 storage arrays 15 (BA0, BA1, BA2, BA3), at this time, the second preset value is 4 (represented by binary "00"), that is, the read / write command generation circuit 143 needs to generate 4 groups of internal signals during the period when the operation identification signal IMWR_FLAG is at the valid level. At time t3, the SR trigger 146 in the identification signal generation circuit 142 sets the operation identification signal IMWR_FLAG to the valid level (high level) according to the received internal error check command signal IMWRAB, and then during the period when the operation identification signal IMWR_FLAG is at the valid level, that is, during the t3-t7 period, 4 internal read signals IRD and 4 internal write signals IWR are alternately generated, which are respectively recorded as a group of internal signals IRD1 and IWR1 corresponding to BA0 (in the t3-t4 period), and a group of internal signals IRD2 and IWR2 corresponding to BA1 (in the t4-t5 period). A group of internal signals IRD3 and IWR3 corresponding to BA2 (in the t5-t6 stage), a group of internal signals IRD4 and IWR4 corresponding to BA3 (in the t6-t7 stage), and each group of internal signals is used to control the error correction circuit 16 to perform an internal read-modify-write operation on the storage data corresponding to the internal error check address in the four storage arrays 15 in turn, and each internal read-modify-write operation first performs the reading of the storage data RD_Data, as well as error detection and correction operations according to the internal read signal IRD, and then writes the correction data WR_Data after error detection and correction into the storage array according to the internal write signal IWR. In order to ensure that all storage arrays have completed the internal read-modify-write operation normally, it is necessary to use the command counting circuit 144 to count the internal write signal IWR or the inverted signal IWRB of the internal write signal. At time t7, the count is performed based on the last rising edge of the inverted signal IWRB of the internal write signal. When the count value IWR_cnt of the internal write signal output by the command counting circuit 144 is the second preset value 4 (represented by binary "00"), the error correction circuit 16 has written the corresponding correction data into the corresponding storage array BA3 according to the last internal write signal IWR4, and the second decoding circuit 145 will output IMWR_END to indicate that all storage arrays 15 have completed the internal read-modify-write operation. At this time, the operation identification signal IMWR_FLAG can be set to an invalid level to stop continuing to generate the internal signal IRD / IWR.

[0114] It should be noted that, in order to ensure that the last write operation performed by the error correction circuit 16 according to the internal write signal IWR4 is completed normally, the inverted signal IWRB of the internal write signal can be counted to generate the count value IWR_cnt of the internal write signal. This solution can ensure that when the count value of the internal write signal reaches the second preset value 4 (i.e. Figure 4At time t7 in the figure, the 4th rising edge of IWRB corresponds to the 4th falling edge of IWR), the error correction circuit 16 has completed the last write operation according to the internal write signal IWR (valid level, high level "1"). At this time, even if the operation identification signal IMWR_FLAG is set to an invalid level, the control read / write command generation circuit 143 no longer generates the internal signal IRD / IWR, and it will not affect the last internal read-modify-write operation performed by the error correction circuit 16.

[0115] It should also be noted that Figure 4 The count value IWR_cnt of the internal write signal shown in is represented by a 2-bit signal, and the second preset value = 4 corresponds to the signal "00", which is exactly the initial value of the count value IWR_cnt of the internal write signal. Therefore, after the operation identification signal IMWR_FLAG is set to an invalid level, there is no need to reset the count value IWR_cnt of the internal write signal. However, in some other embodiments, the count value IWR_cnt of the internal write signal is represented by a 3-bit signal, and the second preset value = 4 corresponds to the signal "100". At this time, after the operation identification signal IMWR_FLAG is set to an invalid level, the count value IWR_cnt of the internal write signal needs to be reset to the initial value 000.

[0116] In some embodiments, Fig.14 As shown, the read / write command generation circuit 143 includes: a second NAND gate 1431, a first input end of the second NAND gate 1431 receives the operation identification signal IMWR_FLAG, and a second input end of the second NAND gate 1431 receives the internal error check command signal IMWRAB; a first NOR gate 1432, a first input end of the first NOR gate 1432 is electrically connected to the output end of the second NAND gate 1431, and the output end of the first NOR gate 1432 is used to output the internal read signal IRD; a second NOR gate 1433, a first input end of the second NOR gate 1433 is electrically connected to the output end of the first NOR gate 1432, and the output end of the second NOR gate 1433 is electrically connected to the second input end of the first NOR gate 1432; a delay unit 1434, the input end of the delay unit 1434 is electrically connected to the output end of the first NOR gate 1432; the first NOR gate 1435, the input end of the first NOR gate 1435 is electrically connected to the output end of the delay unit 1434, and the output end of the first NOR gate 1435 is electrically connected to the second input end of the second NOR gate 1433; the second NOR gate 1436, the input end of the second NOR gate 1436 receives the operation identification signal IMWR_FLAG; the third NOR gate 1437, the first input end of the third NOR gate 1437 is electrically connected to the output end of the second NOR gate 1436, the second input end of the third NOR gate 1437 is electrically connected to the output end of the first NOR gate 1432, and the output end of the third NOR gate 1437 is used to output the internal write signal IWR.

[0117] It should be noted that the delay time of the delay unit 1434 for the input signal is equal to the pulse width of the internal read signal IRD and the internal write signal IWR. Here, the delay time, the pulse width of the internal write signal IWR and the pulse width of the internal read signal IRD are all 2ns for illustration; in some embodiments, the delay time of the delay unit 1434 may also be adjustable. Specifically, the delay time of the delay unit 1434 may be adjusted according to the timing requirements of the internal read-modify-write operation, that is, to ensure that within the pulse width time of the internal read signal IRD, the error correction circuit 16 can complete the reading, error detection and error correction operations on the storage data of the target storage unit of the storage array 15, and within the pulse width time of the internal write signal IWR, the error correction circuit 16 can write the correction data after error detection and correction into the target storage unit of the storage array 15; in some embodiments, the pulse width of the internal write signal IWR and the pulse width of the internal read signal IRD may also be different, which is not limited here.

[0118] In some embodiments, Fig.13 As shown, the storage array control circuit 141 also includes: a self-refresh control circuit 147, which is configured to receive an operation identification signal IMWR_FLAG and a self-refresh address SREF_Row, and when the operation identification signal IMWR_FLAG flips to an invalid level, controls the corresponding storage array 15 to perform a refresh operation according to the self-refresh address SREF_Row.

[0119] In some embodiments, Fig.15 As shown, the error correction circuit 16 is also configured to generate and output an error identification signal Error flag when an internal read-modify-write operation is performed on the target storage unit if there is an error in the storage data RD_Data in the target storage unit; the internal error checking circuit 10 also includes: an error register 17, configured to receive an internal error checking address IMWR_AD and an error identification signal Error flag, and store the internal error checking address IMWR_AD in response to the error identification signal Error flag.

[0120] It should be noted that the error register 17 can be a mode register reserved in the memory, and the internal error check address IMWR_AD is stored according to the error identification signal Error flag. The memory can perform various repair operations based on the stored error information, or the stored error information can be regularly provided to the memory controller. The memory controller can perform redundant repair processing based on the error signal, or skip the storage address where the data error occurs when performing the next read and write operation, thereby protecting the accuracy of the data and providing stability of the storage system.

[0121] In another embodiment of the present disclosure, see Fig.16 , which shows a schematic diagram of the composition structure of a memory 20 provided by an embodiment of the present disclosure. Fig.16 As shown, the memory 20 may include the internal error checking circuit 10 of any of the aforementioned embodiments.

[0122] In some embodiments, the memory 20 may include DRAM.

[0123] It should be noted that the disclosed embodiment introduces an internal error checking circuit design in the DRAM LPDDR series chips and the DRAM DDR4 chips, realizing a new function similar to the ECS operation in DDR5, and the memory error checking circuit 10 reuses the original clock generation circuit for self-refresh operation, the operation circuit and path for executing external read-modify-write commands, and will not affect the timing of the original self-refresh operation and external read-modify-write operation. Moreover, only simple improvements need to be made to the original internal command generation circuit, the address generation circuit and the control logic circuit to realize regular data error detection / correction operations on multiple storage arrays. On the premise of realizing the internal error checking mechanism to effectively improve the stability of stored data, the circuit design is optimized and the circuit area of ​​the DRAM chip is saved.

[0124] In the embodiments of the present disclosure, for DRAM, it can not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, DDR6, etc., but also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6, etc., without any limitation here.

[0125] In the embodiment of the present disclosure, the memory 20 includes the internal error checking circuit 10 of any of the aforementioned embodiments, thereby being able to implement an internal error checking operation on the memory, thereby improving the performance of the memory.

[0126] The above description is merely an exemplary embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0127] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0128] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0129] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0130] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An internal error checking circuit comprising: Clock generation circuit, internal command generation circuit, address generation circuit, control logic circuit and error correction circuit; The clock generation circuit is configured to generate and output a self-refresh clock signal in response to a self-refresh enable signal; The internal command generation circuit is configured to receive the self-refresh clock signal and the error check enable signal, count the self-refresh clock signal when the error check enable signal indicates that the internal error check function is turned on, and generate and output an internal error check command signal when the count value of the self-refresh clock signal is a first preset value; The address generation circuit is configured to receive the internal error check command signal, and counting the row address and the column address of the storage array according to the internal error check command signal to generate and output an internal error check address; The control logic circuit is configured to receive the internal error check command signal and the internal error check address, and in response to the internal error check command signal, control the error correction circuit to sequentially perform an internal read-modify-write operation on target storage cells corresponding to the internal error check address in a plurality of storage arrays; Wherein, the multiple storage arrays share the error correction circuit.

2. The internal error checking circuit as claimed in claim 1, wherein: The control logic circuit includes a plurality of storage array control circuits, and the plurality of storage array control circuits correspond one-to-one to the plurality of storage arrays; Each of the storage array control circuits is configured to receive the internal error check command signal and the internal error check address, sequentially generate a plurality of groups of internal signals in response to the internal error check command signal, and control the error correction circuit to perform an internal read-modify-write operation on the target storage unit in the corresponding storage array according to the corresponding group of internal signals when the corresponding storage array is in an enabled state; Each group of internal signals includes an internal read signal and an internal write signal.

3. The internal error checking circuit as claimed in claim 2, wherein: The error correction circuit is configured to read storage data from the target storage unit according to the internal read signal, and perform error detection and error correction on the storage data to generate correction data; The error correction circuit is further configured to write the correction data into the target storage unit according to an internal write signal.

4. The internal error checking circuit as claimed in claim 1, wherein: The internal command generation circuit is further configured to generate and output an internal self-refresh command signal in response to each pulse on the self-refresh clock signal when the error check enable signal indicates that the internal error check function is not enabled; And when the error check enable signal indicates that the internal error check function is turned on and the count value of the self-refresh clock signal is not a first preset value, an internal self-refresh command signal is generated and output.

5. The internal error checking circuit as claimed in claim 1, wherein: The control logic circuit is further configured to control a self-refresh operation to be performed on all storage arrays after controlling the error correction circuit to sequentially perform an internal read-modify-write operation on target storage cells corresponding to the internal error check addresses in multiple storage arrays.

6. The internal error checking circuit as claimed in claim 2, wherein: The address generation circuit includes a column address generation circuit, a first decoding circuit and a row address generation circuit; The column address generation circuit is configured to receive the internal error check command signal, perform column counting on the current storage row according to the internal error check command signal, and generate and output a target column address; The first decoding circuit is configured to decode the target column address, and generate and output a column end signal when the target column address indicates that the column count of the current storage row is completed; The row address generation circuit is configured to receive the column end signal and the internal error check command signal, count rows of the storage array according to the column end signal, and generate and output a target row address signal.

7. The internal error checking circuit as claimed in claim 6, wherein: The row address generation circuit comprises: A row counting circuit configured to receive the column end signal, count rows of the storage array according to the column end signal, and generate and output a row count value; The row address sampling circuit is configured to receive the internal error check command signal and the row count value, and to sample the row count value in response to the internal error check command signal to generate and output the target row address signal.

8. The internal error checking circuit of claim 4, wherein: The address generation circuit further includes a refresh address generation circuit configured to receive the internal self-refresh command signal, count rows of the storage array according to the internal self-refresh command signal, and generate and output a self-refresh address; The control logic circuit is further configured to perform a refresh operation on all storage arrays based on the self-refresh address control.

9. The internal error checking circuit as claimed in claim 6, wherein: The column address generation circuit includes N cascaded first flip-flops, where N is an integer greater than or equal to 1; the clock control terminal of the first flip-flop of the first stage serves as the input terminal of the column address generation circuit to receive the internal error check command signal; the inverting output terminal of the first flip-flop of each stage is connected to its own data input terminal; the clock control terminals of the other first flip-flops except the first flip-flop of the first stage are all connected to the inverting output terminal of the first flip-flop of the previous stage; the positive output terminals of the N first flip-flops jointly output the target column address; The first decoding circuit includes a first NAND gate, N input terminals of the first NAND gate are respectively connected to the positive phase output terminals of the N first flip-flops, and the output terminal of the first NAND gate is used to output the column end signal.

10. The internal error checking circuit as claimed in claim 7, wherein: The row counting circuit comprises M cascaded second flip-flops, where M is an integer greater than or equal to 1; the clock control terminal of the first-stage second flip-flop serves as the input terminal of the row counting circuit to receive the column end signal; the inverting output terminal of each stage of the second flip-flop is connected to its own data input terminal; the clock control terminals of the other second flip-flops except the first-stage second flip-flop are all connected to the inverting output terminal of the previous stage of the second flip-flop; the positive output terminals of the M second flip-flops jointly output the row count value; The row address sampling circuit includes M third triggers; the clock control end of each of the third triggers receives the internal error check command signal; the data input ends of the M third triggers are connected one-to-one with the positive phase output ends of the M second triggers to receive the row count value; the positive phase output ends of the M third triggers jointly output the target row address.

11. The internal error checking circuit of claim 2, wherein: The storage array control circuit comprises: an identification signal generating circuit configured to receive the internal error check command signal and, in response to the internal error check command signal, generate and output an operation identification signal at a valid level; a read / write command generation circuit configured to receive the operation identification signal and the internal error check command signal, and in response to the internal error check command signal, sequentially generate a plurality of sets of internal signals during a period when the operation identification signal is at an effective level; The identification signal generating circuit is further configured to receive the internal write signal and set the operation identification signal to an invalid level when the count value of the internal write signal reaches a second preset value.

12. The internal error checking circuit of claim 11, wherein: The identification signal generating circuit comprises: A command counting circuit configured to count the inverted signal of the internal write signal to generate and output a count value of the internal write signal; A second decoding circuit is configured to receive a count value of the internal write signal, and generate and output an operation end signal when the count value of the internal write signal is a second preset value; The SR trigger is configured to receive the internal error check command signal and the operation end signal, and in response to the internal error check command signal, set the operation identification signal to a valid level, and when the count value of the internal write signal reaches a second preset value, set the operation identification signal to an invalid level.

13. The internal error checking circuit of claim 11, wherein: The read / write command generation circuit comprises: a second NAND gate, wherein a first input terminal of the second NAND gate receives the operation identification signal, and a second input terminal of the second NAND gate receives the internal error check command signal; a first NOR gate, wherein a first input terminal of the first NOR gate is electrically connected to an output terminal of the second NAND gate, and an output terminal of the first NOR gate is used to output the internal read signal; a second NOR gate, wherein a first input terminal of the second NOR gate is electrically connected to an output terminal of the first NOR gate, and an output terminal of the second NOR gate is electrically connected to a second input terminal of the first NOR gate; A delay unit, wherein an input terminal of the delay unit is electrically connected to an output terminal of the first NOR gate; a first NOT gate, wherein an input terminal of the first NOT gate is electrically connected to an output terminal of the delay unit, and an output terminal of the first NOT gate is electrically connected to a second input terminal of the second NOR gate; a second NOT gate, wherein an input end of the second NOT gate receives the operation identification signal; A third NOR gate, wherein the first input terminal of the third NOR gate is electrically connected to the output terminal of the second NOR gate, the second input terminal of the third NOR gate is electrically connected to the output terminal of the first NOR gate, and the output terminal of the third NOR gate is used to output the internal write signal.

14. The internal error checking circuit of claim 11, wherein: The storage array control circuit also includes: The self-refresh control circuit is configured to receive the operation identification signal and the self-refresh address, and when the operation identification signal flips to an invalid level, control the corresponding storage array to perform a refresh operation according to the self-refresh address.

15. The internal error checking circuit of claim 1, wherein: The error correction circuit is further configured to generate and output an error identification signal when an internal read-modify-write operation is performed on the target storage unit if there is an error in the storage data in the target storage unit; The internal error checking circuit further includes an error register configured to receive the internal error checking address and the error identification signal, and store the internal error checking address in response to the error identification signal.

16. A memory, characterized in that: The memory comprises an internal error checking circuit as claimed in any one of claims 1 to 15.

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