Transistor with top gate structure, method of manufacturing the same and electronic device

Abstract

The application relates to the field of electronic devices, in particular to a transistor with a top gate structure and a preparation method thereof and an electronic device. The preparation method comprises the following steps: providing a substrate with a two-dimensional material layer on the surface; forming a patterned source electrode and a patterned drain electrode on the two-dimensional material layer; sequentially forming a buffer layer and a seed layer on the two-dimensional material layer in the region between the source electrode and the drain electrode; removing the buffer layer to realize stress-free and damage-free contact between the two-dimensional material layer and the seed layer; sequentially forming a dielectric layer and a top gate on the seed layer to obtain the transistor with the top gate structure. The method realizes stress-free and damage-free integration of the two-dimensional material and the high-dielectric-constant dielectric, reduces the two-dimensional material-dielectric interface state density, and guarantees good gate control performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic devices, and particularly relates to a transistor with a top gate structure, a preparation method thereof and an electronic device. BACKGROUND

[0002] Integration of high-k dielectric and two-dimensional material is an important step to build top gate structure of two-dimensional material transistor and other electronic devices. On the one hand, due to the absence of dangling bonds on the surface of two-dimensional material, it is difficult to achieve uniform deposition of high-k dielectric by traditional atomic layer deposition (ALD) technology. On the other hand, two-dimensional material has only atomic thickness, and it is necessary to minimize the stress and damage of two-dimensional material caused by dielectric integration process, so as to reduce the interface state density of two-dimensional material-dielectric and achieve good gate control performance.

[0003] The existing integration process of high-k dielectric and two-dimensional material has the following several kinds: (1) a seed layer of about 1 nm thickness of Al, Ta and other metals is pre-deposited, then it is oxidized, and then high-k top gate dielectric such as Al2O3, HfO2 is deposited by atomic layer deposition technology (High Current Density in Monolayer MoS2 Doped by AlO xACS nano, 2021, 15(1): 1587-1596. DOI: 10.1021 / acsnano.0c09078). This method may introduce stress and damage on the two-dimensional material when depositing metal seed layers such as Al, Ta, etc., and introduce more interface states at the two-dimensional material-dielectric interface, making it difficult to achieve good gate control performance. (2) A seed layer of about 1 nm thick Sb2O3, PTCA, etc. is pre-deposited, and then Al2O3, HfO2, etc. high-k top gate dielectric is deposited by atomic layer deposition technology (Scalable integration of hybrid high-κ dielectric materials on two-dimensional semiconductors. Nature Materials, 2023, 22(9): 1078-1084. DOI: 10.1038 / s41563-023-01626-w). This method has problems in thermal stability due to the low volatilization temperature of Sb2O3, PTCA, etc. molecules, and the dielectric constant of these molecules is not high, which will reduce the equivalent oxide thickness (EOT) of the transistor. (3) Al2O3, HfO2, etc. high-k top gate dielectric is transferred to the two-dimensional material by mechanical transfer (The splanchnic mesenchyme is the tissue of origin for pancreatic fibroblasts during homeostasis and tumorigenesis. Nature Communications, 2023, 14(1): 2340. DOI: 10.1038 / s41467-022-34464-6); or HfS2, TaS2, etc. two-dimensional Hf-based and Ta-based materials are transferred to the two-dimensional material by mechanical transfer, and are converted into HfO2, Ta2O3, etc. high-k dielectric by further oxidation (Oxidation of tantalum disulfide (TaS2) films for gate dielectric and process design of two-dimensional field-effect device. Nanotechnology, 2022, 33(37): 375204. DOI: 10.1088 / 1361-6528 / ac75f9). This method needs to realize the integration of high-k dielectric and two-dimensional material by mechanical transfer, which has problems in device uniformity, etc.

[0004] In summary, there are many problems in the integration of high dielectric constant dielectric and two-dimensional material in existing two-dimensional material transistor and other electronic devices, which need to be improved and developed. SUMMARY

[0005] In view of the deficiencies of the prior art described above, the purpose of the present application is to provide a transistor with a top gate structure and a preparation method thereof and an electronic device, aiming to solve the problem that the existing method will introduce stress and damage to the two-dimensional material when depositing a metal seed layer.

[0006] Specifically, the technical solutions of the present application are as follows:

[0007] In a first aspect of the present application, a preparation method of a transistor with a top gate structure is provided, which comprises the following steps:

[0008] providing a substrate with a two-dimensional material layer on the surface;

[0009] forming a patterned source electrode and a drain electrode on the two-dimensional material layer;

[0010] forming a buffer layer and a seed layer on the two-dimensional material layer in the region between the source electrode and the drain electrode in sequence;

[0011] removing the buffer layer to achieve stress-free and damage-free contact between the two-dimensional material layer and the seed layer;

[0012] forming a dielectric layer and a top gate electrode on the seed layer in sequence to obtain the transistor with a top gate structure.

[0013] In a second aspect of the present application, a transistor with a top gate structure prepared by the preparation method of the present application is provided.

[0014] In a third aspect of the present application, an electronic device comprising the transistor with a top gate structure of the present application is provided.

[0015] Beneficial effects: First, the method of the present application can reduce the stress and damage to the two-dimensional material during the deposition of the seed layer by introducing a buffer layer. After removing the buffer layer, stress-free and damage-free contact can be achieved between the two-dimensional material layer and the seed layer. Subsequently, the deposition of the dielectric layer is realized, achieving stress-free and damage-free integration of the two-dimensional material and the high dielectric constant dielectric, reducing the interface state density of the two-dimensional material-dielectric, and ensuring the gate control performance of the device. Second, the method of the present application can realize stress-free and damage-free integration of the two-dimensional material and the high dielectric constant dielectric without mechanical transfer, avoiding bubbles, impurity contamination, etc. during the mechanical transfer process, achieving large-scale uniformity; and without the need to introduce low-volatility temperature, low-dielectric constant Sb2O3, PTCA, etc. seed layer, thus having high thermal stability, and also not reducing the dielectric constant of the top gate structure, further ensuring the gate control performance of the device. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the fabrication process of the transistor with a top-gate structure provided by the present invention.

[0017] Figure 2 This is a schematic diagram of the fabrication process of the transistor with a top-gate structure provided by the present invention.

[0018] Figure 3 This is a schematic diagram of the fabrication of the bottom electrode (source and drain) in Example 1.

[0019] Figure 4 This is a schematic diagram of the preparation of the buffer layer and seed layer in Example 1.

[0020] Figure 5 This is a schematic diagram of the fabrication of the top gate in Example 1.

[0021] Figure 6 The curves show the transfer characteristics of device A in its initial state, the MoS2 transistor in Example 1, device B in its initial state, and the MoS2 transistor in Comparative Example 1.

[0022] Figure 7 The image shows the Raman spectra of MoS2 in the MoS2 transistors prepared in Example 1 and Comparative Example 1. Detailed Implementation

[0023] This invention provides a transistor with a top-gate structure, a method for fabricating the same, and an electronic device. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention is further described in detail below. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0024] The basic idea of ​​this invention is as follows: (1) First, a buffer layer is deposited on the surface of the two-dimensional material layer. The material of the buffer layer has a low melting point and vaporization temperature, so it will not damage the two-dimensional material during the deposition process and can be removed by a simple annealing process later; (2) A metal seed layer is deposited on the buffer layer. The presence of the buffer layer avoids stress and damage to the surface of the two-dimensional material during the deposition process of the metal seed layer; (3) The buffer layer is removed by an annealing process at a low temperature to achieve stress-free and damage-free contact between the two-dimensional material layer and the seed layer; (4) A high dielectric constant dielectric material is deposited by ALD (atomic layer deposition) and other technologies to form a dielectric layer, thereby achieving stress-free and damage-free integration of the two-dimensional material and the high dielectric constant dielectric.

[0025] According to an embodiment of the present invention, a method for fabricating a transistor having a top-gate structure is provided, comprising the steps of:

[0026] S1, providing a substrate with a two-dimensional material layer on a surface thereof;

[0027] S2, forming a patterned source electrode and a patterned drain electrode on the two-dimensional material layer;

[0028] S3, sequentially forming a buffer layer and a seed layer on the two-dimensional material layer in a region between the source electrode and the drain electrode;

[0029] S4, removing the buffer layer so that the two-dimensional material layer and the seed layer are in stress-free and damage-free contact;

[0030] S5, sequentially forming a dielectric layer and a top gate on the seed layer to obtain the transistor with a top gate structure.

[0031] In the embodiment, a buffer layer is first deposited on the surface of the two-dimensional material layer, and then a metal seed layer is deposited on the buffer layer. The buffer layer avoids stress and damage to the surface of the two-dimensional material during the deposition of the metal seed layer. Moreover, the material of the buffer layer has a low melting point and a low vaporization temperature, so that the two-dimensional material is not damaged during the deposition, and the buffer layer can be removed by an annealing process at a low temperature, so that the two-dimensional material and the seed layer are in stress-free and damage-free contact. Then, a high dielectric constant dielectric is deposited, so that the two-dimensional material and the high dielectric constant dielectric are integrated in stress-free and damage-free manner, the interface state density of the two-dimensional material-dielectric is reduced, and the gate control performance of the device is ensured.

[0032] The material of the seed layer is selected from aluminum oxide (Al2O3), tantalum oxide (Ta2O5), hafnium oxide (HfO2), magnesium oxide (MgO), and yttrium oxide (Y2O3) in the embodiment, so that the use of Sb2O3, PTCA and other materials with low volatilization temperature and low dielectric constant is avoided. Therefore, the seed layer has high thermal stability, the dielectric constant of the top gate is not reduced, and the gate control performance of the device is further ensured. In the embodiment, the seed layer is selected from insulating materials with large band gap, high dielectric constant, and high thermal stability. These characteristics help to achieve good transistor gate control performance and good thermal stability.

[0033] In step S1, in an embodiment, the material of the two-dimensional material layer can be selected from the two-dimensional materials commonly used in the prior art, and preferably is MoS2, WSe2, WS2, or the like, but is not limited thereto.

[0034] In the present application, the two-dimensional material layer can be transferred onto a substrate or directly grown on the surface of the substrate. Both the transfer and direct growth of the two-dimensional material are conventional techniques in the art, which are not limited herein. For example, the transfer of the two-dimensional material can use a mechanical exfoliation method to exfoliate and transfer a two-dimensional material (MoS2, WSe2, WS2) layer on a substrate; or use a mechanical transfer method to transfer a single-layer two-dimensional material grown by chemical vapor deposition (CVD) on a substrate.

[0035] In step S2, in an embodiment, the step of forming a patterned source electrode and a drain electrode on the two-dimensional material layer specifically comprises:

[0036] S11, applying photoresist on the two-dimensional material layer, and using a photolithography process to pattern the two-dimensional material layer;

[0037] S12, evaporating electrode material, removing the photoresist, and forming a patterned source electrode and a drain electrode.

[0038] In the present application, photoresist and a photolithography process can be used to make a photolithography pattern at a specific position of the substrate with a two-dimensional material layer according to specific needs. The specific shape of the photolithography pattern can be set according to actual needs, and the specific shape is not limited herein. After evaporating the electrode material, the photoresist on the two-dimensional material layer needs to be removed to form a predetermined patterned source electrode and a drain electrode. Using photoresist and a photolithography process to pattern the two-dimensional material layer, and subsequently removing the photoresist are conventional techniques in the art, which are not limited herein.

[0039] In step S11, in an embodiment, the photoresist is applied on the two-dimensional material layer using a spin coating method, and then the substrate is pre-baked. A laser direct writing photolithography machine is used to expose a preset electrode pattern on the substrate. After development, a patterned substrate is obtained.

[0040] In step S12, in an embodiment, the electrode material can be a metal material used to form a source electrode and a drain electrode. In the present application, Bi material and Au material are used.

[0041] In an embodiment, the photoresist can be removed by soaking in acetone to obtain a substrate with a patterned source electrode and a drain electrode.

[0042] In step S3, in an embodiment, the material of the buffer layer is selenium material or tellurium material. Both selenium material and tellurium material have a relatively low melting point and vaporization temperature, and will not cause stress and damage to the two-dimensional material during deposition. Subsequently, the buffer layer can be removed by an annealing process at a relatively low temperature.

[0043] In an embodiment, the material of the seed layer is an aluminum oxide material, a tantalum oxide material, a hafnium oxide material, a magnesium oxide material, or a yttrium oxide material. Preferably, the material of the seed layer is an aluminum oxide material or a tantalum oxide material.

[0044] In an embodiment, the step of sequentially forming the buffer layer and the seed layer on the two-dimensional material layer in the region between the source and the drain specifically comprises:

[0045] Applying photoresist on the two-dimensional material layer, the source, and the drain, and performing a photoetching process on the two-dimensional material layer to patternize the two-dimensional material layer;

[0046] Sequentially evaporating the buffer layer and the seed layer, and removing the photoresist, so that the buffer layer and the seed layer are sequentially formed on the two-dimensional material layer in the region between the source and the drain.

[0047] In this embodiment, the two-dimensional material layer is also subjected to a preset patternization process using photoresist and a photoetching process, and then the buffer layer and the seed layer are sequentially evaporated, and then the photoresist is removed, so that the buffer layer and the seed layer are sequentially formed on the two-dimensional material layer in the region between the source and the drain (the buffer layer and the seed layer are not formed on the source and the drain).

[0048] In step S4, in an embodiment, the buffer layer is removed by an annealing process.

[0049] In an embodiment, the annealing process can be a vacuum annealing process or an atmosphere annealing process. The annealing process can be selected according to the material of the buffer layer. The annealing temperature can be adjusted according to the melting point of the material of the buffer layer, which is generally slightly lower than the melting point of the material of the buffer layer. The annealing time can be determined according to the thickness of the buffer layer.

[0050] In a preferred embodiment, when a vacuum annealing process is used, the vacuum degree used is less than or equal to 1x10 -1 Pa, and the annealing time is 0.5h-24h; for example, the annealing time can be 0.5h, 1h, 2h, 3h, 4h, 5h, 6h, 7h, 8h, 9h, 10h, 15h, 20h, 24h, etc.

[0051] In a preferred embodiment, when an atmosphere annealing process is used, the gas used is one or more of hydrogen, argon, and nitrogen, the annealing temperature is 50℃-1000℃, and the annealing time is 0.5h-24h.

[0052] In a more preferred embodiment, when the atmosphere annealing process is adopted, the gas used is a mixture of argon and hydrogen, the annealing temperature is 50-500℃, and the annealing time is 0.5-12h. The ratio of argon and hydrogen can be 95:5, the annealing temperature can be 50℃, 100℃, 150℃, 200℃, 250℃, 300℃, 350℃, 400℃, 450℃, 500℃, etc., and the annealing time can be 0.5h, 1h, 2h, 3h, 4h, 5h, 6h, 7h, 8h, 9h, 10h, 11h, 12h, etc.

[0053] In the embodiments of the present application, the buffer layer is removed by the annealing process, so that the two-dimensional material layer and the seed layer achieve stress-free and damage-free contact, avoiding the problem of damage to the surface of the two-dimensional material and stress caused by directly depositing the seed layer on the two-dimensional material.

[0054] In an embodiment, the thickness of the buffer layer is 5-100nm, for example, it can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, etc. Within this thickness range, the buffer layer material can be well removed in the subsequent annealing process, without affecting the electrical properties of the two-dimensional material.

[0055] In an embodiment, the thickness of the seed layer is 0.2-5nm, for example, it can be 0.2nm, 0.5nm, 1nm, 1.5nm, 2nm, 2.5nm, 3nm, 3.5nm, 4nm, 4.5nm, 5nm, etc. Within this thickness range, the seed layer can be rapidly oxidized in an air environment without the need for additional steps, and in addition, the dielectric constant of the seed layer and the dielectric layer as a whole can remain at a relatively high level, without affecting the voltage regulation ability of the gate.

[0056] In step S5, in an embodiment, the material of the dielectric layer is selected from materials with high dielectric constant, such as HfO2, Al2O3, Ta2O5, etc., but is not limited thereto.

[0057] In an embodiment, the thickness of the dielectric layer is 1-50nm, for example, it can be 1nm, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, etc.

[0058] In an embodiment, the dielectric layer and the top gate are sequentially formed on the seed layer, which are conventional techniques in the art and are not limited herein.

[0059] In a preferred embodiment, the material of the two-dimensional material layer in the transistor with top gate structure is MoS2, the material of the buffer layer is Se, the material of the seed layer is Al2O3, and the material of the dielectric layer is HfO2. The transistor prepared by using these materials has no serious doping effect, and the electrical properties before and after the deposition of the dielectric layer are well maintained, and the subthreshold swing is small.

[0060] In the present application, each layer of the transistor with top gate structure can be prepared by using a method including a magnetron sputtering technique, a thermal evaporation technique, an electron beam evaporation technique, or a vacuum arc evaporation technique, etc. The related film coating techniques are conventional techniques in the field, and are not limited herein.

[0061] According to an embodiment of the present application, a transistor with top gate structure prepared by using the preparation method of the present application is provided.

[0062] According to an embodiment of the present application, an electronic device including the transistor with top gate structure of the present application is provided.

[0063] In combination Figure 1 and Figure 2 As shown in the present application, a preparation method of a transistor with top gate structure includes:

[0064] A substrate with a two-dimensional material layer 1 on the surface is provided, a patterned metal electrode is formed as a source electrode 2 and a drain electrode 3 by using an electron beam evaporation, a photolithography process, etc., and then a buffer layer material is deposited on the two-dimensional material channel (in the region between the source electrode 2 and the drain electrode 3) to form a buffer layer 4. Then a seed layer 5 is deposited on the buffer layer 4, and then the buffer layer 4 is removed by vacuum annealing or atmosphere annealing. A high dielectric constant dielectric is deposited by using an atomic layer deposition technique to form a dielectric layer 6, and finally a patterned metal electrode is deposited as a top gate 7, thereby obtaining the transistor with top gate structure of the present application.

[0065] The present application will be further described below by means of specific examples.

[0066] Example 1

[0067] The present embodiment provides a preparation method of a MoS2 transistor with top gate structure, which is specifically as follows:

[0068] Step one, substrate cleaning: the SiO2 / Si (300 nm SiO2) substrate is ultrasonically cleaned with acetone, isopropyl alcohol, and deionized water, respectively, and the cleaning time is 7 min. After blowing dry with a nitrogen gun, Ar plasma cleaning is performed.

[0069] Step two, two-dimensional material transfer: the mechanical exfoliation method is used to exfoliate and transfer a MoS2 two-dimensional material layer 11 on the substrate.

[0070] Step 3: Fabrication of the bottom electrodes (source and drain): On a substrate with a MoS2 two-dimensional material layer 11, a 1 μm thick photoresist 12 is spin-coated. The substrate is pre-baked, and the preset electrode pattern is exposed on the substrate using a laser direct-write lithography machine. After development, a patterned substrate with a MoS2 two-dimensional material layer is obtained. Electron beam evaporation deposition is used to coat the substrate at a thickness of less than 10 μm. -4 At a vacuum of Pa, Electrode materials Bi and Au were deposited at different rates, with thicknesses of 40 nm and 20 nm, respectively. Then, the photoresist was removed by immersion in acetone, forming patterned source 13 and drain 14 on the MoS2 substrate. Figure 3 This is a schematic diagram of the fabrication of the bottom electrode (source and drain).

[0071] Step 4: Preparation of the buffer layer and seed layer: On the substrate after the above steps, two photolithography processes are performed. A 1μm thick photoresist 21 is applied using spin coating. The substrate is pre-baked, and a preset electrode pattern is exposed on the substrate using a laser direct-write lithography machine. After development, a patterned substrate with a two-dimensional material layer is obtained. On the above substrate, a 1μm thick photoresist 22 is applied using spin coating. The substrate is pre-baked to evaporate the solvent in the photoresist, and the film dries and sets. A preset pattern is exposed on the substrate using a laser direct-write lithography machine, and after development, a patterned substrate is obtained. Then, an electron beam evaporation coating machine is used to coat the substrate at a depth of less than 10 μm. -4 At a vacuum of Pa, The buffer layer material, selenium (Se), was deposited at a rate of 5 nm to form a buffer layer 23. Subsequent deposition was also carried out at a rate less than 10 nm. -4 At a vacuum of Pa, Al material was deposited at a rate of 1 nm. It was then naturally oxidized in air to form aluminum oxide, creating a seed layer 24. The photoresist was then removed by immersion in acetone, resulting in a channel pattern with a buffer layer 23 and a seed layer 24. Figure 4 This is a schematic diagram of the preparation of the buffer layer and the seed layer.

[0072] Step 5: Annealing to remove the buffer layer: Place the substrate obtained in the above steps in an annealing furnace and introduce an argon-hydrogen mixed gas (Ar:H2 = 95:5) at a gas flow rate of 100 standard cubic centimeters per minute (sccm). The annealing temperature is 150℃ and the annealing time is 3 hours. Remove the buffer layer 23 to ensure that there is no stress and no damage between the two-dimensional material layer 11 and the seed layer 24.

[0073] Step six, deposition of HfO2 high dielectric constant dielectric layer: HfO2 high dielectric constant dielectric layer 25 is deposited by atomic layer deposition technology, wherein TEMAH (tetra (methyl ethyl amino) hafnium) is used as Hf precursor, the source bottle temperature is 120°C, the reaction is carried out with water, the chamber temperature is 140°C, 100 cycles are carried out, and 10 nm of HfO2 high dielectric constant dielectric layer 25 is obtained.

[0074] Step seven, preparation of top gate Figure 5 is a schematic diagram of the preparation of the top gate): on the substrate obtained after the above steps, a photoresist 31 with a thickness of 1 μm is coated by spin coating, the substrate is pre-baked, and the substrate is exposed to a preset electrode pattern by a laser direct writing photoetching machine. After development, a patterned substrate is obtained. An electron beam evaporation coating machine is used to evaporate the electrode materials Bi and Au at a vacuum degree of less than 10 -4 Pa at a rate of 40 nm and 20 nm, respectively, to form a top gate 32. Then, the photoresist is removed by soaking in acetone, and a MoS2 transistor with a top gate structure is formed.

[0075] Comparative example 1

[0076] The preparation method is the same as that of example 1, and the only difference is that in step four, the seed layer is deposited directly on the two-dimensional material layer without depositing the buffer layer, and finally a comparative MoS2 transistor with a top gate structure is prepared.

[0077] The device containing the source and the drain prepared by steps one to three in example 1 is defined as device A, and the transfer characteristic curve of device A in the initial state is tested. Then, a MoS2 transistor with a top gate structure is prepared on device A according to the method of depositing a buffer layer first and then depositing a seed layer in example 1, and the transfer characteristic curve of the MoS2 transistor in example 1 is tested. Similarly, the device containing the source and the drain prepared by steps one to three in comparative example 1 is defined as device B, and the transfer characteristic curve of device B in the initial state is tested. Then, a comparative MoS2 transistor with a top gate structure is prepared on device B according to the method of depositing a seed layer directly on the two-dimensional material layer without depositing a buffer layer in comparative example 1, and the transfer characteristic curve of the MoS2 transistor in comparative example 1 is tested.

[0078] Figure 6 is the transfer characteristic curve of device A in the initial state, the MoS2 transistor in example 1, device B in the initial state, and the MoS2 transistor in comparative example 1, according to Figure 6It can be seen that the threshold voltage of device A and device B is similar to the initial state, about -40V. The threshold voltage of MoS2 transistor of comparative example 1 by directly depositing a seed layer on the two-dimensional material layer is seriously left shifted, and the leakage current is also increased by one order of magnitude (from 10 -12 order to 10 -11 order), while the performance of MoS2 transistor of example 1 by first depositing a buffer layer and then depositing a seed layer does not decrease significantly, and the leakage current remains at 10 -12 order before and after the process.

[0079] Figure 7 is the Raman spectrum of MoS2 in the MoS2 transistor prepared in example 1 and comparative example 1, according to Figure 7 It can be seen that, compared with the initial state of MoS2, the seed layer of comparative example 1 is directly deposited on the two-dimensional material layer, the half peak width of the characteristic peak A 1g of MoS2 is increased, which indicates that the lattice structure of the two-dimensional material surface is destroyed, and the two-dimensional semiconductor material at the channel is n-doped. The method of example 1 is to first deposit a buffer layer and then deposit a seed layer on the buffer layer, and the characteristic peak of MoS2 remains unchanged before and after the process, indicating that the performance of the two-dimensional material remains unchanged.

[0080] Example 2

[0081] The preparation method of example 2 is the same as that of example 1, and the difference is only that the deposition of HfO2 high dielectric constant dielectric layer in step six is adjusted to the deposition of Al2O3 high dielectric constant dielectric layer, specifically: an Al2O3 high dielectric constant dielectric layer is deposited by atomic layer deposition technology, in which TMA (trimethylaluminum) is used as Al precursor, and reacts with water, the chamber temperature is 120℃, and 100 cycles are performed to obtain an Al2O3 high dielectric constant dielectric layer of 10nm. Finally, a MoS2 transistor with a top gate structure is prepared.

[0082] Example 3

[0083] The preparation method of example 3 is the same as that of example 1, and the difference is only that the evaporation of Al material in the seed layer in step four is adjusted to the evaporation of Ta material, specifically: the evaporation of Ta material is carried out at a vacuum degree of less than 10 -4 Pa at a rate of 0.1 nm. Then natural oxidation in air is carried out to generate tantalum oxide to form a seed layer. Finally, a MoS2 transistor with a top gate structure is prepared.

[0084] Example 4

[0085] The preparation method of Example 1 is adopted, with the difference that the method of transferring the two-dimensional material in Step One is adjusted to mechanical transfer, specifically: a single-layer MoS2 two-dimensional material layer grown by chemical vapor deposition (CVD) is transferred on a substrate by mechanical transfer. Finally, a MoS2 transistor with a top gate structure is prepared.

[0086] Example 5

[0087] The preparation method of Example 1 is adopted, with the difference that the evaporation thickness of Se material in the buffer layer in Step Four is adjusted to 20 nm, and the annealing time in Step Five is adjusted to 8 h. The adjusted steps are as follows: Se material is evaporated at a vacuum degree of less than 10 -4 Pa, at a rate of 20 nm. Then, the seed layer is prepared according to the method in Example 1, and then the substrate is placed in an annealing furnace, argon-hydrogen mixed gas (Ar:H2=95:5) is introduced at a gas flow rate of 100 standard cubic centimeters per minute (sccm), the annealing temperature is 150°C, and the annealing time is 8 h. The buffer layer is removed to enable stress-free and damage-free contact between the two-dimensional material layer and the seed layer. Finally, a MoS2 transistor with a top gate structure is prepared.

[0088] It should be understood that the application of the present application is not limited to the above examples, and those of ordinary skill in the art can make improvements or changes according to the above description, and all such improvements and changes shall fall within the scope of protection of the appended claims of the present application.

Claims

1. A method for fabricating a transistor having a top-gate structure, characterized by, The method comprises the steps of: providing a substrate with a two-dimensional material layer on a surface thereof; forming a patterned source electrode and a patterned drain electrode on the two-dimensional material layer; forming a buffer layer and a seed layer on the two-dimensional material layer in the region between the source electrode and the drain electrode in sequence; removing the buffer layer so that the two-dimensional material layer and the seed layer are in stress-free and damage-free contact; forming a dielectric layer and a top gate on the seed layer in sequence to obtain the transistor with a top gate structure; the material of the buffer layer is a selenium material or a tellurium material, and the material of the seed layer is an aluminum oxide material, a tantalum oxide material, a hafnium oxide material, a magnesium oxide material or a yttrium oxide material; the material of the dielectric layer is a hafnium oxide material, an aluminum oxide material or a tantalum oxide material; the buffer layer is removed through an annealing process.

2. The method of manufacturing a transistor having a top-gate structure according to claim 1, wherein The thickness of the buffer layer is 5 nm-100 nm, the thickness of the seed layer is 0.2 nm-5 nm, and the thickness of the dielectric layer is 1 nm-50 nm.

3. The method of manufacturing a transistor having a top-gate structure according to claim 1, wherein The annealing process is a vacuum annealing process or an atmosphere annealing process; when the vacuum annealing process is used, the vacuum degree used is less than or equal to 1x10 -1 Pa, and the annealing time is 0.5h-24h; when the atmosphere annealing process is used, the gas used is one or more of hydrogen, argon and nitrogen, the annealing temperature is 50℃-1000℃, and the annealing time is 0.5h-24h.

4. The method of manufacturing a transistor having a top-gate structure according to claim 1, wherein The step of forming the patterned source electrode and the patterned drain electrode on the two-dimensional material layer specifically comprises: applying photoresist on the two-dimensional material layer, and performing a photoetching process on the two-dimensional material layer to form the patterned source electrode and the patterned drain electrode; evaporating electrode material and removing the photoresist to form the patterned source electrode and the patterned drain electrode.

5. The method of manufacturing a transistor having a top-gate structure according to claim 1, wherein The step of forming the buffer layer and the seed layer on the two-dimensional material layer in the region between the source electrode and the drain electrode in sequence specifically comprises: applying photoresist on the two-dimensional material layer, the source electrode and the drain electrode, and performing a photoetching process on the two-dimensional material layer to form the patterned source electrode and the patterned drain electrode; evaporating the buffer layer and the seed layer in sequence, and removing the photoresist to form the buffer layer and the seed layer on the two-dimensional material layer in the region between the source electrode and the drain electrode.

6. A transistor with a top gate structure prepared by the method of any one of claims 1-5.

7. An electronic device, comprising: A transistor with a top gate structure as claimed in claim 6.

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