SOI (Silicon On Insulator) semiconductor structure of integrated longitudinal device and manufacturing method of SOI semiconductor structure

Abstract

The invention relates to an SOI semiconductor structure integrated with a longitudinal device and a manufacturing method thereof, and the method comprises the steps: obtaining a wafer which comprises a substrate, a buried dielectric region on the substrate, and a top semiconductor layer on the buried dielectric region; patterning the wafer to expose the substrate in the longitudinal device region; forming a first insulating isolation part on the side surface of the longitudinal device region; epitaxially forming a first conductive type region in the longitudinal device region; forming a CMOS device main body in the first device region through a CMOS process, and forming a first well region and a first source region in the longitudinal device region; the first well region is formed in the first conductive type region, and the first source region is formed in the first well region; a first drain region is formed at the bottom of the substrate. The depletion region of the second conduction type can optimize the electric field of the longitudinal device, so that the area of the depletion region is reduced, and the chip area is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, in particular to an SOI semiconductor structure integrating vertical devices, and also to a manufacturing method of the SOI semiconductor structure integrating vertical devices. Background Art

[0002] BCD (Bipolar-CMOS-DMOS) technology is a monolithic integration process technology that can produce Bipolar (bipolar transistors), CMOS (metal oxide semiconductor field effect transistors) and DMOS devices (double diffused metal oxide semiconductor field effect transistors) on the same chip. The devices prepared by this process combine the advantages of high transconductance and strong load driving capability of bipolar devices and high integration and low power consumption of CMOS; at the same time, DMOS can carry a larger voltage and has extremely low power consumption when working in switching mode, and can transfer high power to the load without expensive packaging and cooling systems. This technology has been widely used in automotive electronics, power management, lighting, and radio frequency communications. Among them, DMOS, which is responsible for the power part, is the core of this type of circuit. Because it needs to carry relatively large current and voltage, the area often occupies 30%-90% of the entire area, and is the key to the entire integrated circuit.

[0003] In the exemplary BCD process, DMOS uses lateral channel LDMOS (lateral double diffused metal oxide semiconductor field effect transistor). For LDMOS, the drift region needs to bear the withstand voltage, so for devices with higher withstand voltage requirements, the drift region needs to be long enough to bear the withstand voltage, and the size of the device is larger. Summary of the invention

[0004] Based on this, it is necessary to provide an SOI semiconductor structure with integrated vertical devices and a manufacturing method thereof.

[0005] A SOI semiconductor structure for integrating vertical devices, comprising: a substrate having a first conductivity type; a buried dielectric region, arranged on the substrate; a first conductivity type region, arranged in a region of the substrate without the buried dielectric region; a second conductivity type region, arranged on the buried dielectric region, wherein the first conductivity type and the second conductivity type are opposite conductivity types; a first device body, arranged on the buried dielectric region; a vertical device body, comprising a first well region, a first source region, a first drain region and a first gate, wherein the first well region has a second conductivity type and is arranged in the first conductivity type region, the first source region is arranged in the first well region, and the first drain region is arranged at the bottom of the substrate; an isolation structure, comprising a first insulating isolation portion and a depletion region, wherein the depletion region is located between the second conductivity type region and the first conductivity type region, the bottom of the first insulating isolation portion reaches the buried dielectric region, the depletion region and the first conductivity type region are separated by the first insulating isolation portion, the depletion region is located between the first insulating isolation portion and the second conductivity type region, and the depletion region has the second conductivity type.

[0006] The SOI semiconductor structure with integrated vertical devices integrates vertical devices with relatively small areas (for reference, the area of ​​VDMOS is smaller than that of LDMOS), so that devices with higher power density can be obtained. The isolation structure between the first device and the vertical device adopts a structure in which the depletion region of the second conductivity type cooperates with the first insulating isolation portion. The depletion region of the second conductivity type can optimize the electric field of the vertical device, thereby reducing the area of ​​the depletion region and reducing the chip area.

[0007] In one of the embodiments, the withstand voltage of the vertical device is greater than the withstand voltage of the first device.

[0008] In one embodiment, the vertical device is a high voltage device and the first device is a low voltage device.

[0009] In one embodiment, the isolation structure further includes a second insulating isolation portion, the depletion region is located between the first insulating isolation portion and the second insulating isolation portion, and the bottom of the second insulating isolation portion reaches the buried dielectric region.

[0010] In one embodiment, the first insulating isolation portion is disposed close to the first conductive type region, and the second insulating isolation portion is disposed close to the second conductive type region.

[0011] In one embodiment, the vertical device is a VDMOS device, the first source region and the first drain region have a first conductivity type, and the doping concentration of the first drain region is greater than the doping concentration of the substrate.

[0012] In one embodiment, the first device body is a body of a CMOS device, and the first device body includes: a CMOS well region having a second conductivity type, arranged above the buried dielectric region; a CMOS source region having a first conductivity type, arranged in the CMOS well region; a CMOS drain region having a first conductivity type, arranged in the CMOS well region; and a CMOS gate, arranged on the CMOS well region between the CMOS source region and the CMOS drain region.

[0013] In one embodiment, the CMOS source region, the CMOS drain region and the first source region are located at the same level in the SOI semiconductor structure.

[0014] In one embodiment, the second insulating isolation portion is a closed ring structure, surrounding the second conductive type region in a lateral direction.

[0015] In one embodiment, the first conductivity type is N type, and the second conductivity type is P type.

[0016] A method for manufacturing an SOI semiconductor structure with integrated vertical devices, comprising: obtaining a wafer, the wafer comprising a substrate, a buried dielectric region on the substrate, and a top semiconductor layer on the buried dielectric region; the substrate having a first conductivity type, the top semiconductor layer having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; patterning the wafer, removing the top semiconductor layer and the buried dielectric region of the vertical device region to expose the substrate of the vertical device region; forming a first insulating isolation portion on the side of the vertical device region; epitaxially forming a first conductivity type region in the vertical device region; forming a CMOS device body in the top semiconductor layer, a first well region and a first source region in the vertical device region by a CMOS process; the first well region is formed in the first conductivity type region, the first well region has the second conductivity type, and the first source region is formed in the first well region; in the top semiconductor layer, a portion between the first insulating isolation portion and the CMOS device body serves as a depletion region; and forming a first drain region at the bottom of the substrate.

[0017] The manufacturing method of the SOI semiconductor structure with integrated vertical devices can integrate relatively small vertical devices, thereby obtaining devices with higher power density. The second conductivity type depletion region can optimize the electric field of the vertical device, thereby reducing the area of ​​the depletion region and reducing the chip area.

[0018] In one embodiment, the step of patterning the wafer also includes forming an isolation trench, wherein the isolation trench separates the top semiconductor layer into a first device region and the depletion region, wherein the depletion region is located between the isolation trench and the first insulating isolation portion; the step of forming the first insulating isolation portion on the side of the vertical device region includes depositing an insulating dielectric material on the front side of the wafer, thereby filling the isolation trench with the insulating dielectric material to form a second insulating isolation portion, and forming the first insulating isolation portion on the side of the vertical device region; and forming a CMOS device body in the top semiconductor layer through a CMOS process is to form a CMOS device body in the first device region.

[0019] In one of the embodiments, in the step of obtaining a wafer, the obtained wafer also includes a dielectric layer on the top semiconductor layer; after the step of epitaxially forming a first conductive type region in the vertical device region and before forming the CMOS device body, it also includes a step of removing the dielectric layer.

[0020] In one embodiment, the critical dimension of the isolation trench is 0.8 to 2 microns.

[0021] In one of the embodiments, the step of forming a CMOS device body in the first device area through a CMOS process includes: forming a CMOS well area, a CMOS source area, a CMOS drain area and a CMOS gate through a CMOS process; the CMOS well area has a second conductivity type and is formed above the buried dielectric area, the CMOS source area and the CMOS drain area have a first conductivity type and are formed in the CMOS well area, and the CMOS gate is formed on the CMOS well area between the CMOS source area and the CMOS drain area; the first source area and the first drain area have a first conductivity type, and the doping concentration of the first drain area is greater than the doping concentration of the substrate.

[0022] In one of the embodiments, the wafer is patterned to remove the top semiconductor layer and the buried dielectric region of the vertical device region to expose the substrate of the vertical device region, and an isolation groove is formed at the same time, wherein the isolation groove separates the first device region from the vertical device region, and the top semiconductor layer between the isolation groove and the vertical device region serves as a depletion region. In the step of removing the top semiconductor layer and the buried dielectric region of the vertical device region and forming the isolation groove, photolithography and etching are performed, and the photolithography and etching of the vertical device region and the isolation groove are performed using the same photomask and are formed in the same etching step.

[0023] In one of the embodiments, the step of filling the isolation trench with an insulating dielectric material includes depositing the insulating dielectric material on the front side of the wafer, wherein the deposition forms a second insulating isolation portion on both sides of the vertical device region.

[0024] In one of the embodiments, the withstand voltage of the vertical device is greater than the withstand voltage of a CMOS device.

[0025] In one embodiment, the vertical device is a VDMOS device, the first source region and the first drain region have a first conductivity type, and the doping concentration of the first drain region is greater than the doping concentration of the substrate.

[0026] In one embodiment, the second groove has a closed ring structure.

[0027] In one embodiment, the first conductivity type is N type, and the second conductivity type is P type. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0029] Figure 1 is a flow chart of a method for manufacturing an SOI semiconductor structure with integrated vertical devices in one embodiment of the present application;

[0030] Figure 2a to Figure 2d is based on Figure 1 A schematic cross-sectional view of a device during manufacturing by the method shown;

[0031] Figure 3 is a schematic cross-sectional structural diagram of an SOI semiconductor structure with integrated vertical devices in one embodiment of the present application;

[0032] Figure 4 is a flow chart of a method for manufacturing an SOI semiconductor structure with integrated vertical devices in another embodiment of the present application;

[0033] Figure 5a to Figure 5e is based on Figure 4 A schematic cross-sectional view of a device during manufacturing by the method shown;

[0034] Figure 6 It is a schematic cross-sectional structure diagram of an SOI semiconductor structure with integrated vertical devices in another embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0037] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. "Connection" in this specification should be understood as "electrical connection", "communication connection" and the like if the connected circuits, modules, units, etc. have transmission of electrical signals or data to each other. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

[0038] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0039] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used herein, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It is understood that "at least one" refers to one or more, and "multiple" refers to two or more. "At least part of an element" refers to part or all of an element. It should also be understood that the terms "compose" and / or "comprise" when used in this specification determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0041] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0042] With the wide application of ultra-large-scale integrated circuits in various fields, the system has higher and higher requirements for the development of high-voltage and high-power semiconductor devices. Integrated high-voltage devices using silicon on insulator (SOI) technology have the advantages of SOI technology and the device itself, with fast operating speed, low parasitic effects, high breakdown voltage, simple process preparation, and convenient integration, so they have been widely studied and applied. This application proposes a process method for integrating a vertical channel VDMOS (vertical double diffused metal oxide semiconductor field effect transistor) device on an SOI substrate, which can integrate a VDMOS with low on-resistance, small area, and high withstand voltage into a BCD process platform to obtain a DMOS with higher power density. At the same time, because VDMOS can be packaged together with integrated CMOS, complex circuits can be miniaturized.

[0043] Figure 1 1 is a flow chart of a method for manufacturing an SOI semiconductor structure with integrated vertical devices in an embodiment of the present application, comprising the following steps:

[0044] S110, obtaining a wafer.

[0045] See also Figure 2a The wafer includes a substrate 12, a buried dielectric region 20 on the substrate 12, and a top semiconductor layer 14 on the buried dielectric region 20. The substrate 12 has a first conductivity type, and the top semiconductor layer 14 has a second conductivity type. In one embodiment of the present application, the first conductivity type is N-type, the second conductivity type is P-type, and the top semiconductor layer 14 is a P+ region. In other embodiments of the present application, the first conductivity type may be P-type, and the second conductivity type may be N-type. In one embodiment of the present application, the thickness of the top semiconductor layer 14 is 1 to 5 microns.

[0046] In one embodiment of the present application, the substrate 12 is a silicon substrate with a high doping concentration. The isolation region between adjacent devices in the SOI semiconductor structure will be depleted from the device end to the substrate 12. If a substrate 12 with a high doping concentration is used, the corresponding depletion region will be narrower, so the distance between two adjacent devices can be closer (that is, the isolation region can be narrower), and the area of ​​the device will be smaller. In one embodiment of the present application, the doping concentration of the substrate 12 is controlled to make its resistivity reach 8 to 45Ω×cm.

[0047] In one embodiment of the present application, the buried dielectric region 20 is a buried oxide layer, and its material may be silicon oxide, such as silicon dioxide. In one embodiment of the present application, the buried dielectric region 20 has a thickness of 0.5 to 3 microns.

[0048] exist Figure 2aIn the illustrated embodiment, the wafer further includes a dielectric layer 22 on the top semiconductor layer 14. In one embodiment of the present application, the dielectric layer 22 may be made of silicon oxide, such as silicon dioxide.

[0049] S120, patterning the wafer to expose the substrate in the vertical device region.

[0050] The top semiconductor layer 14 and the buried dielectric region 20 of the vertical device region are removed, thereby exposing the substrate 12 of the vertical device region.

[0051] See also Figure 2a and Figure 2b The patterning of step S120 is formed by photolithography and etching. That is, a photoresist is coated on the front side of the wafer, and then a photomask is used for exposure, and a photoresist layer 94 is formed after development; then the photoresist layer 94 is used as an etching barrier layer to etch the dielectric layer 22, the top semiconductor layer 14 and the buried dielectric region 20, and the dielectric layer 22, the top semiconductor layer 14 and the buried dielectric region 20 above the substrate 12 in the vertical device region are etched away, thereby exposing the substrate 12.

[0052] S130, forming a first insulating isolation portion on a side surface of the vertical device region.

[0053] In one embodiment of the present application, step S130 includes depositing an insulating dielectric material on the front side of the wafer after removing the photoresist layer 94. In one embodiment of the present application, step S130 deposits the insulating dielectric material by a low pressure chemical vapor deposition (LPCVD) process using TEOS (tetraethyl orthosilicate) as a reactant.

[0054] In one embodiment of the present application, after the insulating dielectric material is deposited, the insulating dielectric material on the upper surface of the substrate 12 in the vertical device region needs to be removed to expose the substrate 12. In one embodiment of the present application, the insulating dielectric material on the upper surface of the substrate 12 is removed by general etching (i.e., direct etching without photolithography). After deposition and general etching, the insulating dielectric material remaining on both sides of the vertical device region serves as the first insulating isolation portion 26, see Figure 2c .

[0055] S140, epitaxially forming a first conductive type region in the vertical device region.

[0056] exist Figure 2d In the illustrated embodiment, a first conductivity type epitaxial layer (ie, the first conductivity type region 16 ) is grown in the vertical device region by selective epitaxy.

[0057] For the embodiment in which the dielectric layer 22 is formed on the top semiconductor layer 14 in the previous step, the dielectric layer 22 will prevent the formation of the silicon epitaxial layer during selective epitaxy, so the epitaxial layer will only be formed at the position on the substrate 12 that is not covered by the buried dielectric region 20, the first insulating isolation portion 26 and the second insulating isolation portion 24, and will not be formed on the top semiconductor layer 14 covered with the dielectric layer 22.

[0058] S150, forming a CMOS device body, a first well region and a first source region through a CMOS process.

[0059] The vertical device is a high voltage device, which is isolated from the CMOS device by the first insulating isolation portion 26. In one embodiment of the present application, the vertical device is a VDMOS device, and the first well region 44 and the first source region 46 are the well region and source region of the VDMOS device.

[0060] Specifically, after removing the dielectric layer 22 on the front side of the wafer, a CMOS device body is formed in the first device region, and a first well region 44 and a first source region 46 are formed in the vertical device region by a CMOS process. The first well region 44 is formed in the first conductive type region 16, the first well region 44 has the second conductive type, and the first source region 46 is formed in the first well region 44.

[0061] Reference Figure 3 , a CMOS well region 54, a CMOS source region 562, a CMOS drain region 564 and a CMOS gate 58 can be formed in the first device region by conventional CMOS processes, and a first well region 44 and a first source region 46 are formed in the vertical device region. The first well region 44 has a second conductivity type and is formed in the first conductivity type region 16. The first source region 46 is formed in the first well region 44. The CMOS well region 54 has a second conductivity type and is formed in the top semiconductor layer 14 (second conductivity type region) and above the buried dielectric region 20. The CMOS source region 562 and the CMOS drain region 564 have the first conductivity type and are formed in the CMOS well region 54. The CMOS gate 58 is formed on the CMOS well region 54 between the CMOS source region 562 and the CMOS drain region 564.

[0062] In the SOI structure, the electric field lines on the high-voltage side will enter the silicon on the other side of the isolation trench, forming a depletion region that will affect the performance of other devices. Figure 3In the embodiment shown, the CMOS well region 54 only occupies a part of the top semiconductor layer 14 in the lateral direction, and the top semiconductor layer 14 outside the CMOS well region 54 serves as a depletion region. Exemplarily, the influence of the depletion region can be avoided by using the amplified isolation rule. First, other devices are kept away from the isolation trench boundary, but the chip area will be increased; second, the number and width of the isolation trenches are increased, but the more isolation trenches are etched, the higher the warpage of the wafer, and the wafer will crack due to increased stress.

[0063] In the present application, after the buried dielectric region 20 of the vertical device region is etched away, a first conductive type region 16 having a conductive type different from that of the top semiconductor layer 14 is regrown in the vertical device region, which can not only optimize the electric field of the vertical device, but also require a smaller area for the depletion region, thereby reducing the chip area and eliminating the need to set a wider isolation trench between the first device region and the vertical device region, thereby avoiding the possibility that a larger isolation trench size will increase the stress of the wafer, leading to wafer warping or even cracking.

[0064] S160, forming a first drain region at the bottom of the substrate.

[0065] The first drain region 42 is formed on the bottom surface of the substrate 12 by an ion implantation process. The doping concentration of the first drain region 42 is greater than the doping concentration of the substrate 12 .

[0066] The manufacturing method of the SOI semiconductor structure with integrated vertical devices can integrate relatively small vertical devices in the process platform to obtain devices with higher power density. The second conductivity type depletion region can optimize the electric field of the vertical device, thereby reducing the area of ​​the depletion region and reducing the chip area.

[0067] In one embodiment of the present application, the aforementioned SOI semiconductor structure adopts a BCD process platform. In one embodiment of the present application, the vertical device may also be an IGBT (Insulated Gate Bipolar Transistor) device, an SGT (Shielded Gate Trench) device, or the like.

[0068] The present application accordingly provides an SOI semiconductor structure with integrated vertical devices. Figure 3The semiconductor structure includes a substrate 12, a buried dielectric region 20, a first conductive type region 16, a top semiconductor layer 14, a first device body, a vertical device body and a first insulating isolation portion 26. The substrate 12 has a first conductive type. The buried dielectric region 20 is disposed on the substrate 12. The first conductive type region 16 is disposed in a region of the substrate 12 where there is no buried dielectric region 20. The top semiconductor layer 14 is disposed on the buried dielectric region 20, includes a second conductive type region located in the first device region, and a depletion region located between the second conductive type region and the first conductive type region 16, and the top semiconductor layer 14 has a second conductive type. The first device body is disposed on the buried dielectric region 20 and is located in the first device region. The vertical device body includes a first well region 44, a first source region 46, a first drain region 42 and a first gate 48. The first well region 44 has a second conductive type and is disposed in the first conductive type region 16. The first source region 46 is disposed in the first well region 44, and the first drain region 42 is disposed at the bottom of the substrate 12. The isolation structure includes a first insulating isolation portion 26 and a depletion region, wherein the depletion region is located between the second conductive type region and the first conductive type region 16, and the bottom of the first insulating isolation portion 26 reaches the buried dielectric region 20. The depletion region and the first conductive type region 16 are separated by the first insulating isolation portion 26, and the depletion region is located between the first insulating isolation portion 26 and the second conductive type region. In one embodiment of the present application, the first conductive type is N-type and the second conductive type is P-type; in other embodiments of the present application, the first conductive type may also be P-type and the second conductive type may be N-type.

[0069] The SOI semiconductor structure with integrated vertical devices integrates vertical devices with relatively small areas, so that devices with higher power density can be obtained. The isolation structure between the first device and the vertical device adopts a structure in which the depletion region of the second conductivity type cooperates with the first insulating isolation portion. The depletion region of the second conductivity type can optimize the electric field of the vertical device, thereby reducing the area of ​​the depletion region and reducing the chip area.

[0070] In one embodiment of the present application, the substrate 12 is a silicon substrate with a high doping concentration. The isolation region between adjacent devices in the SOI semiconductor structure will be depleted from the device end substrate 12. If a substrate with a high doping concentration is used, the corresponding depletion region will be narrower, so the distance between two adjacent devices can be closer (that is, the isolation region can be narrower), and the area of ​​the device will be smaller. In one embodiment of the present application, the doping concentration of the substrate 12 is controlled to make its resistivity reach 8 to 45Ω×cm.

[0071] In one embodiment of the present application, the isolation structure further includes a second insulating isolation portion 24. The depletion region is located between the first insulating isolation portion 26 and the second insulating isolation portion 24, the bottom of the second insulating isolation portion 24 reaches the buried dielectric region 20, the first insulating isolation portion 26 is arranged close to the first conductive type region 16, and the second insulating isolation portion 24 is arranged close to the second conductive type region.

[0072] In one embodiment of the present application, the first device is a low voltage device (e.g., a CMOS device), the vertical device is a high voltage device (e.g., a VDMOS device), and the low voltage device and the high voltage device are isolated by an isolation structure consisting of a first insulating isolation portion 26, a second insulating isolation portion 24, and a depletion region. The first source region 46 and the first drain region 42 have a first conductivity type, and the doping concentration of the first drain region 42 is greater than the doping concentration of the substrate 12.

[0073] In one embodiment of the present application, the first device body includes a CMOS well region 54, a CMOS source region 562, a CMOS drain region 564, and a CMOS gate 58. The CMOS well region 54 has a second conductivity type and is formed in the second conductivity type region and above the buried dielectric region 20. The CMOS source region 562 and the CMOS drain region 564 have a first conductivity type and are formed in the CMOS well region 54. The CMOS gate 58 is formed on the CMOS well region 54 between the CMOS source region 562 and the CMOS drain region 564.

[0074] exist Figure 3 In the illustrated embodiment, the first source region 46 , the CMOS source region 562 , and the CMOS drain region 564 are located at the same level in the SOI semiconductor structure.

[0075] In one embodiment of the present application, the SOI semiconductor structure adopts a structure of thin top silicon and thin buried oxide layer. The thickness of the top semiconductor layer 14 is 1-5 microns. The thickness of the buried dielectric region 20 is 0.5 to 3 microns.

[0076] Figure 4 1 is a flow chart of a method for manufacturing an SOI semiconductor structure with integrated vertical devices in another embodiment of the present application, comprising the following steps:

[0077] S410, obtaining a wafer.

[0078] See also Figure 5aThe wafer includes a substrate 12, a buried dielectric region 20 on the substrate 12, and a top semiconductor layer 14 on the buried dielectric region 20. The substrate 12 has a first conductivity type, and the top semiconductor layer 14 has a second conductivity type. In one embodiment of the present application, the first conductivity type is N-type, the second conductivity type is P-type, and the top semiconductor layer 14 is a P+ region. In other embodiments of the present application, the first conductivity type may be P-type, and the second conductivity type may be N-type. In one embodiment of the present application, the thickness of the top semiconductor layer 14 is 1 to 5 microns.

[0079] In one embodiment of the present application, the substrate 12 is a silicon substrate with a high doping concentration. The isolation region between adjacent devices in the SOI semiconductor structure will be depleted from the device end to the substrate 12. If a substrate 12 with a high doping concentration is used, the corresponding depletion region will be narrower, so the distance between two adjacent devices can be closer (that is, the isolation region can be narrower), and the area of ​​the device will be smaller. In one embodiment of the present application, the doping concentration of the substrate 12 is controlled to make its resistivity reach 8 to 45Ω×cm.

[0080] In one embodiment of the present application, the buried dielectric region 20 is a buried oxide layer, and its material may be silicon oxide, such as silicon dioxide. In one embodiment of the present application, the buried dielectric region 20 has a thickness of 0.5 to 3 microns.

[0081] exist Figure 5a In the illustrated embodiment, the wafer further includes a dielectric layer 22 on the top semiconductor layer 14. In one embodiment of the present application, the dielectric layer 22 may be made of silicon oxide, such as silicon dioxide.

[0082] S420, patterning the wafer to expose the substrate in the vertical device region and simultaneously forming an isolation trench and a depletion region.

[0083] The top semiconductor layer 14 and the buried dielectric region 20 of the vertical device region are removed, thereby exposing the substrate 12 of the vertical device region. While removing the top semiconductor layer 14 and the buried dielectric region 20 of the vertical device region, an isolation trench 13 is also patterned. The isolation trench 13 separates the first device region from the vertical device region, and the top semiconductor layer 14 between the isolation trench 13 and the vertical device region serves as a depletion region 14a.

[0084] See also Figure 5a and Figure 5bThe patterning of step S420 is formed by photolithography and etching. That is, photoresist is coated on the front side of the wafer, and then a photomask is used for exposure, and a photoresist layer 94 is formed after development; then the photoresist layer 94 is used as an etching barrier layer to etch the dielectric layer 22, the top semiconductor layer 14 and the buried dielectric region 20 to form the isolation groove 13, and at the same time, the dielectric layer 22, the top semiconductor layer 14 and the buried dielectric region 20 above the substrate 12 of the vertical device region are etched away, thereby exposing the substrate 12. The photolithography and etching of the vertical device region and the isolation groove 13 are formed using the same photomask in the same etching step.

[0085] In one embodiment of the present application, the critical dimension (CD) of the isolation trench 13 is 0.8 to 2 microns.

[0086] In one embodiment of the present application, the isolation trench 13 surrounds the first device region in the lateral direction. In one embodiment of the present application, the isolation trench 13 is a closed ring structure, which can be a circular ring, a square ring, or a closed ring of other shapes.

[0087] S430, filling the isolation groove with an insulating dielectric material.

[0088] In one embodiment of the present application, the insulating dielectric material is silicon oxide, such as silicon dioxide. The insulating dielectric material filled in the isolation groove 13 serves as the second insulating isolation portion 24. In one embodiment of the present application, step S430 includes depositing the insulating dielectric material on the front side of the wafer after removing the photoresist layer 94. After the deposition is completed, the first insulating isolation portion 26 will be formed on both sides of the vertical device region, see Figure 5c .

[0089] In one embodiment of the present application, step S430 of depositing the insulating dielectric material is a low pressure chemical vapor deposition (LPCVD) process using TEOS (tetraethyl orthosilicate) as a reactant.

[0090] In one embodiment of the present application, after depositing the insulating dielectric material, it is also necessary to remove the insulating dielectric material on the upper surface of the substrate 12 in the vertical device region, thereby exposing the substrate 12. Figure 5d In one embodiment of the present application, the insulating dielectric material on the upper surface of the substrate 12 is removed by general etching (ie, direct etching without photolithography).

[0091] S440, epitaxially forming a first conductive type region in the vertical device region.

[0092] exist Figure 5e In the illustrated embodiment, a first conductivity type epitaxial layer (ie, the first conductivity type region 16 ) is grown in the vertical device region by selective epitaxy.

[0093] For the embodiment in which the dielectric layer 22 is formed on the top semiconductor layer 14 in the previous step, the dielectric layer 22 will prevent the formation of the silicon epitaxial layer during selective epitaxy, so the epitaxial layer will only be formed at the position on the substrate 12 that is not covered by the buried dielectric region 20, the first insulating isolation portion 26 and the second insulating isolation portion 24, and will not be formed on the top semiconductor layer 14 covered with the dielectric layer 22.

[0094] In the SOI structure, the electric field lines on the high-voltage side will enter the silicon on the other side of the isolation trench, forming a depletion region, which will affect the performance of other devices. For example, the amplified isolation rule can be used to avoid the influence of the depletion region. First, other devices are kept away from the isolation trench boundary, but the chip area will increase; second, the number and width of the isolation trenches are increased, but the more isolation trenches are etched, the higher the warpage of the wafer, and the wafer will crack due to increased stress.

[0095] In the present application, after the buried dielectric region 20 of the vertical device region is etched away, a first conductive type region 16 having a conductive type different from that of the top semiconductor layer 14 is regrown in the vertical device region, which can not only optimize the electric field of the vertical device, but also require a smaller area for the depletion region 14a, thereby reducing the chip area and eliminating the need to set a wider isolation trench 13 between the first device region and the vertical device region, thereby avoiding the possibility that a larger isolation trench size will increase the stress of the wafer, thereby causing the wafer to warp or even crack.

[0096] S450, forming a CMOS device body, a first well region, and a first source region through a CMOS process.

[0097] The vertical device is a high voltage device, which is isolated from the CMOS device by an isolation structure composed of the first insulating isolation portion 26, the second insulating isolation portion 24 and the depletion region 14a. In one embodiment of the present application, the vertical device is a VDMOS device, and the first well region 44 and the first source region 46 are the well region and source region of the VDMOS device.

[0098] Specifically, after removing the dielectric layer 22 on the front side of the wafer, a CMOS device body is formed in the first device region, and a first well region 44 and a first source region 46 are formed in the vertical device region by a CMOS process. The first well region 44 is formed in the first conductive type region 16, the first well region 44 has the second conductive type, and the first source region 46 is formed in the first well region 44.

[0099] Reference Figure 6, a CMOS well region 54, a CMOS source region 562, a CMOS drain region 564 and a CMOS gate 58 can be formed in the first device region by conventional CMOS processes, and a first well region 44 and a first source region 46 are formed in the vertical device region. The first well region 44 has a second conductivity type and is formed in the first conductivity type region 16. The first source region 46 is formed in the first well region 44. The CMOS well region 54 has a second conductivity type and is formed in the top semiconductor layer 14 (second conductivity type region) and above the buried dielectric region 20. The CMOS source region 562 and the CMOS drain region 564 have the first conductivity type and are formed in the CMOS well region 54. The CMOS gate 58 is formed on the CMOS well region 54 between the CMOS source region 562 and the CMOS drain region 564.

[0100] S460, forming a first drain region at the bottom of the substrate.

[0101] The first drain region 42 is formed on the bottom surface of the substrate 12 by an ion implantation process. The doping concentration of the first drain region 42 is greater than the doping concentration of the substrate 12 .

[0102] The manufacturing method of the SOI semiconductor structure with integrated vertical devices can integrate relatively small vertical devices, thereby obtaining devices with higher power density. The second conductivity type depletion region can optimize the electric field of the vertical device, thereby reducing the area of ​​the depletion region and reducing the chip area.

[0103] The present application accordingly provides an SOI semiconductor structure with integrated vertical devices. Figure 6 , the semiconductor structure includes a substrate 12, a buried dielectric region 20, a first conductive type region 16, a second conductive type region (i.e., a portion of the top semiconductor layer 14), a first device body, a vertical device body and an isolation structure. The substrate 12 has a first conductive type. The buried dielectric region 20 is disposed on the substrate 12. The first conductive type region 16 is disposed in an area of ​​the substrate 12 where there is no buried dielectric region 20. The second conductive type region is disposed on the buried dielectric region 20. The first device body is disposed on the buried dielectric region 20 and is located in the first device region. The vertical device body includes a first well region 44, a first source region 46, a first drain region 42 and a first gate 48. The first well region 44 has a second conductive type and is disposed in the first conductive type region 16. The first source region 46 is disposed in the first well region 44, and the first drain region 42 is disposed at the bottom of the substrate 12. The isolation structure includes a first insulating isolation portion 26, a second insulating isolation portion 24 and a depletion region 14a, and the depletion region 14a is located in the second conductive type region ( Figure 6The first insulating isolation portion 26 and the bottom of the second insulating isolation portion 24 reach the buried dielectric region 20. The depletion region 14a and the second conductive type region are separated by the second insulating isolation portion 24, and the depletion region 14a and the first conductive type region 16 are separated by the first insulating isolation portion 26. The depletion region 14a has the second conductive type. In one embodiment of the present application, the first conductive type is N-type and the second conductive type is P-type; in other embodiments of the present application, the first conductive type may be P-type and the second conductive type may be N-type.

[0104] The SOI semiconductor structure with integrated vertical devices can integrate vertical devices with relatively small areas in the process platform to obtain devices with higher power density. The isolation structure between the first device and the vertical device adopts a structure in which the depletion region of the second conductivity type cooperates with the first insulating isolation portion 26 and the second insulating isolation portion 24. The depletion region of the second conductivity type can optimize the electric field of the vertical device, thereby reducing the area of ​​the depletion region and reducing the chip area.

[0105] In one embodiment of the present application, the substrate 12 is a silicon substrate with a high doping concentration. The isolation region between adjacent devices in the SOI semiconductor structure will be depleted from the device end substrate 12. If a substrate with a high doping concentration is used, the corresponding depletion region will be narrower, so the distance between two adjacent devices can be closer (that is, the isolation region can be narrower), and the area of ​​the device will be smaller. In one embodiment of the present application, the doping concentration of the substrate 12 is controlled to make its resistivity reach 8 to 45Ω×cm.

[0106] In one embodiment of the present application, the first device is a low voltage device (e.g., a CMOS device), the vertical device is a high voltage device (e.g., a VDMOS device), and the low voltage device and the high voltage device are isolated by an isolation structure consisting of a first insulating isolation portion 26, a second insulating isolation portion 24, and a depletion region 14a. The first source region 46 and the first drain region 42 have a first conductivity type, and the doping concentration of the first drain region 42 is greater than the doping concentration of the substrate 12.

[0107] In one embodiment of the present application, the second insulating isolation portion 24 surrounds the second conductive type region (i.e., the top semiconductor layer 14 of the first device region) in the lateral direction. In one embodiment of the present application, the second insulating isolation portion 24 is a closed ring structure, which surrounds the second conductive type region to insulate and isolate the first device. The ring structure can be a closed ring of a circular ring, a square ring, or other shapes.

[0108] In one embodiment of the present application, the first device body includes a CMOS well region 54, a CMOS source region 562, a CMOS drain region 564, and a CMOS gate 58. The CMOS well region 54 has a second conductivity type and is formed in the second conductivity type region and above the buried dielectric region 20. The CMOS source region 562 and the CMOS drain region 564 have a first conductivity type and are formed in the CMOS well region 54. The CMOS gate 58 is formed on the CMOS well region 54 between the CMOS source region 562 and the CMOS drain region 564.

[0109] exist Figure 6 In the illustrated embodiment, the first source region 46 , the CMOS source region 562 , and the CMOS drain region 564 are located at the same level in the SOI semiconductor structure.

[0110] In one embodiment of the present application, the SOI semiconductor structure adopts a structure of thin top silicon and thin buried oxide layer. The thickness of the top semiconductor layer 14 is 1-5 microns. The thickness of the buried dielectric region 20 is 0.5 to 3 microns.

[0111] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0112] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0113] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0114] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. An SOI semiconductor structure with integrated vertical devices, characterized in that: include: a substrate having a first conductivity type; A buried dielectric region is disposed on the substrate; A first conductive type region is provided in a region on the substrate where the buried dielectric region is not present; A second conductive type region, disposed on the buried dielectric region, wherein the first conductive type and the second conductive type are opposite conductive types; A first device body, disposed on the buried dielectric region; A vertical device body, comprising a first well region, a first source region, a first drain region and a first gate, wherein the first well region has a second conductivity type and is disposed in the first conductivity type region, the first source region is disposed in the first well region, and the first drain region is disposed at the bottom of the substrate; An isolation structure includes a first insulating isolation portion and a depletion region, wherein the depletion region is located between the second conductive type region and the first conductive type region, the bottom of the first insulating isolation portion reaches the buried dielectric region, the depletion region and the first conductive type region are separated by the first insulating isolation portion, the depletion region is located between the first insulating isolation portion and the second conductive type region, and the depletion region has the second conductive type.

2. The SOI semiconductor structure with integrated vertical devices according to claim 1, characterized in that: The isolation structure also includes a second insulating isolation portion, the depletion region is located between the first insulating isolation portion and the second insulating isolation portion, the bottom of the second insulating isolation portion reaches the buried dielectric region, the first insulating isolation portion is arranged close to the first conductive type region, and the second insulating isolation portion is arranged close to the second conductive type region.

3. The SOI semiconductor structure with integrated vertical devices according to claim 1, characterized in that: The vertical device is a VDMOS device, the first source region and the first drain region have a first conductivity type, and the doping concentration of the first drain region is greater than the doping concentration of the substrate.

4. The SOI semiconductor structure with integrated vertical devices according to claim 1, characterized in that: The first device body is a body of a CMOS device, and the first device body comprises: A CMOS well region, having a second conductivity type, disposed above the buried dielectric region; A CMOS source region, having a first conductivity type, disposed in the CMOS well region; A CMOS drain region, having a first conductivity type, disposed in the CMOS well region; The CMOS gate is disposed on the CMOS well region between the CMOS source region and the CMOS drain region.

5. The SOI semiconductor structure with integrated vertical devices according to claim 4, characterized in that: The CMOS source region, the CMOS drain region and the first source region are located at the same level in the SOI semiconductor structure.

6. The SOI semiconductor structure with integrated vertical devices according to claim 1, characterized in that: The second insulating isolation portion is a closed ring structure, surrounding the second conductive type region in a lateral direction.

7. A method for manufacturing a SOI semiconductor structure with an integrated vertical device, comprising: Obtaining a wafer, the wafer comprising a substrate, a buried dielectric region on the substrate, and a top semiconductor layer on the buried dielectric region; The substrate has a first conductivity type, the top semiconductor layer has a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; Patterning the wafer, removing the top semiconductor layer and the buried dielectric region of the vertical device region so as to expose the substrate of the vertical device region and form a first insulating isolation portion on the side of the vertical device region; Epitaxially forming a first conductive type region in the vertical device region; the first conductive type region and the top semiconductor layer are separated by the first insulating isolation portion; Forming a CMOS device body on the top semiconductor layer by a CMOS process, forming a first well region and a first source region in the vertical device region; the first well region is formed in the first conductive type region, the first well region has a second conductive type, and the first source region is formed in the first well region; In the top semiconductor layer, a portion between the first insulating isolation portion and the CMOS device body is a depletion region; A first drain region is formed at the bottom of the substrate.

8. The method for manufacturing a SOI semiconductor structure with integrated vertical devices according to claim 7, characterized in that: The step of patterning the wafer further includes forming an isolation trench, the isolation trench separating the top semiconductor layer into a first device region and the depletion region, the depletion region being located between the isolation trench and the first insulating isolation portion; The step of forming the first insulating isolation portion on the side of the vertical device region includes depositing an insulating dielectric material on the front side of the wafer, so that the isolation groove is filled with the insulating dielectric material to form a second insulating isolation portion, and forming the first insulating isolation portion on the side of the vertical device region; The forming of the CMOS device body in the top semiconductor layer by using the CMOS process is to form the CMOS device body in the first device region.

9. The method for manufacturing a SOI semiconductor structure with integrated vertical devices according to claim 7, characterized in that: In the step of obtaining a wafer, the obtained wafer further includes a dielectric layer on the top semiconductor layer; After the step of forming the first conductive type region by epitaxially in the vertical device region and before forming the CMOS device body, the method further includes the step of removing the dielectric layer.

10. The method for manufacturing a SOI semiconductor structure with integrated vertical devices according to claim 7, characterized in that: The step of forming a CMOS device body in the first device area by using a CMOS process includes: forming a CMOS well area, a CMOS source area, a CMOS drain area and a CMOS gate by using a CMOS process; the CMOS well area has a second conductivity type and is formed above the buried dielectric area, the CMOS source area and the CMOS drain area have a first conductivity type and are formed in the CMOS well area, and the CMOS gate is formed on the CMOS well area between the CMOS source area and the CMOS drain area; the first source area and the first drain area have a first conductivity type, and the doping concentration of the first drain area is greater than the doping concentration of the substrate.

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