Semiconductor structure, preparation method thereof and electronic equipment

Abstract

The invention discloses a semiconductor structure and a preparation method thereof, and electronic equipment, and relates to the technical field of semiconductors, and the structure comprises a substrate on which a germanium channel layer is formed; the first side wall structures are oppositely arranged at intervals and are located on the germanium channel layer; the first laminated structure is located on the germanium channel layer between the first side wall structures and extends to cover the side walls, close to the first laminated structure, of the first side wall structures, and the first laminated structure comprises a first gate dielectric layer, a first interface dipole layer and a first work function layer which are laminated; the first source electrode and the first drain electrode are provided with a first conduction type, penetrate through the germanium channel layer, extend into the substrate and are located on the side, away from the first laminated structure, of the first side wall structure; wherein the first laminated structure, the first source electrode and the first drain electrode form a first transistor. The driving current of the first transistor is improved, the performance of the first transistor is improved, and the performance of the semiconductor structure is integrally improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for preparing the same, and an electronic device. Background Art

[0002] As the size of transistors decreases, the active area pitch (AA pitch), polysilicon pitch (poly pitch), via pitch (contact pitch), and interconnect line pitch (M1 / M2 pitch) in the metal interconnect layer become smaller, resulting in a decrease in the drive current of a single transistor. How to overcome the decrease in transistor drive current has become an urgent problem to be solved. Summary of the invention

[0003] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, and an electronic device, which can optimize the performance of the semiconductor structure.

[0004] A semiconductor structure comprising:

[0005] A substrate having a germanium channel layer formed thereon;

[0006] A first spacer structure arranged relatively spaced apart and located on the germanium channel layer;

[0007] A first stacked structure is located on the germanium channel layer between the first spacer structures and extends to cover the sidewall of the first spacer structure close to the first stacked structure, wherein the first stacked structure includes a stacked first gate dielectric layer, a first interface dipole layer and a first work function layer;

[0008] A first source electrode and a first drain electrode of a first conductivity type penetrate the germanium channel layer and extend into the substrate, and are located on a side of the first spacer structure away from the first stacked structure;

[0009] The first stacked structure, the first source and the first drain constitute a first transistor.

[0010] In one embodiment, the substrate comprises a silicon substrate, and the semiconductor structure further comprises:

[0011] Si 1-x Ge x A buffer layer, located between the germanium channel layer and the silicon substrate;

[0012] Here, x is greater than or equal to 0 and less than or equal to 1, and the value of x increases from the surface of the silicon substrate to the surface away from the silicon substrate.

[0013] In one embodiment, the semiconductor structure further comprises:

[0014] A second spacer structure is arranged relatively spaced apart and is located on the germanium channel layer;

[0015] A second stacked structure is located on the germanium channel layer between the second spacer structures and extends to cover the sidewall of the second spacer structure close to the second stacked structure, wherein the second stacked structure includes a stacked second gate dielectric layer, a second interface dipole layer and a second work function layer;

[0016] A second source and a second drain having a second conductivity type, penetrating the germanium channel layer and extending into the substrate, and located on a side of the second sidewall structure away from the second stacked structure, the second conductivity type being opposite to the first conductivity type;

[0017] The second stacked structure, the second source and the second drain constitute a second transistor.

[0018] In one embodiment, the first conductivity type is P type, the second conductivity type is N type, the constituent materials of the first gate dielectric layer and the second gate dielectric layer include high dielectric constant materials, the constituent materials of the first interface dipole layer include aluminum oxide, the constituent materials of the first work function layer include titanium nitride, the constituent materials of the second interface dipole layer include lanthanum oxide, the constituent materials of the second work function layer include titanium aluminide, the first source is an in-situ doped SiGe source, the first drain is an in-situ doped SiGe drain, the second source is an in-situ doped SiP source, and the second drain is an in-situ doped SiP drain.

[0019] In one embodiment, the semiconductor structure further comprises:

[0020] A first gate structure, located on the first stacked structure;

[0021] A first protection layer is located on the first gate structure, wherein a lower surface of the first protection layer close to the substrate is lower than an upper surface of the first spacer structure away from the substrate;

[0022] A second gate structure, located on the second stacked structure;

[0023] The second protection layer is located on the second gate structure. The lower surface of the second protection layer close to the substrate is lower than the upper surface of the second sidewall structure away from the substrate.

[0024] In one embodiment, the substrate includes a device region and a peripheral region, the first stacked structure includes a first main stacked structure and a first auxiliary stacked structure, the first transistor includes a first main transistor located in the device region and a first auxiliary transistor located in the peripheral region, the first main transistor includes a first main gate oxide layer and a first main stacked structure, the first auxiliary transistor includes a first auxiliary gate oxide layer and a first auxiliary stacked structure, and the thickness of the first auxiliary gate oxide layer is greater than the thickness of the first main gate oxide layer;

[0025] The first main gate oxide layer is located between the first main stacked structure and the germanium channel layer, and the first auxiliary gate oxide layer is located between the first auxiliary stacked structure and the germanium channel layer.

[0026] In the semiconductor structure, the germanium channel layer serves as a conductive channel between the first source and the first drain, and improves the mobility of the first conductive type carriers in the conductive channel, thereby achieving the purpose of improving the driving current of the first transistor. A first stacked structure including a stacked first gate dielectric layer, a first interface dipole layer and a first work function layer is provided on the germanium channel layer between the first source and the first drain. The threshold voltage of the first transistor can be adjusted through the first work function layer, and the performance of the first transistor can be improved through the first interface dipole layer, thereby achieving the purpose of improving the performance of the semiconductor structure as a whole.

[0027] The present disclosure also provides a method for preparing a semiconductor structure, comprising:

[0028] Providing a substrate, on which a germanium channel layer is formed;

[0029] A first dummy gate structure is formed on the germanium channel layer, wherein a first spacer structure is formed on the opposite sidewall of the first dummy gate structure;

[0030] A first source and a first drain having a first conductivity type are formed on a side of the first spacer structure away from the first dummy gate structure, penetrating the germanium channel layer and extending into the substrate;

[0031] removing the first dummy gate structure to form a first trench;

[0032] forming a first stacked structure on the inner wall of the first trench, the first stacked structure comprising a stacked first gate dielectric layer, a first interface dipole layer and a first work function layer;

[0033] The first stacked structure, the first source and the first drain constitute a first transistor.

[0034] In one embodiment, a substrate is provided, on which a germanium channel layer is formed, comprising:

[0035] providing a silicon substrate;

[0036] Forming Si on a silicon substrate 1-x Ge x Buffer layer;

[0037] Yu Si 1-x Ge x forming a germanium channel layer on the surface of the buffer layer facing away from the silicon substrate;

[0038] Here, x is greater than or equal to 0 and less than or equal to 1, and the value of x increases from the surface of the silicon substrate to the surface away from the silicon substrate.

[0039] In one embodiment, at Si 1-x Ge xAfter forming a germanium channel layer on the surface of the buffer layer away from the silicon substrate, the method further comprises:

[0040] A shallow trench isolation structure is formed in the germanium channel layer, and the shallow trench isolation structure penetrates the Si 1-x Ge x The buffer layer extends into the silicon substrate, and the shallow trench isolation structure isolates a plurality of active areas arranged at intervals in the silicon substrate;

[0041] The first dummy gate structure is located on the active region, and the first source and the first drain are located in the active region.

[0042] In one embodiment, a Si substrate is formed on the Si substrate. 1-x Ge x Before the buffer layer, including:

[0043] A shallow trench isolation structure is formed in the silicon substrate, wherein the top surface is higher than the top surface of the silicon substrate, and the shallow trench isolation structure isolates a plurality of active areas arranged at intervals in the silicon substrate;

[0044] The top surface of the germanium channel layer in the active area away from the silicon substrate is lower than the top surface of the shallow trench isolation structure, the first pseudo gate structure is located on the active area, and the first source and the first drain are located in the active area.

[0045] In one embodiment, the first dummy gate structure includes a first main dummy gate structure and a first auxiliary dummy gate structure, the first trench includes a first main trench and a first auxiliary trench, and before forming the first dummy gate structure on the substrate, the method further includes:

[0046] forming a silicon buffer layer on a surface of the germanium channel layer facing away from the substrate;

[0047] Oxidizing the upper surface of the silicon buffer layer away from the silicon substrate to form a first oxide layer, wherein the first main dummy gate structure and the first auxiliary dummy gate structure are both located on the surface of the first oxide layer;

[0048] Removing the first dummy gate structure to form a first trench includes:

[0049] Removing the first main dummy gate structure and the first auxiliary dummy gate structure respectively to obtain a first main trench and a first auxiliary trench;

[0050] removing the first oxide layer exposed by the first main trench;

[0051] Simultaneously, the silicon buffer layer at the bottom of the first main trench and the silicon buffer layer at the bottom of the first auxiliary trench are oxidized to form a second oxide layer;

[0052] The first gate dielectric layer contacts the surface of the second oxide layer in the first main trench, and contacts the surface of the first oxide layer in the first auxiliary trench.

[0053] In one embodiment, the method for preparing a semiconductor structure further includes:

[0054] A second dummy gate structure is formed on the germanium channel layer and is spaced apart from the first dummy gate structure, and a second spacer structure is formed on the opposite sidewall of the second dummy gate structure;

[0055] A second source and a second drain having a second conductivity type are formed on a side of the second spacer structure away from the second dummy gate structure, penetrating the germanium channel layer and extending into the substrate, wherein the second conductivity type is opposite to the first conductivity type;

[0056] removing the second dummy gate structure to form a second trench;

[0057] forming a second stacked structure on the inner wall of the second trench, the second stacked structure comprising a stacked second gate dielectric layer, a second interface dipole layer and a second work function layer;

[0058] The second stacked structure, the second source and the second drain constitute a second transistor.

[0059] In one embodiment, the first conductivity type is P type, the second conductivity type is N type, a first source and a first drain having the first conductivity type are formed on a side of the first sidewall structure away from the first dummy gate structure, and penetrate the germanium channel layer and extend into the substrate, and a second source and a second drain having the second conductivity type are formed on a side of the second sidewall structure away from the second dummy gate structure, and penetrate the germanium channel layer and extend into the substrate, including:

[0060] Forming a first source trench and a first drain trench extending to the substrate in the germanium channel layer on a side of the first spacer structure away from the first dummy gate structure;

[0061] forming a second source trench and a second drain trench extending to the substrate in the germanium channel layer on a side of the second spacer structure away from the second dummy gate structure;

[0062] Forming an in-situ doped SiGe source in the first source trench and forming an in-situ doped SiGe drain in the first drain trench respectively;

[0063] An in-situ doped SiP source is formed in the second source trench and an in-situ doped SiP drain is formed in the second drain trench respectively.

[0064] In one embodiment, the first gate dielectric layer and the second gate dielectric layer are made of the same material, a first stacked structure is formed on the inner wall of the first trench, and a second stacked structure is formed on the inner wall of the second trench, including:

[0065] forming a third gate dielectric material layer on the inner wall of the first trench and the inner wall of the second trench, wherein the third dielectric material layer includes a first gate dielectric material layer in a region corresponding to the first transistor and a second gate dielectric material layer in a region corresponding to the second transistor;

[0066] forming a second interface dipole material layer on the second gate dielectric material layer;

[0067] forming a first interface dipole material layer on the first gate dielectric material layer;

[0068] forming a first work function material layer on the first interface dipole material layer;

[0069] forming a second work function material layer on the second interface dipole material layer;

[0070] forming a first gate structure in the first trench and forming a second gate structure in the second trench;

[0071] Filling the first trench and the second trench to form a third protective material layer;

[0072] The CMP process is used to remove the third gate dielectric material layer, the first interface dipole material layer, the first work function material layer and the third protective material layer above the first trench, as well as the third gate dielectric material layer, the second interface dipole material layer, the second work function material layer and the third protective material layer above the second trench, to obtain a first stacked structure, a second stacked structure, a first protective layer and a second protective layer.

[0073] In one embodiment, forming a second interface dipole material layer on the second gate dielectric material layer includes: forming a second interface dipole material film layer on the third gate dielectric material layer, and etching and removing the second interface dipole material film layer on the region where the first transistor is located to obtain the second interface dipole material layer;

[0074] Forming a first interface dipole material layer on the first gate dielectric material layer, including: forming a first interface dipole material film layer on the third gate dielectric material layer, and etching and removing the first interface dipole material film layer on the second interface dipole material layer to obtain the first interface dipole material layer;

[0075] Before forming the first work function material layer on the first interface dipole material layer, the method further includes: forming a work function etching stop layer on the first interface dipole material layer and the second interface dipole material layer;

[0076] Forming a first work function material layer on the first interface dipole material layer includes: forming a first work function material film layer on a substrate, and removing the first work function material film layer on the second interface dipole material layer by etching with a work function etch stop layer as an etch stop layer to obtain the first work function material layer;

[0077] Forming a second work function material layer on the second interface dipole material layer includes: forming a second work function material film layer on the substrate, and etching and removing the second work function material film layer on the first work function material layer to obtain a second work function material layer located on the second interface dipole material layer.

[0078] In one embodiment, after forming the first stacked structure on the inner wall of the first trench, the method further includes:

[0079] forming a first gate structure and a first protection layer in the first trench in sequence;

[0080] The first protection layer fills up the first trench.

[0081] In the method for preparing the semiconductor structure, the germanium channel layer on the substrate serves as a conductive channel between the first source and the first drain, thereby improving the mobility of the first conductive type carriers in the conductive channel, thereby achieving the purpose of improving the driving current of the first transistor. A first stacked structure including a stacked first gate dielectric layer, a first interface dipole layer and a first work function layer is formed on the germanium channel layer between the first source and the first drain, the threshold voltage of the first transistor can be adjusted through the first work function layer, and the performance of the first transistor can be improved through the first interface dipole layer, thereby achieving the purpose of improving the performance of the semiconductor structure as a whole.

[0082] The present disclosure also provides an electronic device, comprising: the semiconductor structure as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0084] Figure 1 is a schematic flow chart of a method for preparing a semiconductor structure in one embodiment;

[0085] Figure 2 A schematic diagram of a process for forming a germanium channel layer on a substrate is provided in one embodiment;

[0086] Figure 3 is a schematic cross-sectional view of a semiconductor structure after a germanium channel layer is formed in one embodiment;

[0087] Figure 4 is a schematic cross-sectional view of a semiconductor structure after a germanium channel layer is formed in another embodiment;

[0088] Figure 5is a schematic cross-sectional view of a semiconductor structure after a first spacer structure is formed in one embodiment;

[0089] Figure 6 is a cross-sectional schematic diagram of a semiconductor structure after a first source electrode and a first drain electrode are formed in one embodiment;

[0090] Figure 7 It is a schematic diagram of a process of forming a first source and a first drain of a first conductivity type on a side of the first spacer structure away from the first dummy gate structure in one embodiment;

[0091] Figure 8 is a schematic diagram of a process of removing a first dummy gate structure and forming a first trench in an embodiment;

[0092] Fig. 9 is a schematic cross-sectional view of a first transistor in a semiconductor structure after a first trench is formed in one embodiment;

[0093] Fig.10a is a schematic cross-sectional view of a first transistor in a semiconductor structure after a first protective material layer is formed in one embodiment;

[0094] Fig.10b is a cross-sectional schematic diagram of a first main transistor and a second main transistor in a semiconductor structure after a first protective material layer is formed in one embodiment;

[0095] Fig.11a is a schematic cross-sectional view of a first transistor in a semiconductor structure after a first protective layer is formed in one embodiment;

[0096] Fig.11b is a cross-sectional schematic diagram of a first main transistor and a second main transistor in a semiconductor structure after a first protective layer is formed in one embodiment;

[0097] Fig.12 is a cross-sectional schematic diagram of a first transistor in a semiconductor structure after a first source lead-out structure and a first drain lead-out structure are formed in one embodiment;

[0098] Fig.13 is a schematic flow chart of a method for preparing a semiconductor structure in another embodiment;

[0099] Fig.14 The figure is a schematic diagram of a process of forming a first stacked structure on an inner wall of a first trench and forming a second stacked structure on an inner wall of a second trench in one embodiment.

[0100] Description of reference numerals:

[0101] 102, substrate; 104, germanium channel layer; 106, Si 1-x Ge xBuffer layer; 108, shallow trench isolation structure; 110, silicon buffer layer; 112, first source; 114, first drain; 116, second oxide layer; 118, first gate structure; 120, first stacked structure; 122, first protection layer; 202, first oxide layer; 204, first pseudo gate structure; 206, first sidewall structure; 208, first etch stop layer; 210, filling layer; 214, first stacked structure material layer; 215, second stacked structure material layer; 216, first Main gate structure; 217, second main gate structure; 218, first auxiliary gate structure; 220, first protective material layer; 221, second protective material layer; 222, first main stacked structure; 224, first auxiliary stacked structure; 226, first main protective layer; 227, second main protective layer; 228, first auxiliary protective layer; 230, first main source lead-out structure; 232, first auxiliary source lead-out structure; 234, first main drain lead-out structure; 236, first auxiliary drain lead-out structure; 302, The first main sidewall structure; 304, the first auxiliary sidewall structure; 306, the first main source; 308, the first auxiliary source; 310, the first main drain; 312, the first auxiliary drain; 314, the first main trench; 316, the first auxiliary trench; 318, the first gate dielectric material layer; 319, the second gate dielectric material layer; 320, the first interface dipole material layer; 321, the second interface dipole material layer; 322, the first work function material layer; 323, the second work function material layer; 324, the first main gate dielectric layer; material layer; 325, the second main gate dielectric layer; 326, the first main interface dipole layer; 327, the second main interface dipole layer; 328, the first main work function layer; 329, the second main work function layer; 330, the first auxiliary gate dielectric layer; 332, the first auxiliary interface dipole layer; 334, the first auxiliary work function layer; 336, the capping layer structure; 338, the work function etch stop layer; 402, the second main sidewall structure; 406, the second main source; 408, the second main stacked structure; 410, the first main drain. DETAILED DESCRIPTION

[0102] In order to facilitate understanding of the embodiments of the present application, the embodiments of the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the embodiments of the present application are given in the drawings. However, the embodiments of the present application can be implemented in many different forms and are not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the embodiments of the present application more thorough and comprehensive.

[0103] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the technical field of the embodiments of the present application. The terms used herein in the specification of the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present application. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0104] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the methods or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0105] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first source may be referred to as a second source, and similarly, a second source may be referred to as a first source. Both the first source and the second source are sources, but they are not the same source.

[0106] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the description of the present application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0107] As used herein, the terms "substrate" and "base" mean and include the base material or structure of the material of the semiconductor structure introduced in the present disclosure. The substrate can be a semiconductor substrate, a basic semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures or regions formed thereon. The substrate can be a conventional silicon substrate or other bulk substrate including a semiconductor material layer. In the present disclosure, the upper surface of the substrate is the surface close to the germanium channel layer, the lower surface of the substrate is the surface away from the germanium channel layer, and the upper surface and lower surface of other structures or layers are relative to the upper surface of the substrate. Of the two surfaces, the one close to the upper surface of the substrate is the lower surface / bottom surface / bottom, and the one away from the upper surface of the substrate is the upper surface or top surface.

[0108] Figure 1FIG. 1 is a schematic diagram of a process for preparing a semiconductor structure in an embodiment. Figure 1 As shown, in this embodiment, a method for preparing a semiconductor structure is provided, comprising:

[0109] S102, providing a substrate, on which a germanium channel layer is formed.

[0110] A substrate is provided, on which a germanium channel layer is formed, and the substrate is made of undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc. As an example, in this embodiment, the constituent material of the substrate is single crystal silicon.

[0111] S104 , forming a first dummy gate structure on the germanium channel layer, wherein a first spacer structure is formed on opposite sidewalls of the first dummy gate structure.

[0112] A first dummy gate structure is formed on the germanium channel layer, wherein the first dummy gate structure defines the shape and position of the first gate structure. A first sidewall structure symmetrical to the first dummy gate structure is formed on the germanium channel layer on opposite sides of the first dummy gate structure. The first sidewall structure protects the sidewalls of the first dummy gate structure and serves as a mask for the subsequent formation of a first source and a first drain.

[0113] S106 , forming a first source and a first drain of a first conductivity type on a side of the first spacer structure away from the first dummy gate structure.

[0114] A first source of the first conductivity type and a first drain of the first conductivity type are formed on one side of the first sidewall structure away from the first dummy gate structure, and a first source and a first drain are formed on both sides of the first sidewall structure formed on the first dummy gate structure, and the first source and the first drain both penetrate the germanium channel layer and extend into the substrate, wherein the upper surfaces of the first source and the first drain are flush with the lower surface of the first sidewall structure.

[0115] S108, removing the first dummy gate structure to form a first trench.

[0116] After the first dummy gate structure is removed, a first trench having the same shape as the first dummy gate structure is formed, wherein the bottom of the first trench is flush with the bottom of the first spacer structure.

[0117] S110 , forming a first stacked structure on an inner wall of the first trench.

[0118] A first stacked structure is formed on the inner wall of the first trench, and the first stacked structure includes a first gate dielectric layer, a first interface dipole layer, and a first work function layer stacked in sequence; wherein the first stacked structure, the first source, and the first drain constitute a first transistor. It is clear that the inner wall of the first trench includes the sidewall and the bottom of the first trench, and the stacking direction of the first gate dielectric layer, the first interface dipole layer, and the first work function layer is from the inner wall of the first trench to the direction away from the sidewall of the first trench.

[0119] In the method for preparing the semiconductor structure, the germanium channel layer of the substrate serves as a conductive channel between the first source and the first drain, thereby improving the mobility of the first conductive type carriers in the conductive channel, thereby achieving the purpose of improving the driving current of the first transistor. A first stacked structure including a stacked first gate dielectric layer, a first interface dipole layer and a first work function layer is formed on the germanium channel layer between the first source and the first drain, the threshold voltage of the first transistor can be adjusted through the first work function layer, and the performance of the first transistor can be improved through the first interface dipole layer, thereby achieving the purpose of improving the performance of the semiconductor structure as a whole.

[0120] Figure 2 The present invention is a schematic diagram of a process for forming a germanium channel layer on a substrate in one embodiment. Figure 3 is a schematic cross-sectional view of a semiconductor structure after a germanium channel layer is formed in one embodiment, Figure 4 FIG. 4 is a cross-sectional schematic diagram of a semiconductor structure after a germanium channel layer is formed in another embodiment. Figure 2-Figure 4 As shown, in this embodiment, a substrate 102 is provided, and a germanium channel layer 104 is formed on the substrate 102, including:

[0121] S202, providing a silicon substrate.

[0122] S204, forming Si on the silicon substrate 1-x Ge x Buffer layer.

[0123] 206, Yu Si 1-x Ge x A germanium channel layer is formed on the surface of the buffer layer facing away from the silicon substrate.

[0124] A substrate 102 is provided, wherein the substrate 102 is a silicon substrate. Then, a Si 1-x Ge x The buffer layer 106 is used to eliminate the strain caused by the lattice matching between the substrate 102 and the germanium channel layer 104. 1-x Ge x The percentage of germanium in the buffer layer 106, x, is greater than or equal to 0 and less than or equal to 1, and the value of x increases from the surface of the substrate 102 (silicon substrate) to the surface away from the substrate 102 (silicon substrate).1-x Ge x A germanium channel layer 104 is formed on the upper surface of the buffer layer 106. Exemplarily, the germanium channel layer 104 is formed by an epitaxial growth process to obtain a conductive channel with good compactness. Exemplarily, the thickness of the germanium channel layer 104 is 100 nm.

[0125] In some embodiments, a Si substrate (substrate 102) is formed on the silicon substrate. 1-x Ge x The buffer layer 106 step includes: in the longitudinal direction, the starting value of x is 0.1, and the value of x increases by 0.1. When the value of x increases by 0.1, a Si layer of a preset thickness (for example, 1 um) is generated on the substrate 102. 1-x Ge x Buffer layer 106, until x is 1, that is, Si 1-x Ge x The surface of the buffer layer 106 in contact with the germanium channel layer 104 is a germanium film layer. 1-x Ge x The thickness of the buffer layer 106 is 10 times the preset thickness. It is understandable that the step length of x may also be other values, such as 0.2.

[0126] In some embodiments, a Si substrate (substrate 102) is formed on the silicon substrate. 1-x Ge x The buffer layer 106 includes: first, epitaxially growing Si with a first thickness on the upper surface of the substrate 102 at a first temperature; 0.4 Ge 0.6 The film layer, that is, x is 0.6. Exemplarily, the first temperature includes 350°C to 450°C, such as 350°C, 370°C, 390°C, 400°C, 420°C, 450°C, etc.; the first thickness includes 1um; secondly, at the second temperature, at Si 0.4 Ge 0.6 The second thickness of Si is epitaxially grown on the upper surface of the film layer. 0.3 Ge 0.7 The second temperature is higher than the first temperature, that is, x is 0.7. Exemplarily, the second temperature includes 550°C to 650°C, such as 550°C, 570°C, 590°C, 600°C, 620°C, 650°C, etc. By setting Si 1-x Ge x The percentage of silicon in the lower surface layer of the buffer layer 106 close to the substrate 102 is greater than that of Si 1-x Ge x The percentage of silicon in the upper surface layer of the buffer layer 106 close to the germanium channel layer 104 can reduce the stress problem caused by the lattice matching between germanium atoms and silicon atoms. Optionally, x can also choose other values ​​as long as Si 1-x Ge xThe percentage of silicon in the lower surface layer of the buffer layer 106 close to the substrate 102 is greater than that of Si 1-x Ge x The percentage of silicon in the upper surface layer of the buffer layer 106 close to the germanium channel layer 104 can be used. 1- x Ge x The stress generated by the lower surface of the buffer layer 106 close to the substrate 102 and the Si 1-x Ge x The stresses generated by the upper surface of the buffer layer 106 close to the germanium channel layer 104 offset each other.

[0127] like Figure 3 As shown, in one embodiment, at Si 1-x Ge x After forming the germanium channel layer 104 on the surface of the buffer layer 106 away from the substrate 102 (silicon substrate), the method further includes:

[0128] A shallow trench isolation structure 108 is formed in the germanium channel layer 104. The shallow trench isolation structure 108 penetrates the Si 1-x Ge x The buffer layer 106 extends into the substrate 102 (silicon substrate), and the shallow trench isolation structure 108 isolates a plurality of active regions arranged at intervals in the substrate 102 (silicon substrate); wherein the first dummy gate structure is located on the active region, and the first source and the first drain are located in the active region.

[0129] like Figure 4 As shown, in one embodiment, Si is formed on the substrate 102 (silicon substrate). 1-x Ge x Before the buffer layer 106, it includes:

[0130] A shallow trench isolation structure 108 having a top surface higher than the top surface of the substrate 102 (silicon substrate) is formed in the substrate 102 (silicon substrate), and the shallow trench isolation structure 108 isolates a plurality of active areas arranged at intervals in the substrate 102 (silicon substrate); wherein the top surface of the germanium channel layer 104 in the active area facing away from the substrate 102 (silicon substrate) is lower than the top surface of the shallow trench isolation structure 108, the first dummy gate structure is located on the active area, and the first source and the first drain are located in the active area.

[0131] Exemplarily, after providing a substrate 102 (silicon substrate), a shallow trench isolation structure 108 is formed in the substrate. The shallow trench isolation structure 108 isolates a plurality of active regions arranged at intervals in the substrate 102 (silicon substrate), and then each active region is etched back so that the top surface of the active region is lower than the top surface of the substrate 102 (silicon substrate). Exemplarily, TIMAH is used to remove the substrate 102 with a thickness of 70 nm in the active region. For a fin field effect transistor, the substrate 102 at the fin position can be etched back. Secondly, a Si is formed on at least the active region. 1-x Ge x Buffer layer 106, in the active region, Si 1-x Ge x The top surface of the buffer layer 106 is lower than the top surface of the shallow trench isolation structure 108. 1-x Ge x A germanium channel layer 104 is formed on the buffer layer 106. In the active region, the top surface of the germanium channel layer 104 is lower than the top surface of the shallow trench isolation structure 108. 1-x Ge x The thickness of the buffer layer 106 is 10 nm, and the thickness of the germanium channel layer 104 is 50 nm.

[0132] Figure 5 FIG. 1 is a cross-sectional schematic diagram of a semiconductor structure after forming a first spacer structure in an embodiment. Figure 3 , Figure 5 As shown, in one embodiment, before forming the first dummy gate structure on the substrate 102, the method further includes:

[0133] In the first step, a silicon buffer layer 110 is formed on the surface of the germanium channel layer 104 away from the substrate 102. Optionally, after the silicon buffer layer 110 is formed on the surface of the germanium channel layer 104 away from the substrate 102, a shallow trench isolation structure 108 is formed that penetrates the silicon buffer layer 110 and extends into the substrate 102. Optionally, a Si 1-x Ge xIn an embodiment in which a shallow trench isolation structure 108 is formed before the buffer layer 106, after the silicon buffer layer 110 is formed on the upper surface of the germanium channel layer 104, the top surface of the silicon buffer layer 110 is flush with the top surface of the shallow trench isolation structure. In the second step, the upper surface of the silicon buffer layer 110 away from the substrate 102 is oxidized to form a first oxide layer 202, and the first oxide layer 202 has a high density. Exemplarily, the upper surface of the silicon buffer layer 110 away from the substrate 102 is oxidized using ozone gas to form the first oxide layer 202. In the third step, a first dummy gate structure 204 is formed on the first oxide layer 202, and a first sidewall structure 206 is formed on the opposite sidewall of the first dummy gate structure 204 away from the first dummy gate structure 204. Exemplarily, the first dummy gate structure 204 is located on the upper surface of the first oxide layer 202.

[0134] Exemplarily, the first dummy gate structure 204 includes a first dummy gate layer and a first dummy gate protection layer located on the upper surface of the first dummy gate layer, the constituent material of the first dummy gate layer includes but is not limited to polysilicon or silicon carbide, and the constituent material of the first dummy gate protection layer includes but is not limited to one or more of oxides (such as silicon dioxide), nitride oxides (such as silicon oxynitride) and nitrides (such as silicon nitride).

[0135] Exemplarily, the constituent material of the first spacer structure 206 is a low-k dielectric material to improve the performance of the first transistor, and the low-k dielectric material is a material with a dielectric constant less than or equal to 3.9. The constituent material of the first spacer structure 206 includes but is not limited to one or more of silicon oxycarbide (SiOC) and silicon oxycarbon nitride (SiOCN).

[0136] Figure 6 is a cross-sectional schematic diagram of a semiconductor structure after a first source electrode and a first drain electrode are formed in one embodiment, Figure 7 FIG. 1 is a schematic diagram of a process of forming a first source and a first drain of a first conductivity type on a side of the first spacer structure away from the first dummy gate structure in an embodiment. Figure 6 , Figure 7 As shown, a first source and a first drain having a first conductivity type are formed on a side of the first spacer structure away from the first dummy gate structure, penetrating the germanium channel layer and extending into the substrate, including:

[0137] S302 , forming a first source trench and a first drain trench on a side of the first spacer structure away from the first dummy gate structure.

[0138] Specifically, using the first sidewall structure 206 as a mask, a first source trench and a first drain trench extending to the substrate 102 are formed in the germanium channel layer 104 on the side of the first sidewall structure 206 away from the first dummy gate structure 204, wherein the first sidewall structure 206, the first dummy gate structure 204, the first source trench and the first drain trench are located in the same active area, and the first source trench and the first drain trench penetrate the first oxide layer 202 and extend into the substrate 102.

[0139] S304 , forming a SiGe source in the first source trench and forming a SiGe drain in the first drain trench.

[0140] An epitaxial growth process is used to form an in-situ doped SiGe structure in the first source trench and the first drain trench, wherein the SiGe structure has doped ions of the first conductivity type. The SiGe structure in the first source trench is a SiGe source, i.e., a first source 112, and the SiGe structure in the first drain trench is a SiGe drain, i.e., a first drain 114. It is understood that the SiGe source and the SiGe drain can be interchangeable.

[0141] Continue to refer Figure 6 In one embodiment, after forming a first source 112 and a first drain 114 with a first conductivity type penetrating the germanium channel layer and extending into the substrate on the side of the first sidewall structure 206 away from the first dummy gate structure 204, it also includes: forming a first etch stop layer 208 on the substrate 102 (first source 112, first drain 114), wherein the first etch stop layer 208 extends along the first source 112 and the first drain 114 to cover the first sidewall structure 206 and the first dummy gate structure 204. The first etch stop layer 208 serves as an etch stop layer in the subsequent etching to form the first source lead-out structure of the first source 112 and the first drain lead-out structure of the first drain 114, reducing the influence of the process deviation of the etching process and the deposition process on the contact between the first source lead-out structure and the first source 112, and the influence of the first drain lead-out structure and the first drain 114, so that the first source lead-out structure and the top of the first source 112, the first drain lead-out structure and the top of the first drain 114 are fully in contact, while protecting the first sidewall structure 206.

[0142] Optionally, the material constituting the first etch stop layer 208 includes, but is not limited to, one or more of nitride (eg, silicon nitride), oxide (eg, silicon dioxide), or oxynitride (eg, silicon oxynitride).

[0143] Continue to refer Figure 6In one embodiment, after forming a first source 112 and a first drain 114 having a first conductivity type penetrating the germanium channel layer and extending into the substrate on the side of the first spacer structure 206 away from the first dummy gate structure 204, the method further includes: forming a filling layer 210 on the substrate 102 to obtain a substrate 102 with a flat surface. Exemplarily, the filling layer 210 is formed on the substrate 102 by a chemical vapor deposition process and a chemical planarization process, and the upper surface of the filling layer 210 is flush with the top surface of the first etch stop layer 208.

[0144] Exemplarily, the constituent material of the filling layer 210 includes, but is not limited to, one or more of oxide (such as silicon dioxide), oxynitride (such as silicon oxynitride), and nitride (such as silicon nitride).

[0145] Figure 8 is a schematic diagram of a process of removing the first dummy gate structure and forming a first trench in an embodiment. Fig. 9 FIG. 4 is a cross-sectional schematic diagram of a first transistor in a semiconductor structure after a first trench is formed in an embodiment. Figure 8 , Fig. 9 As shown, in this embodiment, the first transistor includes a first main transistor and a first auxiliary transistor, where the main transistor is a transistor located in the device area 1, and the auxiliary transistor is a transistor located in the peripheral area 2, the first dummy gate structure 204 includes a first main dummy gate structure and a first auxiliary dummy gate structure, the first sidewall structure 206 includes a first main sidewall structure 302 located on both sides of the first main dummy gate structure and a first auxiliary sidewall structure 304 located on both sides of the first auxiliary dummy gate structure, the first source 112 includes a first main source 306 and a first auxiliary source 308, the first drain 114 includes a first main drain 310 and a first auxiliary drain 312, the first trench includes a first main trench 314 and a first auxiliary trench 316, and the first main dummy gate structure and the first auxiliary dummy gate structure are both located on the surface of the first oxide layer 202; removing the first dummy gate structure 204 to form the first trench includes:

[0146] S402 , removing the first main dummy gate structure and the first auxiliary dummy gate structure respectively to obtain a first main trench and a first auxiliary trench.

[0147] Specifically, an etching process is used to remove the first main dummy gate structure on the device area 1 and the first auxiliary dummy gate structure on the peripheral area 2 to obtain a first main trench 314 located in the device area 1 and a first auxiliary trench 316 located in the peripheral area 2, wherein the first main trench 314 and the first auxiliary trench 316 expose the top surface of the first oxide layer 202.

[0148] S404, removing the first oxide layer exposed by the first main trench.

[0149] The first oxide layer 202 exposed by the first main trench 314 is removed by an etching process until the silicon buffer layer 110 in contact with the lower surface of the first oxide layer 202 is exposed.

[0150] S406, simultaneously oxidizing the silicon buffer layer at the bottom of the first main trench and the silicon buffer layer at the bottom of the first auxiliary trench to form a second oxide layer.

[0151] At the same time, the silicon buffer layer 110 at the bottom of the first main trench 314, the first oxide layer 202 at the bottom of the first auxiliary trench 316, and the silicon buffer layer 110 below the first oxide layer 202 at the bottom of the first auxiliary trench 316 are oxidized, and the oxidized silicon buffer layer 110 forms a second oxide layer 116, wherein the second oxide layer 116 at the bottom of the first main trench 314 serves as the first main gate oxide layer of the first main transistor, and the first oxide layer 202 and the second oxide layer 116 at the bottom of the first auxiliary trench 316 together serve as the first auxiliary gate oxide layer of the first auxiliary transistor, and the subsequently formed first gate dielectric layer contacts the surface of the second oxide layer 116 in the first main trench 314, and contacts the surface of the first oxide layer 202 in the first auxiliary trench 316. It is understandable that when there are unoxidized or incompletely oxidized silicon elements in the first oxide layer 202 below the first auxiliary trench 316, the unoxidized or incompletely oxidized silicon elements in the first oxide layer 202 below the first auxiliary trench 316 are oxidized while forming the second oxide layer 116, thereby obtaining a more stable first auxiliary gate oxide layer. When there are no unoxidized or incompletely oxidized silicon elements in the first oxide layer 202 below the first auxiliary trench 316, the process of forming the second oxide layer 116 does not affect the first oxide layer 202 below the first auxiliary trench 316.

[0152] Exemplarily, the silicon buffer layer 110 at the bottom of the first main trench 314 , the first oxide layer 202 at the bottom of the first auxiliary trench 316 , and the silicon buffer layer 110 below the first oxide layer 202 at the bottom of the first auxiliary trench 316 are oxidized by ozone gas to form a second oxide layer 116 .

[0153] In one embodiment, after forming the first stacked structure on the inner wall of the first trench, the method further includes: forming a first gate structure and a first protection layer in the first trench in sequence; wherein the first protection layer fills up the first trench.

[0154] Fig.10a is a schematic cross-sectional view of a first transistor in a semiconductor structure after a first protective material layer is formed in one embodiment, Fig.10b is a cross-sectional schematic diagram of a first main transistor and a second main transistor in a semiconductor structure after a first protective material layer is formed in one embodiment, Fig.11a is a schematic cross-sectional view of a first transistor in a semiconductor structure after a first protective layer is formed in one embodiment, Fig.11b FIG. 1 is a cross-sectional schematic diagram of a first main transistor and a second main transistor in a semiconductor structure after a first protective layer is formed in an embodiment. Fig.10a , Fig.10b , Fig.11a , Fig.11bAs shown, the first gate structure 118 includes a first main gate structure 216 in the first main transistor and a first auxiliary gate structure 218 in the first auxiliary transistor, the first gate dielectric layer includes a first main gate dielectric layer in the first main transistor and a first auxiliary gate dielectric layer in the first auxiliary transistor, the first stacked structure 120 includes a first main stacked structure 222 in the first main transistor and a first auxiliary stacked structure 224 in the first auxiliary transistor, and the first protective layer 122 includes a first main protective layer 226 located on the first main gate structure 216 and a first auxiliary protective layer 228 located on the first auxiliary gate structure 218. After removing the first pseudo-gate structure and forming the first trench, the method also includes: a first step of simultaneously forming a stacked first gate dielectric material layer 318, a first interface dipole material layer 320 and a first work function material layer 322 on the inner walls of the first main trench 314 and the first auxiliary trench 316, wherein the stacking direction is from the inner wall of the first main trench 314 toward the direction away from the inner wall of the first main trench 314, and the gate dielectric material layer 318, the first interface dipole material layer 320 and the first work function material layer 322 constitute a first stacked structure material layer 214; illustratively, the first stacked structure material layer 214 extends along the side walls of the first main trench 314 and the side walls of the first auxiliary trench 316 to cover the substrate 102. In the second step, a first main gate structure 216 is formed in the first main trench 314 and a first auxiliary gate structure 218 is formed in the first auxiliary trench 316, wherein the upper surface of the first main gate structure 216 is lower than the opening of the first main trench 314, and the upper surface of the first auxiliary gate structure 218 is lower than the opening of the first auxiliary trench 316, that is, the upper surface of the first main gate structure 216 and the upper surface of the first auxiliary gate structure 218 are both lower than the upper surface of the filling layer 210. In the third step, the first main trench 314 and the first auxiliary trench 316 are filled with the first protection material layer 220 at the same time, and the first protection material layer 220 extends along the sidewalls of the first main trench 314 and the sidewalls of the first auxiliary trench 316 to cover the substrate 102. In the fourth step, the first stacked structure material layer 214 and the first protective material layer 220 located on the substrate 102 are removed to obtain a first main stacked structure 222 located on the inner wall of the first main groove 314 and a first auxiliary stacked structure 224 located on the inner wall of the first auxiliary groove 316, a first main protective layer 226 located on the first main gate structure 216 and composed of the remaining first protective material layer 220, and a first auxiliary protective layer 228 located on the first auxiliary gate structure 218 and composed of the remaining first protective material layer 220.The first main stacked structure 222 includes a first main gate dielectric layer 324 composed of a first gate dielectric material layer 318 remaining on the inner wall of the first main trench 314, a first main interface dipole layer 326 composed of a first interface dipole material layer 320 remaining on the first main gate dielectric layer 324, and a first main work function layer 328 composed of a first work function material layer 322 remaining on the first main interface dipole layer 326; the first auxiliary stacked structure 224 includes a first auxiliary trench 316 remaining on the inner wall of the first auxiliary trench 314, and a first main interface dipole layer 326 composed of a first interface dipole material layer 320 remaining on the first main gate dielectric layer 324. a first auxiliary gate dielectric layer 330 formed by the first gate dielectric material layer 318, a first main interface dipole layer 332 formed by the first interface dipole material layer 320 remaining on the first auxiliary gate dielectric layer 330, and a first auxiliary work function layer 334 formed by the first work function material layer 322 remaining on the first auxiliary interface dipole layer 332; an upper surface of the first main protective layer 226 is flush with the opening of the first main trench 314, and an upper surface of the first auxiliary protective layer 228 is flush with the opening of the first auxiliary trench 316.

[0155] Exemplarily, the constituent material of the first gate structure 118 includes, but is not limited to, one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi). Optionally, the constituent material of the first main gate structure 216 and the constituent material of the first auxiliary gate structure 218 may be the same or different.

[0156] Exemplarily, the constituent materials of the first gate dielectric material layer 318 include, but are not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), nitride (e.g., silicon nitride), metal oxide (e.g., Al2O3), metal oxynitride (e.g., AlON), metal silicide, high-k dielectric material (dielectric constant greater than 3.9), low-k dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), ultra-low-k dielectric material (dielectric constant less than 2.5), ferroelectric material, anti-ferroelectric material, carbide (silicon carbide), or a combination thereof. Exemplarily, the high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). Exemplarily, the constituent material of the first main gate dielectric layer 324 and the constituent material of the first auxiliary gate dielectric layer 330 may be the same or different.

[0157] In one embodiment, after forming the first stacked structure on the inner wall of the first trench, it also includes: forming a first source lead-out structure and a first drain lead-out structure on the substrate, wherein the first source lead-out structure is electrically connected to the first source, and the first drain lead-out structure is electrically connected to the first drain.

[0158] Fig.12 FIG. 1 is a cross-sectional schematic diagram of a semiconductor structure after a first source lead-out structure and a first drain lead-out structure are formed in one embodiment. Fig.12 As shown, in this embodiment, the first source lead-out structure includes a first main source lead-out structure 230 electrically connected to the first main source 306 and a first auxiliary source lead-out structure 232 electrically connected to the first auxiliary source 308, and the first drain lead-out structure includes a first main drain lead-out structure 234 electrically connected to the first main drain 310 and a first auxiliary drain lead-out structure 236 electrically connected to the first auxiliary drain 312. The first source lead-out structure and the first drain lead-out structure are formed on the substrate 102, including:

[0159] A first source through hole exposing the first source 112 and a first drain through hole exposing the first drain 114 are formed in the filling layer 210, wherein the first source through hole includes a first main source through hole exposing the first main source 306 and a first auxiliary source through hole exposing the first auxiliary source 308, and the first drain through hole includes a first main drain through hole exposing the first main drain 310 and a first auxiliary drain through hole exposing the first auxiliary drain 312;

[0160] A first source lead-out structure is formed in the first source through hole, and a first drain lead-out structure is formed in the first drain through hole, wherein the first source lead-out structure includes a first main source lead-out structure 230 in contact with the first main source 306 and a first auxiliary source lead-out structure 232 in contact with the first auxiliary source 308; the first drain lead-out structure includes a first main drain lead-out structure 234 in contact with the first main drain 310 and a first auxiliary drain lead-out structure 236 in contact with the first auxiliary drain 312.

[0161] Optionally, the constituent materials of the first source lead-out structure and / or the first drain lead-out structure include, but are not limited to, one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi). Optionally, the constituent materials of the first source lead-out structure and the constituent materials of the first drain lead-out structure may be the same or different.

[0162] Exemplarily, before forming the first source lead-out structure and the first drain lead-out structure on the substrate, it also includes: forming a capping structure 336 on the substrate 102, wherein the capping structure 336 is located on the filling layer 210, and the upper surface of the capping structure 336 is higher than the upper surface of the first protective layer 122.

[0163] Optionally, the constituent material of the capping structure 336 includes, but is not limited to, one or more of oxides (such as silicon dioxide), oxynitrides (such as silicon oxynitride), and nitrides (such as silicon nitride).

[0164] Fig.13 FIG. 1 is a schematic flow chart of a method for preparing a semiconductor structure in another embodiment. Fig.13 As shown, in this embodiment, the method for preparing the semiconductor structure further includes:

[0165] S502 , forming a second dummy gate structure on the germanium channel layer and spaced apart from the first dummy gate structure, and forming a second spacer structure on the opposite sidewalls of the second dummy gate structure.

[0166] A second dummy gate structure is formed on the germanium channel layer 104 and is spaced apart from the first dummy gate structure 204. A second sidewall structure is formed on the opposite sidewall of the second dummy gate structure. Exemplarily, the second dummy gate structure can be formed simultaneously with the first dummy gate structure 204, and the second sidewall structure can be formed simultaneously with the first sidewall structure 206. The second dummy gate structure is similar to the first dummy gate structure 204, and the second sidewall structure is similar to the first sidewall structure 206, which will not be described in detail here. The constituent materials and structures of the second dummy gate structure and the first dummy gate structure 204 can be the same or different, and the constituent materials and structures of the second sidewall structure and the first sidewall structure 206 can be the same or different.

[0167] S504 , forming a second source and a second drain of a second conductivity type on a side of the second spacer structure away from the second dummy gate structure.

[0168] A second source and a second drain with a second conductivity type are formed on the side of the second sidewall structure away from the second dummy gate structure, penetrating the germanium channel layer 104 and extending into the substrate 102, and the second conductivity type is opposite to the first conductivity type, wherein the second sidewall structure, the second dummy gate structure, the second source trench and the second drain trench are located in the same active area.

[0169] S506, removing the second dummy gate structure to form a second trench.

[0170] After the second dummy gate structure is removed, a second trench having the same shape as the second dummy gate structure is formed, wherein the bottom of the second trench is flush with the bottom of the second spacer structure.

[0171] S508 , forming a second stacked structure on the inner wall of the second trench.

[0172] A second stacked structure is formed on the inner wall of the second trench, and the second stacked structure includes a stacked second gate dielectric layer, a second interface dipole layer, and a second work function layer; wherein the second stacked structure, the second source electrode, and the second drain electrode constitute a second transistor. It is clear that the inner wall of the second trench includes the sidewall and the bottom of the second trench, and the stacking direction of the second gate dielectric layer, the second interface dipole layer, and the second work function layer is from the inner wall of the second trench to the direction away from the sidewall of the second trench.

[0173] In one embodiment, a second source and a second drain having a second conductivity type are formed on a side of the second spacer structure away from the second dummy gate structure, penetrating the germanium channel layer and extending into the substrate, including:

[0174] forming a second source trench and a second drain trench extending to the substrate in the germanium channel layer on a side of the second spacer structure away from the second dummy gate structure;

[0175] An in-situ doped SiP source is formed in the second source trench and an in-situ doped SiP drain is formed in the second drain trench, respectively, wherein the SiP source and the SiP drain have doping ions of the second conductivity type.

[0176] Exemplarily, the first conductivity type is P type, the second conductivity type is N type, the first transistor uses SiGe source and SiGe drain, and the second transistor uses SiP source and SiP drain, which reduces the overall stress of the first transistor and the second transistor.

[0177] Optionally, the semiconductor structure includes a first transistor and a second transistor, and the first gate dielectric layer and the second gate dielectric layer are made of the same material. Fig.14 FIG. 1 is a schematic diagram of a process of forming a first stacked structure on an inner wall of a first trench and forming a second stacked structure on an inner wall of a second trench in an embodiment. Fig.10a , Fig.11a , Fig.11b , Fig.12 , Fig.14 As shown, a cross-sectional view of a first transistor and a second main transistor is used as an exemplary illustration, a first stacked structure is formed on the inner wall of the first trench, and a second stacked structure is formed on the inner wall of the second trench, including:

[0178] S602 , forming a third gate dielectric material layer on the inner wall of the first trench and the inner wall of the second trench.

[0179] Exemplarily, a third gate dielectric material layer is formed on the inner wall of the first trench 212, and the third gate dielectric material layer extends along the sidewall of the first trench to cover the inner wall of the second trench and the substrate 102, wherein the third gate dielectric material layer in the region corresponding to the first transistor serves as the first gate dielectric material layer 318, and the third gate dielectric material layer in the region corresponding to the second transistor serves as the second gate dielectric material layer 319 for subsequently forming the second gate dielectric layer. Exemplarily, the third gate dielectric material layer includes a hafnium oxide material layer and a tantalum nitride material layer located on the upper surface of the hafnium oxide material layer, wherein the tantalum nitride material layer also serves as an etching stop layer for etching to form the second interface dipole material layer 321.

[0180] S604, forming a second interface dipole material layer on the second gate dielectric material layer.

[0181] Exemplarily, a second interface dipole material film layer is formed on the third gate dielectric material layer, and the second interface dipole material film layer on the region where the first transistor is located is etched away using the tantalum nitride material layer as an etch stop layer to obtain a second interface dipole material layer 321 located in the region of the second transistor.

[0182] S606 , forming a first interface dipole material layer on the first gate dielectric material layer.

[0183] Exemplarily, a first interface dipole material film layer is formed on the third gate dielectric material layer, the first interface dipole material film layer extends along the sidewall of the first groove to cover the second interface dipole material layer 321, and the first interface dipole material film layer on the second interface dipole material layer 321 is etched and removed to obtain the first interface dipole material layer 320 located in the area of ​​the first transistor.

[0184] S608 , forming a work function etching stop layer on the first interface dipole material layer and the second interface dipole material layer.

[0185] Exemplarily, a work function etch stop layer 338 is formed on the first interface dipole material layer 320 and the second interface dipole material layer 321 to subsequently form the first work function layer and the second work function layer. Exemplarily, the constituent material of the work function etch stop layer 338 includes but is not limited to tantalum nitride.

[0186] S610 , forming a first work function material layer on the first interface dipole material layer.

[0187] Exemplarily, a first work function material film layer is formed on the substrate 102 , and the first work function material film layer on the second interface dipole material layer 321 is etched away using the work function etch stop layer 338 as an etch stop layer to obtain a first work function material layer 322 located on the first interface dipole material layer 320 .

[0188] S612, forming a second work function material layer on the second interface dipole material layer.

[0189] Exemplarily, a second work function material film layer is formed on the substrate 102, and the second work function material film layer on the first work function material layer 322 is etched away to obtain a second work function material layer 323 located on the second interface dipole material layer 320, wherein the second gate dielectric material layer 319, the second interface dipole material layer 321 and the second work function material layer 323 constitute a second stacked structure material layer 215.

[0190] S614, forming a first gate structure in the first trench and forming a second gate structure in the second trench.

[0191] Exemplarily, a first gate structure 118 is formed in the first trench 314 and a second gate structure (second main gate structure 217) is formed in the second trench, wherein the upper surface of the first gate structure 118 is lower than the opening of the first trench 314, and the upper surface of the second gate structure (second main gate structure 217) is lower than the opening of the second trench. Exemplarily, the first gate structure 118 and the second gate structure (second main gate structure 217) are formed in the same process step.

[0192] S616, filling the first trench and the second trench to form a third protection material layer.

[0193] Exemplarily, a third protective material layer is formed by filling the first trench and the second trench, the third protective material layer fills the first trench and the second trench, and the upper surface of the third protective material layer is higher than the opening of the first trench and the opening of the second trench at the same time, wherein the third protective material layer on the first work function material layer 322 serves as the first protective material layer 220, and the third protective material layer on the second work function material layer 323 serves as the second protective material layer 221.

[0194] S618, forming a first stacked structure, a second stacked structure, a first protective layer, and a second protective layer.

[0195] Exemplarily, a CMP process is used to remove the third gate dielectric material layer, the first interface dipole material layer, the work function etch stop layer, the first work function material layer and the third protective material layer above the first trench to obtain a first stacked structure consisting of the first gate dielectric layer, the first interface dipole layer and the first work function layer, and a first protective layer; a CMP process is used to remove the third gate dielectric material layer, the second interface dipole material layer, the work function etch stop layer, the second work function material layer and the third protective material layer (second protective material layer 221) above the second trench to obtain a second stacked structure (second main stacked structure 408) consisting of the second gate dielectric layer (second main gate dielectric layer 325), the second interface dipole layer (second main interface dipole layer 327) and the second work function layer (second work function layer 329), and a second protective layer (second main protective layer 227).

[0196] Exemplarily, the first conductivity type is P type, the second conductivity type is N type, the constituent material of the second interface dipole material layer includes but is not limited to lanthanum oxide, the constituent material of the first interface dipole material layer includes but is not limited to aluminum oxide, the constituent material of the first work function material layer includes but is not limited to titanium nitride, and the constituent material of the second work function material layer includes but is not limited to aluminum nitride.

[0197] It is understandable that the preparation method of the second transistor is similar to the preparation method of the first transistor, and will not be elaborated here.

[0198] It should be understood that although Figure 1 , Figure 2 , Figure 7 , Figure 8 , Fig.13 and Fig.14 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 , Figure 2 , Figure 7 , Figure 8 , Fig.13 and Fig.14 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0199] like Fig.11aAs shown, in this embodiment, a semiconductor structure is provided, including: a substrate 102, a first spacer structure 206, a first stacked structure 120, a first source 112 and a first drain 114; a germanium channel layer 104 is formed on the substrate 102; the first spacer structures 206 are relatively spaced and located on the germanium channel layer 104; the first stacked structure 120 is located on the germanium channel layer 104 between the first spacer structures 206, and extends to cover the side wall of the first spacer structure 206 close to the first stacked structure 120, the first stacked structure 120 includes a stacked first gate dielectric layer, a first interface dipole layer and a first work function layer; a first source and a first drain of a first conductivity type both penetrate the germanium channel layer 104 and extend into the substrate 102, and are located on a side of the first spacer structure 206 away from the first stacked structure 120; wherein the first stacked structure 120, the first source 112 and the first drain 114 constitute a first transistor. Exemplarily, the spaced first spacer structures 206 and the germanium channel layer 104 between the first spacer structures 206 form a first U-shaped groove, and the first stacked structure 120 is located on the inner wall of the first U-shaped groove (the bottom and sidewall of the first U-shaped groove).

[0200] In the above semiconductor structure, the germanium channel layer serves as a conductive channel between the first source and the first drain, and improves the mobility of the first conductive type carriers in the conductive channel, thereby achieving the purpose of improving the driving current of the first transistor. A first stacked structure including a stacked gate dielectric layer, a first interface dipole layer and a first work function layer is arranged on the germanium channel layer between the first source and the first drain. The threshold voltage of the first transistor can be adjusted through the first work function layer, and the performance of the first transistor can be improved through the first interface dipole layer, thereby achieving the purpose of improving the performance of the semiconductor structure as a whole.

[0201] like Fig.12 As shown, in one embodiment, the substrate 102 includes a silicon substrate, and the semiconductor structure further includes: Si 1- x Ge x The buffer layer 106 is located between the germanium channel layer 104 and the silicon substrate; wherein x is greater than or equal to 0 and less than or equal to 1, and the value of x increases from the surface of the silicon substrate to the surface away from the silicon substrate. 1-x Ge x The description of the buffer layer 106 is similar to that in the aforementioned semiconductor manufacturing method and is not repeated here.

[0202] like Fig.12 As shown, in this embodiment, the semiconductor structure further includes a shallow trench isolation structure 108, and the shallow trench isolation structure 108 penetrates the Si 1-x Ge xThe buffer layer 106 extends into the substrate 102 (silicon substrate), and the shallow trench isolation structure 108 isolates a plurality of active regions arranged at intervals in the substrate 102 (silicon substrate); wherein the first stacked structure 120, the first source 112 and the first drain 114 are located in the same active region.

[0203] In one embodiment, the first source 112 is an in-situ doped SiGe source, the first drain 114 is an in-situ doped SiGe drain, and the SiGe source and the SiGe drain have doping ions of the first conductivity type. It is understandable that the SiGe source and the SiGe drain can be interchangeable. Exemplarily, the first conductivity type is P-type, and the first transistor uses a SiGe source and a SiGe drain, which reduces the overall stress of the first transistor device.

[0204] In one embodiment, the first source 112 is an in-situ doped SiP source, the first drain 114 is an in-situ doped SiP drain, and the SiP source and the SiP drain have doping ions of the first conductivity type. It is understandable that the SiP source and the SiP drain can be interchangeable. Exemplarily, the first conductivity type is N-type, and the first transistor uses the SiP source and the SiP drain, which reduces the overall stress of the first transistor device.

[0205] like Fig.12 As shown, in one embodiment, the semiconductor structure further includes: a first etch stop layer 208, the first etch stop layer 208 extends along the first source 112 and the first drain 114 to cover the first sidewall structure 206, the first etch stop layer 208 is used as an etch stop layer when etching to form the first source lead-out structure of the first source 112 and the first drain lead-out structure of the first drain 114, reducing the influence of process deviations of the etching process and the deposition process on the contact between the first source lead-out structure and the first source 112, and the influence of the first drain lead-out structure on the contact with the first drain 114, so that the first source lead-out structure and the top of the first source 112, the first drain lead-out structure and the top of the first drain 114 are fully in contact, while protecting the first sidewall structure 208.

[0206] like Fig.12As shown, in this embodiment, the first transistor includes a first main transistor and a first auxiliary transistor, where the main transistor is a transistor located in the device area 1, and the auxiliary transistor is a transistor located in the peripheral area 2. The first main transistor includes: a first main sidewall structure 302, a first main stacked structure 222, a first main source 306, a first main drain 310 and a first main gate oxide layer arranged oppositely, and the first auxiliary transistor includes: a first auxiliary sidewall structure 304, a first auxiliary stacked structure 224, a first auxiliary source 308, a first auxiliary drain 312 and a first auxiliary gate oxide layer; wherein the first main spacer structure 302 is located in the device area 1, the first auxiliary spacer structure 304 is located in the peripheral area 2, the first main stacked structure 222 is located on the germanium channel layer 104 between the first main spacer structures 302, and extends to cover the sidewall of the first main spacer structure 302 close to the first main stacked structure 302, the first main stacked structure 222 includes a stacked first main gate dielectric layer 324, a first main interface dipole layer 326 and a first main work function layer 328, a first main source 306 and a first main The drain 310 is located on a side of the first main spacer structure 302 away from the first main stacked structure 222, and penetrates the germanium channel layer 104 and extends into the substrate 102. The first main gate oxide layer is located on the germanium channel layer 104 between the first main spacer structures 302 and is in contact with the first main stacked structure 222. The first auxiliary stacked structure 224 is located on the germanium channel layer 104 between the first auxiliary spacer structures 304 and extends to cover the sidewall of the first auxiliary spacer structure 304 close to the first auxiliary stacked structure 304. The first auxiliary stacked structure 224 is located on the germanium channel layer 104 between the first auxiliary spacer structures 304 and is in contact with the first main stacked structure 222. 24 includes a stacked first auxiliary gate dielectric layer 330, a first auxiliary interface dipole layer 332 and a first auxiliary work function layer 334, the first auxiliary source 308 and the first auxiliary drain 312 are located on the side of the first auxiliary sidewall structure 304 away from the first auxiliary stack structure 224, and penetrate the germanium channel layer 104 and extend into the substrate 102, the first auxiliary gate oxide layer is located on the germanium channel layer 104 between the first auxiliary sidewall structures 304, and is in contact with the first auxiliary stack structure 224, and the thickness of the first auxiliary gate oxide layer is greater than the thickness of the first main gate oxide layer.

[0207] like Fig.10a , Fig.11a As shown, in one embodiment, the semiconductor structure further includes: a first gate structure 118 and a first protection layer 112, the first gate structure 118 is located on the first stacked structure 120; the first protection layer 112 is located on the first gate structure 118, and the lower surface of the first protection layer 112 close to the substrate 112 is lower than the upper surface of the first spacer structure 206 away from the substrate 102. Exemplarily, the first gate structure 118 is filled in the first U-shaped groove, and the top surface of the first gate structure 118 is lower than the opening of the first U-shaped groove, and the first protection layer 112 fills the first U-shaped groove.

[0208] Exemplarily, the first gate structure 118 includes a first main gate structure 216 in the first main transistor and a first auxiliary gate structure 218 in the first auxiliary transistor. The first protection layer 122 includes a first main protection layer 226 on the first main gate structure 216 and a first auxiliary protection layer 228 on the first auxiliary gate structure 218.

[0209] In one embodiment, the semiconductor structure further includes: a filling layer 210, a first source lead-out structure and a first drain lead-out structure, wherein the upper surface of the filling layer 210 is higher than or equal to the upper surface of the first sidewall structure 206, so as to obtain a substrate 102 with a flat surface. Exemplarily, the upper surface of the filling layer 210 is flush with the top surface of the first etch stop layer 208; the first source lead-out structure penetrates the filling layer 210 and contacts the first source, and the first drain lead-out structure penetrates the filling layer 210 and contacts the first drain.

[0210] like Fig.11a As shown, exemplarily, the first source lead-out structure includes a first main source lead-out structure 230 electrically connected to the first main source 306 and a first auxiliary source lead-out structure 232 electrically connected to the first auxiliary source 308, and the first drain lead-out structure includes a first main drain lead-out structure 234 electrically connected to the first main drain 310 and a first auxiliary drain lead-out structure 236 electrically connected to the first auxiliary drain 312.

[0211] In one embodiment, the semiconductor structure further includes: a capping structure 336 located on the filling layer 210 , and an upper surface of the capping structure 336 is higher than an upper surface of the first protection layer 122 .

[0212] In one embodiment, the semiconductor structure further includes: a second spacer structure, a second stacked structure, a second source and a second drain arranged at intervals relative to each other, the second spacer structure being located on the germanium channel layer and being isolated from the second spacer structure; the second stacked structure being located on the germanium channel layer between the second spacer structures and extending to cover the sidewall of the second spacer structure close to the second stacked structure, the second stacked structure including a stacked second gate dielectric layer, a second interface dipole layer and a second work function layer; a second source and a second drain having a second conductivity type, penetrating the germanium channel layer and extending into the substrate, being located on the side of the second spacer structure away from the second stacked structure, the second conductivity type being opposite to the first conductivity type; wherein the second stacked structure, the second source and the second drain constitute a second transistor, the second spacer structure, the second pseudo-gate structure, the second source trench and the second drain trench being located in the same active region. Exemplarily, the germanium channel layer between the second spacer structure and the second spacer structure arranged at intervals encloses a second U-shaped groove, and the second stacked structure is located on the inner wall of the second U-shaped groove (the bottom and sidewall of the second U-shaped groove).

[0213] In one embodiment, the first conductivity type is P type, the second conductivity type is N type, the constituent materials of the first gate dielectric layer and the constituent materials of the second gate dielectric layer include but are not limited to high dielectric constant materials, the constituent materials of the second interface dipole layer include but are not limited to lanthanum oxide, the constituent materials of the first interface dipole material layer include but are not limited to aluminum oxide, the constituent materials of the first work function layer include but are not limited to titanium nitride, and the constituent materials of the second work function layer include but are not limited to aluminum nitride. The first source is an in-situ doped SiGe source, the first drain is an in-situ doped SiGe drain, the second source is an in-situ doped SiP source, and the second drain is an in-situ doped SiP drain.

[0214] In another embodiment, the first conductivity type is N-type, the second conductivity type is P-type, the constituent materials of the first gate dielectric layer and the constituent materials of the second gate dielectric layer include but are not limited to high dielectric constant materials, the constituent materials of the first interface dipole layer include but are not limited to lanthanum oxide, the constituent materials of the second interface dipole layer include but are not limited to aluminum oxide, the constituent materials of the second work function layer include but are not limited to titanium nitride, and the constituent materials of the first work function layer include but are not limited to aluminum nitride. The second source is an in-situ doped SiGe source, the second drain is an in-situ doped SiGe drain, the first source is an in-situ doped SiP source, and the first drain is an in-situ doped SiP drain.

[0215] In one embodiment, the semiconductor structure further includes: a second gate structure and a second protective layer, the second gate structure is located on the second stacked structure; the second protective layer is located on the second gate structure, and the lower surface of the second protective layer close to the substrate is lower than the upper surface of the second sidewall structure away from the substrate. Exemplarily, the second gate structure is filled in the second U-shaped groove, and the top surface of the second gate structure is lower than the opening of the second U-shaped groove, and the second protective layer fills the second U-shaped groove. Fig.11bAs shown, in one embodiment, the second transistor includes a second main transistor and a second auxiliary transistor, the second main transistor includes: a second main spacer structure 402, a second main stacked structure 408, a second main source 406, a second main drain 410 and a second main gate oxide layer arranged oppositely, and the second auxiliary transistor includes: a second auxiliary spacer structure, a second auxiliary stacked structure, a second auxiliary source, a second auxiliary drain and a second auxiliary gate oxide layer arranged oppositely; wherein the second main spacer structure 402 is located in the device area 1, the second auxiliary spacer structure is located in the peripheral area 2, the second main stacked structure 408 is located on the germanium channel layer 104 between the second main spacer structures 402, and extends to cover the side wall of the second main spacer structure 402 close to the second main stacked structure 402, the second main stacked structure 408 includes a stacked second main gate dielectric layer 325, a second main interface dipole layer 327 and a second main work function layer 329, the second main source 406 and the second main drain 410 are located The second main sidewall structure 402 is away from the side of the second main stacked structure 408, penetrates the germanium channel layer 104 and extends into the substrate 102, the second main gate oxide layer is located on the germanium channel layer 104 between the second main sidewall structures 402, and is in contact with the second main stacked structure 408; the second auxiliary stacked structure is located on the germanium channel layer 104 between the second auxiliary sidewall structures, and extends to cover the side wall of the second auxiliary sidewall structure close to the second auxiliary stacked structure, the second auxiliary stacked structure includes a stacked second auxiliary gate dielectric layer, a second auxiliary interface dipole layer and a second auxiliary work function layer, the second auxiliary source and the second auxiliary drain are located on the side of the second auxiliary sidewall structure away from the second auxiliary stacked structure, penetrate the germanium channel layer 104 and extend into the substrate 102, the second auxiliary gate oxide layer is located on the germanium channel layer 104 between the second auxiliary sidewall structures, and is in contact with the second auxiliary stacked structure, and the thickness of the second auxiliary gate oxide layer is greater than the thickness of the second main gate oxide layer (second oxide layer 116).

[0216] It is understandable that the structure of the second transistor is similar to that of the first transistor, and will not be elaborated here.

[0217] The present disclosure also provides an electronic device, comprising: the semiconductor structure as described above.

[0218] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0219] The above-mentioned embodiments only express several implementation methods of the embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the embodiments of the present application, and these all belong to the protection scope of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized in that: include: A substrate having a germanium channel layer formed thereon; A first spacer structure arranged relatively spaced apart and located on the germanium channel layer; A first stacked structure, located on the germanium channel layer between the first spacer structures, and extending to cover the sidewall of the first spacer structure close to the first stacked structure, wherein the first stacked structure includes a stacked first gate dielectric layer, a first interface dipole layer and a first work function layer; A first source electrode and a first drain electrode of a first conductivity type, which penetrate the germanium channel layer and extend into the substrate, and are located on a side of the first spacer structure away from the first stacked structure; The first stacked structure, the first source and the first drain constitute a first transistor.

2. The semiconductor structure according to claim 1, characterized in that: The substrate comprises a silicon substrate, and the semiconductor structure further comprises: Si 1-x Ge x A buffer layer, located between the germanium channel layer and the silicon substrate; Wherein, x is greater than or equal to 0 and less than or equal to 1, and the value of x increases from the surface of the silicon substrate to the surface away from the silicon substrate.

3. The semiconductor structure according to claim 1, characterized in that: Also includes: A second spacer structure arranged relatively spaced apart and located on the germanium channel layer; a second stacked structure, located on the germanium channel layer between the second spacer structures, and extending to cover the sidewall of the second spacer structure close to the second stacked structure, wherein the second stacked structure includes a stacked second gate dielectric layer, a second interface dipole layer, and a second work function layer; a second source and a second drain having a second conductivity type, penetrating the germanium channel layer and extending into the substrate, and located on a side of the second sidewall structure away from the second stacked structure, the second conductivity type being opposite to the first conductivity type; The second stacked structure, the second source and the second drain constitute a second transistor.

4. The semiconductor structure according to claim 3, characterized in that: The first conductivity type is P type, the second conductivity type is N type, the constituent materials of the first gate dielectric layer and the second gate dielectric layer include high dielectric constant materials, the constituent materials of the first interface dipole layer include aluminum oxide, the constituent materials of the first work function layer include titanium nitride, the constituent materials of the second interface dipole layer include lanthanum oxide, the constituent materials of the second work function layer include titanium aluminide, the first source is an in-situ doped SiGe source, the first drain is an in-situ doped SiGe drain, the second source is an in-situ doped SiP source, and the second drain is an in-situ doped SiP drain.

5. The semiconductor structure according to claim 3, characterized in that: Also includes: A first gate structure, located on the first stacked structure; A first protection layer, located on the first gate structure, wherein the first protection layer is close to a lower surface of the substrate and is lower than an upper surface of the first spacer structure facing away from the substrate; A second gate structure, located on the second stacked structure; The second protection layer is located on the second gate structure. The lower surface of the second protection layer close to the substrate is lower than the upper surface of the second sidewall structure away from the substrate.

6. The semiconductor structure according to claim 1, characterized in that The substrate includes a device region and a peripheral region, the first stacked structure includes a first main stacked structure and a first auxiliary stacked structure, the first transistor includes a first main transistor located in the device region and a first auxiliary transistor located in the peripheral region, the first main transistor includes a first main gate oxide layer and the first main stacked structure, the first auxiliary transistor includes a first auxiliary gate oxide layer and the first auxiliary stacked structure, and the thickness of the first auxiliary gate oxide layer is greater than the thickness of the first main gate oxide layer; The first main gate oxide layer is located between the first main stacked structure and the germanium channel layer, and the first auxiliary gate oxide layer is located between the first auxiliary stacked structure and the germanium channel layer.

7. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, on which a germanium channel layer is formed; forming a first dummy gate structure on the germanium channel layer, wherein opposite sidewalls of the first dummy gate structure are formed with first spacer structures; forming a first source and a first drain having a first conductivity type, penetrating the germanium channel layer and extending into the substrate, on a side of the first spacer structure away from the first dummy gate structure; removing the first dummy gate structure to form a first trench; forming a first stacked structure on the inner wall of the first trench, wherein the first stacked structure comprises a stacked first gate dielectric layer, a first interface dipole layer and a first work function layer; The first stacked structure, the first source and the first drain constitute a first transistor.

8. The preparation method according to claim 7, characterized in that: The step of providing a substrate, on which a germanium channel layer is formed, comprises: providing a silicon substrate; Forming Si on the silicon substrate 1-x Ge x Buffer layer; In the Si 1-x Ge x forming the germanium channel layer on the surface of the buffer layer away from the silicon substrate; Wherein, x is greater than or equal to 0 and less than or equal to 1, and the value of x increases from the surface of the silicon substrate to the surface away from the silicon substrate.

9. The preparation method according to claim 8, characterized in that: Said in said Si 1-x Ge x After the germanium channel layer is formed on the surface of the buffer layer away from the silicon substrate, the method further comprises: A shallow trench isolation structure is formed in the germanium channel layer, wherein the shallow trench isolation structure penetrates the Si 1-x Ge x The buffer layer extends into the silicon substrate, and the shallow trench isolation structure isolates a plurality of active areas arranged at intervals in the silicon substrate; The first dummy gate structure is located on the active region, and the first source and the first drain are located in the active region.

10. The preparation method according to claim 8, characterized in that: The Si substrate is formed on the 1-x Ge x Before the buffer layer, including: forming a shallow trench isolation structure in the silicon substrate, the top surface of which is higher than the top surface of the silicon substrate, wherein the shallow trench isolation structure isolates a plurality of active areas arranged at intervals in the silicon substrate; The top surface of the germanium channel layer in the active area facing away from the silicon substrate is lower than the top surface of the shallow trench isolation structure, the first dummy gate structure is located on the active area, and the first source and the first drain are located in the active area.

11. The preparation method according to claim 7, characterized in that: The first dummy gate structure includes a first main dummy gate structure and a first auxiliary dummy gate structure, the first trench includes a first main trench and a first auxiliary trench, and before forming the first dummy gate structure on the substrate, the method further includes: forming a silicon buffer layer on a surface of the germanium channel layer facing away from the substrate; Performing oxidation treatment on the upper surface of the silicon buffer layer away from the silicon substrate to form a first oxide layer, wherein the first main dummy gate structure and the first auxiliary dummy gate structure are both located on the surface of the first oxide layer; The removing the first dummy gate structure to form a first trench comprises: Removing the first main dummy gate structure and the first auxiliary dummy gate structure respectively to obtain the first main trench and the first auxiliary trench; removing the first oxide layer exposed by the first main trench; Simultaneously, oxidizing the silicon buffer layer at the bottom of the first main trench and the silicon buffer layer at the bottom of the first auxiliary trench to form a second oxide layer; The first gate dielectric layer contacts a surface of the second oxide layer in the first main trench, and contacts a surface of the first oxide layer in the first auxiliary trench.

12. The preparation method according to claim 7, characterized in that: Also includes: forming a second dummy gate structure on the germanium channel layer and spaced apart from the first dummy gate structure, wherein a second spacer structure is formed on an opposite sidewall of the second dummy gate structure; A second source and a second drain having a second conductivity type are formed on a side of the second spacer structure away from the second dummy gate structure, penetrating the germanium channel layer and extending into the substrate, wherein the second conductivity type is opposite to the first conductivity type; removing the second dummy gate structure to form a second trench; forming a second stacked structure on the inner wall of the second trench, wherein the second stacked structure includes the second gate dielectric layer, the second interface dipole layer and the second work function layer stacked; The second stacked structure, the second source and the second drain constitute a second transistor.

13. The preparation method according to claim 12, characterized in that: The first conductivity type is P type, the second conductivity type is N type, a first source and a first drain having the first conductivity type are formed on a side of the first sidewall structure away from the first dummy gate structure, and penetrate the germanium channel layer and extend into the substrate, and a second source and a second drain having the second conductivity type are formed on a side of the second sidewall structure away from the second dummy gate structure, and penetrate the germanium channel layer and extend into the substrate, including: forming a first source trench and a first drain trench extending to the substrate in the germanium channel layer on a side of the first spacer structure away from the first dummy gate structure; forming a second source trench and a second drain trench extending to the substrate in the germanium channel layer on a side of the second spacer structure away from the second dummy gate structure; An in-situ doped SiGe source is formed in the first source trench and an in-situ doped SiGe drain is formed in the first drain trench; an in-situ doped SiP source is formed in the second source trench and an in-situ doped SiP drain is formed in the second drain trench.

14. The preparation method according to claim 12, characterized in that: The first gate dielectric layer and the second gate dielectric layer are made of the same material, a first stacked structure is formed on the inner wall of the first trench, and a second stacked structure is formed on the inner wall of the second trench, including: forming a third gate dielectric material layer on the inner wall of the first trench and the inner wall of the second trench, wherein the third dielectric material layer includes a first gate dielectric material layer in a region corresponding to the first transistor and a second gate dielectric material layer in a region corresponding to the second transistor; forming a second interface dipole material layer on the second gate dielectric material layer; forming a first interface dipole material layer on the first gate dielectric material layer; forming a first work function material layer on the first interface dipole material layer; forming a second work function material layer on the second interface dipole material layer; forming a first gate structure in the first trench and a second gate structure in the second trench; Filling the first trench and the second trench to form a third protective material layer; Using a CMP process to remove the third gate dielectric material layer, the first interface dipole material layer, the first work function material layer and the third protective material layer above the first trench, and the third gate dielectric material layer, the second interface dipole material layer, the second work function material layer and the third protective material layer above the second trench, to obtain the first stacked structure, the second stacked structure, the first protective layer and the second protective layer; Wherein, the upper surface of the first gate structure is lower than the opening of the first trench, and the upper surface of the second gate structure is lower than the opening of the second trench.

15. The preparation method according to claim 14, characterized in that: The forming of the second interface dipole material layer on the second gate dielectric material layer comprises: forming a second interface dipole material film layer on the third gate dielectric material layer, and etching and removing the second interface dipole material film layer on the region where the first transistor is located to obtain the second interface dipole material layer; The forming of the first interface dipole material layer on the first gate dielectric material layer comprises: forming a first interface dipole material film layer on the third gate dielectric material layer, and etching and removing the first interface dipole material film layer on the second interface dipole material layer to obtain the first interface dipole material layer; Before forming the first work function material layer on the first interface dipole material layer, the method further includes: forming a work function etching stop layer on the first interface dipole material layer and the second interface dipole material layer; The forming of the first work function material layer on the first interface dipole material layer comprises: forming a first work function material film layer on a substrate, and removing the first work function material film layer on the second interface dipole material layer by etching with a work function etch stop layer as an etch stop layer to obtain the first work function material layer; The forming of the second work function material layer on the second interface dipole material layer includes: forming a second work function material film layer on the substrate, and etching and removing the second work function material film layer on the first work function material layer to obtain the second work function material layer located on the second interface dipole material layer.

16. The preparation method according to claim 8, characterized in that: After forming the first stacked structure on the inner wall of the first groove, the method further includes: forming a first gate structure and a first protection layer in the first trench in sequence; Wherein, the first protection layer fills up the first groove.

17. An electronic device, characterized in that: include: A semiconductor structure as claimed in any one of claims 1 to 6.

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