Adaptive battery usage window for extended battery life

Abstract

Methods and apparatus related to adaptive battery usage windows for extending battery life are described. In an embodiment, a state of charge (SOC) of a rechargeable battery is controlled based on a plurality of limited charging modes that may selectively allow / prevent charging / discharging of the rechargeable battery to target level (s). Other embodiments are also disclosed and claimed.

Description

Technical Field

[0001] The present disclosure relates generally to the field of battery technology. More specifically, some embodiments relate to an adaptive battery usage window for extending battery life. Background Art

[0002] Lithium-ion (Li-ion) batteries are commonly used in various mobile devices (such as laptops, smartphones, smart watches, etc.) and electric vehicles (EVs).

[0003] While such batteries can provide a relatively long battery life or driving range at the beginning of their life cycle, they tend to degrade over time, for example, when repeatedly charged / discharged and / or stored at a high state of charge (SOC) for a relatively long period of time, resulting in a reduction in battery life or driving range over time. Therefore, mitigating battery degradation has become a major goal. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The detailed description is provided with reference to the accompanying drawings. In the drawings, the leftmost digit(s) of a reference number identifies the drawing in which the reference number first appears. The use of the same reference numbers in different drawings indicates similar or identical items.

[0005] Figure 1 FIG. 1 illustrates a block diagram of an apparatus for providing an adaptive battery usage window according to an embodiment.

[0006] Figure 2 An example diagram illustrating a conventional limited charging method compared to normal charging is shown.

[0007] Figure 3 A sample diagram illustrating degradation areas for next generation batteries is shown.

[0008] Figure 4 A diagram illustrating an adaptive battery usage window for extending battery life, according to an embodiment.

[0009] Figure 5 FIGURE 1 illustrates a flow chart of a method for providing an adaptive battery usage window for extending battery life, according to an embodiment.

[0010] Figure 6 An example computing system is illustrated.

[0011] Figure 7 The figure illustrates a block diagram of an example processor and / or System on a Chip (SoC) that may have one or more cores and an integrated memory controller. DETAILED DESCRIPTION

[0012] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. However, the various embodiments may be implemented without these specific details. In other instances, well-known methods, processes, components, and circuits are not described in detail to avoid obscuring the particular embodiments. In addition, various aspects of the embodiments may be performed using various means such as integrated semiconductor circuits ("hardware"), computer-readable instructions organized into one or more programs ("software"), or some combination of hardware and software. For the purposes of this disclosure, references to "logic" shall mean hardware (such as, logic circuitry or more generally, circuitry or circuits), software, firmware, or some combination thereof.

[0013] As mentioned above, mitigating battery degradation has become a primary goal for battery-powered devices. To address this issue, many systems today offer "limited charging," in which the charging system manually or automatically identifies a target level of battery charge (e.g., 60% charge) and avoids full charging or charging to 100%. When limited charging is set, battery charge indicators (such as fully charged battery life or driving range) are based on the limited charge level, rather than the actual full charge / mileage. In addition, while conventional limited charging can extend battery life by avoiding high SOC regions, conventional limited charging is useful for existing lithium-ion batteries, but does not provide an ideal solution for next-generation batteries that also have high-level degradation regions at low SOC.

[0014] To this end, some embodiments provide an adaptive battery usage window for extending battery life. At least one embodiment considers the battery degradation rate by SOC region and adjusts the battery usage window in a limited charge mode to avoid highly degraded regions, including high SOC and low SOC regions. Because such embodiments avoid highly degraded regions in both high and low SOC regions, it is envisioned that they provide better life than conventional limited charging that tends to only consider high SOC degradation regions. In an embodiment, the SOC of a rechargeable battery is controlled based on multiple limited charge modes that can selectively allow / prevent the rechargeable battery from charging / discharging to (one or more) target levels.

[0015] Figure 1 FIG2 shows a block diagram of a device 100 for providing an adaptive battery usage window according to an embodiment. The device 100 may be any type of device having a battery, such as a mobile computing device, including a smartphone, a tablet, a UMPC (Ultra Mobile Personal Computer), a laptop, an ultrabook, or a similar device. TMComputing device, wearable device (such as smart watch, smart ring, smart bracelet or smart glasses), etc. Device 100 can also be an electric vehicle (EV), such as an EV car, truck, motorcycle, scooter, bicycle, drone, airplane, helicopter, ship, boat, etc.

[0016] Reference Figure 1 , the device 100 includes a rechargeable battery 101, a battery microcontroller 102, a computing system 103, a display 104 (e.g., for displaying information about the battery, such as SOC, age, charging period, charging speed, battery temperature, available limited charging modes, selected limited charging mode, etc.), and an interface 105 for a charging cable 106. The charging cable 106 is coupled to a charger 107 that is capable of providing charging (including fast charging) to the battery 101. In some embodiments, the battery 101 and the battery microcontroller 102 are part of a battery unit, where the battery 101 includes a plurality of battery cells electrically connected together. In some embodiments, the battery 101 uses lithium-ion technology. In some embodiments, the microcontroller 102 includes a fuel gauge and logic for adaptive battery usage window charging. In some embodiments, the computing system 103 is as described in reference Figure 6 The system on a chip (or "SoC") described.

[0017] Memory (e.g., provided by computing system 103 and / or separate memory in device 100, or memory coupled to device 100 via a communication channel, such as the cloud, a cellular network, a wireless connection, the Internet, an Internet of Things (IoT) device, etc.) can store various information / data related to battery 101, including limited charging mode profiles, historical data, etc. The stored data can be accessed by battery microcontroller 102 and / or a processor (e.g., in computing system 103) to perform analysis, machine learning / deep learning algorithms, etc. to control the charging of battery 101.

[0018] Furthermore, the device 100 comprises an interface 105 which can be connected to a charging cable 106. The charging cable 106 can be a Universal Serial Bus compatible cable or any other suitable cable. The charging cable 106 is connected to a charger 107 which is capable of supplying an electrical charge.

[0019] In some embodiments, logic circuitry provided in device 100 (such as in microcontroller 102 and / or computing system 103) applies an adaptive battery usage window charging algorithm as discussed herein. In some embodiments, microcontroller 102, computing system 103, and / or software (e.g., executed on microcontroller 102 and / or computing system 103) records the state of charge (SOC) of the battery.

[0020] In some embodiments, the microcontroller 102, the computing system 103, and / or the software changes the charging setting to at least one of the following: adaptive battery usage window charging, limited charging, and / or reduced charging speed. Limited charging is performed to mitigate the negative impact of battery degradation caused by full charging of the battery. Reduced charging speed is performed to mitigate the negative impact of battery degradation caused by fast charging.

[0021] Figure 2 The figure shows an example diagram of a conventional limited charging method compared to normal charging. A lithium-ion battery is normally charged from point A to point B, which is equivalent to a 100% charge. To extend battery life, today's systems can avoid high degradation areas above, for example, 60% SOC, where the degradation rate is higher as the SOC approaches 100%. For example, when the system needs 60%, the system uses 60% between 0% and 60% (points A to C). When 80% is needed, the system uses 80% between 0% and 80%. This means that today's battery life, or the charge percentage in limited charging mode, is calculated from 0% SOC.

[0022] Figure 3 The figure shows a sample graph of degradation regions for next generation batteries. Next generation batteries (such as lithium ion batteries with silicon (Si) anodes) show high degradation regions in both low SOC regions and high SOC regions, such as Figure 3 This is because the silicon anode expands / contracts during charge / discharge, for example, at very low SOC (e.g., below 10%) and very high SOC (e.g., above 90%). This mechanical stress leads to battery degradation in the low SOC region. Generally speaking, Si is currently being considered by the industry because it has greater weight and volume capacity than conventional graphite anodes and is also available at an affordable price. Conventional limited charging methods overlap with the high degradation region in low SOC and cannot provide ideal life extension.

[0023] To this end, at least one embodiment optimizes the battery usage window for extending battery life. More specifically, Figure 4 A diagram illustrating an adaptive battery usage window for extending battery life according to an embodiment is shown. Furthermore, while some embodiments are discussed with reference to Si anodes, the embodiments are not limited to Si anodes, and one or more embodiments may be applied to any battery technology using lithium ions, even for future lithium metal anode batteries.

[0024] like Figure 4As shown, the battery degradation rate is considered not only in the high SOC area, but also in the low SOC area. Then, in the limited charging mode, the battery usage window is adjusted to avoid the high degradation rate area in both high SOC and low SOC, and minimize the degradation rate. For example, when a 60% charge is set in the limited charging mode and the battery has a high degradation area below 20% SOC and greater than 80% SOC, the charging mode is charged to 80% (point Y) so that the usage window is from 20% SOC (point X) to 80% SOC (point Y). In contrast, conventional limited charging will charge the battery to 60%, and the battery usage window will overlap with the high degradation area below 20% SOC.

[0025] In various embodiments, the upper and lower limits of the battery usage window can be determined based on the battery SOC, battery voltage level, and / or charge / discharge capacity. Other factors that may be considered include the age of the battery (e.g., the number of charge / discharge cycles) and / or temperature.

[0026] Figure 5 FIG2 is a flowchart illustrating a method 500 for providing an adaptive battery usage window for extending battery life according to an embodiment. One or more of the operations of the method 500 may be performed by Figure 1 One or more components of the device 100 (such as the battery microcontroller 102) and / or Figure 6 The system 600 may be executed by one or more components (eg, including one or more processors / cores, memories, communication devices, etc.).

[0027] In an embodiment, a plurality of restricted charging modes may be used to indicate various charging limitations (e.g., including low charging threshold levels and / or high charging threshold levels) of a rechargeable battery to implement the present disclosure (e.g., reference to Figure 4 )Use window for discussion.

[0028] Reference Figures 1 to 5 At operation 502, a determination is made as to whether the selected limited charge mode implements a low SOC limit. If so, operation 504 determines whether a low discharge threshold has been reached, and if so, operation 506 prevents further discharge according to the selected limited charge criteria. If a low threshold level has not been selected (as determined at operation 502), operation 508 allows discharge, for example, to 0%. In at least one embodiment, the logic circuitry can adaptively switch between different limited charge modes.

[0029] At operation 510, a determination is made as to whether a threshold is set in the selected limited charging mode to limit the maximum SOC of the battery. If so, operation 512 determines whether a high charge threshold level has been reached, and if so, further charging is prevented. In at least one embodiment, all operations of method 500 are performed by logic circuitry (such as a processor / core of battery microcontroller 102 and / or computing system 103).

[0030] In embodiments, a user (locally or remotely (e.g., via an app)) can manually select a charge percentage to use, or alternatively, an algorithm (e.g., machine learning / deep learning) can automatically specify the charge percentage (e.g., based on a fuel gauge and / or historical usage / charging data).

[0031] In one embodiment, the limited charge mode limits the charge amount and displays a full charge battery indicator (eg, full charge capacity or full charge battery life / driving range) based on the limited charge amount, for example, even when the battery is charged to 80%.

[0032] At least one embodiment considers multiple degradation rates across battery SOC regions and adjusts the battery usage window corresponding to a limited charge capacity to minimize the degradation rate. The algorithm for adjusting the battery usage window can reside in a local system or a remote system. Furthermore, the upper and lower limits of the battery usage window can be based on the battery SOC, battery voltage, and / or charge / discharge capacity.

[0033] In addition, the target charge amount can be specified by the user, a machine learning algorithm (e.g., monitoring battery usage patterns), an information technology (IT) department, etc. In some implementations, limited charging modes can be easily found. For example, Microsoft 11. Displays the smart charging icon in limited charge mode. The "powercfg -batteryreport" command in the command prompt displays the change in battery charge capacity (for example, from 100% charged to 80% charged).

[0034] Furthermore, in at least one embodiment, the priority and / or avoidance amount in the high or low SOC region is determined at least in part based on the degradation rate of the high or low SOC region. For example, if 90-100% SOC will result in the most severe degradation, 0-10% SOC will result in the second most severe degradation, and 80-90% SOC will result in the third most severe degradation, then the embodiment adjusts the use window as follows: (1) when 90% charge is required, the window is 0-90% to avoid the most severe degradation region; (2) when 80% charge is required, the window is 10-90%, further avoiding the second most severe degradation region; (3) when 70% charge is required, the window is 10-80%, further avoiding the third most severe degradation region.

[0035] Additionally, some embodiments may be applied to a computing system including one or more processors (eg, where the one or more processors may include one or more processor cores), such as a computing system described with reference to FIG. Figure 1 and those discussed below, include, for example, desktop computers, workstations, computer servers, server blades, or mobile computing devices. Mobile computing devices may include smartphones, tablets, UMPCs (Ultra Mobile Personal Computers), laptops, ultrabooks, and TM Computing devices, wearable devices (such as smart watches, smart rings, smart bracelets or smart glasses), etc. Example computer architecture

[0036] The following describes an example computer architecture. Other system designs and configurations known in the art for laptops, desktop computers, handheld personal computers (PCs), personal digital assistants, engineering workstations, servers, disaggregated servers, network devices, network hubs, switches, routers, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular phones, portable media players, handheld devices, and various other electronic devices are also suitable. In general, various systems or electronic devices that can include a processor and / or other execution logic as disclosed herein are generally suitable.

[0037] Figure 6The figure illustrates an example computing system. Multiprocessor system 800 is an interface system and includes multiple processors or cores, including a first processor 870 and a second processor 880 coupled via an interface 850 such as a point-to-point (PP) interconnect, a fabric, and / or a bus. In some examples, the first processor 870 and the second processor 880 are isomorphic. In some examples, the first processor 870 and the second processor 880 are heterogeneous. Although example system 800 is shown as having two processors, the system can have three or more processors, or can be a single processor system. In some examples, the computing system is a system on chip (SoC).

[0038] Processors 870 and 880 are shown as including integrated memory controller (IMC) circuitry 872 and 882, respectively. Processor 870 also includes interface circuits 876 and 878; similarly, second processor 880 includes interface circuits 886 and 888. Processors 870, 880 can exchange information via interface 850 using interface circuits 878, 888. IMCs 872 and 882 couple processors 870, 880 to respective memories, namely, memory 832 and memory 834, which may be portions of main memory locally attached to the respective processors.

[0039] Processors 870, 880 can each exchange information with a network interface (NW I / F) 890 via separate interfaces 852, 854 using interface circuits 876, 894, 886, 898. Network interface 890 (e.g., one or more of an interconnect, bus, and / or fabric, and in some examples, a chipset) can optionally exchange information with a coprocessor 838 via interface circuit 892. In some examples, coprocessor 838 is a special-purpose processor, such as, for example, a high-throughput processor, a network or communication processor, a compression engine, a graphics processor, a general-purpose graphics processing unit (GPGPU), a neural-network processing unit (NPU), an embedded processor, or the like.

[0040] A shared cache (not shown) may be included in any processor 870, 880, or external to both processors but connected to these processors via an interface (such as a PP interconnect) so that if the processor is placed in a low power mode, the local cache information of either or both processors can be stored in the shared cache.

[0041] The network interface 890 can be coupled to the first interface 816 via the interface circuit 896. In some examples, the first interface 816 can be an interface such as a Peripheral Component Interconnect (PCI) interconnect, a PCI Express interconnect, or another I / O interconnect. In some examples, the first interface 816 is coupled to a power control unit (PCU) 817, which can include circuitry, software, and / or firmware for performing power management operations related to the processors 870, 880, and / or the coprocessor 838. The PCU 817 provides control information to a voltage regulator (not shown) so that the voltage regulator generates an appropriate regulated voltage. The PCU 817 also provides control information to control the generated operating voltage. In various examples, the PCU 817 can include various power management logic units (circuitry) for performing hardware-based power management. Such power management may be entirely controlled by the processor (e.g., by various processor hardware, and which may be triggered by workload and / or power, thermal constraints, or other processor constraints), and / or power management may be performed in response to an external source (such as a platform or power management source or system software).

[0042] The PCU 817 is illustrated as existing as logic separate from the processor 870 and / or the processor 880. In other cases, the PCU 817 may execute on a given one or more cores (not shown) of the processor 870 or 880. In some cases, the PCU 817 may be implemented as a (dedicated or general-purpose) microcontroller or other control logic configured to execute its own dedicated power management code (sometimes referred to as P-code). In still other examples, the power management operations to be performed by the PCU 817 may be implemented external to the processor, such as by way of a separate power management integrated circuit (PMIC) or another component external to the processor. In still other examples, the power management operations to be performed by the PCU 817 may be implemented within the BIOS or other system software.

[0043] Various I / O devices 814 can be coupled to the first interface 816 along with a bus bridge 818, which couples the first interface 816 to the second interface 820. In some examples, one or more additional processors 815 (such as a coprocessor, a high-throughput many integrated core (MIC) processor, a GPGPU, an accelerator (such as a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array (FPGA), or any other processor) are coupled to the first interface 816. In some examples, the second interface 820 can be a low pin count (LPC) interface. Various devices can be coupled to the second interface 820, including, for example, a keyboard and / or mouse 822, a communication device 827, and a storage circuit system 828. The storage circuit system 828 can be one or more non-transitory machine-readable storage media, such as a disk drive or other mass storage device, as described below, which in some examples can include instructions / code and data 830 and can implement the storage of one or more instructions. Further, audio I / O 824 may be coupled to second interface 820. Note that other architectures are possible besides the point-to-point architecture described above. For example, a system such as multiprocessor system 800 may implement a multi-drop interconnect or other such architecture rather than a point-to-point architecture. Example core architectures, processors, and computer architectures

[0044] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) a general-purpose in-order core intended for general-purpose computing; 2) a high-performance general-purpose out-of-order core intended for general-purpose computing; 3) a specialized core intended primarily for graphics and / or scientific (throughput) computing. Different processor implementations may include: 1) a CPU that includes one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor that includes one or more specialized cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors lead to different computer system architectures, which can include: 1) a coprocessor on a separate chip from the CPU; 2) a coprocessor in the same package as the CPU but on a separate die; 3) a coprocessor on the same die as the CPU (in which case such coprocessors are sometimes referred to as dedicated logic or as dedicated cores, such as integrated graphics and / or scientific (throughput) logic); and 4) a system on a chip (SoC), which can include the described CPU (sometimes referred to as application core(s) or application processor(s), the coprocessor described above, and additional functionality on the same die. An example core architecture is described next, followed by a description of an example processor and computer architecture.

[0045] Figure 7 The figure shows a block diagram of an example processor and / or SoC 900 that may have one or more cores and an integrated memory controller. The solid line block diagram shows a processor 900 having a single core 902(A), a system agent unit circuitry 910, and a collection of one or more interface controller unit circuitry 916, while the optional addition of dashed line blocks shows an alternative processor 900 having multiple cores 902(A)-(N), a collection of one or more integrated memory controller units 914 in the system agent unit circuitry 910, and dedicated logic 908 and a collection of one or more interface controller unit circuitry 916. Note that the processor 900 may be Figure 6 processors 870 or 880, or one of the coprocessors 838 or 815.

[0046] Thus, different implementations of processor 900 may include: 1) a CPU, wherein dedicated logic 908 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 902(A)-(N) are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination of the two); 2) a coprocessor, wherein cores 902(A)-(N) are a large number of dedicated cores intended primarily for graphics and / or scientific (throughput); and 3) a coprocessor, wherein cores 902(A)-(N) are a large number of general-purpose in-order cores. Thus, processor 900 may be a general-purpose processor, a coprocessor, or a dedicated processor, such as, for example, a network or communications processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput many-integrated-core (MIC) coprocessor (including 30 or more cores), an embedded processor, or the like. The processor may be implemented on one or more chips. Processor 900 may be part of and / or implemented on one or more substrates using any of a variety of process technologies, such as, for example, complementary metal-oxide-semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0047] The memory hierarchy includes one or more levels of cache unit circuitry 902(A)-(N) within cores 904(A)-(N), a set of one or more shared cache unit circuitry 906, and external memory (not shown) coupled to a set of integrated memory controller unit circuitry 914. The set of one or more shared cache unit circuitry 906 may include one or more intermediate levels of cache (such as level 2 (L2), level 3 (L3), level 4 (L4)) or other levels of cache (such as last level cache (LLC)), and / or combinations thereof. While in some examples, an interface network circuitry 912 (e.g., a ring interconnect) provides an interface to dedicated logic 908 (e.g., integrated graphics logic), the set of one or more shared cache unit circuitry 906, and the system agent unit circuitry 910, alternative examples use any number of well-known techniques for providing interfaces to such units. In some examples, coherency is maintained between the shared cache unit circuitry(s) 906 and one or more of the cores 902(A)-(N). In some examples, the interface controller unit circuitry 916 couples the cores 902 to one or more other devices 918, such as one or more I / O devices, storage, one or more communication devices (e.g., a wireless network, a wired network, etc.), and the like.

[0048] In some examples, one or more of the cores 902(A)-(N) can be multithreaded. System agent unit circuitry 910 includes components that coordinate and operate the cores 902(A)-(N). System agent unit circuitry 910 may include, for example, power control unit (PCU) circuitry and / or display unit circuitry (not shown). The PCU may be, or may include, the logic and components required to regulate the power state of the cores 902(A)-(N) and / or the dedicated logic 908 (e.g., integrated graphics logic). The display unit circuitry is used to drive one or more externally connected displays.

[0049] The cores 902(A)-(N) may be homogeneous in terms of instruction set architecture (ISA). Alternatively, the cores 902(A)-(N) may be heterogeneous in terms of ISA; that is, a subset of the cores 902(A)-(N) may be capable of executing an ISA, while other cores may only be capable of executing a subset of that ISA or another ISA.

[0050] In this description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to one skilled in the art that the embodiments described herein can be practiced without one or more of these specific details. In other instances, well-known features are not described in order to avoid obscuring the details of the present embodiments.

[0051] The following examples relate to further embodiments. Example 1 includes an apparatus comprising: a memory for storing data associated with a rechargeable battery; and logic circuitry for controlling a state of charge (SOC) of the rechargeable battery based on a plurality of limited charging modes, the logic circuitry for preventing the rechargeable battery from discharging below a low threshold level during a first limited charging mode of the plurality of limited charging modes, and the logic circuitry for allowing the rechargeable battery to discharge below the low threshold level during a second limited charging mode of the plurality of limited charging modes, wherein the logic circuitry is for adaptively adjusting a usage window of the rechargeable battery based at least in part on the first limited charging mode and the second limited charging mode.

[0052] Example 2 includes the apparatus of Example 1, wherein the logic circuitry adaptively switches between the first limited charging mode and the second limited charging mode based at least in part on a state of a select signal. Example 3 includes the apparatus of Example 2, wherein the select signal is generated in response to at least one of a user input, a remote system input, an information technology department input, or a machine learning algorithm input. Example 4 includes the apparatus of Example 3, wherein the machine learning algorithm input is generated based at least in part on monitoring a usage pattern of the rechargeable battery. Example 5 includes the apparatus of Example 1, wherein the logic circuitry is configured to prevent the rechargeable battery from charging above a high threshold level during the first limited charging mode or the second limited charging mode. Example 6 includes the apparatus of Example 1, wherein the stored data includes at least one of data associated with the plurality of limited charging modes, historical data, or data generated by a machine learning algorithm. Example 7 includes the apparatus of Example 6, wherein the historical data includes data corresponding to at least one of operation, usage, a timestamp, a charge state, charging, or discharging of the rechargeable battery.

[0053] Example 8 includes the apparatus of Example 1, wherein the logic circuitry is configured to prevent the rechargeable battery from charging above a high threshold level, wherein the low threshold level and the high threshold level are determined based at least in part on at least one of the SOC of the rechargeable battery, the voltage level of the rechargeable battery, or the age of the rechargeable battery. Example 9 includes the apparatus of Example 8, wherein the age of the rechargeable battery is determined based on at least one of the number of charge / discharge cycles performed by the rechargeable battery, the state of health of the rechargeable battery, or the fully charged capacity of the rechargeable battery. Example 10 includes the apparatus of Example 1, wherein the logic circuitry is configured to prevent the rechargeable battery from charging above a high threshold level, wherein the battery indicator is configured to indicate a charge level compared to a capacity of an adjusted window of use of the rechargeable battery. Example 11 includes the apparatus of Example 1, wherein the priority or avoidance amount in a high or low SOC region is determined based at least in part on a degradation rate of the high or low SOC region.

[0054] Example 12 includes one or more non-transitory computer-readable media comprising one or more instructions that, when executed on a processor, configure the processor to perform one or more operations to: store data associated with a rechargeable battery; and control a state of charge (SOC) of the rechargeable battery based on a plurality of limited charge modes, wherein during a first limited charge mode of the plurality of limited charge modes, the rechargeable battery is prevented from discharging below a low threshold level, and wherein during a second limited charge mode of the plurality of limited charge modes, the rechargeable battery is allowed to discharge below the low threshold level, wherein the processor is configured to adaptively adjust a usage window of the rechargeable battery based at least in part on the first limited charge mode and the second limited charge mode. Example 13 includes the one or more computer-readable media of Example 12, further comprising one or more instructions that, when executed on the processor, configure the processor to perform one or more operations to cause adaptive switching between the first limited charge mode and the second limited charge mode based at least in part on a state of a select signal.

[0055] Example 14 includes the one or more computer-readable media of Example 13, further comprising one or more instructions that, when executed on the processor, configure the processor to perform one or more operations to cause the generation of the selection signal in response to at least one of user input, remote system input, information technology department input, or machine learning algorithm input. Example 15 includes the one or more computer-readable media of Example 14, further comprising one or more instructions that, when executed on the processor, configure the processor to perform one or more operations to cause the machine learning algorithm input to be generated based at least in part on monitoring a usage pattern of the rechargeable battery.

[0056] Example 16 includes the one or more computer-readable media of Example 12, further comprising one or more instructions that, when executed on the processor, configure the processor to perform one or more operations to prevent the rechargeable battery from charging above a high threshold level during the first limited charging mode or the second limited charging mode. Example 17 includes the one or more computer-readable media of Example 12, wherein the stored data includes at least one of data associated with the plurality of limited charging modes, historical data, or data generated by a machine learning algorithm. Example 18 includes the one or more computer-readable media of Example 17, wherein the historical data includes data corresponding to at least one of operation, usage, timestamp, charge state, charging, or discharging of the rechargeable battery.

[0057] Example 19 includes the one or more computer-readable media of Example 12, further comprising one or more instructions that, when executed on the processor, configure the processor to perform one or more operations to prevent the rechargeable battery from charging above a high threshold level, wherein the low threshold level and the high threshold level are determined based at least in part on at least one of: an SOC of the rechargeable battery, a voltage level of the rechargeable battery, or an age of the rechargeable battery. Example 20 includes the one or more computer-readable media of Example 12, further comprising one or more instructions that, when executed on the processor, configure the processor to perform one or more operations to determine the age of the rechargeable battery based on at least one of: a number of charge / discharge cycles performed by the rechargeable battery, a state of health of the rechargeable battery, or a fully charged capacity of the rechargeable battery.

[0058] Example 21 includes an apparatus comprising means for performing a method as set forth in any of the preceding examples. Example 22 includes a machine-readable storage device comprising machine-readable instructions that, when executed, are used to implement any of the methods set forth in any of the preceding examples or to implement any of the apparatuses set forth in any of the preceding examples.

[0059] In each embodiment, reference Figure 1 One or more operations discussed in

[0044] and below, etc., may be performed by one or more components (interchangeably referred to herein as "logic") discussed with reference to any of the figures.

[0060] In some embodiments, herein (e.g., with reference to Figure 1 The operations discussed in the accompanying drawings and the following figures) may be implemented as hardware (e.g., logic circuitry), software, firmware, or a combination thereof, which may be provided as a computer program product, for example, comprising one or more tangible (e.g., non-transitory) machine-readable or computer-readable media having stored thereon instructions (or software programs) for programming a computer to perform the processes discussed herein. The machine-readable medium may include storage devices such as those discussed with reference to the accompanying figures.

[0061] Further, while various embodiments described herein use the term system on a chip or system on a chip ("SoC" or "SOC") to describe devices and systems having a processor and associated circuitry (e.g., input / output ("I / O") circuitry, power delivery circuitry, memory circuitry, etc.) monolithically integrated into a single integrated circuit ("Integrated Circuit," "IC") die or chip, the present disclosure is not limited in this respect. For example, in various embodiments of the present disclosure, a device or system may have one or more processors (e.g., one or more processor cores) and associated circuitry (e.g., input / output ("I / O") circuitry, power delivery circuitry, etc.) arranged in a disaggregated collection of discrete dies, chips, and / or chiplets (e.g., one or more discrete processor core dies arranged adjacent to one or more other dies (such as a memory die, I / O die, etc.)). In such disaggregated devices and systems, the individual dies, slices, and / or chiplets may be physically and / or electrically coupled together through a packaging structure including, for example, individual package substrates, interposers, active interposers, photonic interposers, interconnect bridges, etc. The disaggregated collection of discrete dies, slices, and / or chiplets may also be part of a system on a package (“SoP”).

[0062] Additionally, such computer-readable media may be downloaded as a computer program product, where the program may be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a data signal provided in a carrier wave or other propagation medium, via a communication link (e.g., a bus, a modem, or a network connection).

[0063] References in this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, and / or characteristic described in connection with the embodiment may be included in at least one implementation. The appearances of the phrase "in one embodiment" in various places in this specification may or may not all refer to the same embodiment.

[0064] Furthermore, in the specification and claims, the terms "coupled" and "connected," and their derivatives, may be used. In some embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements may not be in direct contact with each other, but may still cooperate or interact with each other.

[0065] Thus, although various embodiments have been described using language specific to structural features and / or methodological acts, it will be understood that the claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as sample forms of implementing the claimed subject matter.

Claims

1. An apparatus for providing an adaptive battery usage window for extending battery life, the apparatus comprising: a memory for storing data associated with the rechargeable battery; as well as a logic circuit system for controlling the state of charge (SOC) of the rechargeable battery based on a plurality of limited charging modes, The logic circuitry is for preventing the rechargeable battery from discharging below a low threshold level during a first limited charging mode of the plurality of limited charging modes, and the logic circuitry being operable to allow the rechargeable battery to discharge below the low threshold level during a second limited charging mode of the plurality of limited charging modes, The logic circuitry is configured to adaptively adjust a usage window of the rechargeable battery based at least in part on the first limited charging mode and the second limited charging mode.

2. The device according to claim 1, characterized in that The logic circuitry adaptively switches between the first limited charging mode and the second limited charging mode based at least in part on a state of a select signal.

3. The device according to claim 2, characterized in that The selection signal is to be generated in response to at least one of a user input, a remote system input, an information technology department input, or a machine learning algorithm input.

4. The device according to claim 3, characterized in that The machine learning algorithm input is to be generated based at least in part on monitoring usage patterns of the rechargeable battery.

5. The device according to claim 1, characterized in that The logic circuitry is for preventing the rechargeable battery from charging above a high threshold level during the first limited charging mode or the second limited charging mode.

6. The device according to claim 1, characterized in that The stored data includes at least one of data associated with the plurality of limited charging modes, historical data, or data generated by a machine learning algorithm.

7. The device according to claim 6, characterized in that The historical data includes data corresponding to at least one of operation, usage, timestamp, charging state, charging, or discharging of the rechargeable battery.

8. The device according to claim 1, characterized in that The logic circuit system is used to prevent the rechargeable battery from charging above a high threshold level, wherein the low threshold level and the high threshold level are determined at least in part based on at least one of: the SOC of the rechargeable battery, the voltage level of the rechargeable battery, or the age of the rechargeable battery.

9. The device according to claim 8, characterized in that The age of the rechargeable battery is to be determined based on at least one of: a number of charge / discharge cycles performed by the rechargeable battery, a state of health of the rechargeable battery, or a fully charged capacity of the rechargeable battery.

10. The device according to claim 1, characterized in that The logic circuitry is for preventing the rechargeable battery from charging above a high threshold level, wherein a battery indicator is for indicating a charge level compared to a capacity of an adjusted window of use of the rechargeable battery.

11. The device according to claim 1, characterized in that The priority or avoidance amount in a high or low SOC region is to be determined based at least in part on the degradation rate of the high or low SOC region.

12. A method for providing an adaptive battery usage window for extending battery life, the method comprising: storing data associated with the rechargeable battery; as well as controlling a state of charge (SOC) of the rechargeable battery based on a plurality of limited charging modes, wherein during a first limited charging mode of the plurality of limited charging modes the rechargeable battery is prevented from discharging below a low threshold level, wherein during a second limited charging mode of the plurality of limited charging modes the rechargeable battery is allowed to discharge below the low threshold level, The processor is configured to adaptively adjust a usage window of the rechargeable battery based at least in part on the first limited charging mode and the second limited charging mode.

13. The method of claim 12, further comprising causing adaptive switching between the first limited charging mode and the second limited charging mode based at least in part on a state of a select signal.

14. The method of claim 13, further comprising generating the selection signal in response to at least one of a user input, a remote system input, an information technology department input, or a machine learning algorithm input.

15. The method of claim 14, further comprising causing the machine learning algorithm input to be generated based at least in part on monitoring usage patterns of the rechargeable battery.

16. The method of claim 12, further comprising preventing the rechargeable battery from charging above a high threshold level during the first limited charging mode or the second limited charging mode.

17. The method according to claim 12, characterized in that The stored data includes at least one of data associated with the plurality of limited charging modes, historical data, or data generated by a machine learning algorithm.

18. The method according to claim 17, characterized in that The historical data includes data corresponding to at least one of operation, usage, timestamp, charging state, charging, or discharging of the rechargeable battery.

19. The method of claim 12, further comprising preventing the rechargeable battery from charging above a high threshold level, wherein the low threshold level and the high threshold level are to be determined at least in part based on at least one of: an SOC of the rechargeable battery, a voltage level of the rechargeable battery, or an age of the rechargeable battery.

20. The method of claim 12, further comprising determining the age of the rechargeable battery based on at least one of: a number of charge / discharge cycles performed by the rechargeable battery, a state of health of the rechargeable battery, or a fully charged capacity of the rechargeable battery.

21. A machine-readable medium comprising code which, when executed, causes a machine to perform the operations of any one of claims 12 to 20.

22. An apparatus comprising means for performing the operations of any one of claims 12 to 20.

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