SYSTEM AND METHOD FOR SOFT STARTING A Constant ON-TIME POWER CONVERTER

Abstract

The invention relates to a system and method for soft start of a constant on-time power converter. In accordance with an embodiment, a method for controlling a constant on-time switched mode power converter includes: generating a pulsed signal having an on-time; continuously increasing the turn-on time from an initial duration to a final duration during a soft start phase of the power converter, where the final duration is greater than the initial duration; sensing an output voltage of the power converter and generating a feedback signal proportional to the output voltage; adjusting a frequency of the pulse signal based on the feedback signal and the reference signal; and driving the power switch by using the pulse signal to control the power switch and adjust the output voltage.

Description

Technical Field

[0001] The present invention relates generally to systems and methods and, in particular embodiments, to systems and methods for constant on-time power converters. Background Art

[0002] Switched mode power converters (SMPCs) or switched mode power supplies (SMPSs) play a key role in many electronic devices, primarily because they provide tightly regulated output voltages with excellent efficiency. Regulation of output power in these converters is achieved by rapidly switching the power transistors between on and off states. The power delivered to the load is managed by the frequency or duty cycle of this switching.

[0003] The constant on-time (COT) control scheme employed in various types of SMPS is recognized for its fast transient response, uncomplicated structure, and stability over a wide input voltage range. In a COT converter, a fixed on-time period of the switching transistor is maintained, while the off-time, defined by the self-oscillating nature of the system, is adjusted to regulate the output voltage according to the input voltage and load conditions. COT converters find use in a wide range of applications, including but not limited to consumer electronics, automotive electronics, telecommunications, and industrial automation where small, efficient, and responsive power conversion is essential.

[0004] However, conventional COT converters often encounter some challenges, especially during the soft-start phase, which is a transition period when the converter changes from a non-operating state to an operating state. During the transition period, the power converter generates a switching signal to increase the output voltage of the power converter from an inactive voltage (such as ground) to its target voltage. In this phase, the converter must quickly reach a stable operating state without causing destructive voltage overshoot or excessive settling time.

[0005] One problem encountered during the soft-start phase of conventional COT converters involves the occurrence of current transients. Current transients are momentary surges or spikes in current that occur when the converter switches from one state to another, such as during soft-start. These transients can have potentially harmful effects on overall system operation, including electromagnetic interference, thermal stress on components, and undesirable voltage fluctuations, resulting in power supply instability.

[0006] Furthermore, these current transients may become more severe in certain soft-start scenarios, such as when the output voltage is high and / or the converter includes an inductor with a low inductance value and the converter is operating at a high duty cycle (typically occurring during soft-start when the input voltage is very close to the output voltage of the converter). In such cases, these transients may result in an overcurrent condition, potentially damaging the converter and the connected load. Thus, effectively managing these current transients, particularly during soft-start, presents considerable challenges to conventional COT power converters. Summary of the invention

[0007] According to an embodiment, a method for controlling a constant on-time switch mode power converter includes: generating a pulse signal having an on-time; during a soft start phase of the power converter, continuously increasing the on-time from an initial duration to a final duration, wherein the final duration is greater than the initial duration; sensing an output voltage of the power converter and generating a feedback signal proportional to the output voltage; adjusting the frequency of the pulse signal based on the feedback signal and a reference signal; and driving a power switch using the pulse signal to control the power switch and regulate the output voltage.

[0008] According to another embodiment, a switch-mode power converter includes: a feedback processing circuit having an input terminal coupled to an output node of the switch-mode power converter; an on-time timer coupled to an output terminal of the feedback processing circuit, the on-time timer being configured to generate a pulse having an on-time duration based on the value of a signal applied to an on-time duration control port; and a first ramp signal generator having an output terminal coupled to the on-time duration control port, the first ramp signal generator being configured to generate a ramp reference signal during a soft start phase of the switch-mode power converter and to generate a substantially constant reference signal during normal operation of the switch-mode power converter.

[0009] According to another embodiment, a switch-mode power converter includes: a reference signal generator, which is configured to generate a ramp reference signal during a soft start phase of the switch-mode power converter and to generate a substantially constant reference signal during normal operation of the switch-mode power converter; a half-bridge circuit, which has an input terminal coupled to a power supply input node and an output terminal coupled to an output terminal of the switch-mode power converter; a gate driver, which is coupled to a control input terminal of the half-bridge circuit; a feedback processing circuit, which has a first input terminal coupled to the output terminal of the switch-mode power converter and a second input terminal coupled to the output terminal of the reference signal generator, the feedback processing circuit being configured to generate a trigger signal having a frequency based on a difference between a signal at the output terminal of the reference signal generator and a signal at the output terminal of the switch-mode power converter; and a first pulse generator, which is coupled to the output terminal of the feedback processing circuit, and the first pulse generator is configured to generate a pulse having an on-time duration based on the value of the signal at the output terminal of the reference signal generator. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1A depicts a constant on-time power converter according to an embodiment of the present invention; and Figure 1B , Figure 1C and Figure 1D Depicted diagram Figure 1A A waveform diagram of the operation of a constant on-time power converter;

[0012] Figure 2A depicts a constant on-time power converter according to another embodiment of the present invention; Figure 2B and Figure 2C It is a graphic Figure 2A A waveform diagram of the operation of a constant on-time power converter; Figure 2D depicts a constant on-time power converter according to another embodiment of the present invention; Figure 2E It is a graphic Figure 2D A waveform diagram of the operation of a constant on-time power converter; and Figure 2F It is a graphic Figure 1A , Figure 2A and Figure 2D A waveform diagram of the operation of a constant on-time power converter;

[0013] Figure 3A and Figure 3B shows a schematic diagram depicting a circuit level implementation of an embodiment circuit, Figure 3C It is shown Figure 3A and Figure 3B The waveform / timing diagram of the circuit's operation, and Figure 3D and Figure 3E illustrates schematic diagrams depicting circuit level implementations of other embodiment circuits; and

[0014] Figure 4 A flow chart of a method according to an embodiment of the present invention is illustrated.

[0015] Unless otherwise indicated, corresponding numbers and symbols in the different drawings generally refer to corresponding parts. The drawings are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. To more clearly illustrate certain embodiments, letters indicating variations of the same structure, material, or processing step may follow the figure number. DETAILED DESCRIPTION

[0016] The making and use of the currently preferred embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be implemented in various specific contexts. The specific embodiments discussed only illustrate specific ways to make and use the present invention and do not limit the scope of the present invention.

[0017] In various embodiments, during startup of a switch-mode power converter, internal circuit systems such as an internal power regulator begin operation during a first phase of startup (also referred to as an initial power-on phase). Other components within the switch-mode power converter may also be disabled during this first phase of startup. Once the internal power regulator (e.g., a linear regulator) has reached its required operating voltage, the second phase of startup (referred to herein as "soft start") begins. One of the purposes of the second phase of startup is to allow the switch-mode power converter to reach its nominal operating condition in a predictable and controlled manner. In some embodiments, the first phase may last from several hundred microseconds to several milliseconds. The second phase (soft start) following the first phase may last between 2ms and 5ms. It should be understood that these times are examples only, and the actual amount of time spent in each phase may vary.

[0018] In some embodiments, when the output of the internal power regulator has reached a predetermined voltage, the transition from the first stage to the soft start stage can be triggered. In addition, in some cases, the soft start stage of the power supply can be triggered in other situations. For example, when the temperature of the power supply exceeds a first predetermined temperature measured by a temperature sensor circuit, the power supply can be turned off until the temperature drops below a second predetermined temperature (which may be different from the first predetermined temperature or may be the same as the first predetermined temperature). Once the measured temperature drops below the second predetermined temperature, the power supply is restarted by initializing the soft start stage of the power supply. In some embodiments, the power supply is not turned off until the temperature exceeds the first predetermined temperature for a predetermined time period measured, for example, by a timer circuit such as a counter. In some cases, the internal power regulator can remain active during the time when the power converter is shut down during this over-temperature condition.

[0019] In some embodiments, the power converter may be disabled when the output voltage of the internal power supply drops below a first predetermined voltage threshold measured by a voltage sensor such as a comparator. This may occur even when the internal power regulator is still active. Once the output voltage of the internal power supply reaches a second voltage threshold (which may be the same as or different from the first voltage threshold), the soft start mode may be triggered. In some embodiments, the power converter is disabled after the voltage of the internal power supply drops below the first predetermined voltage threshold for a predetermined period of time measured by a timer circuit such as a counter.

[0020] Embodiments of the present invention relate to constant on-time switch mode power converters. In one embodiment, during the soft start (or startup) of the switch mode power converter, the pulse width of the constant on-time pulse is gradually increased from a narrow pulse width to a wider pulse width. This gradual increase in pulse width can advantageously help reduce or prevent large current transients or output current spikes during the soft start period of the converter. As mentioned above, during the soft start period, the power converter generates a switching signal to increase the output voltage of the power converter from an inactive voltage (such as ground) to its target voltage. In addition, in some embodiments, the switching frequency of the pulse can be limited during the soft start, which further saves energy, mitigates current transients, and facilitates a more consistent output voltage trajectory.

[0021] Figure 1AA constant on-time power converter 100 is depicted, which includes a feedback processing circuit 102, an on-time timer 112 (also referred to as a pulse generator or pulse generating circuit), a gate driver 114 (also referred to as a driver circuit), a switching circuit 115, a feedback network 124, and a soft start timer 101 (also referred to as a ramp signal generator or reference signal generator). During nominal operation, the feedback processing circuit 102 generates a periodic trigger signal Cmp, the frequency of which is proportional to the difference between a reference voltage Vref (also referred to as a ramp reference signal) generated by the soft start timer 101 and a feedback voltage Vfb. Whenever the trigger signal Cmp is asserted, the on-time timer 112 generates a pulse signal TON with a fixed pulse width at a signal node TON. The gate driver 114 drives the switching circuit 115 according to the pulse signal TON to provide an output current Iout at an output node Vout that passes through an inductor 120 to a load 128. A capacitor 122 may be employed to smooth the output voltage Vout. The optional feedback network 124 regulates the output voltage Vout to generate a feedback signal Vfb. The feedback network 124 may be implemented using, for example, a resistive voltage divider, or isolation may be provided by an opto-isolator.

[0022] Feedback processing circuit 102 includes error amplifier 106, ramp generator 104, summator 108 and comparator 110. During operation, error amplifier 106 compares reference voltage Vref and feedback voltage Vfb to generate error signal Ve. In some embodiments, error amplifier 106 can be implemented with a transconductance amplifier. In such an embodiment, a capacitor 109 connected to the output of the amplifier can be used as an integration capacitor. Ramp generator 104 generates a ramp signal Vr, which is combined with error signal Ve to form a summation signal Vx. Comparator 110 is used to compare the summation signal Vx with feedback signal Vfb to generate trigger signal Cmp. In some cases, trigger signal Cmp is provided to ramp generator 104 to reset ramp signal Vr. In the illustrated embodiment, the combination of error amplifier 106 and capacitor 109 effectively adds integration to the control loop of power converter 100 and increases the steady-state accuracy of the loop. However, in an alternative embodiment of the present invention, the error amplifier and capacitor 109 may be omitted, so that the reference voltage Vref is connected to the left input of the summer 108 instead of the error voltage Ve.

[0023] Figure 1BThe waveform diagram detailing the operation of the switch mode power converter 100 is shown, which shows the feedback voltage Vfb, the signal Vx (the sum of the error voltage Ve and the ramp voltage Vr), the trigger signal Cmp generated by the comparator 110, and the constant width pulse signal TON. When the signal Vx reaches the feedback voltage Vfb, the comparator 110 generates the trigger signal Cmp at time 132. This signal prompts the on-time timer 113 to generate a pulse with a width t p The pulse signal TON of the comparator 110 is reset, and the ramp generator 104 is reset to generate a new ramp. The reset ramp generator also resets the signal Vx, so that the output Cmp of the comparator 110 becomes low again.

[0024] As depicted, when the pulse signal TON is high, the output current Iout flowing through the inductor 120 increases linearly, and when the pulse signal TON is low, the output current Iout decreases linearly. Operation continues in a similar manner during nominal operation of the switch mode power converter 100 .

[0025] Return to reference Figure 1A , the switch circuit 115 includes a high-side transistor 116 and a low-side transistor 118 forming a half-bridge circuit. Although these transistors are shown as NMOS devices, other transistor types such as BJT, PMOS, IGBT, GaN and SiC can be used. The gate driver 114 can be implemented using gate driver circuits known in the art, and its implementation can vary based on the topology of the switch circuit 115, the type of switching transistors used, and the specifications and architecture of the switch mode power converter 100. Although a buck-type topology is illustrated, embodiments of the present invention can be configured as other types of switch mode power converters like boost or buck-boost converters.

[0026] In one embodiment, the soft start timer 101 generates a reference voltage that increases linearly during the soft start of the switch mode power converter 100 and maintains a substantially constant value under normal operation. By providing an increased reference voltage to the feedback processing circuit 102, the output Vout of the switch mode power converter 100 is ostensibly configured to increase in a controlled ramp manner. However, under certain conditions, the nominal pulse width provided by the on-time timer 112 may initially cause a high output current Iout during the soft start of the power converter. For example, this phenomenon may occur when the gate driver 114 activates the transistor 116 and the capacitor 122 is in its discharge state. In essence, this action applies the entire input voltage Vin to the inductor, resulting in a current Iout that increases as the inductor 120 charges / magnetizes.

[0027] In an embodiment of the present invention, the pulse width provided by the on-time timer 112 is limited during the soft start phase of the switch mode power converter 100. The limited pulse width effectively limits the current conducted by the inductor 120. In some embodiments, the pulse width of the pulse signal TON provided by the on-time timer gradually increases from an initial small value to its nominal value during normal operation. In this case, the on-time timer 112 can be designed to provide a pulse signal with an adjustable pulse width. In the illustrated embodiment, the on-time timer 112 generates an adjustable pulse width based on a signal provided to the on-time duration control port 113. In the illustrated example, the reference voltage Vref from the soft start timer 101 is supplied to the on-time duration control port, so that the pulse width provided by the on-time timer 112 can be increased according to the reference voltage Vref provided to the feedback processing circuit 102. In an alternative embodiment, the signal provided at the on-time duration control port can be separated from the signal supplied to the feedback processing circuit 102.

[0028] Figure 1C 1 shows a waveform diagram representing a reference signal Vref generated by the soft start timer 101 and a pulse signal TON generated by the on-time timer 113 during soft start and normal operation. As shown, during the soft start phase, the reference voltage Vref increases linearly from an initial voltage Vinit to its final nominal voltage Vnom within a soft start period tss and is used as a ramp reference signal. In some embodiments, the soft start period tss may last for a few milliseconds, for example, less than 5ms; however, in some embodiments, depending on the specific application and its specifications, the soft start period tss may be 5ms or more. At the same time, the pulse width of the pulse signal TON increases from an initial pulse width t i Increase to the final fixed pulse width t p During nominal operation, indicated as time tnom, the reference voltage Vref remains substantially fixed at the voltage Vnom to form a constant reference signal, and the pulse width of the pulse signal TON remains substantially constant at t p .

[0029] The initial pulse width t of the pulse signal TON may be selected according to the specific power converter system and its specifications. i and the final pulse width t p In one example, the initial pulse width t of the pulse signal TON is i is greater than zero (e.g., 40 ns to 60 ns), and the final pulse width of the signal t pBetween 50ns and 100μs. For example, in the case where the conversion uses a minimum on-time during a steady-state condition that may occur under high input voltage conditions while operating at a high frequency (e.g., Vin=100V, Vout=5V and switching frequency fsw=1MHz), a lower pulse width such as 50ns may be used. In the case where the conversion uses a higher duty cycle during a steady-state condition that may occur under low input voltage conditions while operating at a lower frequency (e.g., Vin=6V, Vout=5V and switching frequency fsw=83KHz), a higher pulse width such as 10μs may be used. Alternative embodiments may feature initial and final pulse width values ​​outside of these ranges.

[0030] Figure 1D is a waveform diagram comparing the performance of the embodiment switch mode power converter 100 with a conventional constant on-time power converter during the soft start phase. Trace 150 represents the output current of the conventional converter, trace 152 represents the output current Iout of the embodiment converter 100, trace 154 indicates the pulse width of the fixed pulse, trace 156 depicts the pulse width of the pulse signal TON, trace 158 represents the output voltage of the conventional converter, and trace 160 represents the output voltage of the embodiment converter 100. As shown, when a constant pulse width of 1 μs is maintained during the soft start phase (trace 154), the output current 150 of the conventional converter exhibits an initial current spike of more than 300 mA and sharp current transients. In contrast, as the pulse width of the pulse signal TON (trace 156) is gradually increased from approximately 60ns to 1μs, the output current 152 of the embodiment power converter 100 shows a smooth, well-behaved increase. It can also be observed that the output voltage (trace 158) of the conventional power converter is less monotonic than the output voltage (trace 160) of the embodiment switch mode power converter 100. It should be noted that Figure 1D The comparative performance illustrated in is only one of many potential comparative examples. The performance of any particular embodiment switch-mode power converter may vary depending on the embodiment chosen and its specifications.

[0031] Figure 2A A constant on-time power converter 200 according to another embodiment of the present invention is depicted. Figure 2A The power converter 200 shown in FIG. Figure 1A 1, but includes additional circuitry designed to limit the frequency of the pulse signal TON during the soft start phase of the power converter. The frequency limitation is implemented using an AND gate 204 coupled to the on-time timer 112 and an off-time timer 202 (also referred to as a frequency limiting circuit or frequency limiter).

[0032] In an embodiment, the off-time timer 202 generates a delay time t after the falling edge of the pulse signal TON. off The minimum off time signal TOFF_MIN. Figure 2B The waveform diagram of FIG. 200 shows the relationship between the pulse signal TON and the minimum off time signal TOFF_MIN. At time 232, the pulse signal TON shows a falling edge. The off time timer 202 generates a rising edge of the minimum off time signal TOFF_MIN at time 234, which is t off At time 236 at the rising edge of the pulse signal TON, the minimum off time signal is reset.

[0033] Return to reference Figure 2A The delayed assertion of the minimum off time signal TOFF_MIN and the AND gate 204 prevent the period t after the falling edge of the pulse signal TON from off The pulse signal TON is then asserted before the minimum off-time signal TOFF_MIN is asserted. This delay in activating the pulse signal TON effectively limits the frequency of the pulse signal TON.

[0034] In various embodiments, the time period t may be modified by applying a control signal to the off-time duration control port 203 of the off-time timer 202. off Adjusting the control signal during the soft start of the constant on-time power converter 200 allows the maximum frequency of the pulse signal TON to be adjusted during the soft start phase, for example, from a low frequency to a continuously higher frequency.

[0035] In some embodiments, the reference voltage Vref generated by the soft start timer 101 is applied to the off time duration control port 203 of the off time timer 202, so that the off time t off is reduced during the soft-start phase of the constant on-time converter 200. Figure 2C As depicted in FIG, during the time period tss, at the beginning of the soft start phase, the disconnection time t off Initialized to t off_init During the soft start phase, the off time t off At the end of the soft start period, when the reference voltage Vref reaches its final value Vnom, the off time t off reaches its final value t off_final In some embodiments, signal TOFF_MIN is set high during a nominal operation period tnom of power converter 200 in order to disable frequency limiting.

[0036] It is worth noting that, relative to Figure 2A-2C The operation and implementation of the frequency limiting circuit system shown and described represents only one of many possible implementations. Alternative embodiments of the present invention may use different structures to achieve similar functions. For example, the polarity of the signal generated by the off-time timer 202 may be changed, and the AND gate 204 may be replaced with one or more different logic gates to produce logically comparable operations.

[0037] Figure 2D A constant on-time power converter 240 according to another embodiment of the present invention is depicted, which is designed to limit the frequency of the pulse signal TON during the soft start phase of the power converter by sampling the trigger signal Cmp output of the feedback processing circuit 102 using a clock. Figure 2D The power converter 240 shown in FIG. Figure 2A , except that the off-time timer 202 is replaced by an SR latch 242. The reset R input of the SR latch 242 is connected to the output of the on-time timer 112, its set S input is connected to the clock node CLK, and its output Q is connected to the input of the AND gate 204. During operation, the frequency of the pulse signal TON is limited by the clock signal applied to the clock node CLK. Therefore, the SR latch 242 also serves as a frequency limiting circuit.

[0038] Figure 2E The figure shows the comparison when experiencing a load transient Figure 2D The power converter 240 (with a 2 MHz signal applied to node CLK) is connected to Figure 1A 2 is a waveform diagram of the performance of power converter 100. Traces 252 and 254 represent the frequency of pulse signal TON for converters 100 and 240, respectively. As observed, for power converter 100, the frequency of pulse signal TON rises to nearly 5 MHz, but for power converter 240, the frequency of pulse signal TON is limited to 2 MHz. Traces 256 and 258 represent the off-time duration of pulse signal TON for each cycle of converters 100 and 240, respectively. For power converter 100, the off-time duration of pulse signal TON is close to 0.1 μs, but for power converter 240, the off-time duration of pulse signal TON is set to at least 0.4 μs.

[0039] Figure 2F 1 and 10. The diagram compares a conventional constant on-time converter, a power converter 100 ( Figure 1A )、Power converter 200( Figure 2A ) and power converter 240( Figure 2D) operation waveform diagram. Tracks 250, 252, 254 and 256 represent the frequencies of the pulse signal TON during the soft start of the conventional constant on-time converter, the power converter 100, the power converter 200 and the power converter 240, respectively. As shown, the frequency 250 of the conventional power converter remains very low because the power converter starts with a balanced value (regime value) of the on-time, wherein a higher on-time corresponds to a higher off-time and a lower frequency. Due to the short period of the pulse signal TON at the beginning of the soft start, the frequency 252 of the non-frequency-limited power converter 100 reaches a maximum frequency of about 10MHz. The power converter 200 using the off-time timer 202 shows a gradual frequency increase 254 during the soft start, while the power converter 240 using a latch and a fixed clock to limit the frequency 256 of the pulse signal TON shows an operating frequency limited to about 800KHz.

[0040] Traces 258, 260, 262, and 264 represent the output currents of a conventional constant on-time converter, power converter 100, power converter 200, and power converter 240, respectively, during soft start. Output current 258 of non-frequency limited power converter 100 is shown as having multiple high transients with an initial output current of 325 mA. Output currents 260, 262, and 264 are substantially lower, with the output currents 260, 262, and 264 being substantially lower than those of the conventional constant on-time converter, power converter 100, power converter 200, and power converter 240, respectively. Output current 258 of non-frequency limited power converter 100 is shown as having multiple high transients with an initial output current of 325 mA. Figure 2A The corresponding output current 262 of the power converter 200 remains below 50 mA during the first 140 μs of operation.

[0041] Traces 270, 272, 274, and 276 represent the output voltages of the conventional constant on-time converter, power converter 100, power converter 200, and power converter 240, respectively. The output voltage of the conventional constant on-time converter oscillates between 600 mV and 800 mV during the soft start phase of the power converter. The output voltages 272, 274, and 276 corresponding to the embodiment converter exhibit more orderly behavior, where output voltage 274 ( Figure 2A The power converter 200 in FIG. 1 demonstrates a slow, consistent increase during the soft start phase.

[0042] Figure 3A Depicted is a schematic diagram illustrating a circuit level embodiment of an on-time timer 300 that can be used in Figure 1A , Figure 2A and Figure 2D The configuration presented in embodies the on-time timer 112. The on-time timer 300 includes a current source 310, a capacitor C1, a switch S1, a comparator 304, and a SR latch 306.

[0043] In one embodiment, current source 310 is implemented using resistors R1, R2, and R3, transistors M1, M2, and M3, and amplifier 302. Resistors R1 and R2 form a resistor divider, thereby generating a voltage Vin*R2 / (R1+R2) at the positive terminal of amplifier 302. Negative feedback is supplied to the negative terminal (node ​​Va) of amplifier 302 through transistor M1 and the resistor, thereby obtaining a voltage Vin*R2 / (R1+R2) at node Va. Therefore, the current I1 flowing through transistor M1 is Vin×R2 / (R3×(R1+R2)). In some embodiments, the value of R3 is selected to have a value of K*Vout nom / fsw, where K is a constant, Vout nom is the nominal output voltage of the converter, and fsw is the switching frequency of the converter. In some embodiments, the value of R3 may be user programmable, for example, using a switchable resistor network with programmable settings stored in an internal register, and / or addressable via a device pin.

[0044] Transistors M2 and M3 mirror current I1 to form current I2, which charges capacitor C1. In this embodiment, transistor M1 is implemented using an NMOS transistor, and transistors M2 and M3 are implemented using PMOS transistors. It should be noted that the structure of current source 310 is only one of many possible configurations; alternative embodiments may use other known current source circuits.

[0045] Figure 3B FIG. 3 is a schematic diagram of a circuit-level implementation of a disconnection timer 320 according to the present invention. The disconnection timer 320 can be used to implement Figure 2A The disconnection timer 202 in the embodiment of the present invention. The disconnection timer 320 includes a voltage-controlled current source 330, a comparator 322, a capacitor C2, a switch S2 having a load path coupled across the capacitor C2, a voltage source 328, and a current source 326. In one embodiment, the voltage source 328 delivers a fixed voltage to a fixed reference voltage node (connected to the negative input terminal of the comparator 322) and can be implemented using a well-known voltage reference circuit such as a bandgap voltage reference. The specific voltage provided by the voltage source 328 can be, for example, 0.5V; however, any suitable voltage level can be used depending on the specific system and its specifications.

[0046] In an embodiment, a voltage-controlled current source 330 is implemented using resistor R5, amplifier 324, transistors M4, M5 and M6, and current source I5. During operation, amplifier 324 and transistor M6 apply a reference voltage Vref to resistor R5, thereby generating a current I4=(VDD-Vref) / R5 flowing through transistor M6. The positive input terminal of amplifier 324 serves as a control node for the voltage-controlled current source. Current I4 is mirrored by transistors M4 and M5 to generate current I3. The difference between current I3 and I5 generated by current source 326 charges capacitor C2. In an embodiment, transistor M6 is implemented using a PMOS transistor, and transistors M2 and M3 are implemented using NMOS transistors. It should be understood that the structure of voltage-controlled current source 330 is only one of many possible configurations; alternative embodiments may use other known controlled current source circuits.

[0047] Now combine Figure 3C describe Figure 3A The on-time timer 300 depicted in FIG. Figure 3B The operation of the disconnection timer 320 is depicted in Figure 3C Timing diagrams showing the operation of these circuits are illustrated.

[0048] about Figure 3A The on-time timer 300 shown in FIG. 1 is configured to trigger a trigger signal Cmp ( Figure 3C ) is asserted by the feedback processing circuit 102 and applied to the set input of the SR latch 306, Figure 3C At time 352 shown in FIG. 3 , pulse signal TON is activated at the Q output and the inverse TOFF of pulse signal TON is de-asserted at the Q and QB outputs of SR latch 306. De-assertion of TOFF closes switch S1, allowing current source 310 to charge capacitor C1 with current I2, which causes a corresponding increase 353 in capacitor voltage at node TONR.

[0049] When the voltage TONR across capacitor C1 reaches the reference voltage Vref (generated by the soft start timer 101) measured by the comparator 304, the signal TON_END is asserted at time 354, thereby resetting the SR latch 306. When the SR latch 306 is reset, the signal TOFF is asserted, causing the switch S1 to discharge the capacitor C1. The capacitor C1 remains discharged until the signal Cmp is asserted again by the feedback processor 102. Since the comparison voltage TONR is with the reference voltage Vref, it can be seen that the length of the pulse signal TON is proportional to the reference voltage Vref. Therefore, at the beginning of the soft start phase of the power converter, the voltage Vref is very low, which means that the voltage TONR is only charged to a small voltage before the comparator 304 is triggered. As the reference voltage Vref increases, the pulse width of the pulse signal TON increases correspondingly due to the increase in the time it takes for the voltage of TONR to rise to the reference voltage Vref detected by the comparator 304.

[0050] about Figure 3B , during operation, when signal TON is deasserted at time 354, switch S2 is turned off, thereby allowing capacitor C2 to be charged with current I5-I3, thereby causing a corresponding increase 355 in voltage TOFR across capacitor C2. When voltage TOFR reaches voltage VR1 generated by voltage source 328, comparator 322 asserts signal TOFF_MIN at time 356. As described above with respect to Figure 2A As discussed in the embodiments of the present invention, the pulse signal TON is prevented from being asserted before the signal TOFF_MIN is asserted.

[0051] It should be understood that the slope of voltage TOFR is proportional to the reference voltage Vref generated by soft start timer 101, so that the slope of voltage TOFR increases as the reference voltage Vref increases. Therefore, the lower the slope, the longer it takes for signal TOFF_MIN to be asserted, which translates into a lower frequency of pulse signal TON.

[0052] Figure 3D The diagram shows the Figure 1A , Figure 2A and Figure 2D Schematic diagram of an embodiment of the ramp generator 104, a ramp generator 360, is shown in FIG. The ramp generator 360 includes a current source 362, a capacitor C3, a resistor R6, and a switch S3. During operation, the current source 362 charges the parallel RC circuit formed by the capacitor C3 and R6 until the sum Vx of the ramp voltage Vr and the error voltage Ve reaches the comparator 110 ( Figure 1A , Figure 2A and Figure 2D) threshold voltage Vfb, thereby causing comparator 110 to assert trigger signal Cmp. When trigger signal Cmp is asserted, switch S3 closes, thereby resetting ramp voltage Vr to zero volts. The resulting reduction in voltage Vr then causes output terminal Cmp of comparator 110 to go low. When trigger signal Cmp goes low, switch S3 opens again, and the operation cycle repeats, with ramp voltage Vr rising again.

[0053] The current source 362 may be implemented using a known current source circuit.

[0054] Figure 3E The diagram shows the Figure 1A , Figure 2A and Figure 2D 370 of an embodiment of the soft start timer 101 shown in FIG. The soft start timer includes a current source 372, a switch S4, a capacitor C4, a voltage clamp 376, and a voltage buffer 374. During operation, when the power-on reset signal POR becomes deasserted (e.g., becomes low), the switch S4 is opened and the current Iss generated by the current source 372 charges the capacitor C4, thereby obtaining a linearly increasing ramp voltage Vy across the capacitor C4. When the voltage Vy across the capacitor C4 reaches the nominal operating voltage of the reference voltage Vref, the clamp circuit 376 clamps the voltage across the capacitor C4 to the reference voltage Vref. In some embodiments, a buffer amplifier 374 is used to buffer the voltage Vy.

[0055] The current source 372 can be used relative to Figure 3A 3. The buffer amplifier 374 may be implemented using an operational amplifier in a non-inverting unity gain configuration or using a source or emitter follower transistor circuit. The clamp circuit 376 may be implemented using a known clamp circuit such as one or more diodes connected in series between the node Vy and ground (or other reference voltage node).

[0056] In various embodiments, the signal POR is asserted by a controller circuit (not shown) within the embodiment power converter. As mentioned above, during the startup of the power converter, internal circuit systems such as an internal power regulator begin to operate during the first stage of startup. During this first stage of startup, the power converter signal POR can remain asserted so as to maintain the reference voltage Vref at ground potential. Once the internal power regulator has reached its required operating voltage, the second stage of startup (soft start) begins. At this point, the signal POR is de-asserted, and the soft start timer 370 begins to provide a ramp reference voltage Vref.

[0057] Figure 4FIG. 4 is a flow chart of a method 400 according to an embodiment of the present invention. Figure 4 as well as Figure 1A , Figure 2A and Figure 2D , the method starts from step 402, in which a pulse signal having an on-time duration is generated. This step may be performed, for example, by the on-time timer 112 discussed above. In step 404, during the soft start phase of the power converter, the on-time duration is continuously increased from an initial duration to a final duration, wherein the final duration is greater than the initial duration. However, in some cases, the final duration may be equal to the initial duration. The process may be performed, for example, by the on-time timer 112 in conjunction with the soft start timer 101, which generates a ramp reference voltage Vref during the soft start phase. As the reference voltage Vref increases, the on-time of the pulse signal generated by the on-time timer 112 increases accordingly. In some embodiments, step 404 is performed only during the soft start phase of the power converter. In addition, in various embodiments, the on-time duration remains substantially constant (e.g., at the final duration) during the normal operation phase of the power converter.

[0058] Step 406 involves sensing the output voltage of the power converter and generating a feedback signal proportional to the output voltage. This task may be performed by the feedback network 124 and the feedback processing circuit 102. Together, these components allow the output voltage to be monitored and evaluated to achieve voltage regulation.

[0059] Then, in step 408, the feedback signal generated in step 406 is compared with the reference signal to generate an error signal. This comparison is implemented by the error amplifier 106 within the feedback processing circuit 102. By generating the error signal, the system can determine whether any adjustments are necessary to achieve the desired output voltage. In step 408, the frequency of the pulse signal is adjusted based on the feedback signal and the reference obtained in the previous step. This adjustment can be made, for example, by the feedback processing circuit 102 to affect the frequency of the pulses seen at the output terminal Cmp of the comparator 110. In some embodiments, in step 408, the feedback signal generated in step 406 is compared with the reference signal to generate an error signal. This comparison is implemented by the error amplifier 106 within the feedback processing circuit 102. By generating the error signal, the system can determine whether any adjustments are necessary to achieve the desired output voltage. Next, the error signal is summed with the ramp signal, and the summed signal and the feedback signal are compared using the comparator 110 to generate a periodic trigger signal having a frequency that varies according to the feedback valley adjustment relative to the summing node (e.g., Vx=Vr+Ve). Alternatively, the error amplifier may be omitted so that the reference signal is summed with the ramp signal and the summed signal is compared with the feedback signal using the comparator 110 to generate the periodic trigger signal.

[0060] Finally, in step 410, the power switch is driven by a pulse signal to control the power switch and regulate the output voltage. This step can be performed, for example, by the gate driver 114. In various embodiments, in addition to step 404, method steps 402, 406, 408 and 410 are also performed during the soft start phase.

[0061] In various embodiments, Figure 1A , Figure 2A and Figure 2D Some or all of the components of the power converters 100, 200, and 240 depicted in the drawings may be implemented using one or more integrated circuits. In some embodiments, some or all of the components of these power converters may be disposed on a single monolithic semiconductor integrated circuit such as a single semiconductor substrate, and / or disposed on the same monolithic semiconductor integrated circuit as other disclosed system components. The semiconductor substrate may be a silicon substrate. The integrated circuit 102 may be manufactured using one of a variety of different semiconductor processes such as a CMOS process, a BiCMOS process, a bipolar process, or other types of semiconductor processes.

[0062] In some embodiments, except for the inductor 120, the feedback network 124 and / or the capacitor 122 which may be implemented outside the semiconductor substrate, FIG. Figure 2A and Figure 2DAll components of the power converters 100, 200, and 240 depicted in FIG. 1 are disposed on a single semiconductor substrate. In some embodiments, the switch circuit 115 may be implemented outside the single semiconductor substrate.

[0063] Embodiments of the invention are summarized herein. Other embodiments may also be understood from the entire specification and claims submitted herein.

[0064] Example 1. A method for controlling a constant on-time switch mode power converter, the method comprising: generating a pulse signal having an on-time; during a soft start phase of the power converter, continuously increasing the on-time from an initial duration to a final duration, wherein the final duration is greater than the initial duration; sensing an output voltage of the power converter and generating a feedback signal proportional to the output voltage; adjusting the frequency of the pulse signal based on the feedback signal and a reference signal; and driving a power switch using the pulse signal to control the power switch and regulate the output voltage.

[0065] Example 2. The method of Example 1, further comprising limiting a switching frequency of the pulse signal to a first switching frequency during a soft start phase of the power converter.

[0066] Example 3. The method of Example 2, wherein limiting the switching frequency of the pulse signal comprises continuously reducing an off time between pulses of the pulse signal from a first duration to a second duration that is less than the first duration.

[0067] Example 4. The method of Example 2 further includes generating a trigger signal based on the feedback signal and the reference signal, wherein limiting the switching frequency of the pulse signal includes sampling the trigger signal using a clock.

[0068] Example 5. The method of Example 2, wherein limiting the switching frequency of the pulse signal includes clocking a latch having an output coupled to the input of the pulse generation circuit and an input coupled to the output of the pulse generation circuit.

[0069] Example 6. The method of one of Examples 1 to 5, further comprising generating the reference signal by increasing the reference signal from a first value to a second value during a soft start phase of the power converter to form a ramped reference signal.

[0070] Example 7. A method according to Example 6, wherein generating a pulse signal includes: generating a ramp signal; comparing the ramp signal with a threshold proportional to a ramp reference signal; resetting the ramp signal when the ramp signal exceeds the threshold; and asserting the pulse signal when the ramp signal is less than the threshold.

[0071] Example 8. The method of Example 7, wherein: generating the ramp signal comprises charging a capacitor; and resetting the ramp signal comprises turning on a switch coupled between the first terminal and the second terminal of the capacitor.

[0072] Example 9. The method of one of Examples 1 to 8, wherein continuously increasing the on-time from an initial duration to a final duration reduces an output current spike during a soft start phase of the power converter.

[0073] Example 10. The method of one of Examples 1 to 9, wherein the method further comprises maintaining the on-time at the final duration during a normal operation phase of the power converter.

[0074] Example 11. The method of one of Examples 1 to 10, wherein continuously increasing the on-time from the initial duration to the final duration is performed only during a soft-start phase of the power converter.

[0075] Example 12. A method according to one of Examples 1 to 11, wherein the following steps are performed during a soft start phase of the power converter: generating a pulse signal, sensing an output voltage of the power converter, generating a feedback signal, adjusting a frequency of the pulse signal, and driving a power switch.

[0076] Example 13. A switch mode power converter comprises: a feedback processing circuit having an input terminal coupled to an output node of the switch mode power converter; an on-time timer coupled to an output terminal of the feedback processing circuit, the on-time timer being configured to generate a pulse having an on-time duration based on the value of a signal applied to an on-time duration control port; and a first ramp signal generator having an output terminal coupled to the on-time duration control port, the first ramp signal generator being configured to generate a ramp reference signal during a soft start phase of the switch mode power converter and to generate a substantially constant reference signal during normal operation of the switch mode power converter.

[0077] Example 14. The switch-mode power converter of Example 13, further comprising a frequency limiting circuit configured to limit an output frequency of the on-time timer.

[0078] Example 15. A switch-mode power converter according to Example 14, wherein: the frequency limiting circuit includes an off-time timer having an input coupled to the output of the on-time timer and an output coupled to the input of the on-time timer; the off-time timer is configured to generate a pulse having a duration based on the value of a signal applied to a duration control port of the off-time timer; and the output of the first ramp signal generator is also coupled to the duration control port of the off-time timer.

[0079] Example 16. A switch-mode power converter according to Example 15, wherein the off-time timer includes: a first voltage-controlled current source, the first voltage-controlled current source having a control node coupled to the output terminal of the first ramp signal generator; a first capacitor, the first capacitor coupled to the first voltage-controlled current source; a first switch, the first switch having a load path coupled across the first capacitor and a control node coupled to the output terminal of the on-time timer; and a first comparator, the first comparator having a first input terminal coupled to the first capacitor and a second input terminal coupled to a fixed reference voltage node.

[0080] Example 17. A switch-mode power converter according to Example 14, wherein the frequency limiting circuit includes an SR latch having a first input coupled to the output of the on-time timer, a second input coupled to the clock node, and an output coupled to the input of the on-time timer.

[0081] Example 18. A switch-mode power converter according to one of Examples 13 to 17, further comprising: a driver circuit having an input coupled to an output of an on-time timer; and a switch circuit coupled between an input node and an output node of the switch-mode power converter.

[0082] Example 19. The switch-mode power converter of Example 18, wherein the switching circuit comprises a MOS half-bridge circuit.

[0083] Example 20. A switch mode power converter according to one of Examples 13 to 19, wherein the feedback processing circuit comprises: an error amplifier having a first input terminal coupled to the output node of the switch mode power converter and a second input terminal coupled to the output terminal of the first ramp signal generator; a second ramp signal generator; and a comparator having a first input terminal and a second input terminal, the first input terminal being configured to receive the sum of the output of the error amplifier and the output of the second ramp signal generator, and the second input terminal being coupled to the output node of the switch mode power converter.

[0084] Example 21. A switch-mode power converter comprises: a reference signal generator configured to generate a ramp reference signal during a soft start phase of the switch-mode power converter and to generate a substantially constant reference signal during normal operation of the switch-mode power converter; a half-bridge circuit having an input coupled to a power supply input node and an output coupled to an output of the switch-mode power converter; a gate driver coupled to a control input of the half-bridge circuit; a feedback processing circuit having a first input coupled to the output of the switch-mode power converter and a second input coupled to the output of the reference signal generator, the feedback processing circuit being configured to generate a trigger signal having a frequency based on a difference between a signal at the output of the reference signal generator and a signal at the output of the switch-mode power converter; and a first pulse generator coupled to the output of the feedback processing circuit, the first pulse generator being configured to generate a pulse having an on-time duration based on the value of the signal at the output of the reference signal generator.

[0085] Example 22. The switch-mode power converter of Example 21 further comprising a frequency limiter coupled to the first pulse generator.

[0086] Example 23. A switch-mode power converter according to Example 22, wherein the frequency limiter includes a second pulse generator configured to generate a pulse having a pulse width inversely proportional to the signal at the output of the reference signal generator.

[0087] Example 24. The switch-mode power converter of one of Examples 21 to 23, further comprising an inductor coupled between an output of the half-bridge circuit and an output of the switch-mode power converter.

[0088] Although the present invention has been described with reference to exemplary embodiments, this description is not intended to be interpreted as having a limiting meaning. By reference to the description, various modifications and combinations of the exemplary embodiments and other embodiments of the present invention will be apparent to those skilled in the art. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A method for controlling a constant on-time switch mode power converter, the method comprising: generating a pulse signal having an on-time; During a soft start phase of the power converter, continuously increasing the on-time from an initial duration to a final duration, wherein the final duration is greater than the initial duration; sensing an output voltage of the power converter and generating a feedback signal proportional to the output voltage; adjusting the frequency of the pulse signal based on the feedback signal and a reference signal; and The pulse signal is used to drive a power switch to control the power switch and adjust the output voltage. 2 . The method of claim 1 , further comprising limiting a switching frequency of the pulse signal to a first switching frequency during the soft start phase of the power converter.

3. The method according to claim 2, wherein: Limiting the switching frequency of the pulse signal includes continuously reducing an off-time between pulses of the pulse signal from a first duration to a second duration that is less than the first duration.

4. The method according to claim 2, further comprising generating a trigger signal based on the feedback signal and the reference signal, wherein: Limiting the switching frequency of the pulse signal includes sampling the trigger signal using a clock.

5. The method according to claim 2, wherein: Limiting a switching frequency of the pulse signal includes clocking a latch having an output coupled to an input of a pulse generating circuit and an input coupled to the output of the pulse generating circuit. 6 . The method of claim 1 , further comprising generating the reference signal by increasing the reference signal from a first value to a second value during the soft start phase of the power converter to form a ramped reference signal.

7. The method according to claim 6, wherein: Generating the pulse signal comprises: generating a ramp signal; comparing the ramp signal to a threshold proportional to the ramp reference signal; When the ramp signal exceeds the threshold, resetting the ramp signal; and When the ramp signal is less than the threshold, the pulse signal is asserted.

8. The method according to claim 7, wherein: Generating the ramp signal includes charging a capacitor; and Resetting the ramp signal includes turning on a switch coupled between the first terminal and the second terminal of the capacitor.

9. The method according to claim 1, wherein: Continuously increasing the on-time from the initial duration to the final duration reduces an output current spike during the soft-start phase of the power converter. 10 . The method of claim 1 , further comprising maintaining the on-time at the final duration during a normal operating phase of the power converter.

11. The method according to claim 1, wherein: Continuously increasing the on-time from the initial duration to the final duration is performed only during the soft-start phase of the power converter.

12. A switch mode power converter comprising: a feedback processing circuit having an input coupled to an output node of the switch-mode power converter; an on-time timer coupled to an output of the feedback processing circuit, the on-time timer configured to generate a pulse having an on-time duration based on a value of a signal applied to an on-time duration control port; and a first ramp signal generator having an output coupled to the on-time duration control port, the first ramp signal generator being configured to generate a ramp reference signal during a soft start phase of the switch mode power converter and to generate a substantially constant reference signal during normal operation of the switch mode power converter. 13 . The switch mode power converter of claim 12 , further comprising a frequency limiting circuit configured to limit an output frequency of the on-time timer.

14. The switch mode power converter of claim 13, wherein: The frequency limiting circuit includes an off-time timer having an input coupled to an output of the on-time timer and an output coupled to an input of the on-time timer; the off-time timer being configured to generate a pulse having a duration based on a value of a signal applied to a duration control port of the off-time timer; as well as The output of the first ramp signal generator is also coupled to a duration control port of the off-time timer.

15. The switch mode power converter of claim 14, wherein: The disconnection timer comprises: a first voltage-controlled current source having a control node coupled to an output terminal of the first ramp signal generator; a first capacitor coupled to the first voltage-controlled current source; a first switch having a load path coupled across the first capacitor and a control node coupled to an output of the on-time timer; and A first comparator having a first input coupled to the first capacitor and a second input coupled to a fixed reference voltage node.

16. The switch mode power converter of claim 13, wherein: The frequency limiting circuit includes an SR latch having a first input coupled to an output of the on-time timer, a second input coupled to a clock node, and an output coupled to an input of the on-time timer.

17. The switch mode power converter of claim 12, further comprising: a driver circuit having an input coupled to an output of the on-time timer; and A switching circuit is coupled between an input node and an output node of the switch-mode power converter.

18. The switch mode power converter of claim 17, wherein: The switch circuit includes a MOS half-bridge circuit.

19. The switch mode power converter of claim 12, wherein: The feedback processing circuit comprises: an error amplifier having a first input coupled to an output node of the switch mode power converter and a second input coupled to an output of the first ramp signal generator; a second ramp signal generator; and A comparator having a first input terminal configured to receive a sum of the output of the error amplifier and the output of the second ramp signal generator and a second input terminal coupled to an output node of the switch mode power converter.

20. A switch mode power converter comprising: a reference signal generator configured to generate a ramped reference signal during a soft-start phase of the switch-mode power converter and to generate a substantially constant reference signal during normal operation of the switch-mode power converter; a half-bridge circuit having an input coupled to a power supply input node and an output coupled to an output of the switch-mode power converter; a gate driver coupled to a control input of the half-bridge circuit; a feedback processing circuit having a first input coupled to an output of the switch-mode power converter, a second input coupled to an output of the reference signal generator, the feedback processing circuit being configured to generate a trigger signal having a frequency based on a difference between a signal at the output of the reference signal generator and a signal at the output of the switch-mode power converter; and A first pulse generator is coupled to the output of the feedback processing circuit, the first pulse generator being configured to generate a pulse having an on-time duration based on a value of a signal at the output of the reference signal generator.

21. The switch mode power converter of claim 20 further comprising a frequency limiter coupled to the first pulse generator.

22. The switch mode power converter of claim 21, wherein: The frequency limiter includes a second pulse generator configured to generate a pulse having a pulse width inversely proportional to a signal at an output of the reference signal generator.

23. The switch-mode power converter of claim 19, further comprising an inductor coupled between an output of the half-bridge circuit and an output of the switch-mode power converter.

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