Multi-mode voltage regulator voltage feedback loop

Abstract

The invention provides a multi-mode voltage regulator voltage feedback loop. A switched capacitor voltage regulator (SCVR) design, such as a continuous capacitive voltage regulator (C2VR) design, may use capacitors and switches to provide improved cost and space efficiency. Remote sensing circuitry may be used to improve C2VR performance. By adding a remote sensing circuit to a regulation feedback loop within a C2VR circuit design, the C2VR circuit may provide improved accuracy in voltage regulation, for example, by providing correction based on a voltage error between the remote sensing voltage and a reference target. The remote sensing circuit may also provide transient information for undervoltage detection at the output terminals. This detected transient can become an alternating current (AC) part of an under-voltage detection threshold, which improves the ability of the C2VR circuit to provide early detection of any under-voltage fault.

Description

Technical Field

[0001] Embodiments described herein generally relate to power management of electronic devices. Background Art

[0002] In modern semiconductor devices and system on a chip (SoC) designs, voltage regulators can be used to provide a substantially constant voltage to various integrated circuits (ICs) or other semiconductor components. Voltage regulators can use a feedback mechanism to maintain a substantially constant voltage.

[0003] Switched capacitor voltage regulator (SCVR) designs, such as continuous capacitive voltage regulator (C2VR) designs, can use capacitors and switches to provide improved cost and space efficiency. C2VR converters can use single-ended feedback sensing circuits, which may face accuracy challenges in closed-loop regulation. For a given SoC design, the C2VR converter can be placed relatively far away from the load, and the power delivery routing distance may result in a large current-resistance (IR) drop. In some designs, an increase in current load may cause a corresponding drop in output voltage. In addition, due to the voltage ripple changes in various C2VR operating modes (e.g., extreme speed mode, dynamic maximum frequency (fmax)), it may be difficult for C2VR to provide accurate voltage levels in various modes. Summary of the invention

[0004] One aspect of the present disclosure provides a device. The device includes: a voltage regulator coupled to a load, the voltage regulator is used to generate a regulated voltage signal and provide the regulated voltage signal to the load; a load voltage sensing circuit coupled to an input node of the load and an output node of the load, the load voltage sensing circuit is used to generate a differential voltage signal based on the regulated voltage signal; and an output voltage sensing circuit coupled to an output node between the voltage regulator and the load, the output voltage sensing circuit is used to generate an output voltage correction signal based on the differential voltage signal and the regulated voltage signal; wherein the voltage regulator is also used to generate an updated voltage signal based on the output voltage correction signal.

[0005] Another aspect of the present disclosure provides a method, which includes: generating a regulated voltage signal at a voltage regulator coupled to a load; generating a differential voltage signal based on the regulated voltage signal at a load voltage sensing circuit coupled to an input node of the load and an output node of the load; generating an output voltage correction signal based on the differential voltage signal and the regulated voltage signal at an output voltage sensing circuit coupled to an output node between the voltage regulator and the load; and generating an updated voltage signal at the voltage regulator based on the output voltage correction signal.

[0006] Another aspect of the present disclosure provides a circuit. The circuit includes: a capacitive voltage regulator coupled to a load, the capacitive voltage regulator is used to generate a regulated voltage signal and provide the regulated voltage signal to the load; a first voltage sensing circuit coupled to an input node of the load and an output node of the load, the first voltage sensing circuit is used to generate a remote sensing voltage signal based on the regulated voltage signal; and a second voltage sensing circuit coupled at an output node between the capacitive voltage regulator and the load to receive the regulated voltage signal, the second voltage sensing circuit generates an output voltage correction signal based on the remote sensing voltage signal and the regulated voltage signal; wherein the capacitive voltage regulator also generates an updated voltage signal based on the output voltage correction signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different instances of similar components. Some embodiments are shown by way of example and not limitation in the figures of the accompanying drawings, in which:

[0008] Figure 1 The block diagram shows a C2VR digital feedback loop architecture 100 according to one embodiment.

[0009] Figure 2 The block diagram of FIG. 1 illustrates a C2VR mixed signal feedback loop architecture 200 according to one embodiment.

[0010] Figure 3A The block diagram of FIG. 1 shows a reciprocating FSM control circuit 300 according to one embodiment.

[0011] Figure 3B The block diagram shows a reciprocating FSM control sequence 301 according to one embodiment.

[0012] Figure 4A The flow chart of FIG. 4 illustrates frequency based tuning 400 according to one embodiment.

[0013] Figure 4B The flow chart of FIG. 4 illustrates duty cycle based tuning 401 according to one embodiment.

[0014] Figure 5 The diagram of FIG. 5 shows a non-dithered output voltage waveform 500 according to one embodiment.

[0015] Figure 6 The diagram of FIG. 6 shows a dithered output voltage waveform 600 according to one embodiment.

[0016] Figure 7 The diagram of FIG. 7 shows an under-voltage trigger detection waveform 700 according to one embodiment.

[0017] Figure 8 The block diagram shows a C2VR analog feedback loop architecture 800 according to one embodiment.

[0018] Fig. 9 The block diagram shows a C2VR pulse count feedback loop architecture 900 according to one embodiment.

[0019] Fig.10 The flowchart of FIG. 1 shows a voltage regulator method 1000 according to one embodiment.

[0020] Fig.11 is a block diagram of a computing device 1100 employing parallel current source voltage regulation according to one embodiment. DETAILED DESCRIPTION

[0021] Remote sensing circuits can be used to improve C2VR performance. By adding a remote sensing circuit to a regulation feedback loop within a C2VR circuit design, the C2VR circuit can provide improved accuracy in voltage regulation, for example, by providing correction based on a voltage error between a remote sense voltage and a reference target. The remote sensing circuit can also provide transient information for undervoltage detection at the output terminals. This detected transient can become the alternating current (AC) portion of the undervoltage detection threshold, which improves the ability of the C2VR circuit to provide early detection of any undervoltage faults.

[0022] In the following description, for the purpose of explanation, many specific details are recorded to provide a thorough understanding of some example embodiments. However, it is obvious to those skilled in the art that the embodiments of the present disclosure can also be implemented without these specific details.

[0023] Figure 1The block diagram of FIG. 1 shows a C2VR digital feedback loop regulator architecture 100 according to one embodiment. The C2VR digital feedback loop architecture 100 may include a plurality of C2VR circuits 118 arranged in a power train (PTR) circuit such as a C2VR PTR 116, which is coupled to a flying capacitor array 158. The C2VR digital feedback loop architecture 100 includes a remote voltage sensing circuit 122 and a local voltage sensing circuit 160. As used herein, "local" voltage sensing refers to sensing the voltage at the remote voltage sensing circuit 122 from a local voltage intercept location 119 between the C2VR PTR 116 and the load 124. In one example, this local voltage intercept location 119 is located between the C2VR PTR 116 and any parasitic resistance and capacitance 120 attached to the load 124. As used herein, "remote" voltage sensing refers to differential voltage sensing based on voltage intercepts on either side of the load 124 at the remote voltage sensing circuit 160.

[0024] The C2VR digital feedback loop architecture 100 includes a first pair of feedback comparators 148 and 150 coupled to a remote voltage sensing circuit 122. A digital to analog converter (DAC), such as a remote DAC 142, is also coupled to the first pair of feedback comparators 148 and 150. The outputs of the remote voltage sensing circuit 122 and the remote DAC 142 are alternately coupled to either of the first pair of feedback comparators 148 and 150 using a first comparator controller circuit 146 and a first comparator multiplexer 152. In one example, the remote voltage sensing circuit 122 and the remote DAC 142 are initially coupled to the feedback comparator 148, then to the feedback comparator 150, then back to the feedback comparator 148, and so on. Similarly, the C2VR digital feedback loop architecture 100 includes a second pair of feedback comparators 170 and 174 coupled to the local voltage sensing circuit 160. The output of the local voltage sensing circuit 160 and the output of the local DAC 168 may be alternately coupled to a second pair of feedback comparators 170 and 174 using a second comparator controller circuit 176 and a second comparator multiplexer 172 .

[0025] The first comparator controller circuit 146 and the second comparator controller circuit 176 can switch between comparators using an alternating "reciprocating" finite state machine (FSM) control method. This comparator switching allows calibration of comparators that are not currently coupled to the sensing circuit. This alternating comparator calibration allows each pair of comparators to reduce or minimize the effects caused by any input reference offset voltage, thereby providing improved local and remote voltage regulation accuracy. Further reference Figure 3A and Figure 3B The operation of a reciprocating FSM control method and circuit is shown and described.

[0026] The C2VR digital feedback loop architecture 100 may include a digital tuning circuit 154 for implementing tuning of the local voltage sensing circuit 160 by tuning the local DAC 168. In operation, the multiplexed output from the remote voltage sensing circuit 122 is received at the digital tuning circuit 154, which applies an average frequency threshold (e.g., 50% of the C2VR frequency) or an average duty cycle. The output of the digital tuning circuit 154 is received at the DAC code circuit 178, which may be used to increase or decrease the code at the local DAC 168 by one least significant bit (LSB). Further reference Figure 4A and Figure 4B The application of an average frequency threshold or an average duty cycle is shown and described.

[0027] The C2VR digital feedback loop architecture 100 may include a dithering circuit 140 coupled to a remote DAC 142. The limited resolution of the local DAC 168 may affect the reference adjustment of the second pair of feedback comparators 170 and 174 and cause one LSB ripple at the output of the C2VR PTR 116 (e.g., the voltage intercept location 119). The dithering circuit 140 may be used to reduce or minimize this ripple effect, thereby providing a reference to the remote DAC 142 that is within one LSB of the target DAC 114. Further references Figure 5 An example calibration algorithm for the dither circuit 140 is shown and described.

[0028] The C2VR digital feedback loop architecture 100 may include a transient detection circuit 102 coupled to a remote voltage sensing circuit 122. The transient detection circuit 102 may include a non-inverting amplifier 108 that amplifies the common mode voltage V relative to the output of the remote voltage sensing circuit 122. CM 104. The amplified output of the non-inverting amplifier 108 may be used in an underfrequency protection (UVP) threshold circuit 112 to provide improved (eg, shortened duration) detection and alarm for any output voltage droop. Figure 7 and Figure 8 Examples of improved voltage sag detection are shown and further described.

[0029] Figure 2 The block diagram of FIG. 1 illustrates a C2VR mixed signal feedback loop architecture 200 according to an embodiment. Figure 2The C2VR mixed signal feedback loop architecture 200 shown may include Figure 1 The C2VR digital feedback loop architecture 100 shown corresponds to a mixed digital and analog signal implementation.

[0030] The C2VR mixed signal feedback loop architecture 200 includes a C2VR PTR 216 coupled to a remote voltage sensing circuit 222 and a local voltage sensing circuit 260. The C2VR mixed signal feedback loop architecture 200 includes an analog integrator 238 coupled to the remote voltage sensing circuit 222. The analog integrator 238 receives the output of the remote voltage sensing circuit 222 and the integrator DAC 254 and generates an integrated voltage signal output. The use of the analog integrator 238 avoids the need for a local DAC coupled to the local voltage sensing circuit 260, thereby avoiding the need for a dithering circuit to reduce or minimize the ripple effect of one LSB at the C2VR PTR 216.

[0031] The C2VR digital loop voltage regulator architecture 200 includes a first feedback comparator 258 and a second feedback comparator 262. The outputs of the analog integrator 238 and the local voltage sensing circuit 260 are alternately coupled to either the first feedback comparator 258 or the second feedback comparator 262 using a comparator controller circuit 268 and a comparator multiplexer 264. The comparator controller circuit 268 can use an alternating reciprocating FSM control method to switch between the comparators, which allows calibration of comparators that are not currently coupled to the sensing circuit. This alternating comparator calibration allows each pair of comparators to reduce or minimize the effects due to any input reference offset voltage, thereby providing improved local and remote voltage regulation accuracy. Further reference Figure 3A and Figure 3B The operation of a reciprocating FSM control method and circuit is shown and described.

[0032] The C2VR digital loop regulator architecture 200 may include a transient detection circuit 202 coupled to a remote voltage sensing circuit 222. The transient detection circuit 202 may include a non-inverting amplifier 208 that amplifies the common mode voltage V relative to the output of the remote voltage sensing circuit 222. CM 204. The amplified output of the non-inverting amplifier 208 may be used in an under-frequency protection (UVP) threshold circuit 212 to provide improved detection and alarm for any output voltage sag. Further references Figure 6 and Figure 7 Examples of improved voltage sag detection are shown and described.

[0033] Figure 3AThe block diagram of FIG. 3 shows a reciprocating FSM control circuit 300 according to one embodiment. The reciprocating FSM control circuit 300 includes a first comparator 306 and a second comparator 308. The comparator receives a first input from a sensing circuit or an integrator circuit at a first input node 302 and a second input from a DAC reference at a second input node 304. The outputs of the comparators are multiplexed at a multiplexer 310, the output of which is provided to a logic OR gate 312 to generate a reciprocating control circuit output signal.

[0034] Figure 3B The block diagram of FIG. 301 shows a reciprocating FSM control timing according to one embodiment. The C2VR clock signal 314 can run at twice the frequency of the calibration clock signal 316. The FSM state 318 indicates the current state of the reciprocating FSM. In one example, the FSM state 318 transitions from state 0 to calibration of the first comparator 306, then back to state 0, then to state 1, then to calibration of the second comparator 308, then to state 1, then back to state 0, and so on. Each transition of the FSM state 318 into and out of the calibration state is controlled by the comparator calibration start signal 320. The comparator multiplexer signal 322 is used to control the multiplexer 310, which switches its output to the uncalibrated comparator. The first comparator code calibration signal 324 and the second comparator code calibration signal 326 are used to provide code calibration signals C1-C6 to the first comparator 306 and the second comparator 308, respectively, during calibration. In one example, the code calibration signals C1 - C6 correspond to calibration voltage levels that may be received from a DAC.

[0035] Figure 4A The flowchart of FIG. 4 shows frequency-based tuning 400 according to one embodiment. The frequency-based tuning 400 can be used to tune a digital tuning circuit, such as Figure 1. The frequency-based tuning 400 may first determine whether the input C2VR frequency 402 is below 45% of the target frequency value. If the C2VR frequency 402 is below 45% of the target frequency value, the digital tuning circuit may generate a signal to adjust the local DAC down 404 and adjust the trigger frequency threshold 406 to 55%. Subsequently, the frequency-based tuning 400 determines whether the input C2VR frequency 402 is above 55% of the target frequency value. If the C2VR frequency 402 is above 55% of the target frequency value, the digital tuning circuit may generate a signal to adjust the local DAC up 410 and adjust the trigger frequency threshold 412 to 55%. If the C2VR frequency 402 does not exceed the frequency threshold, no changes are made to the DAC or threshold 408. The tuning of the frequency threshold may be used to provide frequency hysteresis, thereby allowing the digital tuning circuit to adjust the DAC to achieve a stable C2VR voltage output while reducing or minimizing excessive switching due to noise. Although this frequency-based tuning 400 is described for values ​​of 45% and 55%, other levels of frequency adjustment may be used to provide frequency hysteresis, such as increasing or decreasing the threshold by 1%, 2%, 10%, 20%, or other frequency increments. The frequency adjustment level may be selected based on an analysis of noise-induced fluctuations in the C2VR frequency or based on a desired C2VR output voltage level accuracy.

[0036] Figure 4B The flow chart of FIG. 4 shows a duty cycle based tuning 401 according to one embodiment. The duty cycle based tuning 401 can also be used to tune a digital tuning circuit, such as Figure 14. The digital tuning circuit 154 shown in FIG. 4. The duty cycle based tuning 401 may first determine whether the current C2VR duty cycle 414 is below 45% of the target duty cycle value. If the C2VR duty cycle 414 is below 45% of the target duty cycle value, the digital tuning circuit may generate a signal to adjust the local DAC down 416 and adjust the trigger duty cycle threshold 418 to 55%. Subsequently, the duty cycle based tuning 401 determines whether the input C2VR duty cycle 414 is above 55% of the target duty cycle value. If the C2VR duty cycle 414 is above 55% of the target duty cycle value, the digital tuning circuit may generate a signal to adjust the local DAC up 422 and adjust the trigger duty cycle threshold 424 to 55%. If the C2VR duty cycle 414 does not exceed the duty cycle threshold, no changes are made to the DAC or threshold 420. Tuning of the duty cycle threshold can be used to provide duty cycle hysteresis, thereby allowing the digital tuning circuit to adjust the DAC to achieve a stable C2VR voltage output while reducing or minimizing excessive switching due to noise. Although this duty cycle based tuning 401 is described for values ​​of 45% and 55%, other levels of duty cycle adjustment can also be used to provide duty cycle hysteresis, such as increasing or decreasing the threshold by 1%, 2%, 10%, 20%, or other duty cycle increments. The duty cycle adjustment level can be selected based on an analysis of noise induced fluctuations in the C2VR duty cycle or based on the desired C2VR output voltage level accuracy.

[0037] Figure 5 The diagram of FIG. 5 shows a non-dithered output voltage waveform 500 according to one embodiment. The non-dithered output voltage waveform 500 shows a local output voltage 502 and a remote output voltage 504 without dithering. An expanded portion 510 shows a subset of the local output voltage 502 as it passes through a target voltage value 512. As can be seen from the expanded portion 510, the local output voltage 502 oscillates in time intervals 514 above and below the target voltage value 512. This oscillation (e.g., ripple) above and below the target voltage value 512 is caused by the limited DAC resolution. As shown in FIG. Figure 6 As shown, this ripple effect caused by limited DAC resolution can be reduced or minimized by applying dither.

[0038] Figure 6 The diagram of FIG. 6 shows a dithered output voltage waveform 600 according to one embodiment. The dithered output voltage waveform 600 is generated by applying a dithered DAC input, such as Figure 1The dithering circuit 140 shown in FIG. 6 shows the remote comparator output pulse 602 and the average duty cycle conversion voltage 604 in the upper portion of the dithering output voltage waveform 600. The lower portion of the dithering output voltage waveform 600 shows the local comparator DAC adjustment waveform 612 and the remote comparator DAC flip waveform 614. The local comparator DAC adjustment waveform 612 increases incrementally, reaching the lower end of the oscillation range of the remote comparator DAC flip waveform 614 at time 610. The average duty cycle conversion voltage 604 rises steadily until time 610. Starting from time 610, the remote comparator output pulse 602 begins to oscillate between a logic zero value and a logic one value, and the average duty cycle conversion voltage 604 decreases steadily toward the target voltage value. Figure 5 In contrast to the oscillating voltage values ​​shown, adding dither will reduce or minimize the effect of this voltage ripple, resulting in Figure 6 The overall average duty cycle shown produces a stable value in the converted voltage 604.

[0039] Figure 7 The diagram of FIG. 700 shows an undervoltage trigger detection waveform 700 according to one embodiment. The undervoltage trigger detection waveform 700 shows an undervoltage protection (UVP) trigger waveform 702 and a clock comparator output waveform 704. The UVP trigger waveform 702 can detect an undervoltage event by comparing a direct current (DC) voltage value with an undervoltage protection threshold. In contrast, the clock comparator output waveform 704 can detect an undervoltage event by comparing a voltage value with an undervoltage protection threshold with transient detection information. In one example, a remote sensing circuit can be used to detect a transient signal, and this transient signal detection can be an AC portion of the undervoltage detection threshold, such as an oscillating AC portion of the clock comparator output waveform 704 starting at time V1712.

[0040] Each of the UVP trigger waveform 702 and the clock comparator output waveform 704 shows detection of a sag in the voltage of the remote voltage output 706, such as when the remote voltage output 706 drops below a voltage sag threshold 722. The clock comparator output waveform 704 shows detection of this voltage sag at time V1 712 when the remote voltage output 706 reaches an intermediate voltage 724. In contrast, the UVP trigger waveform 702 shows detection of this voltage sag at a later time V2 714 when the remote voltage output 706 reaches a lower voltage 726. By using the AC portion of the transient signal detection, a smaller voltage differential can be used and a voltage sag event can be detected at an earlier time. This improves the ability of the C2VR circuit to provide early detection of any undervoltage fault or warning.

[0041] Figure 8The block diagram shows a C2VR analog feedback loop architecture 800 according to one embodiment. Figure 8 The illustrated C2VR analog feedback loop architecture 800 may include Figure 1 The C2VR digital feedback loop architecture 100 shown corresponds to an analog signal implementation.

[0042] The C2VR analog feedback loop architecture 800 includes a C2VR PTR 816 coupled to a remote voltage sensing circuit 822 and a local voltage sensing circuit 860. The C2VR analog feedback loop architecture 800 includes a first pair of feedback comparators 848 and 850 coupled to the remote voltage sensing circuit 822. The remote DAC 840 is also coupled to the first pair of feedback comparators 848 and 850. The outputs of the remote voltage sensing circuit 822 and the remote digital-to-analog converter 842 are alternately coupled to either of the first pair of feedback comparators 848 and 850 using a first comparator controller circuit 846 and a first comparator multiplexer 852. Similarly, the C2VR analog feedback loop architecture 800 includes a second pair of feedback comparators 870 and 874 coupled to the local voltage sensing circuit 860. The outputs of the local voltage sensing circuit 860 and the outputs of the local DAC 868 are alternately coupled to the second pair of feedback comparators 870 and 874 using a second comparator controller circuit 876 and a second comparator multiplexer 872. The first comparator controller circuit 846 and the second comparator controller circuit 876 use a reciprocating FSM control method to switch between comparators, for example, to calibrate a comparator that is not currently coupled to a sensing circuit. The C2VR analog feedback loop architecture 800 may also include a transient detection circuit 802 coupled to the remote voltage sensing circuit 822, which may be used to provide improved detection and alerting for any output voltage sag.

[0043] The output of the first comparator multiplexer 852 is provided to a first resistor-capacitor (RC) filter 882, which generates a filtered remote DC output. Similarly, the output of the second comparator multiplexer 872 is provided to a second RC filter 884, which generates a filtered local DC output. The filtered remote DC output and the filtered local DC output are provided to an analog comparator 864, which compares the two filtered DC outputs. When the analog comparator 864 determines that the filtered remote DC output is greater than the filtered local DC output, this indicates that the DC portion of the first comparator multiplexer 852 is lower than the target voltage value, which may occur when the load is increased and a corresponding voltage drop occurs due to the load. When the analog comparator 864 determines that the filtered remote DC output is greater than the filtered local DC output, the analog comparator 864 can send a signal to the DAC code circuit 878, which can be used to increase the code by one least significant bit (LSB) at the local DAC 868, which will cause the output voltage to increase until it reaches the target voltage.

[0044] Fig. 9 The block diagram shows a C2VR pulse count feedback loop architecture 900 according to one embodiment. Fig. 9 The C2VR pulse count feedback loop architecture 900 shown includes Figure 8 The illustrated C2VR analog feedback loop architecture 800 has several similar components, including common component 910. Unlike the C2VR analog feedback loop architecture 800, the C2VR pulse count feedback loop architecture 900 includes a modified output voltage sag detection circuit 902 and a pulse chasing detection circuit 966.

[0045] The modified output voltage sag detection circuit 902 can be used to generate the AC portion of the under voltage detection threshold, which improves the ability of the C2VR pulse count feedback loop architecture 900 to provide early detection of an under voltage fault. The modified output voltage sag detection circuit 902 includes a first comparator 904 coupled to the output of the remote digital-to-analog converter 842, a second comparator 906 coupled to the remote voltage sensing circuit 822, and a third comparator 908 coupled to the output of the remote digital-to-analog converter 842. The output of the third comparator 908 is capacitively coupled to the UVP threshold circuit 912. The UVP threshold circuit 912 can then detect when the remote voltage output drops below the UVP threshold voltage value by detecting the presence of an AC value, such as with respect to FIG. Figure 7 shown and described.

[0046] The C2VR pulse count feedback loop architecture 900 includes a pulse chase detection circuit 966. The pulse chase detection circuit 966 includes a digital circuit that receives the output from the first comparator multiplexer 952 and counts pulses within a first detection window 968. The pulse chase detection circuit 966 also receives the output from the second comparator multiplexer 972 and counts pulses within a second detection window 970. When the pulse chase detection circuit 966 determines that the pulse count from the first comparator multiplexer 952 is greater than the pulse count from the second comparator multiplexer 972, the pulse chase detection circuit 966 may send a signal to the DAC code circuit 978, which may be used to increase the code at the local DAC 868 by one least significant bit (LSB), which in turn will cause the output voltage to increase until it reaches the target voltage.

[0047] Fig.10 1 illustrates a voltage regulator method 1000 according to one embodiment. At step 1005, the method 1000 includes generating a regulated voltage signal at a voltage regulator coupled to a load. At step 1010, the method 1000 includes generating a differential voltage signal based on the regulated voltage signal at a differential load voltage sensing circuit coupled to an input node of the load and an output node of the load. At step 1015, the method 1000 includes generating an output voltage correction signal based on the differential voltage signal and the regulated voltage signal at an output voltage sensing circuit coupled to an output intercept node between the voltage regulator and the load. At step 1020, the method 1000 includes generating an updated voltage signal at the voltage regulator based on the output voltage correction signal.

[0048] At step 1025, method 1000 may further include generating a transient detection signal at a transient detection circuit coupled to the differential load voltage sensing circuit. The generation of the updated voltage signal at the voltage regulator may be further based on the transient detection signal.

[0049] At step 1030, method 1000 may further include generating a first target voltage signal at a first digital-to-analog converter circuit coupled to the differential load voltage sensing circuit. Generating the differential voltage signal at the differential load voltage sensing circuit may be further based on the first target voltage signal.

[0050] At step 1035, method 1000 may further include generating a dithering signal at a dithering circuit coupled to the first digital-to-analog converter circuit. Generating a first target voltage signal at the first digital-to-analog converter circuit may be based on the dithering signal. The differential load voltage sensing circuit includes a first comparator circuit coupled to the differential load voltage sensing circuit and the first digital-to-analog converter circuit. A differential voltage signal may be generated at the differential load voltage sensing circuit based on the first target voltage signal and the differential voltage signal.

[0051] At step 1040, method 1000 may further include generating a second target voltage signal at the second digital-to-analog converter circuit. Generating the output voltage correction signal at the differential load voltage sensing circuit may be further based on the second target voltage signal.

[0052] At step 1045, the method 1000 may further include generating, at the code modulation circuit, a code modulation signal based on the differential voltage signal. The generation of the second target voltage signal may be further based on the code modulation signal.

[0053] At step 1050, the method 1000 may also include generating a resistor voltage divider signal at a resistor voltage divider sensing circuit coupled to the output intercept node. The output voltage sensing circuit includes a first comparator for generating an output voltage correction signal based on the second target voltage signal and the resistor voltage divider signal. The differential load voltage sensing circuit also includes a first calibration control circuit and a second remote comparator. The first calibration control circuit may be configured to oscillate the differential voltage signal and the first target voltage signal between the first comparator circuit and the second remote comparator. The resistor voltage divider sensing circuit also includes a second calibration control circuit and a second comparator. The second calibration control circuit may be configured to oscillate the differential voltage signal and the first target voltage signal between the first comparator and the second comparator.

[0054] At step 1055, method 1000 may further include generating an integrator signal at the integrator circuit based on the differential voltage signal. Generating the updated voltage signal at the voltage regulator may be further based on a comparison between the output voltage correction signal and the integrator signal.

[0055] Fig.11 is a block diagram of a computing device 1100 employing parallel current source voltage regulation according to one embodiment. The performance of one or more components within the computing device 1100 may be improved by including one or more circuits or circuit methods described herein. The computing device 1100 may include a load voltage sensing circuit to generate a load voltage correction signal based on a received regulated voltage signal; an output voltage sensing circuit to generate an output voltage correction signal based on the load voltage correction signal; and a voltage regulator to generate an updated voltage signal based on the load voltage correction signal.

[0056] In one embodiment, multiple such computer systems are used in a distributed network to implement multiple components in a transaction-based environment. Object-oriented, service-oriented, or other architectures may be used to implement such functionality and communicate between multiple systems and components. In some embodiments, Fig.11 The computing device is an example of a client device that can call the methods described herein over a network. In some embodiments, Fig.11The computing device is an example of one or more of a personal computer, a smart phone, a tablet device, or various servers.

[0057] An example computing device in the form of a computer 1110 may include a processing unit 1102, a memory 1104, a removable storage device 1112, and a non-removable storage device 1114. Although the example computing device is illustrated and described as a computer 1110, the computing device may take different forms in different embodiments. For example, the computing device may instead be a smartphone, a tablet device, or other computing device, including those described with reference to FIG. Fig.11 The same or similar components as shown and described.In addition, although various data storage elements are illustrated as part of the computer 1110, the storage may include cloud-based storage accessible via a network (eg, the Internet).

[0058] Returning to the computer 1110, the memory 1104 may include a volatile memory 1106 and a non-volatile memory 1108. The computer 1110 may include various computer-readable media, or may have access to a computing environment that includes various computer-readable media, such as the volatile memory 1106 and the non-volatile memory 1108, a removable storage device 1112 and a non-removable storage device 1114. Computer storage devices include random access memory (RAM), read only memory (ROM), erasable programmable read-only memory (EPROM) and electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD ROM), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium capable of storing computer-readable instructions. Computer 1110 may include or be able to access a computing environment that includes input 1116, output 1118, and communication connection 1120. Input 1116 may include one or more of a touch screen, a touchpad, a mouse, a keyboard, a camera, and other input devices. Input 1116 may include navigation sensor input, such as a GNSS receiver, a SOP receiver, an inertial sensor (e.g., an accelerometer, a gyroscope), a local range sensor (e.g., a LIDAR), an optical sensor (e.g., a camera), or other sensors. The computer may operate in a networked environment, using communication connection 1120 to connect to one or more remote computers, such as a database server, a web server, and other computing devices. Example remote computers may include personal computers (personal computers, PCs), servers, routers, network PCs, peer devices, or other common network nodes, and the like. Communication connection 1120 may be a network interface device that can be connected to a network, such as one or both of an Ethernet card and a wireless network card or circuit. The network may include one or more of a local area network (LAN), a wide area network (WAN), the Internet, and other networks.

[0059] The processing unit 1102 of the computer 1110 can execute computer-readable instructions stored on a computer-readable medium. Hard drives (disk or solid state), CD-ROMs, and RAM are some examples of items that include non-transitory computer-readable media. For example, various computer programs 1125 or applications, such as one or more applications and modules that implement one or more of the methods illustrated and described herein, or apps or applications that execute on a mobile device or are accessible via a web browser, can be stored on a non-transitory computer-readable medium.

[0060] Embodiments may be implemented in one or a combination of hardware, firmware, and software. Embodiments may also be implemented as instructions stored on a machine-readable storage device, which may be read and executed by at least one processor to perform the operations described herein. A machine-readable storage device may include any non-transient mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable storage medium may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium, an optical storage medium, a flash memory device, and other storage devices and media.

[0061] The processor subsystem may be used to execute instructions on a machine-readable medium. The processor subsystem may include one or more processors, each processor having one or more cores. In addition, the processor subsystem may be arranged on one or more physical devices. The processor subsystem may include one or more specialized processors, such as a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), or a fixed function processor.

[0062] Examples as described herein may include logic or several components, modules or mechanisms, or may operate on logic or several components, modules or mechanisms. A module may be hardware, software or firmware that is communicatively coupled to one or more processors to perform the operations described herein. A module may be a hardware module, so a module may be considered to be a tangible entity that can perform a specified operation and may be configured or arranged in a certain manner. In one example, a circuit may be arranged as a module in a specified manner (e.g., internally or relative to an external entity, such as other circuits). In one example, all or part of one or more computer systems (e.g., a stand-alone, client or server computer system) or one or more hardware processors may be configured by firmware or software (e.g., instructions, application parts or applications) to operate to perform a specified operation. In one example, software may reside on a machine-readable medium. In one example, software causes the hardware to perform a specified operation when executed by the underlying hardware of the module. Thus, the term "hardware module" is understood to encompass a tangible entity, whether a physically constructed entity, a specifically configured (e.g., hardwired) entity, or an entity that is temporarily (e.g., transiently) configured (e.g., programmed) to operate in a specified manner or to perform part or all of any of the operations described herein. Considering the example of a temporarily configured module, each module need not be instantiated at any one time. For example, where a module comprises a general-purpose hardware processor configured using software; the general-purpose hardware processor may be configured as various different modules at various times. The software may accordingly configure the hardware processor to, for example, constitute a particular module at one time and constitute a different module at a different time. Modules may also be software or firmware modules that operate to perform the methods described herein.

[0063] Each of the following non-limiting examples may stand alone or may be combined with one or more of the other examples in various permutations or combinations.

[0064] Example 1 is a device comprising: a voltage regulator coupled to a load, the voltage regulator being used to generate a regulated voltage signal and provide the regulated voltage signal to the load; a load voltage sensing circuit coupled to an input node of the load and an output node of the load, the load voltage sensing circuit being used to generate a differential voltage signal based on the regulated voltage signal; and an output voltage sensing circuit coupled to an output node between the voltage regulator and the load, the output voltage sensing circuit being used to generate an output voltage correction signal based on the differential voltage signal and the regulated voltage signal; wherein the voltage regulator is also used to generate an updated voltage signal based on the output voltage correction signal.

[0065] In Example 2, the subject matter of Example 1 includes a transient detection circuit coupled to the load voltage sensing circuit, the transient detection circuit being used to generate a transient detection signal, wherein the generation of the updated voltage signal at the voltage regulator is also based on the transient detection signal.

[0066] In Example 3, the subject matter described in Example 2 includes a first digital-to-analog converter circuit coupled to the load voltage sensing circuit, the first digital-to-analog converter circuit being used to generate a first target voltage signal, wherein generation of the differential voltage signal at the load voltage sensing circuit is also based on the first target voltage signal.

[0067] In Example 4, the subject matter of Example 3 includes a dithering circuit coupled to the first DAC circuit, the dithering circuit being used to generate a dithering signal, wherein generation of the first target voltage signal at the first DAC circuit is based on the dithering signal.

[0068] In Example 5, the subject matter as described in Examples 3-4 includes wherein the load voltage sensing circuit includes a first comparator circuit coupled to the load voltage sensing circuit and the first digital-to-analog converter circuit, and the load voltage sensing circuit is used to generate the differential voltage signal based on the first target voltage signal and the differential voltage signal.

[0069] In Example 6, the subject matter of Example 5 includes a second digital-to-analog converter circuit to generate a second target voltage signal, wherein the generation of the output voltage correction signal at the load voltage sensing circuit is also based on the second target voltage signal.

[0070] In Example 7, the subject matter of Example 6 includes a code modulation circuit to generate a code modulation signal based on the differential voltage signal, wherein the generation of the second target voltage signal is also based on the code modulation signal.

[0071] In Example 8, the subject matter described in Examples 6-7 includes a resistor voltage divider sensing circuit coupled to the output node, the resistor voltage divider sensing circuit being used to generate a resistor voltage divider signal, wherein the output voltage sensing circuit includes a first comparator being used to generate the output voltage correction signal based on the second target voltage signal and the resistor voltage divider signal.

[0072] In Example 9, the subject matter as described in Example 8 includes wherein the load voltage sensing circuit further includes a first calibration control circuit and a second remote comparator, and the first calibration control circuit is used to oscillate the differential voltage signal and the first target voltage signal between the first comparator circuit and the second remote comparator.

[0073] In Example 10, the subject matter as described in Example 9 includes, wherein the resistor voltage divider sensing circuit further includes a second calibration control circuit and a second comparator, and the second calibration control circuit is used to oscillate the differential voltage signal and the first target voltage signal between the first comparator and the second comparator.

[0074] In Example 11, the subject matter as described in Examples 1-10 includes an integrator circuit for generating an integrator signal based on the differential voltage signal generated at the load voltage sensing circuit, wherein generation of the updated voltage signal at the voltage regulator is also based on a comparison between the output voltage correction signal and the integrator signal.

[0075] In Example 12, the subject matter as described in Examples 1-11 includes, wherein: the load includes a processor; the device also includes the processor and a processor power supply; and the processor power supply includes the voltage regulator, the load voltage sensing circuit, and the output voltage sensing circuit.

[0076] In Example 13, the subject matter as described in Examples 1-12 includes wherein: the load includes a memory device; the apparatus further includes the memory device and a memory power supply; and the memory power supply includes the voltage regulator, the load voltage sensing circuit, and the output voltage sensing circuit.

[0077] In Example 14, the subject matter as described in Examples 1-13 includes wherein: the load includes a communication interface, the communication interface complies with at least one of the following: Universal Serial Bus (USB), High-Definition Multimedia Interface (HDMI), Thunderbolt, Peripheral Component Interconnect Express (PCIe), or Ethernet specifications; the device also includes the communication interface and a communication power supply source; and the communication power supply source includes the voltage regulator, the load voltage sensing circuit, and the output voltage sensing circuit.

[0078] Example 15 is a method, comprising: generating a regulated voltage signal at a voltage regulator coupled to a load; generating a differential voltage signal based on the regulated voltage signal at a load voltage sensing circuit coupled to an input node of the load and an output node of the load; generating an output voltage correction signal based on the differential voltage signal and the regulated voltage signal at an output voltage sensing circuit coupled to an output node between the voltage regulator and the load; and generating an updated voltage signal at the voltage regulator based on the output voltage correction signal.

[0079] In Example 16, the subject matter of Example 15 includes generating a transient detection signal at a transient detection circuit coupled to the load voltage sensing circuit, wherein the generation of the updated voltage signal at the voltage regulator is also based on the transient detection signal.

[0080] In Example 17, the subject matter as described in Example 16 includes: generating a first target voltage signal at a first digital-to-analog converter circuit coupled to the load voltage sensing circuit, wherein generation of the differential voltage signal at the load voltage sensing circuit is also based on the first target voltage signal.

[0081] In Example 18, the subject matter of Example 17 includes generating a dithering signal at a dithering circuit coupled to the first digital-to-analog converter circuit, wherein generation of the first target voltage signal at the first digital-to-analog converter circuit is based on the dithering signal.

[0082] In Example 19, the subject matter as described in Examples 17-18 includes wherein: the load voltage sensing circuit includes a first comparator circuit coupled to the load voltage sensing circuit and the first digital-to-analog converter circuit; and the differential voltage signal is generated at the load voltage sensing circuit based on the first target voltage signal and the differential voltage signal.

[0083] In Example 20, the subject matter as described in Example 19 includes: generating a second target voltage signal at a second digital-to-analog converter circuit, wherein the generation of the output voltage correction signal at the load voltage sensing circuit is also based on the second target voltage signal.

[0084] In Example 21, the subject matter of Example 20 includes generating, at a code modulation circuit, a code modulation signal based on the differential voltage signal, wherein generation of the second target voltage signal is also based on the code modulation signal.

[0085] In Example 22, the subject matter as described in Examples 20-21 includes: generating a resistor voltage divider signal at a resistor voltage divider sensing circuit coupled to the output node, wherein the output voltage sensing circuit includes a first comparator for generating the output voltage correction signal based on the second target voltage signal and the resistor voltage divider signal.

[0086] In Example 23, the subject matter as described in Example 22 includes wherein: the load voltage sensing circuit also includes a first calibration control circuit and a second remote comparator; and the first calibration control circuit is configured to oscillate the differential voltage signal and the first target voltage signal between the first comparator circuit and the second remote comparator.

[0087] In Example 24, the subject matter as described in Example 23 includes wherein: the resistor voltage divider sensing circuit also includes a second calibration control circuit and a second comparator; and the second calibration control circuit is configured to oscillate the differential voltage signal and the first target voltage signal between the first comparator and the second comparator.

[0088] In Example 25, the subject matter as described in Examples 15-24 includes: generating an integrator signal at an integrator circuit based on the differential voltage signal, wherein the generation of the updated voltage signal at the voltage regulator is also based on a comparison between the output voltage correction signal and the integrator signal.

[0089] Example 26 is a circuit comprising: a capacitive voltage regulator coupled to a load, the capacitive voltage regulator being used to generate a regulated voltage signal and provide the regulated voltage signal to the load; a first voltage sensing circuit coupled to an input node of the load and an output node of the load, the first voltage sensing circuit being used to generate a remote sensing voltage signal based on the regulated voltage signal; and a second voltage sensing circuit coupled at an output node between the capacitive voltage regulator and the load to receive the regulated voltage signal, the second voltage sensing circuit generating an output voltage correction signal based on the remote sensing voltage signal and the regulated voltage signal; wherein the capacitive voltage regulator also generates the updated voltage signal based on the output voltage correction signal.

[0090] In Example 27, the subject matter of Example 26 includes wherein the first voltage sensing circuit includes a load voltage sensing circuit to generate a differential voltage signal based on the regulated voltage signal, wherein the remote sensing voltage signal is based on the differential voltage signal.

[0091] In Example 28, the subject matter of Examples 26-27 includes a transient detection circuit coupled to the first voltage sensing circuit, the transient detection circuit being used to generate a transient detection signal, wherein generation of the updated voltage signal at the capacitive voltage regulator is also based on the transient detection signal.

[0092] In Example 29, the subject matter described in Example 28 includes a first digital-to-analog converter circuit coupled to the first voltage sensing circuit, the first digital-to-analog converter circuit being used to generate a first target voltage signal, wherein generation of the remote sensing voltage signal at the first voltage sensing circuit is also based on the first target voltage signal.

[0093] In Example 30, the subject matter of Example 29 includes a dithering circuit coupled to the first digital-to-analog converter circuit, the dithering circuit being used to generate a dithering signal, wherein generation of the first target voltage signal at the first digital-to-analog converter circuit is based on the dithering signal.

[0094] In Example 31, the subject matter as described in Examples 29-30 includes wherein the first voltage sensing circuit includes a first comparator circuit coupled to the first voltage sensing circuit and the first digital-to-analog converter circuit, and the first voltage sensing circuit is used to generate the remote sensing voltage signal based on the first target voltage signal and the remote sensing voltage signal.

[0095] In Example 32, the subject matter of Example 31 includes a second digital-to-analog converter circuit to generate a second target voltage signal, wherein the generation of the output voltage correction signal at the first voltage sensing circuit is also based on the second target voltage signal.

[0096] In Example 33, the subject matter of Example 32 includes a code modulation circuit to generate a code modulation signal based on the remote sensing voltage signal, wherein the generation of the second target voltage signal is also based on the code modulation signal.

[0097] In Example 34, the subject matter as described in Examples 32-33 includes a resistor voltage divider sensing circuit coupled to the output node, the resistor voltage divider sensing circuit being used to generate a resistor voltage divider signal, wherein the second voltage sensing circuit includes a first comparator being used to generate the output voltage correction signal based on the second target voltage signal and the resistor voltage divider signal.

[0098] In Example 35, the subject matter as described in Example 34 includes, wherein the first voltage sensing circuit further includes a first calibration control circuit and a second remote comparator, and the first calibration control circuit is used to oscillate the remote sensing voltage signal and the first target voltage signal between the first comparator circuit and the second remote comparator.

[0099] In Example 36, the subject matter as described in Example 35 includes wherein the resistor voltage divider sensing circuit further includes a second calibration control circuit and a second comparator, and the second calibration control circuit oscillates the remote sensing voltage signal and the first target voltage signal between the first comparator and the second comparator.

[0100] In Example 37, the subject matter as described in Examples 26-36 includes an integrator circuit for generating an integrator signal based on the remote sensing voltage signal generated at the first voltage sensing circuit, wherein generation of the updated voltage signal at the capacitive voltage regulator is also based on a comparison between the output voltage correction signal and the integrator signal.

[0101] Example 38 is at least one machine-readable medium comprising instructions that, when executed by a processing circuit, cause the processing circuit to perform operations to implement any of Examples 1-37.

[0102] Example 39 is an apparatus comprising components for implementing any of Examples 1-37.

[0103] Example 40 is a system for implementing any of Examples 1-37.

[0104] Example 41 is a method for implementing any of Examples 1-37.

[0105] As used in this document, circuit systems or circuits may include, for example, hardwired circuits, programmable circuits (e.g., a computer processor including one or more individual instruction processing cores), state machine circuits, and / or firmware storing instructions executed by programmable circuits, alone or in any combination. Circuits or modules may be collectively or individually embodied as circuits that form part of a larger system, such as an integrated circuit (IC), a system on a chip (SoC), a desktop computer, a laptop computer, a tablet computer, a server, a smart phone, and the like.

[0106] The term "logic" used in any example herein may refer to firmware and / or circuitry configured to perform any of the above operations. The firmware may be embodied as code, instructions or instruction sets and / or data hard-coded (e.g., non-volatile) in a memory device and / or circuitry.

[0107] The "circuitry" used in any example herein may include hardwired circuits, programmable circuits, state machine circuits, logic, and / or firmware storing instructions executed by programmable circuits, either alone or in any combination. The circuit system may be implemented as an integrated circuit, such as an integrated circuit chip. In some examples, the circuit may be formed at least in part by a processor circuit executing a code and / or instruction set (e.g., software, firmware, etc.) corresponding to the functions described herein, thereby transforming a general-purpose processor into a dedicated processing environment to perform one or more operations described herein. In some examples, the processor circuit may be embodied as an independent integrated circuit or may be included as one of several components on an integrated circuit. In some examples, various components and circuits of a node or other system may be combined in a SoC architecture.

[0108] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The accompanying drawings illustrate specific examples that can be implemented. These examples are also referred to as "examples" in this article. Such examples may include additional elements other than those shown or described. However, examples including the elements shown or described are also contemplated. In addition, examples (or one or more aspects thereof) using any combination or arrangement of these elements shown or described are also contemplated, whether for a specific example (or one or more aspects thereof), or for other examples (or one or more aspects thereof) shown or described herein.

[0109] In this document, the terms "a" or "an" are used to include one or more than one, as is common in patent documents, independent of any other instance or use of "at least one" or "one or more". In this document, the term "or" is used to refer to a non-exclusive or, so that "A or B" includes "A but not B", "B but not A", and "A and B", unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the plain English equivalents of the corresponding terms "comprising" and "wherein". In addition, in the appended claims, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles, or processes that include other elements in addition to those listed after such terms in the claim are still considered to fall within the scope of the claim. In addition, in the appended claims, the terms "first", "second", and "third", etc. are used merely as labels and are not intended to imply a numerical order to their objects.

[0110] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with other examples. Other examples may be used, for example, by a person of ordinary skill in the art after consulting the above description. The abstract is used to allow the reader to quickly determine the nature of the technical disclosure. It is submitted with the following understanding: it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features may be grouped together to simplify the present disclosure. However, the claims may not record every feature disclosed herein, because the examples may be characterized by a subset of the features. In addition, the examples may include fewer features than those disclosed in a particular example. Thus, the attached claims are hereby incorporated into the detailed description section, and a claim is independently used as a separate example. The scope of the examples disclosed herein should be determined with reference to the attached claims and the full scope of equivalents to which such claims are entitled.

Claims

1. A device comprising: a voltage regulator coupled to a load, the voltage regulator being configured to generate a regulated voltage signal and provide the regulated voltage signal to the load; a load voltage sensing circuit coupled to an input node of the load and an output node of the load, the load voltage sensing circuit being configured to generate a differential voltage signal based on the regulated voltage signal; as well as an output voltage sensing circuit coupled to an output node between the voltage regulator and the load, the output voltage sensing circuit being operable to generate an output voltage correction signal based on the differential voltage signal and the regulated voltage signal; The voltage regulator is further configured to generate an updated voltage signal based on the output voltage correction signal.

2. The apparatus of claim 1, further comprising: A transient detection circuit is coupled to the load voltage sensing circuit, the transient detection circuit being used to generate a transient detection signal, wherein the generation of the updated voltage signal at the voltage regulator is also based on the transient detection signal.

3. The apparatus of claim 2, further comprising: A first digital-to-analog converter circuit is coupled to the load voltage sensing circuit, the first digital-to-analog converter circuit is used to generate a first target voltage signal, wherein the generation of the differential voltage signal at the load voltage sensing circuit is also based on the first target voltage signal.

4. The apparatus of claim 3, further comprising: A dithering circuit is coupled to the first DAC circuit, the dithering circuit is configured to generate a dithering signal, wherein generation of the first target voltage signal at the first DAC circuit is based on the dithering signal.

5. The device as claimed in claim 3, wherein: The load voltage sensing circuit includes a first comparator circuit coupled to the load voltage sensing circuit and the first digital-to-analog converter circuit, and the load voltage sensing circuit is configured to generate the differential voltage signal based on the first target voltage signal and the differential voltage signal.

6. The apparatus of claim 5, further comprising: A second digital-to-analog converter circuit is configured to generate a second target voltage signal, wherein the generation of the output voltage correction signal at the load voltage sensing circuit is also based on the second target voltage signal.

7. The apparatus of claim 6, further comprising: A resistor voltage divider sensing circuit is coupled to the output node, the resistor voltage divider sensing circuit is used to generate a resistor voltage divider signal, wherein the output voltage sensing circuit includes a first comparator, which is used to generate the output voltage correction signal based on the second target voltage signal and the resistor voltage divider signal.

8. The apparatus of claim 1, further comprising: An integrator circuit is configured to generate an integrator signal based on the differential voltage signal generated at the load voltage sensing circuit, wherein the generation of the updated voltage signal at the voltage regulator is also based on a comparison between the output voltage correction signal and the integrator signal.

9. The apparatus of claim 1, wherein: The load includes a processor; The apparatus further comprises the processor and a processor power supply; and The processor power supply includes the voltage regulator, the load voltage sensing circuit, and the output voltage sensing circuit.

10. The apparatus of claim 1, wherein: The load includes a memory device; The apparatus further comprises the memory device and a memory power supply; and The memory power supply includes the voltage regulator, the load voltage sensing circuit, and the output voltage sensing circuit.

11. The apparatus of claim 1, wherein: The load includes a communication interface that complies with at least one of the following: a Universal Serial Bus (USB), a High Definition Multimedia Interface (HDMI), Thunderbolt, a Peripheral Component Interconnect Express (PCIe), or an Ethernet specification; The apparatus further comprises the communication interface and a communication power supply; and The communications power supply source includes the voltage regulator, the load voltage sensing circuit, and the output voltage sensing circuit.

12. A method comprising: generating, at a voltage regulator coupled to the load, a regulated voltage signal; generating a differential voltage signal based on the regulated voltage signal at a load voltage sensing circuit coupled to an input node of the load and an output node of the load; generating, at an output voltage sensing circuit coupled to an output node between the voltage regulator and the load, an output voltage correction signal based on the differential voltage signal and the regulated voltage signal; and At the voltage regulator, an updated voltage signal is generated based on the output voltage correction signal.

13. The method of claim 12, further comprising: At a transient detection circuit coupled to the load voltage sensing circuit, a transient detection signal is generated, wherein the generation of the updated voltage signal at the voltage regulator is also based on the transient detection signal.

14. The method of claim 13, further comprising: A first target voltage signal is generated at a first digital-to-analog converter circuit coupled to the load voltage sensing circuit, wherein generation of the differential voltage signal at the load voltage sensing circuit is also based on the first target voltage signal.

15. The method of claim 14, further comprising: A dithering signal is generated at a dithering circuit coupled to the first digital-to-analog converter circuit, wherein generation of the first target voltage signal at the first digital-to-analog converter circuit is based on the dithering signal.

16. The method of claim 14, wherein: The load voltage sensing circuit includes a first comparator circuit coupled to the load voltage sensing circuit and the first digital-to-analog converter circuit; and The differential voltage signal is generated at the load voltage sensing circuit based on the first target voltage signal and the differential voltage signal.

17. The method of claim 16, further comprising: At the second digital-to-analog converter circuit, a second target voltage signal is generated, wherein the generation of the output voltage correction signal at the load voltage sensing circuit is also based on the second target voltage signal.

18. The method of claim 17, further comprising: A resistor voltage division signal is generated at a resistor voltage division sensing circuit coupled to the output node, wherein the output voltage sensing circuit includes a first comparator for generating the output voltage correction signal based on the second target voltage signal and the resistor voltage division signal.

19. The method of claim 18, wherein: The load voltage sensing circuit also includes a first calibration control circuit and a second remote comparator; and The first calibration control circuit is configured to oscillate the differential voltage signal and the first target voltage signal between the first comparator circuit and the second remote comparator.

20. A circuit comprising: a capacitive voltage regulator coupled to a load, the capacitive voltage regulator being configured to generate a regulated voltage signal and provide the regulated voltage signal to the load; a first voltage sensing circuit coupled to an input node of the load and an output node of the load, the first voltage sensing circuit being operable to generate a remote sense voltage signal based on the regulated voltage signal; as well as a second voltage sensing circuit coupled at an output node between the capacitive voltage regulator and the load to receive the regulated voltage signal, the second voltage sensing circuit generating an output voltage correction signal based on the remote sense voltage signal and the regulated voltage signal; The capacitive voltage regulator further generates the updated voltage signal based on the output voltage correction signal.

21. The circuit of claim 20, wherein: The first voltage sensing circuit includes a load voltage sensing circuit to generate a differential voltage signal based on the regulated voltage signal, wherein the remote sensing voltage signal is based on the differential voltage signal.

22. The circuit of claim 20, further comprising: A transient detection circuit is coupled to the first voltage sensing circuit, the transient detection circuit being configured to generate a transient detection signal, wherein the generation of the updated voltage signal at the capacitive voltage regulator is further based on the transient detection signal.

23. The circuit of claim 22, further comprising: A first digital-to-analog converter circuit is coupled to the first voltage sensing circuit, the first digital-to-analog converter circuit being used to generate a first target voltage signal, wherein generation of the remote sense voltage signal at the first voltage sensing circuit is also based on the first target voltage signal.

24. The circuit of claim 23, wherein: The first voltage sensing circuit includes a first comparator circuit coupled to the first voltage sensing circuit and the first digital-to-analog converter circuit, and the first voltage sensing circuit generates the remote sensing voltage signal based on the first target voltage signal and the remote sensing voltage signal.

25. The circuit of claim 20, further comprising: An integrator circuit is configured to generate an integrator signal based on the remote sense voltage signal generated at the first voltage sensing circuit, wherein generation of the updated voltage signal at the capacitive voltage regulator is also based on a comparison between the output voltage correction signal and the integrator signal.

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