A dual-mode power amplifier, control method and transmitter

Abstract

The present application discloses a dual-mode power amplifier, a control method and a transmitter. The power amplifier comprises: a first mode branch and a second mode branch; a first end of at least one transistor of the first mode branch connected in series is connected to an input end of the first mode branch through a first mode input pre-matching network, and a first two ends of at least one transistor of the first mode branch connected in series are connected to an output end of the first mode branch through a first mode output pre-matching network; at least one transistor of the second mode branch is connected in series and respectively connected to an input end of the second mode branch and an output end of the second mode branch; an input end of the first mode branch is connected to an input end of the second mode branch, and an output end of the first mode branch is connected to an output end of the second mode branch; when one mode branch is working, the transistor in the other mode branch acts as an impedance match and does not participate in signal amplification. The power amplifier can reduce the circuit area and power consumption.

Description

Technical Field

[0001] The present application relates to the field of radio frequency circuit technology, and in particular to a dual-mode power amplifier, a control method and a transmitter. Background Art

[0002] Power amplifiers are widely used in radio frequency circuits, for example, in radar systems. Due to the complex and varied application scenarios, power amplifiers that can operate in dual modes are required. The first mode is a high-efficiency, high-power pulse operating mode. The second mode is a high-linearity, low-power continuous wave operating mode.

[0003] In order to realize the above two modes, the dual-mode power amplifier will use switching elements to switch the impedance matching network. For example, the switching elements can be used to switch the multiplexed impedance network. However, the introduction of switching elements will increase the area of ​​the circuit and increase additional losses. At the same time, the switching elements are active devices, which will also increase the complexity of the power supply of the power amplifier. Summary of the invention

[0004] In view of this, the present application provides a dual-mode power amplifier, a control method and a transmitter, which can reduce the circuit area and reduce power consumption.

[0005] The present application provides a dual-mode power amplifier, comprising: a first mode branch and a second mode branch;

[0006] The first mode branch includes a first mode input pre-matching network, a first mode output pre-matching network and at least one transistor, and the second mode branch includes at least one transistor; a first end of the at least one transistor of the first mode branch connected in series is connected to the input end of the first mode branch through the first mode input pre-matching network, and a second end of the at least one transistor of the first mode branch connected in series is connected to the output end of the first mode branch through the first mode output pre-matching network; and at least one transistor of the second mode branch is connected in series to the input end of the second mode branch and the output end of the second mode branch respectively;

[0007] The input end of the first mode branch is connected to the input end of the second mode branch, and the output end of the first mode branch is connected to the output end of the second mode branch;

[0008] When the power amplifier operates in the first mode, the first mode input pre-matching network, the gate-source parasitic capacitance of the driving transistor in the first mode branch, and the gate-source parasitic capacitance of the driving transistor in the second mode branch form the input impedance of the first mode branch; the first mode output pre-matching network, the source-drain parasitic capacitance of the final stage transistor in the first mode branch, and the source-drain parasitic capacitance of the final stage transistor in the second mode branch form the output impedance of the first mode branch;

[0009] When the power amplifier operates in the second mode, the gate-source parasitic capacitance of the driving transistor in the second mode branch forms the input impedance of the second mode branch; the source-drain parasitic capacitance of the final stage transistor in the second mode branch forms the output impedance of the second mode branch.

[0010] In a possible implementation, when the power amplifier operates in the first mode, the transistors in the first mode branch operate in class A, class B or class AB, and the transistors in the second mode branch are turned off;

[0011] When the power amplifier operates in the second mode, the transistors in the second mode branch operate in class A, class B or class AB, and the transistors in the first mode branch are turned off.

[0012] In one possible implementation, the phase of the impedance network formed by the first mode input pre-matching network, the gate-source parasitic capacitance of the driving transistor of the first mode branch, and the gate-source parasitic capacitance of the driving transistor of the second mode branch is 0 degree, positive 180 degrees, or negative 180 degrees.

[0013] In one possible implementation, the source-drain parasitic capacitance of the final-stage transistor of the first mode branch, the source-drain parasitic capacitance of the final-stage transistor of the second mode branch, and the first mode output pre-matching network form an impedance network with a phase of 0 degrees, positive 180 degrees, or negative 180 degrees.

[0014] A possible implementation also includes: an input matching network and an output matching network; the input end of the first mode branch is connected to the input matching network, and the output end of the first mode branch is connected to the output matching network; the input end of the second mode branch is connected to the input matching network, and the output end of the second mode branch is connected to the output matching network.

[0015] A possible implementation also includes a controller; the controller is used to control the power amplifier to operate in the first mode when receiving a first control instruction; and is also used to control the power amplifier to operate in the second mode when receiving a second control instruction.

[0016] In a possible implementation manner, the controller is specifically configured to control the gate voltage of the transistor in the first mode branch so that the transistor in the first mode branch operates in class A, class B or class AB, and control the gate voltage of the transistor in the second mode branch so that the transistor in the second mode branch is turned off;

[0017] The controller is specifically used to control the gate voltage of the transistors in the second mode branch so that the transistors in the second mode branch operate in class A, class B or class AB, and to control the gate voltage of the transistors in the first mode branch so that the transistors in the first mode branch operate in class C.

[0018] The present application also provides a control method for a dual-mode power amplifier, the dual-mode power amplifier comprising: a first mode branch and a second mode branch; the first mode branch comprises a first mode input pre-matching network, a first mode output pre-matching network and at least one transistor, and the second mode branch comprises at least one transistor; a first end of at least one transistor of the first mode branch connected in series is connected to the input end of the first mode branch through the first mode input pre-matching network, and a second end of at least one transistor of the first mode branch connected in series is connected to the output end of the first mode branch through the first mode output pre-matching network; at least one transistor of the second mode branch is connected in series to the input end of the second mode branch and the output end of the second mode branch respectively; the input end of the first mode branch is connected to the input end of the second mode branch, and the output end of the first mode branch is connected to the output end of the second mode branch;

[0019] The control method comprises:

[0020] When the power amplifier operates in the first mode, the transistors in the first mode branch are controlled to operate in class A, class B or class AB, and the transistors in the second mode branch are controlled to be turned off; the first mode input pre-matching network, the gate-source parasitic capacitance of the driving transistor in the first mode branch, and the gate-source parasitic capacitance of the driving transistor in the second mode branch form the input impedance of the first mode branch; the first mode output pre-matching network, the source-drain parasitic capacitance of the final stage transistor in the first mode branch, and the source-drain parasitic capacitance of the final stage transistor in the second mode branch form the output impedance of the first mode branch;

[0021] When the power amplifier operates in the second mode, the transistors in the second mode branch are controlled to operate in Class A, Class B or Class AB, and the transistors in the first mode branch are controlled to be turned off; the parasitic capacitance of the driving transistor in the second mode branch forms the input impedance of the second mode branch; and the source-drain parasitic capacitance of the final stage transistor in the second mode branch forms the output impedance of the second mode branch.

[0022] The present application also provides a transmitter, comprising the dual-mode power amplifier introduced above.

[0023] The present application also provides a dual-mode power amplifier, comprising: a first mode branch and a second mode branch;

[0024] The first mode branch includes a first mode input pre-matching network, a first mode output pre-matching network and at least one transistor, and the second mode branch includes at least one transistor; a first end of the at least one transistor of the first mode branch connected in series is connected to the input end of the first mode branch through the first mode input pre-matching network, and a second end of the at least one transistor of the first mode branch connected in series is connected to the output end of the first mode branch through the first mode output pre-matching network; and at least one transistor of the second mode branch is connected in series to the input end of the second mode branch and the output end of the second mode branch respectively;

[0025] The input end of the first mode branch is connected to the input end of the second mode branch, and the output end of the first mode branch is connected to the output end of the second mode branch;

[0026] The phase of the impedance network formed by the first mode input pre-matching network, the gate-source parasitic capacitance of the driving transistor of the first mode branch and the gate-source parasitic capacitance of the driving transistor of the second mode branch is 0 degree, positive 180 degrees or negative 180 degrees;

[0027] The source-drain parasitic capacitance of the final transistor of the first mode branch, the source-drain parasitic capacitance of the final transistor of the second mode branch and the first mode output pre-matching network form an impedance network with a phase of 0 degree, positive 180 degrees or negative 180 degrees.

[0028] The dual-mode power amplifier provided in the embodiment of the present application can be implemented to work in dual modes, that is, the first mode is a high-power pulse working mode, and the second mode is a low-power continuous wave working mode. In addition, there is no need to set a special switching device to isolate the two working modes, but a first mode branch and a second mode branch are set, and the two mode branches are similar to parallel, and only the input pre-matching network and the output pre-matching network are set in the first mode branch. When one of the mode branches is working, the transistor in the other mode branch acts as an impedance match and does not participate in the signal amplification work, so there is no need to set a separate switching device to switch the matching network of the two paths. Therefore, the power amplifier provided in the embodiment of the present application can realize dual-mode operation while saving circuit area and reducing the insertion loss of the matching network. Since the switching devices are all active devices, the power supply complexity is also reduced without the switching devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of a dual-mode power amplifier provided in an embodiment of the present application;

[0030] Figure 2 A schematic diagram of another dual-mode power amplifier provided in an embodiment of the present application;

[0031] Figure 3 A schematic diagram of another dual-mode power amplifier provided in an embodiment of the present application;

[0032] Figure 4 A schematic diagram of another dual-mode power amplifier provided in an embodiment of the present application;

[0033] Figure 5 An equivalent diagram of a dual-mode power amplifier provided in an embodiment of the present application operating in a first mode;

[0034] Figure 6 An equivalent diagram of a dual-mode power amplifier provided in an embodiment of the present application operating in a second mode;

[0035] Figure 7 A flow chart of a control method for a dual-mode power amplifier provided in an embodiment of the present application

[0036] Figure 8 A schematic diagram of a transmitter provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the technical solutions provided by the embodiments of the present application, professional terms are first introduced below.

[0038] The power amplifier may include multiple categories according to the conduction time of the transistor in one cycle, and the embodiments of the present application relate to Class A, Class B, Class AB and Class C.

[0039] Class A: refers to a type of amplifier in which any power output element of the power amplifier will not have current cutoff (i.e. stop output) during the entire cycle of the signal, i.e. the positive and negative half cycles of the sine wave, i.e. the Class A amplifier has signal output during the entire cycle. Class A amplifiers generate high heat when working and have very low efficiency, but their inherent advantage is that there is no crossover distortion. Single-ended amplifiers all work in Class A mode, and push-pull amplifiers can be Class A, Class B, or Class AB.

[0040] Class B: refers to a type of amplifier in which the positive and negative half cycles of the sine wave are amplified and output by the two "arms" of the push-pull output stage in turn. The conduction time of each "arm" is half a cycle of the signal, that is, the Class B amplifier only outputs a signal for half a cycle in one cycle. The advantage of the Class B amplifier is high efficiency, and the disadvantage is that it will produce crossover distortion.

[0041] Class AB: Between Class A and Class B, the conduction time of each "arm" of the push-pull amplifier is greater than half a cycle of the signal but less than one cycle. Class AB amplification effectively solves the crossover distortion problem of Class B amplifiers, and its efficiency is higher than that of Class A amplifiers, so it has been widely used.

[0042] Class C: A Class C amplifier is a switching amplifier that works by converting the input signal into a pulse width modulated (PWM) signal and then amplifying it through a power amplifier. In a Class C amplifier, the transistor is in the off state most of the time and only turns on near the positive and negative peaks of the input signal. In this way, the transistor is turned on for a very short time, achieving high efficiency.

[0043] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0044] See also Figure 1 , which is a schematic diagram of a dual-mode power amplifier provided in an embodiment of the present application.

[0045] The dual-mode power amplifier provided in the embodiment of the present application includes: an input matching network 10, an output matching network 20, a first mode branch 100 and a second mode branch 200; the input end of the dual-mode power amplifier is in, and the output end is out.

[0046] The first mode branch 100 includes at least one transistor, and the second mode branch 200 includes at least one transistor; the present application does not specifically limit the number of transistors included in the first mode branch 100, Figure 1In the description, n transistors are taken as an example, where n is an integer greater than or equal to 1, and the n transistors are connected in series in sequence, namely, the driving transistor G11 of the first mode branch 100, the intermediate transistor of the first mode branch 100, and the final transistor G1n of the first mode branch 100. Similarly, the present application does not specifically limit the number of transistors included in the second mode branch 200. Figure 1 In the description, n transistors are taken as an example, where n is an integer greater than or equal to 1, and the n transistors are connected in series in sequence, namely the driving transistor G21 of the second mode branch 200, the middle stage transistor of the second mode branch 200, and the final stage transistor G2n of the second mode branch 200.

[0047] The first mode branch 100 includes a first mode input pre-matching network 101, a first mode output pre-matching network 102 and at least one transistor, and the second mode branch 200 includes at least one transistor; the first end of at least one transistor of the first mode branch 100 after being connected in series is connected to the input end of the first mode branch through the first mode input pre-matching network 101, and the second end of at least one transistor of the first mode branch after being connected in series is connected to the output end of the first mode branch through the first mode output pre-matching network 102; at least one transistor of the second mode branch is connected in series to the input end and the output end of the second mode branch respectively.

[0048] The present application does not specifically limit the implementation of the first mode input pre-matching network 101. For example, the first mode input pre-matching network 101 may include at least one of a microstrip line, a resistor, a capacitor, an inductor, and a transformer.

[0049] The present application does not specifically limit the implementation of the first mode output pre-matching network 102. For example, the first mode output pre-matching network 102 may include at least one of a microstrip line, a capacitor, an inductor, and a transformer.

[0050] The input end of the first mode branch is connected to the input end of the second mode branch, and the output end of the first mode branch is connected to the output end of the second mode branch; that is, the two mode branches are connected in parallel.

[0051] When the power amplifier operates in the first mode, the first mode input pre-matching network 101, the gate-source parasitic capacitance Cgs1 of the driving transistor in the first mode branch, and the gate-source parasitic capacitance Cgs2 of the driving transistor in the second mode branch form the input impedance of the first mode branch; the first mode output pre-matching network 102, the source-drain parasitic capacitance Cds1 of the final stage transistor in the first mode branch, and the source-drain parasitic capacitance Cds2 of the final stage transistor in the second mode branch form the output impedance of the first mode branch.

[0052] When the power amplifier operates in the second mode, the gate-source parasitic capacitance Cgs2 of the driving transistor in the second mode branch forms the input impedance of the second mode branch; the source-drain parasitic capacitance Cds2 of the final transistor in the second mode branch forms the output impedance of the second mode branch.

[0053] When the power amplifier works in the first mode, the transistors in the first mode branch 100 work in class A, class B or class AB, and the transistors in the second mode branch 200 work in class C; the transistors work in class C, that is, the transistors are equivalent to switching devices, and there is no need to set up switching devices separately for additional isolation. It should be understood that when the power amplifier works in the first mode, the transistors in the second mode branch 200 are biased in class C, and they are externally characterized as grounding capacitors, which can also be called parasitic capacitors. The parasitic capacitance of G21 is Cgs2, and the parasitic capacitance of G2n is Cds2. That is, the transistors in the second mode branch 200 can be used as matching impedances for the first mode branch 100.

[0054] When the power amplifier works in the second mode, the transistors in the second mode branch 200 work in class A, class B or class AB, and the transistors in the first mode branch 100 work in class C. That is, at this time, the transistors in the first mode branch are equivalent to switching devices, which are externally characterized as grounding capacitors, the parasitic capacitance of G11 is Cgs1, and the parasitic capacitance of G1n is Cds1, that is, the transistors in the first mode branch 100 can be used as matching impedances for the second mode branch 200.

[0055] The power amplifier provided in the embodiment of the present application does not specifically limit the number of transistors included in each branch. It should be understood that each branch includes at least one transistor, and the number of transistors in the two branches can be the same or different, without specific limitation. When each branch includes only one transistor, the transistor serves as a driving transistor and a final-stage transistor. When a branch includes two transistors, the two transistors are connected in series, the transistor at the input end serves as a driving transistor, and the transistor at the output end serves as a final-stage transistor. When a branch includes three or more transistors, except for the driving transistor and the final-stage transistor, the remaining transistors are intermediate-stage transistors.

[0056] Specifically, when the first mode branch includes one transistor, the transistor is a first mode branch driving transistor and is also a final stage transistor of the first mode branch;

[0057] When the first mode branch includes at least two transistors, the first ends of the at least two transistors connected in series are connected to the input matching network, and the second ends of the at least two transistors connected in series are connected to the output matching network; the transistor connected to the input matching network is the driving transistor of the first mode branch, the transistor connected to the output matching network is the final transistor of the first mode branch, and the remaining transistors are intermediate transistors of the first mode branch;

[0058] When the second mode branch includes a transistor, the transistor is a driving transistor of the second mode branch and is also a final stage transistor of the second mode branch;

[0059] When the second mode branch includes at least two transistors, the first ends of the at least two transistors are connected in series in sequence to the input matching network, and the second ends of the at least two transistors are connected in series in sequence to the output matching network; the transistor connected to the input matching network is the driving transistor of the second mode branch, the transistor connected to the output matching network is the final stage transistor of the second mode branch, and the remaining transistors are intermediate stage transistors of the second mode branch.

[0060] Figure 2 The schematic diagram is a dual-mode power amplifier with two mode branches each including one transistor as an example. That is, the first mode branch 100 includes a driving transistor G11, and G11 is also a final stage transistor. Similarly, the second mode branch 200 includes a driving transistor G21, and G21 is also a final stage transistor.

[0061] In addition, the two mode branches in the dual-mode power amplifier may also each include two transistors, see Figure 3 , which is a schematic diagram of another dual-mode power amplifier provided in an embodiment of the present application.

[0062] The first mode branch 100 includes a driving transistor G11 and a final stage transistor G11. It should be understood that a plurality of transistors in a single branch generally need to be connected together through a matching network, that is, the driving transistor G11 and the final stage transistor G11 are connected through an inter-stage matching network.

[0063] The second mode branch 200 includes a driving transistor G21 and a final stage transistor G22. Similarly, the driving transistor G21 and the final stage transistor G22 are connected via an inter-stage matching network.

[0064] The dual-mode power amplifier provided in the embodiment of the present application also includes a controller; it should be understood that in an actual working scenario, the dual-mode power amplifier will switch between the first mode and the second mode due to different working conditions. At this time, the controller is required to control the transistors in the first mode branch and the second mode branch to complete the switching of the working mode. Specifically, the controller is used to control the power amplifier to operate in the first mode when receiving a first control instruction; and is also used to control the power amplifier to operate in the second mode when receiving a second control instruction.

[0065] The controller is specifically used to control the gate voltage of the transistors in the first mode branch so that the transistors in the first mode branch operate in class A, class B or class AB, and control the gate voltage of the transistors in the second mode branch so that the transistors in the second mode branch operate in class C;

[0066] The controller is specifically used to control the gate voltage of the transistor in the second mode branch so that the transistor in the second mode branch works in class A, class B or class AB, and control the gate voltage of the transistor in the first mode branch so that the transistor in the first mode branch works in class C.

[0067] The embodiment of the present application does not specifically limit the implementation method of the controller, which may be a control chip that controls the gate voltage of the transistor, or an integrated drive circuit.

[0068] In addition, the dual-mode power amplifier provided in the embodiment of the present application may further include at least one of a first-mode input pre-matching network and a first-mode output pre-matching network.

[0069] In the following, in conjunction with the accompanying drawings, a dual-mode power amplifier including a first-mode input pre-matching network and a first-mode output pre-matching network is taken as an example for introduction.

[0070] See also Figure 4 , which is a schematic diagram of another dual-mode power amplifier provided in an embodiment of the present application.

[0071] The input end of the first mode branch 100 is connected to the input matching network 10, and the output end of the first mode branch 100 is connected to the output matching network 20; the input end of the second mode branch 200 is connected to the input matching network 10, and the output end of the second mode branch 200 is connected to the output matching network 20. The first end of the first mode input pre-matching network 101 is connected to the input matching network 10, and the second end of the first mode input pre-matching network 101 is connected to the driving transistor G11 of the first mode branch.

[0072] The first mode input pre-matching network 101, the parasitic capacitance Cgs1 of the driving transistor G11 of the first mode branch and the parasitic capacitance Cgs2 of the driving transistor G21 of the second mode branch form an impedance network with a phase of 0 degree, positive 180 degrees or negative 180 degrees.

[0073] A first end of the first mode output pre-matching network 102 is connected to the final transistor of the first mode branch, and a second end of the first mode output pre-matching network 102 is connected to the output matching network 20 .

[0074] The parasitic capacitance of the final transistor of the first mode branch, the parasitic capacitance of the final transistor of the second mode branch and the first mode output pre-matching network form an impedance network with a phase of 0 degree, positive 180 degrees or negative 180 degrees.

[0075] When the power amplifier operates in the second mode, the matching network of the second mode branch includes an input matching network and an output matching network, and the first mode input pre-matching network, the transistor of the first mode branch and the first mode output pre-matching network do not participate in the impedance matching of the second mode branch.

[0076] When the power amplifier operates in the first mode, for the final transistor of the first mode branch, Cds1, the first mode output pre-matching network, Cds2 and the output matching network constitute the output matching network of the final transistor of the first mode branch, wherein the phase of the impedance network composed of Cds1, the first mode output pre-matching network and Cds2 is 0 degree, positive 180 degrees or negative 180 degrees. For the driving transistor of the first mode branch, Cgs1, the first mode input pre-matching network, Cgs2 and the input matching network constitute the input matching network of the driving transistor of the first mode branch, wherein the phase of the impedance network composed of Cgs1, the first mode input pre-matching network and Cgs2 is 0 degree, positive 180 degrees or negative 180 degrees.

[0077] When the power amplifier operates in the second mode, for the final transistor of the second mode branch, since the phase of the impedance network composed of Cds1, the first mode output pre-matching network and Cds2 is 0 degree, positive 180 degrees or negative 180 degrees, and the final transistor of the first mode branch is biased in Class C at this time, the drain end of the tube core is open, therefore Cds1, the impedance network composed of the first mode output pre-matching network and Cds2 is open for the drain of the final transistor of the second mode branch and does not participate in impedance matching, and the output matching of the final transistor of the second mode branch only includes the output matching network. For the driving transistor of the second mode branch, since the phase of the impedance network composed of Cgs1, the first mode input pre-matching network and Cgs2 is 0 degree, positive 180 degrees or negative 180 degrees, and the driving transistor of the first mode branch is biased in class C at this time, the gate end of the die is open, so Cgs1, the impedance network composed of the first mode input pre-matching network and Cgs2 is an open circuit for the gate of the final transistor of the second mode branch and does not participate in impedance matching. The input matching of the final transistor of the second mode branch only includes the input matching network.

[0078] The embodiment of the present application designs the phase of the above impedance network to be 0 degree, positive 180 degrees or negative 180 degrees because, when the first mode branch is not working, the final transistor of the first mode branch is in an open circuit state, and the impedance is located at the rightmost end of the Smith circle. When passing through the 0 degree network, it remains unchanged and does not affect the impedance matching of the second mode branch at the open circuit. When passing through positive 180 degrees or negative 180 degrees, it goes around the Smith circle once and returns to the open circuit, which still does not affect the impedance matching of the second mode branch.

[0079] In order to enable those skilled in the art to better understand the dual-mode power amplifier provided in the embodiment of the present application, the equivalent circuit diagrams corresponding to the dual-mode power amplifier operating in the first mode and the second mode are respectively introduced below in conjunction with the accompanying drawings.

[0080] See also Figure 5 , which is an equivalent diagram of the dual-mode power amplifier provided in an embodiment of the present application operating in the first mode.

[0081] from Figure 5It can be seen that when the dual-mode power amplifier works in the first mode, the final transistor of the first mode branch, Cds1, the first mode output pre-matching network, Cds2, and the output matching network constitute the output matching network of the final transistor of the first mode branch. The driving transistor of the first mode branch, Cgs1, the first mode input pre-matching network, Cgs2, and the input matching network constitute the input matching network of the driving transistor of the first mode branch. That is, when the dual-mode power amplifier works in the first mode, the second mode branch only includes the parasitic capacitance Cgs2 of the driving transistor in the second mode branch and the parasitic capacitance Cds2 of the final transistor.

[0082] See also Figure 6 , which is an equivalent diagram of the dual-mode power amplifier provided in an embodiment of the present application operating in the second mode.

[0083] from Figure 6 It can be seen that, since the phase of the impedance network designed in the present application satisfies 0 degrees, positive 180 degrees or negative 180 degrees, when the dual-mode power amplifier operates in the second mode, the first-mode input pre-matching network, the transistor of the first-mode branch and the first-mode output pre-matching network do not participate in the impedance matching of the second-mode branch. That is, the transistor in the first-mode branch is in an open-circuit state, and any device in the first-mode branch does not participate in the operation of the second-mode branch.

[0084] The embodiment of the present application also provides a dual-mode power amplifier, comprising: a first mode branch and a second mode branch;

[0085] The first mode branch includes a first mode input pre-matching network, a first mode output pre-matching network and at least one transistor, and the second mode branch includes at least one transistor; a first end of the at least one transistor of the first mode branch connected in series is connected to the input end of the first mode branch through the first mode input pre-matching network, and a second end of the at least one transistor of the first mode branch connected in series is connected to the output end of the first mode branch through the first mode output pre-matching network; and at least one transistor of the second mode branch is connected in series to the input end of the second mode branch and the output end of the second mode branch respectively;

[0086] The input end of the first mode branch is connected to the input end of the second mode branch, and the output end of the first mode branch is connected to the output end of the second mode branch;

[0087] The phase of the impedance network formed by the first mode input pre-matching network, the gate-source parasitic capacitance of the driving transistor of the first mode branch and the gate-source parasitic capacitance of the driving transistor of the second mode branch is 0 degree, positive 180 degrees or negative 180 degrees;

[0088] The source-drain parasitic capacitance of the final transistor of the first mode branch, the source-drain parasitic capacitance of the final transistor of the second mode branch and the first mode output pre-matching network form an impedance network with a phase of 0 degree, positive 180 degrees or negative 180 degrees.

[0089] The purpose of the above phase settings is that when the first mode branch is working, only the driving transistor and the final transistor of the second mode branch participate in the impedance matching of the first mode branch. The purpose is that when the second mode branch is working, any device in the first mode branch does not participate in the impedance matching of the second mode branch.

[0090] Based on a dual-mode power amplifier provided in the above embodiment, an embodiment of the present application further provides a control method for the dual-mode power amplifier, which is described in detail below in conjunction with the accompanying drawings.

[0091] See also Figure 7 , which is a flow chart of a control method for a dual-mode power amplifier provided in an embodiment of the present application.

[0092] The control method of a dual-mode power amplifier provided in an embodiment of the present application, the dual-mode power amplifier comprises: a first mode branch and a second mode branch; the first mode branch comprises a first mode input pre-matching network, a first mode output pre-matching network and at least one transistor, and the second mode branch comprises at least one transistor; a first end of at least one transistor of the first mode branch connected in series is connected to an input end of the first mode branch through the first mode input pre-matching network, and a second end of at least one transistor of the first mode branch connected in series is connected to an output end of the first mode branch through the first mode output pre-matching network; at least one transistor of the second mode branch is connected in series and respectively connected to an input end of the second mode branch and an output end of the second mode branch; the input end of the first mode branch is connected to an input end of the second mode branch, and the output end of the first mode branch is connected to an output end of the second mode branch;

[0093] Control methods include:

[0094] S501: When the power amplifier operates in the first mode, the transistors in the first mode branch are controlled to operate in class A, class B or class AB, and the transistors in the second mode branch are controlled to be turned off. The first mode input pre-matching network, the gate-source parasitic capacitance of the driving transistor in the first mode branch, and the gate-source parasitic capacitance of the driving transistor in the second mode branch form the input impedance of the first mode branch; the first mode output pre-matching network, the source-drain parasitic capacitance of the final transistor in the first mode branch, and the source-drain parasitic capacitance of the final transistor in the second mode branch form the output impedance of the first mode branch;

[0095] S502: When the power amplifier operates in the second mode, the transistors in the second mode branch are controlled to operate in class A, class B or class AB, and the transistors in the first mode branch are controlled to be turned off. The parasitic capacitance of the driving transistor in the second mode branch forms the input impedance of the second mode branch; the source-drain parasitic capacitance of the final stage transistor in the second mode branch forms the output impedance of the second mode branch.

[0096] The control method of the dual-mode power amplifier provided in the embodiment of the present application can realize operation in dual modes, that is, the first mode is a high-power pulse working mode, and the second mode is a low-power continuous wave working mode. In addition, there is no need to set up a special switching device to isolate the two working modes, but a first mode branch and a second mode branch are set up, and the two mode branches are similar to parallel connection. When one mode branch is working, the transistor in the other mode branch acts as an impedance match and does not participate in the signal amplification work, and there is no need to set up a switching device separately. Therefore, the control method of the power amplifier provided in the embodiment of the present application can realize dual-mode operation while saving circuit area and reducing the insertion loss of the matching network. Since the switching devices are all active devices, the power supply complexity is also reduced without the use of switching devices.

[0097] A possible implementation method is to control the transistors in the first mode branch to operate in class A, class B, or class AB, and control the transistors in the second mode branch to operate in class C, specifically including:

[0098] Controlling the gate voltage of the transistor in the first mode branch so that the transistor in the first mode branch operates in class A, class B or class AB, and controlling the gate voltage of the transistor in the second mode branch so that the transistor in the second mode branch operates in class C;

[0099] Controlling the transistors in the second mode branch to operate in class A, class B, or class AB, and controlling the transistors in the first mode branch to operate in class C, specifically includes:

[0100] The gate voltage of the transistor in the second mode branch is controlled so that the transistor in the second mode branch operates in class A, class B or class AB, and the gate voltage of the transistor in the first mode branch is controlled so that the transistor in the first mode branch operates in class C.

[0101] Based on a dual-mode power amplifier and a control method of the dual-mode power amplifier provided in the above embodiments, the embodiments of the present application further provide a transmitter, which will be described in detail below in conjunction with the accompanying drawings.

[0102] See also Figure 8 , which is a schematic diagram of a transmitter provided in an embodiment of the present application.

[0103] The transmitter 1000 provided in the embodiment of the present application includes the dual-mode power amplifier 600 introduced in the above embodiment.

[0104] The transmitter provided in the embodiment of the present application includes the dual-mode power amplifier introduced above, and can be implemented to work in dual modes, that is, the first mode is a high-power pulse working mode, and the second mode is a low-power continuous wave working mode. Moreover, there is no need to set a special switch device to isolate the two working modes, but a first mode branch and a second mode branch are set, and the two mode branches are similar to parallel connection. When one mode branch is working, the transistor in the other mode branch works in Class C, as impedance matching, and does not participate in signal amplification work, and there is no need to set a switch device separately. Therefore, the power amplifier provided in the embodiment of the present application can realize dual-mode operation while saving circuit area and reducing the insertion loss of the matching network. Since the switch devices are all active devices, the power supply complexity is also reduced without the switch device. Therefore, the circuit area of ​​the transmitter provided in the present application can also be reduced, and there is no need to set an active switch device, saving power and power consumption.

[0105] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A dual-mode power amplifier, characterized in that: include: A first mode branch and a second mode branch; The first mode branch includes a first mode input pre-matching network, a first mode output pre-matching network and at least one transistor, and the second mode branch includes at least one transistor; a first end of the at least one transistor of the first mode branch connected in series is connected to the input end of the first mode branch through the first mode input pre-matching network, and a second end of the at least one transistor of the first mode branch connected in series is connected to the output end of the first mode branch through the first mode output pre-matching network; The at least one transistor of the second mode branch is connected in series and respectively connected to an input end of the second mode branch and an output end of the second mode branch; The input end of the first mode branch is connected to the input end of the second mode branch, and the output end of the first mode branch is connected to the output end of the second mode branch; When the power amplifier operates in a first mode, the first mode input pre-matching network, the gate-source parasitic capacitance of the driving transistor in the first mode branch, and the gate-source parasitic capacitance of the driving transistor in the second mode branch form an input impedance of the first mode branch; The first mode output pre-matching network, the source-drain parasitic capacitance of the final stage transistor in the first mode branch, and the source-drain parasitic capacitance of the final stage transistor in the second mode branch form an output impedance of the first mode branch; When the power amplifier operates in the second mode, the gate-source parasitic capacitance of the driving transistor in the second mode branch forms the input impedance of the second mode branch; The source-drain parasitic capacitance of the final-stage transistor in the second-mode branch forms the output impedance of the second-mode branch.

2. The power amplifier according to claim 1, characterized in that: When the power amplifier operates in the first mode, the transistors in the first mode branch operate in class A, class B or class AB, and the transistors in the second mode branch are turned off; When the power amplifier operates in the second mode, the transistors in the second mode branch operate in class A, class B or class AB, and the transistors in the first mode branch are turned off.

3. The power amplifier according to claim 1, characterized in that: The phase of the impedance network formed by the first mode input pre-matching network, the gate-source parasitic capacitance of the driving transistor of the first mode branch and the gate-source parasitic capacitance of the driving transistor of the second mode branch is 0 degree, positive 180 degrees or negative 180 degrees.

4. The power amplifier according to claim 1, characterized in that: The source-drain parasitic capacitance of the final transistor of the first mode branch, the source-drain parasitic capacitance of the final transistor of the second mode branch and the first mode output pre-matching network form an impedance network with a phase of 0 degree, positive 180 degrees or negative 180 degrees.

5. The power amplifier according to claim 1, characterized in that: Also includes: Input matching network and output matching network; The input end of the first mode branch is connected to the input matching network, and the output end of the first mode branch is connected to the output matching network; An input end of the second mode branch is connected to the input matching network, and an output end of the second mode branch is connected to the output matching network.

6. The power amplifier according to any one of claims 1 to 5, characterized in that: Also includes a controller; The controller is used to control the power amplifier to operate in the first mode when receiving a first control instruction; and is also used to control the power amplifier to operate in the second mode when receiving a second control instruction.

7. The power amplifier according to claim 6, characterized in that: The controller is specifically configured to control the gate voltage of the transistors in the first mode branch so that the transistors in the first mode branch operate in class A, class B or class AB, and control the gate voltage of the transistors in the second mode branch so that the transistors in the second mode branch are turned off; The controller is specifically used to control the gate voltage of the transistors in the second mode branch so that the transistors in the second mode branch operate in class A, class B or class AB, and to control the gate voltage of the transistors in the first mode branch so that the transistors in the first mode branch operate in class C.

8. A control method for a dual-mode power amplifier, characterized in that: The dual-mode power amplifier comprises: a first mode branch and a second mode branch; the first mode branch comprises a first mode input pre-matching network, a first mode output pre-matching network and at least one transistor, and the second mode branch comprises at least one transistor; a first end of at least one transistor of the first mode branch connected in series is connected to an input end of the first mode branch through the first mode input pre-matching network, and a second end of at least one transistor of the first mode branch connected in series is connected to an output end of the first mode branch through the first mode output pre-matching network; at least one transistor of the second mode branch is connected in series to an input end of the second mode branch and an output end of the second mode branch respectively; the input end of the first mode branch is connected to an input end of the second mode branch, and the output end of the first mode branch is connected to an output end of the second mode branch; The control method comprises: When the power amplifier operates in the first mode, the transistors in the first mode branch are controlled to operate in class A, class B or class AB, and the transistors in the second mode branch are controlled to be turned off; the first mode input pre-matching network, the gate-source parasitic capacitance of the driving transistor in the first mode branch, and the gate-source parasitic capacitance of the driving transistor in the second mode branch form the input impedance of the first mode branch; the first mode output pre-matching network, the source-drain parasitic capacitance of the final stage transistor in the first mode branch, and the source-drain parasitic capacitance of the final stage transistor in the second mode branch form the output impedance of the first mode branch; When the power amplifier operates in the second mode, the transistors in the second mode branch are controlled to operate in Class A, Class B or Class AB, and the transistors in the first mode branch are controlled to be turned off; the parasitic capacitance of the driving transistor in the second mode branch forms the input impedance of the second mode branch; and the source-drain parasitic capacitance of the final stage transistor in the second mode branch forms the output impedance of the second mode branch.

9. A transmitter, characterized in that: A dual-mode power amplifier comprising any one of claims 1-7.

10. A dual-mode power amplifier, characterized in that: include: A first mode branch and a second mode branch; The first mode branch includes a first mode input pre-matching network, a first mode output pre-matching network and at least one transistor, and the second mode branch includes at least one transistor; a first end of the at least one transistor of the first mode branch connected in series is connected to the input end of the first mode branch through the first mode input pre-matching network, and a second end of the at least one transistor of the first mode branch connected in series is connected to the output end of the first mode branch through the first mode output pre-matching network; The at least one transistor of the second mode branch is connected in series and respectively connected to an input end of the second mode branch and an output end of the second mode branch; The input end of the first mode branch is connected to the input end of the second mode branch, and the output end of the first mode branch is connected to the output end of the second mode branch; The phase of the impedance network formed by the first mode input pre-matching network, the gate-source parasitic capacitance of the driving transistor of the first mode branch and the gate-source parasitic capacitance of the driving transistor of the second mode branch is 0 degree, positive 180 degrees or negative 180 degrees; The source-drain parasitic capacitance of the final transistor of the first mode branch, the source-drain parasitic capacitance of the final transistor of the second mode branch and the first mode output pre-matching network form an impedance network with a phase of 0 degree, positive 180 degrees or negative 180 degrees.

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