Bandwidth configuration method, device and equipment and computer readable storage medium

Abstract

The invention discloses a bandwidth configuration method, device and equipment and a computer readable storage medium, and relates to the technical field of communication. The method comprises the following steps: acquiring a required bandwidth for data transmission of an aggregation link, wherein the aggregation link comprises a plurality of links; configuration information is obtained based on the required bandwidth and the bandwidth of each link, the configuration information comprises a first number of links needing to be in an open state in the multiple links, the first bandwidth of the links of the first number is larger than or equal to the required bandwidth, and the difference value between the first bandwidth and the required bandwidth is smaller than a difference value threshold value; and configuring the aggregated link according to the configuration information, so that the number of the links in the open state in the plurality of links is the first number. According to the method, the bandwidth of the link in the open state is larger than or equal to the required bandwidth, the requirement of data transmission is met, the difference value between the bandwidth of the link in the open state and the required bandwidth is smaller than the difference value threshold value, and waste of bandwidth resources caused by the fact that the number of the links in the open state is too large is avoided.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a bandwidth configuration method, apparatus, device, and computer-readable storage medium. Background Art

[0002] With the development of communication technology, Ethernet interfaces such as 10 Gigabit Ethernet (GE), 25GE, 50GE, 100GE, 200GE, and 400GE have been widely used, which has increased the transmission bandwidth of the network and also led to an increase in network energy consumption. However, the bandwidth utilization rate of Ethernet interfaces is currently low, resulting in energy waste due to unused bandwidth. Therefore, how to configure the bandwidth of Ethernet interfaces is an urgent problem to be solved. Summary of the invention

[0003] The present application provides a bandwidth configuration method, apparatus, device and computer-readable storage medium for configuring bandwidth of an aggregated link.

[0004] In a first aspect, a bandwidth configuration method is provided, the method comprising: obtaining a required bandwidth for transmitting data on an aggregated link, the aggregated link comprising multiple links; obtaining configuration information based on the required bandwidth and the bandwidth of each link, the configuration information comprising a first number of links that need to be in an open state among the multiple links, a first bandwidth of the first number of links being greater than or equal to the required bandwidth, and a difference between the first bandwidth and the required bandwidth being less than a difference threshold; and configuring the aggregated link according to the configuration information so that the number of links in an open state among the multiple links is a first number.

[0005] The method configures bandwidth by controlling the number of links in an open state, so that the bandwidth of the links in an open state is greater than or equal to the required bandwidth, meeting the demand for data transmission, and making the difference between the bandwidth of the links in an open state and the required bandwidth less than a difference threshold, avoiding waste of bandwidth resources due to an excessive number of links in an open state.

[0006] In one possible implementation, the multiple links are multiple physical media attach (PMA) links, one PMA link corresponds to at least one virtual link, and different virtual links are distinguished by alignment markers (AM) words. In this case, the configuration information also includes a target generation period of the AM word, a target mapping relationship between the multiple virtual links and the first number of PMA links, and a target operating frequency of the multiple virtual links. Among them, the target generation period is used to ensure that the second bandwidth including the AM word transmitted by the multiple virtual links is divisible by the first number, the target mapping relationship is used to ensure that the allocation of the multiple virtual links on the first number of PMA links meets the allocation conditions, and the target operating frequency is used to ensure that the second bandwidth matches the first bandwidth. As a result, the configuration information obtained is more comprehensive, so that the method can be applied to an aggregated link including multiple PMA links.

[0007] In a possible implementation, configuring the aggregated link according to the configuration information includes: controlling the operating status of multiple PMA links based on a first quantity so that the number of links in the multiple PMA links that are in an open state is the first quantity; when the target generation cycle is different from the current generation cycle of the AM word, adjusting the current generation cycle of the AM word to the target generation cycle; mapping multiple virtual links to the first number of PMA links according to the target mapping relationship; and when the target operating frequency is different from the current operating frequency of the multiple virtual links, adjusting the current operating frequency to the target operating frequency. Configuring according to the first quantity makes the unused links in the aggregated link in a closed state, achieving the energy-saving effect of the aggregated link, and configuring according to the target generation cycle, the target mapping relationship and the target operating frequency ensures the correct operation of the aggregated link.

[0008] In a possible implementation, the working clock used by multiple virtual links is the first clock, the first clock and the second clock are in a master-slave relationship with each other, and the time of the second clock indicates the target working frequency. In this case, the method of adjusting the current working frequency to the target working frequency may include switching the working clock used by multiple virtual links from the first clock to the second clock. By directly adjusting the working frequency by switching the standby clock, there is no need to modify the clock in use, and the working frequency can be adjusted quickly, reducing the impact on the business caused by adjusting the working frequency.

[0009] In a possible implementation, the multiple links correspond to the multiple physical ports, and the first number of links in the multiple links that need to be in an open state is the first number of physical ports in the multiple physical ports that need to be in an open state. In this case, the configuration information also includes a link aggregation algorithm, and the link aggregation algorithm is used to map data to the first number of physical ports for transmission. Thus, the configuration information obtained is more comprehensive, so that the method can be applied to an aggregated link including multiple physical ports.

[0010] In a possible implementation, the aggregated link is used to connect the first device and the second device, the time between the first device and the second device is synchronized, and the first device and the second device both configure the aggregated link according to the configuration information, ensuring that the first device and the second device connected to both ends of the aggregated link have the same bandwidth configuration for the aggregated link.

[0011] In a possible implementation, a third device is included between the first device and the second device, the aggregated link includes a first aggregated link and a second aggregated link, the first aggregated link includes multiple first links, the second aggregated link includes multiple second links, the first aggregated link connects the first device and the third device, and the second aggregated link connects the third device and the first device. In this case, the configuration information includes the second number of first links that need to be in an open state in the first aggregated link, the third number of second links that need to be in an open state in the second aggregated link, and the second bandwidth of the second number of first links and the third bandwidth of the third number of second links both match the required bandwidth. This enables the method to be applied to an aggregated link including a first aggregated link and a second aggregated link, thereby improving the wide applicability of the bandwidth configuration method.

[0012] In a possible implementation, obtaining the required bandwidth for transmitting data on the aggregated link includes: obtaining the required bandwidth for transmitting data on the aggregated link when any one of the multiple links is detected to have failed; obtaining configuration information based on the required bandwidth and the bandwidth of each link, including: obtaining configuration information based on the required bandwidth and the bandwidth of each link when the bandwidth of a link that has not failed among the multiple links is greater than the required bandwidth. This allows the bandwidth configuration method to be applied to link failure scenarios, and is used to ensure link energy saving and quickly restore service transmission on the failed link by configuring the bandwidth of other available links in the event of a link failure. In addition, when any one of the multiple links is detected to have failed, and the bandwidth of a link that has not failed among the multiple links is not greater than the required bandwidth, the method can also discard data of services that meet the discard requirements among the services transmitted by the multiple links. By discarding data of services that meet the discard requirements, the transmission of data of other services can be guaranteed.

[0013] In a possible implementation, the method for obtaining the required bandwidth for transmitting data on the aggregated link may include: connecting the aggregated link to multiple user-side interfaces; obtaining the required bandwidth for transmitting data on the aggregated link includes: detecting the interface utilization corresponding to the multiple user-side interfaces at the current time, or determining the interface utilization corresponding to the current time based on the traffic change cycle of the user-side interface, the traffic change cycle being obtained by statistically analyzing the traffic transmission conditions of multiple user-side interfaces in the historical time; and determining the required bandwidth based on the interface utilization. The required bandwidth may be obtained by real-time detection or by statistical traffic change cycles, making the method for obtaining the required bandwidth more flexible.

[0014] In a second aspect, a bandwidth configuration device is provided, the device comprising:

[0015] A first acquisition module is used to acquire a required bandwidth for transmitting data on an aggregated link, where the aggregated link includes multiple links;

[0016] A second acquisition module is used to acquire configuration information based on the required bandwidth and the bandwidth of each link, the configuration information including a first number of links that need to be in an open state among the multiple links, a first bandwidth of the first number of links is greater than or equal to the required bandwidth, and a difference between the first bandwidth and the required bandwidth is less than a difference threshold;

[0017] The configuration module is used to configure the aggregated link according to the configuration information so that the number of links in the open state among the multiple links is a first number.

[0018] In a possible implementation, the multiple links are multiple physical medium associated sublayer PMA links, one PMA link corresponds to at least one virtual link, and different virtual links are distinguished by alignment mark AM words; the configuration information also includes a target generation period of the AM word, a target mapping relationship between the multiple virtual links and the first number of PMA links, and a target operating frequency of the multiple virtual links; the target generation period is used to ensure that the second bandwidth including the AM word transmitted by the multiple virtual links is divisible by the first number, the target mapping relationship is used to ensure that the allocation of the multiple virtual links on the first number of PMA links meets the allocation conditions, and the target operating frequency is used to ensure that the second bandwidth matches the first bandwidth.

[0019] In a possible implementation, a configuration module is configured to control the operating status of multiple PMA links based on a first number so that the number of links in an open state among the multiple PMA links is the first number; when a target generation cycle is different from a current generation cycle of an AM word, adjust the current generation cycle of the AM word to the target generation cycle; map multiple virtual links to the first number of PMA links according to a target mapping relationship; and when a target operating frequency is different from the current operating frequencies of the multiple virtual links, adjust the current operating frequency to the target operating frequency.

[0020] In a possible implementation, the working clock used by multiple virtual links is a first clock, the first clock and the second clock are in a master-standby relationship with each other, and the time of the second clock indicates the target working frequency; a configuration module is used to switch the working clock used by multiple virtual links from the first clock to the second clock.

[0021] In a possible implementation, multiple links correspond to multiple physical ports, and a first number of links among the multiple links that need to be in an open state is a first number of physical ports among the multiple physical ports that need to be in an open state; the configuration information also includes a link aggregation algorithm, and the link aggregation algorithm is used to map data to the first number of physical ports for transmission.

[0022] In a possible implementation, the aggregate link is used to connect the first device and the second device, and the time between the first device and the second device is synchronized. The first device and the second device both configure the aggregate link according to the configuration information.

[0023] In a possible implementation, a third device is included between the first device and the second device, the aggregated link includes a first aggregated link and a second aggregated link, the first aggregated link includes multiple first links, the second aggregated link includes multiple second links, the first aggregated link connects the first device and the third device, and the second aggregated link connects the third device and the first device; the configuration information includes a second number of first links in the first aggregated link that need to be in an open state, a third number of second links in the second aggregated link that need to be in an open state, and the second bandwidth of the second number of first links and the third bandwidth of the third number of second links both match the required bandwidth.

[0024] In a possible implementation, the first acquisition module is used to acquire the required bandwidth for transmitting data on the aggregated link when any link among the multiple links fails; the second acquisition module is used to acquire configuration information based on the required bandwidth and the bandwidth of each link when the bandwidth of a link that has not failed among the multiple links is greater than the required bandwidth;

[0025] The device also includes a discarding module, which is used to discard data of services that meet the discarding requirements among the services transmitted by the multiple links when the bandwidth of the links that have not failed among the multiple links is not greater than the required bandwidth.

[0026] In one possible implementation, an aggregated link is connected to a plurality of user-side interfaces; a first acquisition module is used to detect interface utilization corresponding to the plurality of user-side interfaces at a current time, or to determine the interface utilization corresponding to the current time based on a traffic change cycle of the user-side interface, wherein the traffic change cycle is obtained by statistically analyzing the traffic transmission conditions of the plurality of user-side interfaces in a historical time; and the required bandwidth is determined based on the interface utilization.

[0027] In a third aspect, a network device is provided, comprising: a processor, the processor being coupled to a memory, the memory storing at least one program instruction or code, the at least one program instruction or code being loaded and executed by the processor so that the network device implements the bandwidth configuration method as described in any one of the first aspects above.

[0028] Optionally, the number of the processors is one or more, and the number of the memories is one or more.

[0029] Optionally, the memory may be integrated with the processor, or the memory may be provided separately from the processor.

[0030] In the specific implementation process, the memory can be a non-transitory memory, such as a read-only memory (ROM), which can be integrated with the processor on the same chip or can be set on different chips. This application does not limit the type of memory and the setting method of the memory and the processor.

[0031] In a fourth aspect, a communication device is provided, the device comprising: a transceiver, a memory, and a processor. The transceiver, the memory, and the processor communicate with each other through an internal connection path, the memory is used to store instructions, the processor is used to execute the instructions stored in the memory to control the transceiver to receive signals and control the transceiver to send signals, and when the processor executes the instructions stored in the memory, the communication device executes the method in the first aspect or any possible implementation of the first aspect.

[0032] In a fifth aspect, a computer-readable storage medium is provided, wherein the storage medium stores at least one instruction, and the instruction is loaded and executed by a processor to enable a computer to implement the method in the above-mentioned first aspect or any possible implementation of the first aspect.

[0033] In a sixth aspect, a computer program (product) is provided, wherein the computer program (product) comprises: a computer program code, and when the computer program code is executed by a computer, the computer executes the method in the above-mentioned first aspect or any possible implementation manner of the first aspect.

[0034] In a seventh aspect, a chip is provided, comprising a processor for calling and executing instructions stored in a memory from the memory, so that a communication device equipped with the chip executes a method in the above-mentioned first aspect or any possible implementation of the first aspect.

[0035] In an eighth aspect, another chip is provided, comprising: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected via an internal connection path, and the processor is used to execute the code in the memory. When the code is executed, the processor is used to execute the method in the above-mentioned first aspect or any possible implementation manner of the first aspect.

[0036] It should be understood that the beneficial effects achieved by the technical solutions of the second to eighth aspects of the present application and the corresponding possible implementation methods can be referred to the technical effects of the first aspect and its corresponding possible implementation methods mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of the structure of a communication network provided in an embodiment of the present application;

[0038] Figure 2 A schematic diagram of a system-side interface and a user-side interface provided in an embodiment of the present application;

[0039] Figure 3 A schematic diagram of an implementation environment of a bandwidth configuration method provided in an embodiment of the present application;

[0040] Figure 4 A flow chart of a bandwidth configuration method provided in an embodiment of the present application;

[0041] Figure 5 A schematic diagram of a module for logical link aggregation provided in an embodiment of the present application;

[0042] Figure 6 A schematic diagram of AM word insertion provided in an embodiment of the present application;

[0043] Figure 7 A schematic diagram of a link mapping method provided in an embodiment of the present application;

[0044] Figure 8 A schematic diagram of another link mapping method provided in an embodiment of the present application;

[0045] Fig. 9 A schematic diagram of a module for physical link aggregation provided in an embodiment of the present application;

[0046] Fig.10 A schematic diagram of a PMA2 and PMA4 intercommunication scenario provided in an embodiment of the present application;

[0047] Fig.11 A schematic diagram of another PMA2 and PMA4 intercommunication scenario provided in an embodiment of the present application;

[0048] Fig.12 A schematic diagram of traffic transmission provided in an embodiment of the present application;

[0049] Fig.13 A schematic diagram of a chip 1 and a chip 2 provided in an embodiment of the present application as a part of a photoelectric conversion module;

[0050] Fig.14 A schematic diagram of a chip 1 and a chip 2 provided in an embodiment of the present application as independent chips;

[0051] Fig.15 A schematic diagram of a photoelectric conversion module provided in an embodiment of the present application;

[0052] Fig.16 A schematic diagram of the structure of a bandwidth configuration device provided in an embodiment of the present application;

[0053] Fig.17 A schematic diagram of a network-level bandwidth configuration device provided in an embodiment of the present application;

[0054] Fig.18 A schematic diagram of the structure of a network device provided in an embodiment of the present application;

[0055] Fig.19 A schematic diagram of the structure of another network device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0056] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0057] The application of high-speed Ethernet interfaces enables the bandwidth to be expanded rapidly, but it also leads to a rapid increase in the energy consumption of communication networks. The increasing energy consumption of communication networks not only means huge electricity bills, but also means massive carbon emissions. Therefore, reducing the energy consumption of communication networks to reduce carbon emissions and achieve green energy saving in communication networks is an urgent problem to be solved. Among them, Ethernet interfaces with bandwidths of 25GE, 50GE, 100GE, 200GE, 400GE, etc. can be called high-speed Ethernet interfaces, and Ethernet interfaces with bandwidths of 10GE, 25GE, etc. can be called low-speed Ethernet interfaces. At present, there are scenarios where energy consumption of high-speed Ethernet interfaces is wasted, including but not limited to the following three.

[0058] Scenario 1: The user-side interface is idle. For example, see Figure 1 In the structural diagram of the communication network shown in the figure, the aggregation device and the customer edge (CE) device are connected through an access ring of a high-speed Ethernet interface of M*100GE / M*50GE, and the CE device and the indoor baseband processing unit (building base band unite, BBU) are connected through a low-speed Ethernet interface of N*10GE / N*25GE. Among them, M and N are positive integers, for example, N*10GE represents N links with a bandwidth of 10GE. According to the survey, the utilization rate of the user-side interface bandwidth N*10GE / N*25GE is only about 36.94%, so the user-side interface is idle, which leads to energy waste of the idle user-side interface.

[0059] For the CE device, the bandwidth of the system side interface and the bandwidth of the user side interface are physically matched. Therefore, when the user side interface is idle, it will also lead to energy waste inside the CE device. For example, see Figure 2 , the CE device includes chip 1 and chip 2. The interface between chip 1 and chip 2 is the system-side interface. The system-side interfaces are connected through an aggregated link formed by aggregating M links with a bandwidth of 50GE; the interface between chip 2 and multiple BBUs is the user-side interface. The user-side interfaces are connected through an aggregated link formed by aggregating N links with a bandwidth of 10GE. If the user-side interface has a bandwidth of N*10GE, then the system-side interface can have a bandwidth of M*50GE, where M*50GE is greater than or equal to N*10GE. Referring to the principle of the standard Ethernet interface, even if the user-side interface is idle, the system-side interface is still running in idle (IDLE) coding at the physical (PHY) layer, which leads to energy waste inside the CE device. Therefore, it is a feasible direction to reduce the power consumption of the aggregated link and the internal chip based on the actual bandwidth utilization of the user-side interface.

[0060] Scenario 2: Planning high bandwidth for future expansion. When operators plan to deploy high-speed Ethernet interfaces, in order to be able to expand bandwidth at low cost in the future, the bandwidth of the deployed high-speed Ethernet interfaces is much larger than the actual bandwidth demand, that is, the bandwidth of the aggregated link corresponding to the high-speed Ethernet interface is much larger than the actual bandwidth demand, resulting in some energy waste. Therefore, it is a feasible direction to reduce the power consumption of the aggregated link and chip on the system side of the device based on the actual bandwidth detection of the high-speed Ethernet interface.

[0061] Scenario 3: Periodic differences in user traffic. Periodic differences in user traffic include, but are not limited to, day-night differences, seasonal differences, and holiday differences. Taking the day-night difference as an example, user traffic is usually larger during the day and smaller at night. Therefore, using the same interface bandwidth during the day and night will result in energy waste when user traffic is smaller. Therefore, reducing the power consumption of aggregated links and internal chips based on the periodic differences in user traffic is a feasible direction.

[0062] In the related technology, intelligent adjustments are made based on traffic load to match the energy consumption of the device with the traffic load. For example, when a decrease in traffic is detected, the traffic processing capacity of the device is lowered, and the rate of the high-speed Ethernet interface of the device is reduced; when an increase in traffic is predicted, the traffic processing capacity of the device is increased, and the rate of the high-speed Ethernet interface of the device is increased to match the rate of the high-speed Ethernet interface with the actual bandwidth. However, the method of lowering or raising the rate of the high-speed Ethernet interface of the device based on the traffic load is likely to result in a longer time for re-establishing the link, which in turn leads to more packet loss, which has a greater impact on the business.

[0063] The embodiment of the present application provides a bandwidth configuration method, which configures the bandwidth of an aggregated link by controlling the closed or open state of the link, and can quickly increase or decrease the bandwidth of a device to achieve energy saving of the device. Figure 3 , Figure 3 A schematic diagram of an implementation environment of a bandwidth configuration method provided in an embodiment of the present application. Figure 3 As shown, the implementation environment includes a first device and a second device, and the first device and the second device are connected via an aggregated link including multiple links. For example, the multiple links included in the aggregated link are represented by N*G1, G1 represents the bandwidth of each link, and N represents the number of multiple links. The embodiment of the present application does not limit the first device and the second device connected by the aggregated link, and can be any device, terminal or server that supports the aggregated link. Optionally, the first device can be a network device 1, and the second device can be a network device 2, for example, the network device 1 is a CE device, and the network device 2 is a BBU; or, the first device is a chip 1, and the second device is a chip 2, for example, Figure 2Chip 1 and chip 2 are shown in the CE device.

[0064] See also Figure 4 , Figure 4 A flow chart of a bandwidth configuration method provided in an embodiment of the present application, which can be applied to Figure 3 In the implementation environment shown, for example, Figure 3 The first device or the second device shown in the figure is executed, or the control device connected to the first device or the second device is executed, and the control device can be a network device or a server. Figure 4 As shown, the data transmission method includes but is not limited to the following steps 401 to 403.

[0065] Step 401: Obtain the required bandwidth of an aggregated link for transmitting data, where the aggregated link includes multiple links.

[0066] The aggregated link in the embodiment of the present application includes multiple links (lanes), and high bandwidth is achieved by the aggregation of multiple links. The embodiment of the present application does not limit the method of obtaining the required bandwidth for transmitting data through the aggregated link. For example, the aggregated link is subjected to bandwidth detection, and the required bandwidth is determined according to the bandwidth detection result. The bandwidth detection result includes information such as the traffic load and bandwidth utilization of the aggregated link. Alternatively, statistics are collected on the services that need to be transmitted, and the required bandwidth is determined according to the service requirements.

[0067] In one possible implementation, an aggregated link is connected to multiple user-side interfaces; a method for obtaining the required bandwidth for transmitting data on the aggregated link may include detecting the interface utilization corresponding to the multiple user-side interfaces at the current time, or determining the interface utilization corresponding to the current time based on the traffic change cycle of the user-side interface, the traffic change cycle being obtained by statistically analyzing the traffic transmission conditions of multiple user-side interfaces in the historical time; and determining the required bandwidth based on the interface utilization. The required bandwidth may be obtained by real-time detection, or by statistically analyzing the traffic change cycle, making the method of obtaining the required bandwidth more flexible. Among them, the interface utilization refers to the ratio of the number of interfaces used in the multiple user-side interfaces connected to the aggregated link to the total number of the multiple user-side interfaces.

[0068] For example, the aggregated link is Figure 2 Taking the M*50GE shown as an example, the aggregated link is connected to multiple BBUs through chip 2, and chip 2 and multiple BBUs are connected through N*10GE. One 10GE link corresponds to one user-side interface. The interface utilization corresponding to the N user-side interfaces at the current time is detected. When the interface utilization is 36.94%, the required bandwidth is N*10GE*36.94%.

[0069] In a possible implementation, before obtaining the required bandwidth for transmitting data on the aggregated link, the link status of the aggregated link is also detected. Optionally, the method for obtaining the required bandwidth for transmitting data on the aggregated link may include obtaining the required bandwidth for transmitting data on the aggregated link when any link failure among multiple links is detected. Link failure means that the link cannot transmit data normally, for example, a link failure, a failure of a node directly connected to the link, or a link exceeding the effective duration, etc., can all lead to link failure. As a result, the method can be applied to the scenario of link failure, and the execution of the method is triggered by the link failure as a condition, and the service on the failed link can be restored in time by bandwidth configuration.

[0070] Step 402: acquiring configuration information based on the required bandwidth and the bandwidth of each link, wherein the configuration information includes a first number of links that need to be in an open state among the multiple links, a first bandwidth of the first number of links being greater than or equal to the required bandwidth, and a difference between the first bandwidth and the required bandwidth being less than a difference threshold.

[0071] The difference threshold can be set based on experience or flexibly adjusted according to the application scenario. After obtaining the required bandwidth, the links in the open state required to meet the required bandwidth can be calculated based on the principle that the bandwidth of the links in the open state is greater than but not much greater than the required bandwidth. Thus, energy saving can be achieved by closing the links that do not need to be in the open state. Optionally, the bandwidth of each link in the multiple links can be the same or different. When the bandwidth of each link is different, the configuration information also includes the bandwidth of the link that needs to be in the open state.

[0072] In a possible implementation, the bandwidths of the links are the same as the unit bandwidth, and a quotient of the required bandwidth and the unit bandwidth rounded up is obtained, and the quotient is determined as the first quantity. Figure 2 Taking the M*50GE shown in the figure, where the bandwidth of each link is the same as an example, assuming that M=4, N=10, if the required bandwidth is N*10GE*36.94%≈4*10GE, the quotient of (4*10GE) / 50GE rounded up is 1, then the first number is 1. That is, the number of links that need to be in the open state for the aggregated link is 1, and when the number of links in the open state for the aggregate is greater than 1, the links in the open state other than 1 can be closed to achieve link energy saving.

[0073] The embodiments of the present application do not limit the link aggregation method of the aggregated links, including but not limited to logical link aggregation and physical link aggregation. Logical link aggregation means that each link corresponds to an independent Ethernet interface, and multiple Ethernet interfaces are logically aggregated; physical link aggregation means that each link corresponds to an independent physical link, and multiple physical links are physically aggregated. For different link aggregation methods, on the basis of configuring the number of links in the open state, it is also necessary to configure the relevant information required to implement the aggregated link to ensure the normal operation of the aggregated link.

[0074] In logical link aggregation, each link corresponds to an independent Ethernet interface. For example, multiple links are multiple PMD links, and one PMA link corresponds to at least one virtual link. Different virtual links are distinguished by AM words. For example, see Figure 5 The module schematic diagram of the first device or the second device of the logical link aggregation shown, taking the virtual link as FEC lane as an example, the first device or the second device includes a medium access control (MAC) layer, a physical coding sublayer (PCS), an FEC lane and a PMA lane mapping configuration, and a PMA lane. Among them, the PCS may include forward error correction (FEC) coding or may not include FEC coding. When the PCS does not include FEC coding, the virtual link of the embodiment of the present application refers to the PCS lane. When the PCS includes FEC coding, the virtual link of the embodiment of the present application refers to the FEC lane.

[0075] In a possible implementation, when the aggregated link is a logical link aggregation, the configuration information also includes a target generation period of the AM word, a target mapping relationship between multiple virtual links and a first number of PMA links, and a target operating frequency of the multiple virtual links. The target generation period is used to ensure that the second bandwidth including the AM word transmitted by the multiple virtual links is divisible by the first number. If the second bandwidth is divisible by the first number, the data including the AM word transmitted by the multiple virtual links can be evenly mapped to the first number of PMA links, so that after the receiving side receives the data including the AM word through the first number of PMA links, the AM word in the identification data can be reversely mapped to the multiple virtual links, so that the multiple virtual links on the receiving side are synchronized and aligned with the multiple virtual links on the sending side, that is, the first virtual link on the receiving side transmits the data transmitted by the first virtual link on the sending side, thereby achieving single lane synchronization and multi-lane alignment; but if it cannot be divided evenly, it will cause the receiving side to be unable to perform single lane synchronization and multi-lane alignment according to the AM word.

[0076] The target mapping relationship is used to ensure that the allocation of multiple virtual links on the first number of PMA links meets the allocation conditions. Among them, satisfying the allocation conditions may mean that the allocation is reasonable, and the reasonable allocation may mean that after the data transmitted by multiple virtual links are allocated to the first number of PMA links, the difference in the amount of data transmitted between the first number of PMA links is less than the difference threshold, and the difference threshold can be flexibly adjusted according to the application scenario. For example, referring to the target mapping relationship shown in Table 2, when the first number is 4, 20 virtual links are evenly distributed to 4 PMA links, that is, every 5 virtual links are mapped to one PMA link; or, referring to the target mapping relationship shown in Table 3, when the first number is 3, 5 virtual links out of the 20 virtual links are closed, and every 5 virtual links out of the remaining 15 virtual links are mapped to one PMA link. The target operating frequency is used to ensure that the second bandwidth matches the first bandwidth. As a result, the configuration information obtained is more comprehensive, so that the method can be applied to an aggregated link including multiple PMA links.

[0077] Exemplarily, the following takes aggregated links with bandwidths of 100GE and 200GE as examples, respectively, and illustrates that when the aggregated link is a logical link aggregation, the configuration information also includes a target generation period of AM words, a target mapping relationship between multiple virtual links and a first number of PMA links, and a target operating frequency of multiple virtual links.

[0078] First, an aggregated link with a bandwidth of 100GE is used as an example. Referring to the AM word periodic table under 100GE shown in Table 1, the number of virtual links is 20 and the number of PMA lanes is 4. In the standard, the current generation period of the AM word is 16383 code blocks, such as Figure 6 As shown in (a), taking the virtual link as PCS lane as an example, there are 16383 code blocks between every two AM words. As shown in Table 1, after FEC encoding, the bandwidth value is 22282240, and 22282240 cannot be divided by 30. Therefore, if the number of PMA lanes opened is adjusted to 3 according to the generation cycle of the AM word in the standard, the receiving side will not be able to identify, align and synchronize the virtual link according to the AM word. Among them, considering that data is distributed in units of 10 bits after FEC encoding, 10 times the number of PMA lanes opened is used as the divisor when calculating whether it is divisible.

[0079] In the embodiment of the present application, the target generation period of the AM word is 16392 code blocks, such as Figure 6 As shown in (b), 16392 code blocks are included between every two AM words. As shown in Table 1, after FEC encoding, the bandwidth value is 22293120, and 22293120 can be divided by 40, 30 or 20. Therefore, if the target generation cycle of the AM word in the embodiment of the present application is adjusted, no matter the number of PMA lanes opened is adjusted to 4, 3 or 2, it can be ensured that the receiving side can identify, align and synchronize the virtual link according to the AM word. Considering that the bandwidth value after adjusting the generation cycle of the AM word is larger than the bandwidth value in the standard, the bandwidth can be adjusted by adding or deleting IDLE codes or control codes to match the bandwidth after adjusting the generation cycle of the AM word.

[0080] Table 1

[0081]

[0082]

[0083] Exemplarily, still taking the number of virtual links as 20 and the number of PMA lanes as 4 as an example, one AM word corresponds to one virtual link, then multiple virtual links can be represented by am0-am19, and each AM word recognized by the receiving side represents a virtual link. In an embodiment of the present application, the mapping relationship between the FEC lane and the PMA lane under 100GE can be as shown in Table 2 or Table 3, and the corresponding target mapping relationship is selected by configuring the number of PMA lanes in the open state. In Table 2, when the first number of PMA lanes is 4, the target mapping relationship can be PMA lane0: am0, am4, am8, am12, am16; PMA lane1: am1, am5, am9, am13, am17; PMA lane2: am2, am6, am10, am14, am18; PMA lane3: am3, am7, am11, am15, am19, thereby, the number of FEC lanes and the number of PMA lanes are just evenly divided, and the receiving side can process single lane synchronization and multi-lane alignment according to the standard.

[0084] When the first number of PMA lanes is 3, the target mapping relationship may be PMA lane0: am0, am3, am6, am9, am12, am15, am18; PMA lane1: am1, am4, am7, am10, am13, am16, am19; PMA lane2: am2, am5, am8, am11, am14, am17, XXX. Since the number of FEC lanes and the number of PMA lanes are not evenly divided, the single lane synchronization on the receiving side is different from the standard. In this case, the receiving side can use PMA lane0 to identify am0, am3, am6, am9, am12, am15, and am18 as a group for independent lane synchronization, PMA lane1 to identify am1, am4, am7, am10, am13, am16, and am19 as two groups for independent lane synchronization, and PMA lane2 to identify am2, am5, am8, am11, am14, and am17 as three groups for independent lane synchronization; or, each PMA lane only identifies the first 6 AM words for independent lane synchronization, for example, PMAlane0 identifies am0, am3, am6, am9, am12, and am15 as a group for independent lane synchronization.

[0085] For the target mapping relationship when the first number of PMA lanes is 2 or 1, please refer to Table 2, which will not be described here one by one. In the mapping relationship shown in Table 2, since the number of FEC lanes is still 20 and has not decreased, based on the first number of PMA lanes in the open state, the MAC side can adjust the bandwidth of the virtual ports corresponding to the 20 virtual links in proportion to the first number, so that the MAC side bandwidth matches the first bandwidth of the first number of PMA lanes, and the unused bandwidth can be replaced by the IDLE code and the control code. For the inlet and outlet of the FEC, based on the first number of PMA lanes in the open state and the AM word, the data stream of the used virtual link is selected to flow into or out of the FEC, and the FEC reduces the operating frequency based on the first number of PMA lanes in the open state to match the first bandwidth of the first number of PMA lanes.

[0086] Table 2

[0087]

[0088] In Table 3, the target mapping relationship when the first number of PMA lanes is 4 is the same as Table 2, and will not be repeated here. When the first number of PMA lanes is 3, the target mapping relationship can be PMA lane0: am0, am4, am8, am12, am16; PMA lane1: am1, am5, am9, am13, am17; PMA lane2: am2, am6, am10, am14, am18. When the first number of PMA lanes is 2, the target mapping relationship can be PMA lane0: am0, am4, am8, am12, am16; PMA lane1: am1, am5, am9, am13, am17. It can be seen that when the number of PMA lanes is small, the number of FEC lanes also decreases. That is, in the mapping relationship shown in Table 4, the number of virtual links opened is determined based on the number of PMA lanes opened. For example, when the first number of PMA lanes is 3, the virtual links corresponding to am3, am7, am11, am15, and am19 are closed. Therefore, in the mapping relationship shown in Table 4, different AM word transcodings are corresponding to different AM word transcodings. For example, when the first number of PMA lanes is 3, the AM word transcoding is 3 bits.

[0089] Table 3

[0090]

[0091] For logical link aggregation scenarios, see the link mapping method. Figure 7 The schematic diagram shown. There are 20 virtual ports on the MAC side, and the 20 virtual ports correspond to 20 AM words one by one. Each AM word represents 1 virtual port. The number of FEC lanes after bandwidth configuration is consistent with the first number of PAM lanes in the open state. The number of virtual ports used after bandwidth configuration corresponds to the number of AM words on the FEC lane after bandwidth configuration. Refer to Table 3. For the sending side, based on the first number of PAM lanes in the open state, the MAC side distributes actual traffic according to the virtual ports used after bandwidth configuration. For example, when the first number of PAM lanes in the open state is 1, the virtual ports used after bandwidth configuration include virtual ports corresponding to am0, am4, am8, am12, and am16. Then, the MAC side distributes actual traffic according to the virtual ports corresponding to am0, am4, am8, am12, and am16. Among them, the used virtual ports will be replaced by available data codes in PCS, and the unused virtual ports will be replaced by IDLE codes or control codes in PCS.

[0092] In an embodiment of the present application, the generation cycle of the AM word is flexibly configurable. For example, the generation cycle of the AM word is 16392 code blocks as shown in Table 1, so that the data after the AM word is inserted in each AM cycle can be divided by the first number after FEC encoding, which is convenient for the receiving side to perform AM word recognition, single lane synchronization and multi-lane alignment based on the AM word of each FEC lane. According to the order of AM word distribution under the 100G FEClane standard, the 20 virtual ports are arranged in the order of AM word distribution to form 4 different data streams. For example, stream0: am0, am4, am8, am12, am16; stream1: am1, am5, am9, am13, am17; stream2: am2, am6, am10, am14, am18; stream3: am3, am7, am11, am15, am19. For the inlet and outlet of FEC, as shown in Table 3, based on the first number of PAM lanes in the open state and the PCS AM word identifier, select the data stream in / out FEC of the virtual port to be used. For example, 1lane selects stream0; 2lane selects stream0 and stream1; 3lane selects stream0, stream1, and stream2; 4lane selects stream0, stream1, stream2, and stream3. At the same time, FEC reduces the operating frequency based on the first number of PAM lanes in the open state to match the first bandwidth of the first number of PMA lanes. Then, select the corresponding FEC lane to distribute the data mapping to the first number of PMAlanes. Figure 7 As shown in the figure, for the receiving side, the mapping relationship between the FEC lane and the PMA lane on the receiving side is consistent with the mapping relationship between the FEClane and the PMA lane on the transmitting side. The receiving side deletes the AM word in the PCS through single lane synchronization, multi-lane alignment, skew elimination, and FEC decoding.

[0093] Secondly, take the aggregated link with a bandwidth of 200GE as an example. Referring to the AM word periodic table under 200GE shown in Table 4, in the standard, the current generation period of the AM word is 81920 code blocks, and the bandwidth value after FEC encoding is 22282240, which cannot be divided by 30, 50, 60, and 70. Therefore, if the number of PMAlanes opened is adjusted to 3, 5, 6, and 7 according to the generation period of the AM word in the standard, the receiving side will not be able to identify, align, and synchronize the virtual link according to the AM word. In the embodiment of the present application, the target generation period of the AM word is 82950 code blocks, and the bandwidth value after FEC encoding is 22562400. 22562400 can be divided by 80, 70, 60, 50, 40, 30, 20 and 20. Therefore, if the target generation period of the AM word in the embodiment of the present application is adjusted, no matter how many PMA lanes are opened, it can be ensured that the receiving side can identify, align and synchronize the virtual link according to the AM word.

[0094] Table 4

[0095]

[0096] For logical link aggregation scenarios, see the link mapping method. Figure 8 Schematic diagram shown. There are 8 virtual ports on the MAC side, and each virtual port on the MAC side corresponds to 8 virtual link FEC lanes one by one, and one AM word represents 1 FEC lane. Based on the first number of PAM lanes in the open state, refer to Table 5, and the MAC side distributes the actual traffic according to the virtual ports corresponding to the FEC lane AM words after bandwidth configuration. Among them, the used virtual ports will be replaced by available data codes, etc. in the PCS, and the unused virtual ports will be replaced by IDLE codes or control codes, etc. in the PCS. For the sending side, the generation cycle of the AM word is flexibly configurable. For example, the generation cycle of the AM word is 82950 code blocks as shown in Table 4, so that the data after the AM word is inserted in each AM cycle can be divided by the first number after FEC encoding, which is convenient for the receiving side to perform AM word recognition, single lane synchronization and multi-lane alignment based on the AM word of each FEC lane.

[0097] Table 5

[0098]

[0099] like Figure 8As shown, the data streams of the 8 FEC lanes corresponding to the 8 virtual ports are respectively allocated to FEC A or FEC B in a 1:1 ratio before FEC encoding; each FEC A or FEC B supports a maximum of 4 or 8 FEC lanes. As shown in Table 5, PMAlane0-3 is mapped to FEC-A; PMA lane4-7 is mapped to FEC-B. For the inlet and outlet of FEC, based on the first number of PAM lanes in the open state and the PCS AM word identifier, the data stream of the virtual port to be used is selected to flow in or out of FEC. Among them, the mapping relationship between FEC lanes and PMA lanes includes two situations: supporting interleaving between lanes and not supporting interleaving between lanes.

[0100] In case 1, the mapping relationship between the FEC lane and the PMA lane does not support interleaving between lanes.

[0101] In this case, the embodiment of the present application provides the following two target mapping relationships based on different PMA lanes. The first one is to keep the mapping relationship between FEC lane and FEC-A unchanged, and then reduce one FEC lane in the mapping relationship between FEC lane and FEC-B for each decrease in the number of PMA lanes that need to be in the open state, until the number of FEC lanes in the mapping relationship between FEC lane and FEC-B is 0, and then reduce one FEC lane in the mapping relationship between FEC lane and FEC-A for each decrease in the number of PMA lanes that need to be in the open state.

[0102] Exemplarily, when the first number of PAM lanes in the open state is 8, PMA 8lane: FEC0-3lane is mapped to FEC-A, and FEC 4-7lane is mapped to FEC-B. When the first number of PAM lanes in the open state is 7, PMA 7lane: FEC 0-3lane is mapped to FEC-A; FEC 4-6lane is mapped to FEC-B, and FEC-B is down-converted to match the first bandwidth of the first number of PAM lanes. Down-converting refers to adjusting the current operating frequency to the target operating frequency. When the first number of PAM lanes in the open state is 6, PMA 6lane: FEC 0-3lane is mapped to FEC-A; FEC 4-5lane is mapped to FEC-B, and FEC-B is down-converted. When the first number of PAM lanes in the open state is 5, PMA 5lane: FEC 0-3lane is mapped to FEC-A; FEC 4lane is mapped to FEC-B, and FEC-B is down-clocked. When the first number of PAM lanes in the open state is 4, PMA 4lane: FEC 0-3lane is mapped to FEC-A; FEC-B is closed. When the first number of PAM lanes in the open state is 3, PMA 3lane: FEC 0-2lane is mapped to FEC-A; FEC-B is closed. And so on, no more examples are given.

[0103] Second, as the number of PMA lanes that need to be in the open state decreases by one, one FEC lane is cyclically reduced in the mapping relationship between the FEC lane and FEC-A or the mapping relationship between the FEC lane and FEC-B.

[0104] Exemplarily, when the first number of PAM lanes in the open state is 7, PMA 7lane: FEC0-3lane is mapped to FEC-A; FEC 4-6lane is mapped to FEC-B, and FEC-B is down-clocked. When the first number of PAM lanes in the open state is 6, PMA 6lane: FEC 0-2lane is mapped to FEC-A; FEC 4-6lane is mapped to FEC-B, and FEC-A / B is down-clocked. When the first number of PAM lanes in the open state is 5, PMA5lane: FEC 0-2lane is mapped to FEC-A; FEC 4-5lane is mapped to FEC-B, and FEC-A / B is down-clocked. When the first number of PAM lanes in the open state is 4, PMA 4lane: FEC 0-1lane is mapped to FEC-A; FEC 4-5lane is mapped to FEC-B, and FEC-B is down-clocked. When the first number of PAM lanes in the open state is 3, PMA 3lane: FEC 0-1lane is mapped to FEC-A; FEC 4lane is mapped to FEC-B, and FEC-B is down-clocked. When the first number of PAM lanes in the open state is 2, PMA 2lane: FEC 0lane is mapped to FEC-A; FEC4lane is mapped to FEC-B, and FEC-B is down-clocked. When the first number of PAM lanes in the open state is 1, PMA 1lane: FEC 0lane is mapped to FEC-A; FEC-B is closed, and FEC-A is down-clocked.

[0105] In case 2, the mapping relationship between the FEC lane and the PMA lane supports interleaving between lanes.

[0106] In this second situation, an embodiment of the present application provides a target mapping relationship based on different PMA lanes as shown in Table 6. Table 6 takes PMA 8lane-PMA 5lane as an example to illustrate that when the first number of PAM lanes in the open state is 8, PMA 8lane: FEC 0-7lane is mapped together to FEC-A / FEC-B, and FEC-A / FEC-B is down-clocked. When the first number of PAM lanes in the open state is 7, FEC 0-6lane is mapped together to FEC-A / FEC-B, and FEC-A / FEC-B is down-clocked. When the first number of PAM lanes in the open state is 6, FEC 0-5lane is mapped together to FEC-A / FEC-B, and FEC-A / FEC-B is down-clocked. When the first number of PAM lanes in the open state is 5, FEC 0-4 lanes are mapped to FEC-A / FEC-B together, and FEC-A / FEC-B is down-clocked, and so on. PMA4lane-PMA 1lane is similar to PMA 8lane-PMA 5lane, and will not be repeated here.

[0107] Among them, the processing methods of PRBS9 padding bits and single frames (SF) in the FEC frame header include but are not limited to the following two. Processing method 1, the AM frame header is the same as the AM frame header when all 8 lanes are open, and the total size remains unchanged, so that the AM word containing padding and the used lane is a multiple of 257. Due to the reduction of lanes, other positions are filled with pseudo random binary sequence (pseudo random binary sequence, PRBS) 9 encoding. Exemplarily, 8lane: 4*257=1028bit, can be decomposed into AM word: 8*120=960bit, padding (PAD): PRBS9 65bit, status_field (Status_field): 3bit. 1lane:: 4*257=1028bit, can be decomposed into AM word: 1*120=120bit, the other 7*120bit is filled with PAD, PAD: PRBS9 65bit, Status_field: 3bit.

[0108] Processing method 2: The AM frame header changes based on the number of lanes opened, so that the AM word containing padding and used lanes is a multiple of 257. Due to the reduction of lanes, other positions are filled using PRBS9 encoding. For example, 1lane: 1*257=257bit, which can be decomposed into AM word: 1*120=120bit, PAD: PRBS9 134bit, Status_field: 3bit. 7lane: 7*257=4*1799bit, which can be decomposed into AM word: 7*120=840bit, PAD: PRBS9158bit, Status_field: 3bit.

[0109] Table 6

[0110]

[0111]

[0112] Continue as Figure 8 As shown, based on the first number of PAM lanes in the open state, one by one is selected starting from FEC-A or FEC-Blane0, and the corresponding FEC lane is selected to distribute the data mapping to the first number of PMA lanes. For the receiving side, the mapping relationship between the FEC lane and the PMA lane on the receiving side is consistent with the mapping relationship between the FEC lane and the PMA lane on the transmitting side. The receiving side deletes the AM word in the PCS through single lane synchronization, multi-lane alignment, skew elimination, and FEC decoding.

[0113] The following describes configuration information of aggregated links in a physical link aggregation scenario. In physical link aggregation, a link corresponds to an independent physical link, for example, multiple links correspond to multiple physical ports, and the first number of links in the multiple links that need to be in an open state is the first number of physical ports in the multiple physical ports that need to be in an open state.

[0114] Take multiple links corresponding to two physical ports as an example, see Fig. 9 In the module schematic diagram of physical link aggregation shown in the figure, the first device or the second device includes link aggregation algorithm port mapping, link aggregation member management, port 1MAC, port 1PHY, port 2MAC and port 2PHY. Exemplarily, based on the first number of physical ports in an open state, the link aggregation members include the first number of physical ports, and the link aggregation algorithm is adjusted to map on the physical ports in an open state so that the bandwidth of the first number of physical ports matches the required bandwidth, that is, the bandwidth of the first number of physical ports is greater than the required bandwidth and the difference with the required bandwidth is less than the difference threshold.

[0115] In a possible implementation, when the aggregated link is a physical link aggregation, the configuration information further includes a link aggregation algorithm, and the link aggregation algorithm is used to map data to the first number of physical ports for transmission. Thus, the acquired configuration information is more comprehensive, so that the method can be applied to an aggregated link including multiple physical ports.

[0116] The above is an example of how to obtain configuration information for logical link aggregation scenarios and physical link aggregation scenarios. In an embodiment of the present application, the status of multiple links will also be detected, and then when any link among the multiple links is detected to be failed, the method of obtaining configuration information based on the required bandwidth and the bandwidth of each link may include, when the bandwidth of a non-failed link among the multiple links is greater than the required bandwidth, obtaining configuration information based on the required bandwidth and the bandwidth of each link. This allows the bandwidth configuration method to be applied to link failure scenarios, and is used to ensure link energy saving and quickly restore service transmission of failed links by configuring the bandwidth of other available links in the event of link failure.

[0117] In addition, when it is detected that any one of the multiple links fails, and the bandwidth of the links that have not failed in the multiple links is not greater than the required bandwidth, the method can also discard the data of the services that meet the discard requirements among the services transmitted by the multiple links to reduce the required bandwidth. By discarding the data of the services that meet the discard requirements, the transmission of data of other services can be guaranteed. Among them, the discard requirement can be flexibly set according to the application scenario. For example, the discard requirement can be a low service priority or a low service importance. Taking the case that the discard requirement can be a low service priority, different services include corresponding priorities, and the data transmitted by any service carries the priority identifier of the any service. Therefore, by identifying the priority identifier in the data transmitted by the aggregated link, the priority of each service transmitted by the aggregated link can be determined, and then the data of the service with the lowest priority among the various services transmitted by the aggregated link is discarded.

[0118] Step 403: configure the aggregated link according to the configuration information so that the number of links in the open state among the multiple links is a first number.

[0119] After obtaining the configuration information, the configuration information has not yet taken effect. Therefore, the aggregated link needs to be configured according to the configuration information to make the configuration information effective. Optionally, when the first open number of links in the multiple links that are in an open state is greater than the first number, the first difference number of links in the links that are in an open state are closed, and the first difference number is the difference between the first open number and the first number; when the second open number of links in the multiple links that are in an open state is less than the first number, the second difference number of links in the links that are in a closed state are opened, and the second difference number is the difference between the first number and the second open number. Before opening or closing a link, you need to configure the link to support the ability to open or close individually.

[0120] In an embodiment of the present application, an aggregated link is used to connect a first device and a second device, and the time between the first device and the second device is synchronized, and the first device and the second device both configure the aggregated link according to the configuration information. That is, it is necessary to negotiate unified configuration information between the first device and the second device, and enable time synchronization between the first device and the second device to ensure that the bandwidth configuration of the aggregated link by the first device and the second device connected at both ends of the aggregated link is the same. The embodiment of the present application does not limit the method for time synchronization. For example, the precision time protocol (PTP) can be used for time synchronization. Exemplarily, on the basis of the time synchronization between the first device and the second device, the configuration information of the first device and the second device is enabled at the same time by switching the control switch, so that the links in the open state between the first device and the second device are all the first number. Among them, the switching control switch can be a physical signal or a command configuration, which is not limited in the embodiment of the present application.

[0121] In a possible implementation, in a logical link aggregation scenario, the aggregated link is configured according to the configuration information, including: controlling the operating status of multiple PMA links based on a first quantity so that the number of links in the multiple PMA links that are in an open state is the first quantity; when the target generation cycle is different from the current generation cycle of the AM word, adjusting the current generation cycle of the AM word to the target generation cycle; when the target generation cycle is the same as the current generation cycle of the AM word, there is no need to adjust the current generation cycle of the AM word; mapping multiple virtual links to the first number of PMA links according to a target mapping relationship; when the target operating frequency is different from the current operating frequency of the multiple virtual links, adjusting the current operating frequency to the target operating frequency; when the target operating frequency is the same as the current operating frequency of the multiple virtual links, there is no need to adjust the current operating frequency. Configuring according to the first quantity makes the unused links in the aggregated link in a closed state, achieving the energy-saving effect of the aggregated link, and configuring according to the target generation cycle, the target mapping relationship and the target operating frequency ensures the correct operation of the aggregated link.

[0122] In an embodiment of the present application, the working clock used by multiple virtual links is the first clock, the first clock and the second clock are in a master-slave relationship with each other, and the time of the second clock indicates the target working frequency. In this case, the method of adjusting the current working frequency to the target working frequency may include switching the working clock used by multiple virtual links from the first clock to the second clock. By directly adjusting the working frequency by switching the backup clock, there is no need to modify the clock in use, and the working frequency can be adjusted quickly, reducing the impact on the business caused by adjusting the working frequency. For example, Figure 5 As shown, the first device or the second device also includes a bandwidth detection module, a configuration module and clock synchronization. The bandwidth detection module is used to perform bandwidth detection on the aggregated link to obtain the required bandwidth. The configuration module is used to obtain configuration information and configure clock synchronization, the AM word of PCS, the mapping relationship between FEC lane and PMA lane, and the number of PMA lanes according to the configuration information. The clock synchronization is used to configure time synchronization between different devices.

[0123] In a possible implementation, in a logical link aggregation scenario, configuring the aggregated link according to the configuration information includes: controlling the operating status of multiple PMA links based on a first number so that the number of links in the multiple PMA links that are in an open state is the first number; and adjusting the link aggregation algorithm to map between the links in an open state. For example, Fig. 9As shown, the first device or the second device also includes a bandwidth detection module and a configuration module. The bandwidth detection module is used to perform bandwidth detection on the aggregated link to obtain the required bandwidth. The configuration module is used to obtain configuration information and configure the link aggregation algorithm port mapping and link aggregation members according to the configuration information.

[0124] In an embodiment of the present application, a third device is included between the first device and the second device, the aggregated link includes a first aggregated link and a second aggregated link, the first aggregated link includes multiple first links, the second aggregated link includes multiple second links, the first aggregated link connects the first device and the third device, and the second aggregated link connects the third device and the first device. In this case, the configuration information includes the second number of first links that need to be in an open state in the first aggregated link, the third number of second links that need to be in an open state in the second aggregated link, and the second bandwidth of the second number of first links and the third bandwidth of the third number of second links both match the required bandwidth. This enables the method to be applied to an aggregated link including a first aggregated link and a second aggregated link, thereby improving the wide applicability of the bandwidth configuration method. Among them, the third device is used to enable the first device and the second device to communicate with each other, and optionally, the third device is a coding conversion module or an optoelectronic conversion module.

[0125] Take the first device and the second device as chip 1 and chip 2 that communicate with each other as an example. Considering that the PMA encoding methods between chip 1 and chip 2 may be different, the PMA encoding methods include PMA2 and PMA4, so there are multiple PMA2 and PMA4 intercommunication scenarios. Fig.10 and Fig.11 , Fig.10 Three intercommunication scenarios between chip 1 and chip 2 through electrical interconnection are shown. Fig.11 2 scenarios of intercommunication between chip 1 and chip 2 through optical interconnection are shown. For example, the first device is chip 1, the second device is chip 2, and the third device can be Fig.10 (a) shows the chip 3, Fig.10 (b) and Fig.10 (c) Chip 3 and Chip 4 shown, Fig.11 (a) the photoelectric conversion module shown; or the first device is Fig.11 (b) shows a chip 1, the second device is Fig.11 (b) shows a chip 3, the third device can be Fig.10 (b) The photoelectric conversion module shown.

[0126] against Fig.10In the scenario shown in (a), chip 1 supports PAM2 encoding, chip 2 supports PAM4 encoding, and chip 1 and chip 2 realize electrical link interconnection through a chip 3 that converts PAM2 and PAM4. Among them, chip 3 is used to realize the conversion of any two PAM2 lanes between chip 1 and chip 3 and any one PAM4 lane between chip 3 and chip 2, for example, chip 3 is a coding conversion module. Therefore, the number of PAM2 lanes between chip 1 and chip 3 is twice the number of PAM4 lanes between chip 3 and chip 2. Exemplarily, the number of PAM4 lanes between chip 3 and chip 2 is N, the number of PAM2 lanes between chip 1 and chip 3 is 2N, the bandwidth of a single PAM2 lane is G1, and the bandwidth of a single PAM4 lane is 2*G1. When the traffic on both sides of chip 1 or chip 2 decreases, or the PAM2 lane between chip 1 and chip 3 fails, or the PAM4 lane between chip 3 and chip 2 fails, it can be configured according to the bandwidth configuration method provided in the embodiment of the present application to achieve energy saving of the aggregated link. Among them, PAM2 lane corresponds to the first link in the embodiment of the present application, and PAM4 lane corresponds to the second link in the embodiment of the present application.

[0127] In the embodiment of the present application, when (K-1)*G1<required bandwidth≤K*G1, the second number of PAM2 links that need to be in the open state is K, and the third number of PAM4 links that need to be in the open state is [K / 2], K is an odd number and K≤2N, and [K / 2] represents the value of K / 2 rounded up. Therefore, chip 1 and chip 2 are configured according to the above bandwidth configuration method based on PAM2 K lane and PAM4 [K / 2] lane, respectively, to achieve end-to-end energy saving between chip 1 and chip 2. In this case, the number of PAM2 lanes that need to be closed is (2N-K), and the number of PAM4 lanes that need to be closed is (NK / 2). If the number of PAM2 lanes that need to be closed is an odd number, the number of PAM4 lanes that need to be closed is not an integer, so the PAM4 lanes in the open state include 1 PAM4 lane with a bandwidth utilization rate of 50%.

[0128] See also Fig.12As shown in the schematic diagram of traffic transmission, chip 1 includes PAM2 lane0 / 1, where TX stands for transmit and RX stands for receive. Taking the transmission direction of traffic from chip 1 to chip 2 as an example, PAM2 lane0 / 1 of chip 3 multiplexes the traffic of lane0 / 1 through a multiplexer (multiplexer, MUX), and then converts PAM2 to PAM4 and outputs it to chip 2. Chip 2 converts PAM2 through PAM4, and then outputs 2 data streams through a demultiplexer (demultiplexer, Demux). Exemplarily, when chip 1 / 3 PAM2 lane0 is closed and PAM2 lane1 is opened, the RX side of chip 3 PAM2 lane0 is closed, and the TX side of chip 3 PAM2 lane0 replaces the PAM2 lane0 input data with a fixed code pattern by inserting a fixed code pattern, and the fixed code pattern can refer to the above-mentioned IDLE code and control code. After chip 2 outputs two data streams through Demux, it selects the traffic of lane 1 by identifying the fixed code pattern inserted by chip 3 and discards the traffic of lane 0 with the fixed code pattern.

[0129] against Fig.10 In the scenario shown in (b), chip 1 and chip 2 support PAM2 encoding, and chip 1 and chip 2 achieve electrical link interconnection through two chips 3 and chip 4 that perform PAM2 and PAM4 conversions. Among them, chip 1 and chip 2, chip 4 and chip 2 are connected via PAM2 lanes, respectively, and chip 3 and chip 4 are connected via PAM4 lanes. Therefore, the number of PAM2 lanes between chip 3 and chip 4 is twice the number of PAM4 lanes between chip 1 and chip 2, and between chip 4 and chip 2. When the traffic on both sides of chip 1 or chip 2 decreases, or the PAM2 lane between chip 1 and chip 3 fails, or the PAM4 lane between chip 3 and chip 4 fails, or the PAM2 lane between chip 4 and chip 2 fails, the bandwidth configuration method provided in the embodiment of the present application can be used for configuration to achieve energy saving of the aggregated link. For Fig.10 (b) The implementation method of the bandwidth configuration method for the scenario shown in Fig.10 (c) The implementation method of the bandwidth configuration method of the scenario shown in FIG. Fig.10 The implementation method of the bandwidth configuration method for the scenario shown in (a) will not be described in detail in the embodiments of the present application.

[0130] against Fig.11 The optical interconnection scenario shown in FIG. 1 is shown in FIG. 1 , where E<->O indicates a photoelectric conversion function, where E represents electricity and O represents light. Fig.11In (a), chip 1 and chip 2 are directly connected through the optoelectronic conversion module. The PMA lanes of chip 1 and chip 2 support the same encoding method and multiple lanes are connected through optical links. Fig.11 In (b), chip 1 and chip 3 are directly connected through the optoelectronic conversion module. The PMA lanes of chip 1 and chip 3 support the same PAM2 encoding method. Chip 1 and chip 3 are connected through multi-lane optical links. Chip 3 and chip 2 are connected through PAM4 lane electrical links. The PMA lanes of chip 1 and chip 2 support different encoding methods. Fig.11 In (c), chip 3 and chip 4 are directly interconnected through the optoelectronic conversion module. Chip 3 and chip 4 support the same PAM4 encoding method. Chip 3 and chip 4 are interconnected through multi-lane optical links. The PMA lanes of chip 1 and chip 2 support the same encoding method. Chip 1 and chip 3 are interconnected through PAM4 lane electrical links. Chip 4 and chip 2 are interconnected through PAM4 lane electrical links.

[0131] by Fig.11 (a) is used as an example to illustrate the photoelectric conversion module. Chip 1 and chip 2 can be part of the photoelectric conversion module or can be independent chips. For example, chip 1 and chip 2 are schematic diagrams of a part of the photoelectric conversion module as shown in FIG. Fig.13 As shown, the photoelectric conversion module includes substrate 1, core (Die) 1 and Die2, Die1 corresponds to chip 1, Die2 corresponds to E<->O, and the photoelectric conversion module also includes substrate 2, Die3 and Die4, Die3 corresponds to chip 2, and Die4 corresponds to E<->O. Chip 1 and chip 2 are independent chips. Fig.14 As shown, chip 1 is deployed on single board 1, chip 2 is deployed on single board 2, and the optoelectronic conversion module includes a pluggable optical module 1 and a pluggable optical module 2.

[0132] for Fig.11 For an implementation of bandwidth configuration of an electrical link in the optical interconnection scenario shown in FIG. Figure 4 The implementation method of the bandwidth configuration method shown in FIG. 10( a) or the implementation method of the bandwidth configuration method for the scenario shown in FIG. 10( a) may be referred to, which will not be described in detail here. The implementation methods of bandwidth configuration of the optical link include but are not limited to the following two methods, one is dynamic configuration and the other is static configuration.

[0133] For example, see Fig.15 The schematic diagram of the photoelectric conversion module is shown in FIG. Fig.15As shown, the optoelectronic conversion module includes multiple configuration switches and a control module, and the multiple configuration switches correspond to multiple optical links one by one, and each optical link is represented by OE / OE. Each OE / EO optical link is controlled by an independent configuration switch, and the control of the independent configuration switch is realized through the command interface of the control module to realize the control of opening or closing of each OE / EO optical link route; the control module receives the system command corresponding to the configuration information through the management interface, and the configuration information also includes the fourth number of OE / EO optical links that need to be in the open state, and completes the management and control of the OE / EO optical link according to the system command, and realizes the bandwidth configuration of the OE / EO optical link, so that the number of OE / EO optical links in the open state in the OE / EO optical link is the fourth number.

[0134] exist Fig.15 In the dynamic configuration shown in (a), each configuration switch controls the corresponding OE / EO optical link. For example, the configuration switch controls the laser bias circuit, modulation circuit, receiving detector bias circuit, transimpedance amplifier (TIA) and digital signal processing (DSP) of the OE / EO optical link to achieve dynamic control of the opening or closing of the OE / EO optical link. Fig.15 In the static configuration shown in (b), the configuration switch corresponding to each OE / EO optical link has an independent power input, and then the power supply of the corresponding OE / EO optical link is controlled by each configuration switch, without the need to control the laser bias circuit, modulation circuit, receiving detector bias circuit, TIA and DSP, so as to realize static control of the OE / EO optical link. For example, when power is supplied to any configuration switch, the opening control of the OE / EO optical link corresponding to any configuration switch is realized, and when power is not supplied to any configuration switch, the closing control of the OE / EO optical link corresponding to any configuration switch is realized.

[0135] The bandwidth configuration method provided in the embodiment of the present application configures the bandwidth by controlling the number of links in an open state, so that the bandwidth of the links in an open state is greater than or equal to the required bandwidth, thereby meeting the demand for data transmission, and making the difference between the bandwidth of the links in an open state and the required bandwidth less than a difference threshold, thereby avoiding a waste of bandwidth resources due to an excessive number of links in an open state.

[0136] The bandwidth configuration method of the embodiment of the present application is introduced above. Corresponding to the above method, the embodiment of the present application also provides a bandwidth configuration device. Fig.16 Schematic diagram of a bandwidth configuration device provided in an embodiment of the present application. Fig.16 As shown in the following multiple modules, the Fig.16The bandwidth configuration device shown can perform Figure 4 It should be understood that the device may include more additional modules than the modules shown or omit some of the modules shown, and the embodiments of the present application are not limited to this. Fig.16 As shown, the device comprises:

[0137] A first acquisition module 1601 is used to acquire a required bandwidth for data transmission on an aggregated link, where the aggregated link includes multiple links;

[0138] A second acquisition module 1602 is configured to acquire configuration information based on the required bandwidth and the bandwidth of each link, where the configuration information includes a first number of links that need to be in an open state among the multiple links, a first bandwidth of the first number of links is greater than or equal to the required bandwidth, and a difference between the first bandwidth and the required bandwidth is less than a difference threshold;

[0139] The configuration module 1603 is used to configure the aggregated link according to the configuration information so that the number of links in the open state among the multiple links is a first number.

[0140] In a possible implementation, the multiple links are multiple physical medium associated sublayer PMA links, one PMA link corresponds to at least one virtual link, and different virtual links are distinguished by alignment mark AM words; the configuration information also includes a target generation period of the AM word, a target mapping relationship between the multiple virtual links and the first number of PMA links, and a target operating frequency of the multiple virtual links; the target generation period is used to ensure that the second bandwidth including the AM word transmitted by the multiple virtual links is divisible by the first number, the target mapping relationship is used to ensure that the allocation of the multiple virtual links on the first number of PMA links meets the allocation conditions, and the target operating frequency is used to ensure that the second bandwidth matches the first bandwidth.

[0141] In a possible implementation, the configuration module 1603 is used to control the operating status of multiple PMA links based on a first number so that the number of links in the multiple PMA links that are in an open state is the first number; when the target generation cycle is different from the current generation cycle of the AM word, adjust the current generation cycle of the AM word to the target generation cycle; map the multiple virtual links to the first number of PMA links according to the target mapping relationship; when the target operating frequency is different from the current operating frequencies of the multiple virtual links, adjust the current operating frequency to the target operating frequency.

[0142] In one possible implementation, the working clock used by multiple virtual links is a first clock, the first clock and the second clock are in a master-standby relationship with each other, and the time of the second clock indicates the target working frequency; the configuration module 1603 is used to switch the working clock used by multiple virtual links from the first clock to the second clock.

[0143] In a possible implementation, multiple links correspond to multiple physical ports, and a first number of links among the multiple links that need to be in an open state is a first number of physical ports among the multiple physical ports that need to be in an open state; the configuration information also includes a link aggregation algorithm, and the link aggregation algorithm is used to map data to the first number of physical ports for transmission.

[0144] In a possible implementation, the aggregate link is used to connect the first device and the second device, and the time between the first device and the second device is synchronized. The first device and the second device both configure the aggregate link according to the configuration information.

[0145] In a possible implementation, a third device is included between the first device and the second device, the aggregated link includes a first aggregated link and a second aggregated link, the first aggregated link includes multiple first links, the second aggregated link includes multiple second links, the first aggregated link connects the first device and the third device, and the second aggregated link connects the third device and the first device; the configuration information includes a second number of first links in the first aggregated link that need to be in an open state, a third number of second links in the second aggregated link that need to be in an open state, and the second bandwidth of the second number of first links and the third bandwidth of the third number of second links both match the required bandwidth.

[0146] In a possible implementation, the first acquisition module 1601 is used to acquire the required bandwidth for transmitting data on the aggregated link when any link among the multiple links is detected to be failed; the second acquisition module 1602 is used to acquire configuration information based on the required bandwidth and the bandwidth of each link when the bandwidth of a link that has not failed among the multiple links is greater than the required bandwidth;

[0147] The device also includes a discarding module, which is used to discard data of services that meet the discarding requirements among the services transmitted by the multiple links when the bandwidth of the links that have not failed among the multiple links is not greater than the required bandwidth.

[0148] In one possible implementation, an aggregated link is connected to a plurality of user-side interfaces; a first acquisition module 1601 is used to detect interface utilization corresponding to the plurality of user-side interfaces at the current time, or to determine the interface utilization corresponding to the current time based on a traffic change cycle of the user-side interface, wherein the traffic change cycle is obtained by statistically analyzing the traffic transmission conditions of the plurality of user-side interfaces in a historical time; and the required bandwidth is determined based on the interface utilization.

[0149] The bandwidth configuration device provided in the embodiment of the present application configures the bandwidth by controlling the number of links in an open state, so that the bandwidth of the links in an open state is greater than or equal to the required bandwidth, thereby meeting the demand for data transmission, and making the difference between the bandwidth of the links in an open state and the required bandwidth less than the difference threshold, thereby avoiding the waste of bandwidth resources due to an excessive number of links in an open state.

[0150] It should be understood that the above Fig.16 When the device provided realizes its functions, only the division of the above-mentioned functional modules is used as an example for illustration. In practical applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0151] See also Fig.17 , Fig.17 The present invention provides a schematic diagram of a network-level bandwidth configuration device, which is used to achieve network-level energy saving, that is, to achieve energy saving of each network element device through bandwidth configuration of each network element device in the network, thereby achieving network-level energy saving. Fig.17 As shown, the network-level bandwidth configuration device includes a network element energy-saving module and a network energy-saving module. The network element energy-saving module includes an energy-saving module 1, an energy-saving module 2, a flow monitoring module and an energy-saving control module; the network energy-saving module includes a network-level flow monitoring module and a network-level energy-saving control module. The energy-saving module 1 is used to implement the above Figure 4 The energy-saving module 21 is used to implement the bandwidth configuration of the electrical link. Fig.15 The bandwidth configuration of the optical link shown in the figure; the traffic monitoring module is used to monitor the traffic of the aggregated link of each network element device or the traffic of the high-speed Ethernet interface, as well as to monitor the failure status of each link in the aggregated link, and feed back the monitoring results to the energy-saving control module, or send the monitoring results to the network-level traffic monitoring module through the network-to-network interface (NNI); the energy-saving control module is used to control the energy-saving module 1 and the energy-saving module 2 through the obtained monitoring results. The network-level traffic monitoring module is used to monitor the network traffic of the entire network, and the relevant monitoring results are fed back to the network-level energy-saving control module; the network-level energy-saving control module is used to confirm which network element devices need to be configured with corresponding bandwidth to reduce power consumption and achieve energy saving through the obtained monitoring results of the entire network, and send commands for bandwidth configuration of which network element device to the energy-saving control module through NNI. Therefore, the energy-saving control module also receives commands issued by the network-level energy-saving control module to complete the bandwidth configuration of any network element device.

[0152] See also Fig.18 , Fig.18 A schematic diagram of the structure of a network device 2000 provided by an exemplary embodiment of the present application is shown. Fig.18 The network device 2000 shown is used to perform the above Figure 4 The operations involved in the bandwidth configuration method shown in the figure. The network device 2000 is, for example, a switch, a router, etc. The network device 2000 can be implemented by a general bus architecture.

[0153] like Fig.18 As shown, the network device 2000 includes at least one processor 2001 , a memory 2003 , and at least one communication interface 2004 .

[0154] The processor 2001 is, for example, a general-purpose central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing units (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solution of the present application. For example, the processor 2001 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. It can implement or execute various logic blocks, modules, and circuits described in conjunction with the disclosure of the embodiments of the present invention. The processor can also be a combination that implements a computing function, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0155] Optionally, the network device 2000 further includes a bus. The bus is used to transmit information between the components of the network device 2000. The bus may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.18 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0156] The memory 2003 is, for example, a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 2003 is, for example, independent and connected to the processor 2001 via a bus. The memory 2003 can also be integrated with the processor 2001.

[0157] The communication interface 2004 uses any transceiver type device for communicating with other devices or communication networks, and the communication network can be Ethernet, radio access network (radio access network, RAN) or wireless local area network (wireless local area networks, WLAN) and the like. The communication interface 2004 can include a wired communication interface and can also include a wireless communication interface. Specifically, the communication interface 2004 can be an Ethernet interface, a Fast Ethernet (Fast Ethernet, FE) interface, a Gigabit Ethernet (Gigabit Ethernet, GE) interface, an Asynchronous Transfer Mode (Asynchronous Transfer Mode, ATM) interface, a wireless local area network (wireless local area networks, WLAN) interface, a cellular network communication interface or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface or a combination thereof. In an embodiment of the present application, the communication interface 2004 can be used for the network device 2000 to communicate with other devices.

[0158] In a specific implementation, as an embodiment, the processor 2001 may include one or more CPUs, such as Fig.18 0 and CPU1 shown in FIG. Each of these processors may be a single-core CPU processor or a multi-core CPU processor. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0159] In a specific implementation, as an embodiment, the network device 2000 may include multiple processors, such as Fig.18 2001 and 2005 are shown in FIG. Each of these processors may be a single-core CPU or a multi-core CPU. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0160] In a specific implementation, as an embodiment, the network device 2000 may further include an output device and an input device. The output device communicates with the processor 2001 and may display information in a variety of ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 2001 and may receive user input in a variety of ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensor device.

[0161] In some embodiments, the memory 2003 is used to store the program code 2010 for executing the solution of the present application, and the processor 2001 can execute the program code 2010 stored in the memory 2003. That is, the network device 2000 can implement the bandwidth configuration method provided by the method embodiment through the processor 2001 and the program code 2010 in the memory 2003. The program code 2010 may include one or more software modules. Optionally, the processor 2001 itself can also store the program code or instruction for executing the solution of the present application.

[0162] In a specific embodiment, the network device 2000 of the embodiment of the present application may correspond to the network device 2000 in the above-mentioned various method embodiments. Figure 4 Method, the processor 2001 in the network device 2000 reads the instruction in the memory 2003, so that Fig.18 The network device 2000 shown is capable of performing Figure 4 All or part of the operations performed by a method.

[0163] Specifically, the processor 2001 is used to obtain the required bandwidth for transmitting data through an aggregated link, where the aggregated link includes multiple links; obtain configuration information based on the required bandwidth and the bandwidth of each link, where the configuration information includes a first number of links that need to be in an open state among the multiple links, a first bandwidth of the first number of links is greater than or equal to the required bandwidth, and a difference between the first bandwidth and the required bandwidth is less than a difference threshold; and configure the aggregated link according to the configuration information so that the number of links in an open state among the multiple links is the first number.

[0164] For the sake of brevity, other optional implementations are not described here in detail.

[0165] The network device 2000 may also correspond to the above Fig.16In the bandwidth configuration device shown, each functional module in the bandwidth configuration device is implemented by software of the network device 2000. In other words, the functional modules included in the bandwidth configuration device are generated after the processor 2001 of the network device 2000 reads the program code 2010 stored in the memory 2003.

[0166] in, Figure 4 Each step of the bandwidth configuration method shown is completed by an integrated logic circuit of hardware or software instructions in the processor of the network device 2000. The steps of the method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor, or a combination of hardware and software modules in the processor. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.

[0167] See also Fig.19 , Fig.19 FIG. 2 shows a schematic diagram of the structure of a network device 2100 provided by another exemplary embodiment of the present application. Fig.19 The network device 2100 shown is used to perform the above Figure 4 All or part of the operations involved in the bandwidth configuration method shown. The network device 2100 is, for example, a switch, a router, etc. The network device 2100 can be implemented by a general bus architecture.

[0168] like Fig.19 As shown, the network device 2100 includes: a main control board 2110 and an interface board 2130 .

[0169] The main control board is also called a main processing unit (MPU) or a route processor card. The main control board 2110 is used to control and manage various components in the network device 2100, including routing calculation, device management, device maintenance, and protocol processing functions. The main control board 2110 includes: a central processing unit 2111 and a memory 2112.

[0170] The interface board 2130 is also called a line processing unit (LPU), a line card (linecard) or a service board. The interface board 2130 is used to provide various service interfaces and realize the forwarding of data packets. The service interface includes but is not limited to an Ethernet interface, a POS (Packet over SONET / SDH) interface, etc., and the Ethernet interface is, for example, a Flexible Ethernet Service Interface (Flexible Ethernet Clients, FlexE Clients). The interface board 2130 includes: a central processing unit 2131, a network processor 2132, a forwarding table entry memory 2134 and a physical interface card (physical interface card, PIC) 2133.

[0171] The central processor 2131 on the interface board 2130 is used to control and manage the interface board 2130 and communicate with the central processor 2111 on the main control board 2110 .

[0172] The network processor 2132 is used to implement the forwarding processing of the message. The network processor 2132 can be in the form of a forwarding chip. The forwarding chip can be a network processor (NP). In some embodiments, the forwarding chip can be implemented by an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Specifically, the network processor 2132 is used to forward the received message based on the forwarding table stored in the forwarding table entry memory 2134. If the destination address of the message is the address of the network device 2100, the message is sent to the CPU (such as the central processor 2131) for processing; if the destination address of the message is not the address of the network device 2100, the next hop and the output interface corresponding to the destination address are found from the forwarding table according to the destination address, and the message is forwarded to the output interface corresponding to the destination address. Among them, the processing of the uplink message may include: processing of the message input interface, forwarding table search; the processing of the downlink message may include: forwarding table search, etc. In some embodiments, the central processor can also perform the function of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, so that the forwarding chip is not required in the interface board.

[0173] The physical interface card 2133 is used to implement the physical layer docking function, whereby the original traffic enters the interface board 2130, and the processed message is sent out from the physical interface card 2133. The physical interface card 2133, also called a daughter card, can be installed on the interface board 2130, and is responsible for converting the photoelectric signal into a message and forwarding the message to the network processor 2132 for processing after checking the legitimacy of the message. In some embodiments, the central processor 2131 can also perform the functions of the network processor 2132, such as implementing software forwarding based on a general-purpose CPU, so that the network processor 2132 is not required in the physical interface card 2133.

[0174] Optionally, the network device 2100 includes multiple interface boards, for example, the network device 2100 further includes an interface board 2140, and the interface board 2140 includes: a central processor 2141, a network processor 2142, a forwarding table entry memory 2144, and a physical interface card 2143. The functions and implementation methods of the components in the interface board 2140 are the same or similar to those of the interface board 2130, and are not described in detail here.

[0175] Optionally, the network device 2100 further includes a switching fabric board 2120. The switching fabric board 2120 may also be referred to as a switch fabric unit (SFU). When the network device 2100 has multiple interface boards, the switching fabric board 2120 is used to complete data exchange between the interface boards. For example, the interface board 2130 and the interface board 2140 may communicate via the switching fabric board 2120.

[0176] The main control board 2110 is coupled to the interface board. For example, the main control board 2110, the interface board 2130, the interface board 2140, and the switching network board 2120 are connected to the system backplane through the system bus to achieve intercommunication. In a possible implementation, an inter-process communication (IPC) channel is established between the main control board 2110 and the interface board 2130 and the interface board 2140, and the main control board 2110 and the interface board 2130 and the interface board 2140 communicate through the IPC channel.

[0177] Logically, the network device 2100 includes a control plane and a forwarding plane. The control plane includes a main control board 2110 and a central processing unit 2111. The forwarding plane includes various components for performing forwarding, such as a forwarding table entry memory 2134, a physical interface card 2133, and a network processor 2132. The control plane performs functions such as a router, generating a forwarding table, processing signaling and protocol messages, and configuring and maintaining the status of the network device. The control plane sends the generated forwarding table to the forwarding plane. On the forwarding plane, the network processor 2132 forwards the message received by the physical interface card 2133 based on the forwarding table sent by the control plane. The forwarding table sent by the control plane can be stored in the forwarding table entry memory 2134. In some embodiments, the control plane and the forwarding plane can be completely separated and not on the same network device.

[0178] It is worth noting that there may be one or more main control boards, and when there are multiple boards, they may include a primary main control board and a backup main control board. There may be one or more interface boards. The stronger the data processing capability of the network device, the more interface boards are provided. There may also be one or more physical interface cards on the interface board. There may be no switching network board, or there may be one or more switching network boards. When there are multiple switching network boards, they can jointly realize load sharing and redundant backup. In a centralized forwarding architecture, network devices may not need switching network boards, and the interface board is responsible for processing the service data of the entire system. In a distributed forwarding architecture, network devices may have at least one switching network board, and data exchange between multiple interface boards is realized through the switching network board, providing large-capacity data exchange and processing capabilities. Therefore, the data access and processing capabilities of network devices with distributed architectures are greater than those of network devices with centralized architectures. Optionally, the network device may have only one board, that is, no switching board, and the functions of the interface board and the main control board are integrated on the board. In this case, the central processor on the interface board and the central processor on the main control board can be combined into one central processor on the board to perform the functions of the two. This type of network device has low data exchange and processing capabilities (for example, low-end switches or routers and other network devices). The specific architecture to be adopted depends on the specific networking deployment scenario, and no limitation is made here.

[0179] In a specific embodiment, the network device 2100 corresponds to the above Fig.16 In some embodiments, Fig.16 The first acquisition module 1601 , the second acquisition module 1602 and the configuration module 1603 in the bandwidth configuration apparatus shown are equivalent to the central processor 2111 or the network processor 2132 in the network device 2100 .

[0180] It should be understood that the processor may be a CPU, or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor supporting the advanced reduced instruction set machine (ARM) architecture.

[0181] Further, in an optional embodiment, the memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may also include a non-volatile random access memory. For example, the memory may also store information about the device type.

[0182] The memory may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory. Among them, the nonvolatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM) and direct RAM bus random access memory (DR RAM).

[0183] The embodiment of the present application further provides a computer-readable storage medium, in which at least one instruction is stored. The instruction is loaded and executed by a processor so that a computer implements any of the above bandwidth configuration methods.

[0184] The embodiments of the present application also provide a computer program (product), which, when executed by a computer, can enable a processor or a computer to execute the corresponding steps and / or processes in the above method embodiments.

[0185] An embodiment of the present application also provides a chip, including a processor, for calling and executing instructions stored in the memory from the memory, so that a communication device equipped with the chip executes any of the above bandwidth configuration methods.

[0186] An embodiment of the present application also provides another chip, including: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected via an internal connection path, and the processor is used to execute the code in the memory. When the code is executed, the processor is used to execute any of the above bandwidth configuration methods.

[0187] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integration. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state drive (solid state disk)), etc.

[0188] Those of ordinary skill in the art will appreciate that, in combination with the various method steps and modules described in the embodiments disclosed herein, they can be implemented in software, hardware, firmware, or any combination thereof. In order to clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0189] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0190] When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer program instructions. As an example, the method of the embodiment of the present application can be described in the context of a machine executable instruction, and the machine executable instruction is such as included in the program module executed in the device on the real or virtual processor of the target. Generally speaking, a program module includes a routine, a program, a library, an object, a class, a component, a data structure, etc., which performs a specific task or realizes a specific abstract data structure. In various embodiments, the function of the program module can be merged or divided between the described program modules. The machine executable instruction for the program module can be executed in a local or distributed device. In a distributed device, the program module can be located in both a local and a remote storage medium.

[0191] The computer program code for realizing the method for the embodiment of the present application can be written in one or more programming languages. These computer program codes can be mapped to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device, so that the program code, when executed by a computer or other programmable data processing device, causes the function / operation specified in the flow chart and / or block diagram to be implemented. The program code can be executed completely on a computer, partially on a computer, as an independent software package, partially on a computer and partially on a remote computer or completely on a remote computer or server.

[0192] In the context of the embodiments of the present application, computer program codes or related data may be carried by any appropriate carrier to enable a device, apparatus or processor to perform the various processes and operations described above. Examples of carriers include signals, computer readable media, and the like.

[0193] Examples of signals may include electrical, optical, radio, acoustic or other forms of propagated signals, such as carrier waves, infrared signals, etc.

[0194] A machine-readable medium may be any tangible medium that contains or stores a program for or related to an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of machine-readable storage media include an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0195] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0196] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the module is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or it can be an electrical, mechanical or other form of connection.

[0197] The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0198] In addition, each functional module in each embodiment of the present application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0199] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0200] In the present application, the terms "first", "second", etc. are used to distinguish between identical or similar items having substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is the quantity and execution order limited. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of various examples, a first image may be referred to as a second image, and similarly, a second image may be referred to as a first image. Both the first image and the second image may be images, and in some cases, may be separate and different images.

[0201] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0202] The term "at least one" in this application means one or more, and the term "multiple" in this application means two or more, for example, multiple second messages means two or more second messages. The terms "system" and "network" are often used interchangeably herein.

[0203] It should be understood that the terms used in the description of the various examples herein are only for describing specific examples and are not intended to be limiting. As used in the description of the various examples and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0204] It should also be understood that the term "and / or" used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The term "and / or" is a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application generally indicates that the associated objects before and after are in an "or" relationship.

[0205] It should also be understood that the term “comprise” (also known as “includes,” “including,” “comprises” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0206] It should also be understood that the terms "if" and "if" may be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting." Similarly, the phrases "if it is determined that ..." or "if [a stated individual or event] is detected" may be interpreted to mean "upon determining that ..." or "in response to determining that ..." or "upon detecting [a stated individual or event]" or "in response to detecting [a stated individual or event]," depending on the context.

[0207] It should be understood that determining B based on A does not mean determining B only based on A. B can also be determined based on A and / or other information.

[0208] It should also be understood that the references to "one embodiment", "an embodiment", or "a possible implementation" throughout the specification mean that specific features, structures, or characteristics related to the embodiment or implementation are included in at least one embodiment of the present application. Therefore, the references to "in one embodiment" or "in an embodiment", or "a possible implementation" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0209] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application should be included in the protection scope of the present application.

Claims

1. A bandwidth configuration method, characterized in that: The method comprises: Obtaining a required bandwidth for data transmission on an aggregated link, where the aggregated link includes a plurality of links; acquiring configuration information based on the required bandwidth and the bandwidth of each link, the configuration information including a first number of links that need to be in an open state among the multiple links, a first bandwidth of the first number of links being greater than or equal to the required bandwidth, and a difference between the first bandwidth and the required bandwidth being less than a difference threshold; The aggregated link is configured according to the configuration information so that the number of links in the multiple links that are in an open state is the first number.

2. The method according to claim 1, characterized in that The multiple links are multiple physical medium associated sublayer PMA links, one PMA link corresponds to at least one virtual link, and different virtual links are distinguished by alignment marker AM words; the configuration information also includes a target generation period of the AM word, a target mapping relationship between the multiple virtual links and the first number of PMA links, and a target operating frequency of the multiple virtual links; The target generation period is used to ensure that the second bandwidth including the AM words transmitted by the multiple virtual links is divisible by the first number, the target mapping relationship is used to ensure that the allocation of the multiple virtual links on the first number of PMA links meets the allocation conditions, and the target operating frequency is used to ensure that the second bandwidth matches the first bandwidth.

3. The method according to claim 2, characterized in that The configuring the aggregated link according to the configuration information includes: Controlling the operating states of the plurality of PMA links based on the first number so that the number of links in the plurality of PMA links that are in an open state is the first number; When the target generation period is different from the current generation period of the AM word, adjusting the current generation period of the AM word to the target generation period; Mapping the plurality of virtual links to the first number of PMA links according to the target mapping relationship; When the target operating frequency is different from the current operating frequencies of the multiple virtual links, the current operating frequency is adjusted to the target operating frequency.

4. The method according to claim 3, characterized in that The working clocks used by the multiple virtual links are the first clock, the first clock and the second clock are in a master-slave relationship with each other, and the time of the second clock indicates the target working frequency; The adjusting the current operating frequency to the target operating frequency includes: The working clocks used by the multiple virtual links are switched from the first clock to the second clock.

5. The method according to claim 1, characterized in that The multiple links correspond to multiple physical ports, and the first number of links in the multiple links that need to be in an open state is the first number of physical ports in the multiple physical ports that need to be in an open state; the configuration information also includes a link aggregation algorithm, and the link aggregation algorithm is used to map data to the first number of physical ports for transmission.

6. The method according to any one of claims 1 to 5, characterized in that: The aggregate link is used to connect a first device and a second device, the first device and the second device are time synchronized, and the first device and the second device both configure the aggregate link according to the configuration information.

7. The method according to claim 6, characterized in that A third device is included between the first device and the second device, the aggregated link includes a first aggregated link and a second aggregated link, the first aggregated link includes multiple first links, the second aggregated link includes multiple second links, the first aggregated link connects the first device and the third device, and the second aggregated link connects the third device and the first device; the configuration information includes a second number of first links in the first aggregated link that need to be in an open state, a third number of second links in the second aggregated link that need to be in an open state, and the second bandwidth of the second number of first links and the third bandwidth of the third number of second links both match the required bandwidth.

8. The method according to any one of claims 1 to 7, characterized in that: The obtaining of the required bandwidth for transmission of data via the aggregated link includes: When any one of the multiple links is detected to be failed, obtaining a required bandwidth for transmitting data on the aggregated link; The acquiring configuration information based on the required bandwidth and the bandwidth of each link includes: When the bandwidth of a link that has not failed among the multiple links is greater than the required bandwidth, acquiring configuration information based on the required bandwidth and the bandwidth of each link; The method further includes: when the bandwidth of a link that has not failed among the multiple links is not greater than the required bandwidth, discarding data of services that meet the discarding requirement among the services transmitted by the multiple links.

9. The method according to any one of claims 1 to 8, characterized in that: The aggregated link is connected to a plurality of user-side interfaces; and obtaining the required bandwidth for transmitting data through the aggregated link includes: Detecting the interface utilization rates corresponding to the multiple user-side interfaces at the current time, or determining the interface utilization rates corresponding to the current time based on the traffic change cycle of the user-side interfaces, wherein the traffic change cycle is obtained by statistically analyzing the traffic transmission conditions of the multiple user-side interfaces in the historical time; The required bandwidth is determined based on the interface utilization.

10. A bandwidth configuration device, characterized in that: The device comprises: A first acquisition module, used to acquire a required bandwidth for transmitting data on an aggregated link, where the aggregated link includes a plurality of links; A second acquisition module, configured to acquire configuration information based on the required bandwidth and the bandwidth of each link, wherein the configuration information includes a first number of links that need to be in an open state among the multiple links, a first bandwidth of the first number of links is greater than or equal to the required bandwidth, and a difference between the first bandwidth and the required bandwidth is less than a difference threshold; A configuration module is used to configure the aggregated link according to the configuration information so that the number of links in the multiple links that are in an open state is the first number.

11. A network device, characterized in that: The network device includes: a processor, the processor is coupled to a memory, the memory stores at least one program instruction or code, and the at least one program instruction or code is loaded and executed by the processor so that the network device implements the bandwidth configuration method described in any one of claims 1-9.

12. A computer-readable storage medium, characterized in that: The computer storage medium stores at least one instruction, and the at least one instruction is loaded and executed by a processor, so that the computer implements the bandwidth configuration method according to any one of claims 1 to 9.

13. A computer program product, characterized in that The computer program product comprises: a computer program code, wherein the computer program code is loaded and executed by a computer so as to enable the computer to implement the bandwidth configuration method according to any one of claims 1 to 9.

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