Adaptive light intensity high-speed wide dynamic pulse pixel structure and image sensor, electronic device

Abstract

The application discloses a high-speed wide-dynamic pulse pixel structure with adaptive light intensity, an image sensor and electronic equipment, and the high-speed wide-dynamic pulse pixel structure comprises a photodiode, a plurality of MOS switch transistors, a capacitor trans-impedance amplifier, a CTIA capacitor, a comparator, a plurality of inverters, a pulse signal latch, and a 3bit counter. The pixel structure disclosed by the application can adaptively select a photosensitive node gain according to light intensity, improve low-light sensitivity, expand a dynamic range, and can realize response to a high-speed scene, and the problem that a plurality of signals need to be read out and read-out time is long due to high dynamic range requirement of a CMOS image sensor, capacitor overflow or a double-gain structure is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of pixel structures, and in particular to a high-speed, wide-dynamic pulse pixel structure with adaptive light intensity, an image sensor, and electronic equipment. Background Art

[0002] In the field of complementary metal oxide semiconductor (CMOS) image sensors, dynamic range (DR) is a critical parameter in applications such as surveillance, security, and drones, directly impacting the quality of the image sensor's scene perception. During the image sensor design process, maximizing the dynamic range is typically sought to expand its applicability.

[0003] Classic active-pixel image sensors have a limited dynamic range. At a fixed exposure time, the lowest perceptible light intensity is limited by quantization and readout noise, while the maximum perceptible light intensity is typically limited by the full-well capacity. Increasing the exposure time allows for the perception of lower light intensities, but the maximum measurable light intensity decreases. Reducing the exposure time allows for responses at higher illumination levels, but accuracy is lost in areas of lower illumination. Therefore, the sensor's dynamic range is limited by the pixel design itself and cannot be expanded by globally adjusting the integration time. Typically, the dynamic range of active-pixel image sensors is below 70dB. For human vision, the dynamic range of perceptible scenes is around 120dB. In comparison, the dynamic range of classic active-pixel image sensors cannot meet our daily needs.

[0004] Traditional image sensors' ability to quantize scenes is limited by exposure time and capacitor node size, resulting in a restricted dynamic range. To address this limitation, pixel designs often employ a Lateral Overflow Integration Capacitor (LOFIC) or a dual conversion gain (DCG) structure. This expands the charge storage capacity of the capacitor nodes to extend the response to high light intensities. However, this requires quantized readout of multiple signals, which takes a long time and is unsuitable for high-speed scenarios. Furthermore, to address exposure time limitations, dynamic range is often expanded by capturing multiple exposures and fusing the image data from different frames. However, this approach places high demands on computational load, hardware, and power consumption.

[0005] In pulse modulation type image sensors, quantization is no longer performed in a manner of encoding charges, voltages or currents, instead, image data is represented by pulse timing or pulse edges, which avoids the limitation of fixed exposure time on pixel photosensitivity, and improves dynamic range and signal-to-noise ratio. In addition, pulse modulation type image sensors perform analog-to-digital conversion in pixels, thereby achieving high time resolution. The high speed and high dynamic range characteristics of pulse modulation imaging make it have wide application prospects in high performance machine vision.

[0006] However, due to the unique reset and encoding mode of the pulse modulation (PM) type image sensor, the number of transistors in the pixel unit is large, in order to ensure the pixel fill factor, the photosensitive node capacitance is usually 10~100fF, and the photosensitive conversion gain is low, so the low light intensity sensitivity of the structure is poor, which limits its application in dark high-speed scenes.

[0007] In summary, the prior art usually improves the dynamic range by expanding the charge storage capacity of the photosensitive node (DCG or LOFIC structure) or multi-frame sampling, but the DCG and other large dynamic range structures require a long readout time, and the multi-frame exposure image fusion method also lengthens the response time, both of which cannot be used in high-speed scenes. SUMMARY

[0008] The purpose of the present application is to provide a self-adaptive light intensity high-speed wide dynamic pulse pixel structure and image sensor, electronic equipment, which aims to solve the problem that the CMOS image sensor requires a long readout time due to the high dynamic range requirement, the use of capacitor overflow or the use of double gain structure, the use of multi-frame exposure image fusion method also lengthens the response time, both of which cannot be used in high-speed scenes. The proposed pixel structure can adaptively select the gain of the photosensitive node according to the light intensity, improve the low light intensity sensitivity, expand the dynamic range, and at the same time realize the response to high-speed scenes.

[0009] In a first aspect of the present application, a self-adaptive light intensity high-speed wide dynamic pulse pixel structure is provided, comprising a photodiode, a plurality of MOS switch transistors, a capacitor trans-impedance amplifier, a CTIA capacitor, a comparator, a plurality of inverters, a pulse signal latch, and a 3bit counter.

[0010] One end of the first MOS switch transistor is connected to the non-grounded end of the photodiode and the other end is connected to the negative input end of the capacitor transimpedance amplifier; one end of the parallel circuit structure of the second MOS switch transistor, the third MOS switch transistor, and the CTIA capacitor is connected to the non-grounded end of the photodiode and the other end is connected to the output end of the capacitor transimpedance amplifier; the positive input end of the capacitor transimpedance amplifier is connected to the reset voltage signal Vrst, and the output end is connected to the negative input end of the comparator;

[0011] One end of the fourth MOS switch transistor, the fifth MOS switch transistor, the sixth MOS switch transistor, and the seventh MOS switch transistor are commonly connected to the positive input end of the comparator, and the other ends are respectively connected to the pre-judgment working threshold voltage Vth0, the reset voltage signal Vrst, the first working threshold voltage Vth1 of the pixel working under low light intensity conditions, and the second working threshold voltage Vth2 of the pixel working under high light intensity conditions; the output end of the comparator is connected to one end of the parallel circuit of the eighth MOS switch transistor and the ninth MOS switch transistor and one end of the tenth MOS switch transistor, and the other end of the tenth MOS switch transistor is connected to the first inverter input The other end of the parallel circuit of the eighth MOS switch transistor and the ninth MOS switch transistor is connected to the output end of the first inverter and the input end of the second inverter. The output of the second inverter is connected to the pulse signal latch input end and the 3-bit counter input end. The output end of the 3-bit counter is connected to the input end of the third inverter and is input with the global clock signal clk; the input end of the pulse signal latch clk is connected to the latch signal latch, the output end of the pulse signal latch Q is connected to the input end of the fourth inverter, and outputs the latch output signal Latchout; the third inverter and the fourth inverter are respectively input with the row selection signal Sel, and the output ends are connected to the column bus.

[0012] Among them, it includes a working mode switching logic control unit, which is used to control the output of multiple working mode switching control signals to correspondingly control the first MOS switch transistor, the second MOS switch transistor, the sixth MOS switch transistor, the seventh MOS switch transistor, the ninth MOS switch transistor, and the tenth MOS switch transistor to switch the working mode.

[0013] Among them, the signal input end of the working mode switching logic control unit is connected to the pre-judgment logic unit output signal S0 and the latch input signal Latchin, and controls the output of multiple working mode switching control signals according to the pre-judgment logic unit output signal S0 and the latch input signal Latchin.

[0014] Among them, it includes a reset logic control unit, which is used to control the output reset control signal, and correspondingly controls the reset of the third MOS switch transistor, the eighth MOS transistor switch tube and the fifth MOS switch transistor; the input end of the reset logic control unit is connected to the output end of the pulse signal latch, and is also connected to the reset signal Rst.

[0015] Among them, it includes a pre-judgment logic unit, which is used to adaptively switch the photosensitive node gain according to the light intensity. The input end of the pre-judgment logic unit is connected to the pre-judgment signal SN1 and the output signal Latchout of the pulse signal latch, and the output end of the pre-judgment logic unit is connected to the S0 signal input end of the working mode switching logic control unit.

[0016] In the working mode switching logic unit, the first MOS switch transistor, the second MOS switch transistor, the sixth MOS switch transistor, the seventh MOS switch transistor, the ninth MOS switch transistor, and the tenth MOS switch transistor are controlled together by the input S0 signal and the Latchin signal to achieve working state control of the CTIA capacitor and the first inverter.

[0017] Among them, when quantizing high light intensity, the second MOS switch transistor and the ninth MOS switch transistor are closed, the capacitive transimpedance amplifier does not work, the CTIA capacitor does not work, the first inverter does not work, and the photodiode in the pixel is connected to the negative input terminal of the comparator; during the exposure process, the voltage of the photodiode node gradually decreases and is compared with the second working threshold voltage Vth2 of the comparator in real time. When the threshold voltage is reached, the Vpulse node is triggered to flip, and the flip signal is connected to the pulse signal latch in the pixel by the second inverter; when the latch signal latch arrives, the flip signal is latched in the pulse signal latch, and a 1-bit pulse is output to the column bus when the row selection signal Sel arrives, and a reset is triggered when the reset signal Rst arrives; after Vpulse flips, the flip moment is recorded by a 3-bit counter, and the recorded 3-bit data is output off-chip at the end of the flip frame and combined with the 1-bit pulse data to quantize the light intensity.

[0018] When quantizing low light intensity, the second and ninth MOS switching transistors are turned off, the CTIA capacitor operates, the first inverter operates, and the photodiode is connected to the negative input terminal of the CTIA capacitor. The photogenerated charge during exposure is amplified by the CTIA capacitor gain and compared with the first operating threshold voltage Vth1 in the comparator. When the threshold voltage is reached, the Vpulse node is triggered to flip. The flip signal is connected to the pulse signal latch within the pixel via the first inverter and the second inverter. When the latch signal latch arrives, the flip signal is latched in the pulse signal latch, and a 1-bit pulse is output to the column bus when the select signal Sel arrives. In this operating mode, a 3-bit counter records the Vpulse flip moment. At the end of the flip frame, the recorded 3-bit data is output off-chip and combined with the 1-bit pulse data to quantize the light intensity.

[0019] Among them, the pre-judgment logic unit enters the pre-judgment processing process after the pixel outputs a 1-bit high-level pulse. During the pre-judgment processing, the photodiode end is connected to the negative input end of the comparator, and is compared with the set pre-judgment working threshold voltage Vth0 in the comparator. According to the comparison result, the logic gate is controlled to select the pixel working mode of the next frame, and then enters the reset stage.

[0020] A second aspect of the present invention provides an image sensor comprising the adaptive light intensity high-speed wide dynamic pulse pixel structure.

[0021] According to a third aspect of the present invention, an electronic device is provided, comprising the image sensor.

[0022] The present invention's pulse pixel structure, which adaptively adjusts the gain of the photosensitive node, builds on the foundation of conventional pulse-structured pixels by incorporating a CTIA capacitor into the photosensitive node. This structure also incorporates a pre-judgment module, enabling the pixel to control the operation of the CTIA capacitor during the pre-judgment period. Under high light intensities, the pixel's pre-judgment phase disables the CTIA capacitor, allowing the integrated signal from the photodiode (PD) node to directly enter the subsequent analog-to-digital conversion and readout. Under low light intensities, the pixel's pre-judgment phase activates the CTIA capacitor, allowing the integrated signal from the photodiode (PD) node to undergo gain amplification before entering the subsequent analog-to-digital conversion and readout. This pre-judgment gain selection enables pixel gain amplification in low-light conditions and adaptive pixel gain selection for varying light intensities, improving the pixel's dynamic range under low light intensities.

[0023] In addition, the pixel structure introduces a 3-bit counter to record and read out the comparator flipping moment, which improves the quantization accuracy and quantization capability of high light intensity and expands the high light intensity dynamic range.

[0024] In summary, the pixel structure proposed in the present invention can adaptively select the gain of the photosensitive node according to the light intensity, thereby improving the sensitivity at low light intensity and expanding the dynamic range. At the same time, it can respond to high-speed scenes, solving the problem that CMOS image sensors have high dynamic range requirements, use capacitor overflow or dual gain structures, need to read out multiple signals, and have a long readout time. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram of the structure of a high-sensitivity wide dynamic pulse pixel with adaptive light intensity according to an embodiment of the present invention.

[0026] Figure 2 This is a timing diagram of pixel operation under high light intensity according to an embodiment of the present invention.

[0027] Figure 3 This is a timing diagram of pixel operation under low light intensity according to an embodiment of the present invention.

[0028] Figure 4 4 is a pixel operation timing diagram of adaptive gain switching according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0030] The pixel structure of the embodiment of the present invention, based on the traditional pulse modulation pixel structure, adds a gain conversion structure to the photosensitive node, improving the pixel's sensitivity to low light intensities. It also adds a pixel light pre-judgment structure, allowing the pixel to adaptively adjust the conversion gain based on light intensity, thereby improving the pixel's dynamic range while ensuring high-speed response. Furthermore, the pixel structure combines the quantization methods of pulse width modulation and pulse frequency modulation, introducing a global clock and counter to record the comparator flip-flop moment of the analog-to-digital conversion module within the pixel, thereby expanding the dynamic range under high light intensities.

[0031] See also Figure 1As shown, in the embodiment of the present application, the high-speed, wide dynamic pulse pixel structure with adaptive light intensity includes a photodiode (PD) 1, multiple MOS switch transistors, a capacitor feedback transimpedance amplifier (CTIA) 6, a CTIA capacitor (CS) 5, a comparator (COMP) 7, multiple inverters, a pulse signal latch 20, and a 3-bit counter 28; the MOS switch transistors include a first MOS switch transistor 2, a second MOS switch transistor 4, a third MOS switch transistor 3, a fourth MOS switch transistor 8, a fifth MOS switch transistor 9, a sixth MOS switch transistor 10, a seventh MOS switch transistor 11, an eighth MOS switch transistor 12, a ninth MOS switch transistor 13, and a tenth MOS switch transistor 14.

[0032] The first MOS switch transistor (SW3_1) 2 is controlled by the output signal SW3_1 of the working mode switching logic control unit 16, the third MOS switch transistor (SW1_2) 3 is controlled by the output signal S1_2 of the reset logic control unit 23, the second MOS switch transistor (SW1_1) 4 is controlled by the output signal S1_1 of the working mode switching logic control unit 16, the fourth MOS switch transistor (SW0) 8 is controlled by the output signal S0 of the pre-judgment logic unit 22; the fifth MOS switch transistor (SW2) 9 is controlled by the output signal S2 of the reset logic control unit 23; the sixth MOS switch transistor (SW5) 10 is controlled by the working mode switching logic control unit 1 6 output signal S5; the seventh MOS switch transistor (SW4) 11 is controlled by the output signal S4 of the working mode switching logic control unit 16; the tenth MOS switch transistor (SW3_1) 14 is controlled by the output signal S3_1 of the working mode switching logic control unit; the eighth MOS switch transistor (SW1_2) 12 is controlled by the output signal S1_2 of the reset logic control unit 23, and the ninth MOS switch transistor (SW1_1) 13 is controlled by the output signal S1_1 of the working mode switching logic control unit 16; the input end of the working mode switching logic control unit 16 is connected to the output end of the first inverter (inv1) 15, and is also connected to the output signal S0 of the pre-determination logic unit.

[0033] Among them, the input end of the second inverter (inv2) 17 is connected to the output end of the first inverter (inv1) 15, the output end of the second inverter (inv2) 17 is connected to the D input end of the pulse signal latch 20, the input end of the 3-bit counter 18 is connected to the output end of the second inverter (inv2) 17 and is also connected to the global clock signal clk. The output end of the 3-bit counter 18 is connected to the input end of the third inverter 19; the third inverter 19 is connected to the row select signal Sel, the output end is connected to the column bus, and outputs the num signal; the Q output end of the pulse signal latch 20 is connected to the latch output signal Latchout, the clk end is connected to the latch signal latch, and the Q output end is connected to the input end of the fourth inverter 21. There is a Vpulse node between the first inverter 15 and the tenth MOS switch transistor 14, and there is a Vspike node between the second inverter 17 and the pulse signal latch 20. The fourth inverter 21 is connected to the row select signal Sel, the output end is connected to the column bus, and outputs the Spike signal.

[0034] In the present invention, the pre-judgment signal SN1 is the same as the Sel, latch, clk, and Rst signals, which are all periodic timing signals provided externally. In the present invention, when the light intensity is quantized, the second and ninth MOS switch transistors (corresponding to Figure 1 The two switches marked SW1_1 in the figure are closed, the CTIA capacitor (CS) is not working, the first inverter (inv1) is not working, and the photodiode (PD), the light-sensitive node in the pixel, is connected to the negative input of the comparator (COMP). During the exposure process, the voltage of the photodiode (PD) node gradually decreases and is compared with the positive threshold Vth2 of the comparator (COMP) in real time. When the threshold voltage is reached, the Vpulse node is triggered to flip. The flip signal is connected to the pulse signal latch in the pixel by the second inverter (inv2) and serves as the input signal Latchin of the pulse signal latch. When the latch signal latch arrives, the flip signal is latched in the pulse signal latch, and a 1-bit pulse is output to the column bus when the row select signal Sel arrives. A reset is triggered when the reset signal Rst arrives.

[0035] In addition, after the node Vpulse flips, the flipping moment is recorded by a 3-bit counter, and at the end of the flipping frame, the recorded 3-bit data is output off-chip and combined with the 1-bit pulse data to quantize the light intensity, thereby improving the dynamic range of the pulse pixel and the quantization accuracy under medium and high light intensities.

[0036] like Figure 2 Shown is the pixel operation timing for quantizing high light intensity.

[0037] The Latchout signal is latched to low level after the previous frame trigger pulse, and enters the current frame pre-judgment when the signal SN1 arrives in the subsequent cycle. The pre-judgment logic unit outputs the signal S0 to control the working mode switching logic control unit to select the working mode. Due to the quantification of high light intensity, the working mode switching logic control unit controls the second and ninth MOS switch transistors (corresponding to the two marked SW1_1 switches in Figure 1 ) to be closed, the first and tenth MOS switch transistors (corresponding to the two marked SW3_1 switches in Figure 1 ) to be turned off, the CTIA capacitor to be inactivated, the first inverter (inv1) to be inactivated, and the in-pixel photosensitive node--photodiode (PD) to be connected to the negative input terminal of the comparator (COMP); the seventh MOS switch transistor (SW4) is closed, and the positive terminal of the comparator (COMP) is connected to the working threshold voltage Vth2 when the CTIA capacitor is inactivated.

[0038] After the pre-judgment stage ends, the reset stage is entered, and the reset logic control unit outputs to control the third and eighth two MOS switch transistors (corresponding to the two marked SW1_2 switches in Figure 1 ) to be closed, and the photodiode (PD) to be connected to the negative input terminal of the CTIA capacitor; the fifth MOS switch transistor (SW2) is closed, and the negative terminal of the comparator (COMP) is connected to the reset threshold voltage Vrst.

[0039] When the reset is completed, the third and eighth two MOS switch transistors (corresponding to the two marked SW1_2 switches in Figure 1 ) and the reset threshold voltage Vrst are turned off, the working state of the circuit after the pre-judgment ends is restored, and then the exposure begins.

[0040] During the exposure, the voltage at the photodiode (PD) node gradually decreases and is compared with the working threshold voltage Vth2 at the negative terminal of the comparator (COMP) in real time. If the voltage at the photodiode (PD) in the current frame does not reach Vth2, the output signal Vpulse (periodic pulse signal) at the output terminal of the comparator (COMP) does not flip, and therefore the subsequent pre-judgment logic unit, working mode switching logic control unit and reset logic control unit are not triggered.

[0041] When the latch signal latch arrives, the Vspike signal latched by the in-pixel pulse signal latch 20 is a high level signal, and when the row selection signal Sel arrives, the high level signal latched by the latch is inverted by the inverter and outputs a low level 0 to the column bus.

[0042] Because no pulse is triggered and there is no level flip signal in the current frame, the 3-bit counter does not record the flip position. When the row select signal Sel arrives, the 3-bit counter outputs a code value of 000 to the column bus. If the photodiode (PD) voltage reaches Vth2 in the current frame, the comparator (COMP) output signal Vpulse flips. When the latch signal latch arrives, the pulse signal latch in the pixel latches the Vspike signal low. When the row select signal Sel arrives, the latched low signal is latched through the inverter and outputs a high level 1 to the column bus. The 3-bit counter also records the Vpulse flip moment. When the row select signal Sel arrives, the 3-bit counter outputs a 3-bit code value to the column bus. After the row select signal Sel ends, the low signal latched by the pulse signal latch triggers the pre-judgment, mode switching, and reset for the next frame.

[0043] When the light intensity is low, the second and ninth MOS switch transistors (corresponding to Figure 1 The two switches (marked SW1_1) in the pixel are turned off, the CTIA capacitor operates, the first inverter (inv1) operates, and the photodiode (PD) is connected to the negative input terminal of the CTIA capacitor. The photogenerated charge during exposure is amplified by the CTIA capacitor and compared with the set threshold Vth1 in the comparator (COMP). When the threshold voltage is reached, the Vpulse node is triggered to flip. The flip signal is connected to the pulse signal latch within the pixel via the first inverter (inv1) and the second inverter (inv2). When the latch signal "latch" arrives, the flip signal is latched in the pulse signal latch and a 1-bit pulse is output to the column bus when the row select signal "Sel" arrives. In this operating mode, a 3-bit counter also records the Vpulse flip moment and outputs the recorded 3-bit data off-chip at the end of the flip frame. It is combined with the 1-bit pulse data to quantify the light intensity.

[0044] like Figure 3 Shown is the pixel operation timing for quantizing low light intensity.

[0045] After the previous frame trigger pulse, the Latchout signal is latched to a low level. When the subsequent periodic signal SN1 arrives, the current frame pre-judgment is entered. The pre-judgment logic unit outputs the signal S0 to control the working mode switching logic control unit to select the working mode. Due to the quantized low light intensity, the working mode switching logic control unit controls the second and ninth MOS switch transistors (corresponding to Figure 1 The two SW1_1 switches marked in the figure are turned off, and the first and tenth MOS switch transistors (corresponding to Figure 1The two switches (marked SW3_1) are closed, the CTIA capacitor is connected to the photodiode (PD) in a negative feedback manner, and the first inverter (inv1) and the second inverter (inv2) work together; the sixth MOS switch transistor (SW5) 10 is closed, and the negative terminal of the comparator (COMP) is connected to the threshold value Vth1 when the CTIA capacitor is operating.

[0046] After the pre-judgment phase, the reset phase begins. The reset logic control unit outputs the third and eighth MOS switch transistors (corresponding to Figure 1 The two switches SW1_2 marked in the figure are closed, and the photodiode (PD) is connected to the negative input terminal of the CTIA capacitor; the fifth MOS switch transistor (SW2) 9 is closed, and the negative terminal of the comparator (COMP) is connected to the threshold Vrst of the reset stage.

[0047] When the reset is completed, the third and eighth MOS switch transistors are turned off (corresponding to Figure 1 The two switches SW1_2 (marked in the figure) reset the voltage threshold Vrst, restoring the circuit's operating state after the pre-judgment, and then starting exposure. During exposure, the photodiode (PD) node is clamped at the reset threshold voltage Vrst. The photogenerated charge accumulated in the photodiode (PD) is amplified by the CTIA capacitor, causing the voltage at the CTIA capacitor output to rise. This voltage is then compared in real time with the negative operating threshold voltage Vth1 of the comparator (COMP).

[0048] If the photodiode (PD) voltage within the current frame does not reach the operating threshold voltage Vth1, the comparator (COMP) output signal Vpulse does not flip, and therefore does not trigger the subsequent pre-judgment logic unit, operating mode switching logic control unit, and reset logic control unit. When the latch signal latch arrives, the pixel pulse signal latch latches the Vspike signal as a high level. When the row select signal Sel arrives, the latched high level signal is latched through the inverter and outputs a low level 0 to the column bus.

[0049] Because no pulse is triggered and there is no level flip signal in the current frame, the 3-bit counter does not record the flip position. When the row select signal Sel arrives, the 3-bit counter outputs a code value of 000 to the column bus. If the CTIA capacitor output voltage reaches Vth1 within the current frame, the comparator (COMP) output signal Vpulse flips. When the latch signal latch arrives, the pulse signal latch in the pixel latches the Vspike signal low. When the row select signal Sel arrives, the latched low signal is latched and outputs a high level 1 to the column bus through the inverter. The 3-bit counter also records the Vpulse flip moment. When the row select signal Sel arrives, the 3-bit counter outputs a 3-bit code value to the column bus. After the row select signal Sel ends, the low signal latched by the pulse signal latch triggers the pre-judgment, mode switching, and reset for the next frame.

[0050] In order to improve the dynamic range and quantization accuracy of pixel response, the pixel structure is designed with a pre-judgment stage that adaptively switches the gain of the photosensitivity node according to the light intensity. This stage is entered after the pixel outputs a 1-bit high-level pulse. In this stage, the photodiode (PD) end is connected to the negative input of the comparator (COMP) and compared with the set pre-judgment threshold Vth0 in the comparator (COMP). According to the comparison result, the logic gate is controlled to select the pixel operating mode of the next frame (low light intensity quantization mode or high light intensity quantization mode), and then enters the reset stage.

[0051] Figure 4 This is the working timing diagram of the pixel adaptive gain switching process.

[0052] If the previous frame quantizes low light intensity, the potential of the photodiode (PD) node remains unchanged at the clamp reference voltage Vref during the exposure process. The CTIA capacitor output reaches the threshold value Vth1 set by the comparator (COMP), triggering a flip. At this time, the Vspike signal turns from high to low and is latched by the latch signal at the end of the frame, and the Latchout signal is latched to a low level. Subsequently, when the SN1 signal arrives, SN1 and Latchout jointly control the start of the pre-judgment logic and output S0 as a high-level signal. This signal serves as the input of the working mode switching logic and controls the first, second, sixth, seventh, ninth, and tenth MOS switch transistors together with the Latchin signal. During the control pre-judgment period, the CTIA capacitor does not work, the first inverter 15 does not work, the photodiode (PD) is connected to the negative input terminal of the comparator (COMP), and the potential of the photodiode (PD) is compared with the pre-judgment threshold Vth0. If the comparator (COMP) does not flip during the pre-judgment period, indicating that the light intensity is low, the low light intensity quantization mode is still used. The second and ninth MOS switch transistors (corresponding to Figure 1 The two SW1_1 switches marked in the figure are turned off, and the first and tenth MOS switch transistors (corresponding to Figure 1 The two SW3_1 switches marked in the figure are closed, and the photodiode (PD) is connected to the negative terminal of the CTIA capacitor. Figure 3 Working sequence; if the comparator (COMP) flips during the pre-judgment period, it indicates that the light intensity is high, and the high light intensity working mode is switched. The second and ninth MOS switch transistors (SW1_1) are closed, the first and tenth MOS switch transistors (SW3_1) are turned off, and the photodiode (PD) is connected to the negative input terminal of the comparator (COMP). Continue Figure 2 The embodiment of the present application adds a CTIA capacitor to the photodiode (PD) node based on the traditional pulse structure. The voltage signal V converted by the photodiode (PD) sensing the light intensity is PD After being amplified by the CTIA capacitor gain, the signal enters the comparator (COMP) input and is compared with the set threshold Vth1, thereby increasing the photodiode (PD) node conversion gain. This improves the perception sensitivity when quantizing low-light-intensity scenes and ensures responsiveness to high-speed scenes under low-light-intensity conditions.

[0053] In addition, this embodiment of the present application incorporates a pulse-width modulation (PWM) pixel structure, incorporating a global clock (CLK) and a 3-bit counter within the pixel. When the comparator (COMP) triggers a flip, the 3-bit counter records the position within the frame at that moment and outputs the 3-bit code value to the column bus upon the arrival of the row select signal (SEL). This improves the quantization accuracy of the pulse pixel and the dynamic range of its response to high light intensities, while maintaining a constant frame rate.

[0054] In an embodiment of the present application, the pixel structure introduces a pre-judgment logic unit after the trigger pulse. The pre-judgment logic unit controls the pixel to adaptively judge the current light intensity and select the working gain of the next frame. It can simultaneously achieve high speed and high gain under low light intensity and high precision and large dynamic under high light intensity, effectively improving the dynamic range of the pixel.

[0055] In summary, the adaptive light intensity pulse pixel structure of the embodiment of the present invention adds a gain conversion structure to the light intensity sensing node, which can adaptively adjust the conversion gain of the photosensitive node, and at the same time add an adaptive light intensity pre-judgment structure within the pixel, thereby improving the sensitivity of the pixel in low light intensity scenes and enhancing the response to low light intensity and high-speed scenes. At the same time, it combines the working modes of pulse width modulation (PWM) and pulse frequency modulation (PFM), introduces a global clock and counter, expands the dynamic range of high light intensity, and can respond to high-speed scenes.

[0056] According to a second aspect of the embodiments of the present invention, an image sensor is provided, comprising the above-mentioned high-speed and wide dynamic pulse pixel structure with adaptive light intensity.

[0057] In a third aspect, the present application provides an electronic device comprising the image sensor.

[0058] The foregoing merely illustrates the principles of the application and various embodiments are now described with reference to the drawings. The embodiments described with reference to the drawings are illustrative of the application and are not intended to limit the scope of the application as defined by the following claims as properly interpreted under the doctrine of equivalents. It will thus be appreciated that those skilled in the art will be able to devise numerous

[0059] Accordingly, the embodiments are to be considered as illustrative and not restrictive, and the scope of the application is not to be determined by the above description but only by the appended claims, and all changes which come within the meaning and range of equivalents are intended to be embraced therein.

[0060] Furthermore, it should be appreciated that a single independent technical solution is not necessarily contained in each embodiment, and the description of the specification is only for the sake of clarity, and the skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be combined appropriately to form other embodiments which can be understood by the skilled in the art.

Claims

1. High-speed and wide dynamic pulse pixel structure with adaptive light intensity, characterized by: The device comprises a photodiode, multiple MOS switching transistors, a capacitor transimpedance amplifier, a CTIA capacitor, a comparator, multiple inverters, a pulse signal latch, a 3-bit counter, an operating mode switching logic control unit, a reset logic control unit, and a pre-judgment logic unit; one end of a first MOS switching transistor is connected to a non-grounded end of the photodiode and the other end is connected to a negative input end of the capacitor transimpedance amplifier; one end of a parallel circuit structure of a second MOS switching transistor, a third MOS switching transistor, and a CTIA capacitor is connected to a non-grounded end of the photodiode and the other end is connected to an output end of the CTIA capacitor; a positive input end of the capacitor transimpedance amplifier is connected to a reset voltage signal Vrst, and an output end is connected to a negative input end of the comparator; One end of the fourth MOS switch transistor, the fifth MOS switch transistor, the sixth MOS switch transistor, and the seventh MOS switch transistor are commonly connected to the positive input terminal of the comparator, and the other ends are respectively connected to the pre-judgment working threshold voltage Vth0, the reset voltage signal Vrst, the first working threshold voltage Vth1, and the second working threshold voltage Vth2; The comparator output is connected to one end of the parallel circuit of the eighth MOS switch transistor and the ninth MOS switch transistor and one end of the tenth MOS switch transistor. The other end of the tenth MOS switch transistor is connected to the input of the first inverter. The other end of the parallel circuit of the eighth MOS switch transistor and the ninth MOS switch transistor is connected to the output of the first inverter and the input of the second inverter. The output of the second inverter is connected to the input of the pulse signal latch and the input of the 3-bit counter. The output of the 3-bit counter is connected to the input of the third inverter and is input with the global clock signal clk. The input of the pulse signal latch clk is connected to the latch signal latch. The output of the pulse signal latch Q is connected to the input of the fourth inverter and outputs a latch output signal Latchout. The row select signal Sel is respectively input to the third inverter and the fourth inverter, and the outputs are connected to the column bus.

2. The high-speed, wide dynamic pulse pixel structure with adaptive light intensity according to claim 1, characterized in that: The working mode switching logic control unit is used to control the output of multiple working mode switching control signals to correspondingly control the first MOS switch transistor, the second MOS switch transistor, the sixth MOS switch transistor, the seventh MOS switch transistor, the ninth MOS switch transistor, and the tenth MOS switch transistor to switch the working mode.

3. The high-speed, wide dynamic pulse pixel structure with adaptive light intensity according to claim 2, characterized in that: The signal input end of the working mode switching logic control unit is connected to the output signal S0 of the pre-judgment logic unit and the latch input signal Latchin, and controls the output of multiple working mode switching control signals according to the output signal S0 of the pre-judgment logic unit and the latch input signal Latchin.

4. The high-speed, wide dynamic pulse pixel structure with adaptive light intensity according to claim 3, characterized in that: The reset logic control unit is used to control the output reset control signal, which correspondingly controls the reset of the third MOS switch transistor, the eighth MOS transistor switch tube and the fifth MOS switch transistor; the input end of the reset logic control unit is connected to the output end of the pulse signal latch and is also connected to the reset signal Rst.

5. The high-speed, wide dynamic pulse pixel structure with adaptive light intensity according to claim 4, characterized in that: The pre-judgment logic unit is used to adaptively switch the photosensitive node gain according to the light intensity. The input end of the pre-judgment logic unit is connected to the pre-judgment signal SN1 and the output signal Latchout of the pulse signal latch.

6. The high-speed, wide dynamic pulse pixel structure with adaptive light intensity according to any one of claims 1 to 5, characterized in that: When quantizing high light intensity, the second MOS switch transistor and the ninth MOS switch transistor are closed, the capacitive transimpedance amplifier does not work, the CTIA capacitor does not work, the first inverter does not work, and the photodiode in the pixel is connected to the negative input terminal of the comparator; During the exposure process, the voltage at the photodiode node gradually decreases and is compared in real time with the second operating threshold voltage Vth2 of the comparator. When the threshold voltage is reached, the Vpulse node is triggered to flip. The flip signal is connected to the pulse signal latch in the pixel by the second inverter. When the latch signal latch arrives, the flip signal is latched in the pulse signal latch. When the row select signal Sel arrives, a 1-bit pulse is output to the column bus, and a reset is triggered when the reset signal Rst arrives. After Vpulse flips, the flip moment is recorded by a 3-bit counter. When the flip frame ends, the recorded 3-bit data is output outside the chip and combined with the 1-bit pulse data to quantify the light intensity.

7. The high-speed, wide dynamic pulse pixel structure with adaptive light intensity according to claim 6, characterized in that: When quantizing low light intensity, the second and ninth MOS switching transistors are turned off, the CTIA capacitor operates, the first inverter operates, and the photodiode is connected to the negative input terminal of the CTIA capacitor. The photogenerated charge during exposure is amplified by the CTIA capacitor gain and compared with the first operating threshold voltage Vth1 in the comparator. When the threshold voltage is reached, the Vpulse node is triggered to flip. The flip signal is connected to the pulse signal latch within the pixel via the first and second inverters. When the latch signal latch arrives, the flip signal is latched in the pulse signal latch, and a 1-bit pulse is output to the column bus when the select signal Sel arrives. In this operating mode, a 3-bit counter records the Vpulse flip moment. At the end of the flip frame, the recorded 3-bit data is output off-chip and combined with the 1-bit pulse data to quantize the light intensity.

8. The high-speed, wide dynamic pulse pixel structure with adaptive light intensity according to claim 7, characterized in that: The pre-judgment logic unit enters the pre-judgment processing process after the pixel outputs a 1-bit high-level pulse. During the pre-judgment processing, the photodiode end is connected to the negative input end of the comparator, and is compared with the set pre-judgment working threshold voltage Vth0 in the comparator. According to the comparison result, the logic gate is controlled to select the pixel working mode of the next frame, and then the reset stage is entered.

9. An image sensor, characterized in that A high-speed, wide dynamic pulse pixel structure with adaptive light intensity comprising the structure described in any one of claims 1 to 8.

10. An electronic device, characterized in that The image sensor according to claim 9 is included.

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