Single wire multi-device daisy chain addressing system

Abstract

A single-wire multi-device serial addressing system is disclosed. In the multi-device serial addressing system, a plurality of devices are arranged in series and connected to each other, and a first and a last device are connected to a controller. The first device addresses the first device based on a device identification address packet from the controller, adjusts the device identification address packet, and outputs the adjusted device identification address packet to the next device. Each device other than the first device addresses based on the device identification address packet received from the previous device. Each device other than the first and the last device adjusts the device identification address packet received from the previous device, and outputs the adjusted device identification address packet to the next device. The last device outputs the device identification address packet received from the previous device to the controller.

Description

TECHNICAL FIELD

[0001] The present invention relates to a multi-device cascading system, in particular, to a single-wire multi-device cascading addressing system. BACKGROUND

[0002] In a conventional multi-device cascading system, a plurality of devices are arranged in sequence and cascaded with each other. A controller needs to transmit frequency signals to the plurality of devices through additional transmission lines to control the operation time of the plurality of devices, which increases the cost of additional lines. In applications such as driving of a plurality of devices with a plurality of light emitting diodes (LEDs), the data transmitted between the plurality of devices includes command data and corresponding device data of each device. When the command data is transmitted between the plurality of devices, each device needs to transmit corresponding command data, so the plurality of devices collectively needs to transmit the same plurality of command data, resulting in unnecessary waste of bandwidth. SUMMARY

[0003] The present invention provides a single-wire multi-device cascading addressing system to solve the problems in the prior art. The system includes a controller and a plurality of devices. The plurality of devices are arranged in sequence. The first device in the sequence is defined as a first device, and the last device in the sequence is defined as a last device. The input terminal of the first device is connected to the output terminal of the controller. The input terminal of each device other than the first device is connected to the output terminal of the previous device. The output terminal of the last device is connected to the input terminal of the controller. The input terminal of the first device receives an addressing instruction packet from the output terminal of the controller. The first device sets a unique identification code of the first device according to a corresponding device identification address in the addressing instruction packet received from the controller. The first device adjusts the corresponding device identification address in the addressing instruction packet and outputs the adjusted addressing instruction packet to the next device. The input terminal of each device other than the first device receives the addressing instruction packet from the output terminal of the previous device, and each device other than the first device determines its unique identification code according to the corresponding device identification address in the received addressing instruction packet. Each device other than the first device and the last device adjusts the corresponding device identification address in the addressing instruction packet received from the previous device and outputs the adjusted addressing instruction packet to the next device. The last device directly outputs the addressing instruction packet received from the previous device to the controller or adjusts the addressing instruction packet and outputs the adjusted addressing instruction packet to the controller.

[0004] In an embodiment, the controller compares the addressing instruction packet outputted by the controller to the addressing instruction packet received by the controller from the last device to determine the respective device identification address of each of the plurality of devices and the arrangement order and number of the plurality of devices.

[0005] In an embodiment, the output of each of the devices of the controller is in an off state when the addressing instruction packet is not being outputted to the next device.

[0006] In an embodiment, the output of each of the devices other than the last device is switched from an off state to an on state to output the adjusted addressing instruction packet to the input of the next device after the respective device identification address in the addressing instruction packet is adjusted by each of the devices other than the last device.

[0007] In an embodiment, the output of the last device is switched from an off state to an on state to output the adjusted addressing instruction packet to the input of the controller after the respective device identification address in the addressing instruction packet is adjusted by the last device. The outputs of the plurality of devices are sequentially switched from an off state to an on state according to the arrangement order of the plurality of devices.

[0008] In an embodiment, each of the devices sets its own unique identification code to be the same as the respective device identification address in the received addressing instruction packet.

[0009] In an embodiment, each of the devices counts up the respective device identification address in the received addressing instruction packet by one to increase the respective device identification address by one, and sets the counted respective device identification address as its own unique identification code.

[0010] In an embodiment, the addressing instruction packet received by each of the devices has N bit values, and M bit values of the N bit values in the addressing instruction packet represent the respective device identification address of the device, wherein N and M are suitable integer values.

[0011] In an embodiment, the first device adjusts the M bit values in the addressing instruction packet received from the controller that represent the unique identification code of the first device, and outputs the adjusted addressing instruction packet to the next device.

[0012] In an embodiment, each of the devices other than the first device counts up the M-bit value representing its own unique identification code in the addressing instruction packet received from the previous device. The first device and each of the devices other than the last device outputs the addressing instruction packet with the counted M-bit value to the next device. The last device outputs the addressing instruction packet with the counted M-bit value to the controller.

[0013] In an embodiment, the first device counts up the M-bit value representing the first device in the addressing instruction packet received from the controller to increase the size of the M-bit value of the unique identification code of the first device, and outputs the counted addressing instruction packet to the next device.

[0014] In an embodiment, each of the devices other than the first device counts up the M-bit value representing its own unique identification code in the addressing instruction packet received from the previous device. The first device and each of the devices other than the last device outputs the addressing instruction packet with the counted M-bit value to the next device. The last device outputs the addressing instruction packet with the counted M-bit value to the controller.

[0015] In an embodiment, the addressing instruction packet received by each of the devices has a pulse width modulation signal. The duty cycles of some of the waveforms of the pulse width modulation signal respectively represent the M-bit values of the address identifying the corresponding device. The duty cycle of each of the waveforms of the pulse width modulation signal is not greater than a first duty cycle representing the bit value "0". The duty cycle of each of the waveforms of the pulse width modulation signal is not less than a second duty cycle representing the bit value "1", where M is a suitable integer value.

[0016] In an embodiment, the addressing instruction packet received by each of the devices has a pulse width modulation signal. The duty cycles of some of the waveforms of the pulse width modulation signal respectively represent the M-bit values of the address identifying the corresponding device. The duty cycles of each of the waveforms of the pulse width modulation signal fall within a first range of duty cycles representing the bit value "0". The duty cycles of each of the waveforms of the pulse width modulation signal fall within a second range of duty cycles representing the bit value "1", where M is a suitable integer value.

[0017] In an embodiment, the addressing instruction packet received by each of the devices has a pulse width modulation signal. Part of the waveforms of the pulse width modulation signal have duty cycles representing M bit values of the respective device identification address. The duty cycles of each of the waveforms of the pulse width modulation signal equal a first duty cycle representing the bit value "0". The duty cycles of each of the waveforms of the pulse width modulation signal equal a second duty cycle representing the bit value "1", where M is a suitable integer value.

[0018] In an embodiment, each of the devices has a default identification code prior to receiving the addressing instruction packet.

[0019] wherein each of the devices replaces the default identification code with the respective device identification address in the addressing instruction packet as its own unique identification code after receiving the addressing instruction packet, thereby accomplishing the resetting of the unique identification code of each of the devices.

[0020] In an embodiment, each of the devices receives an identification code clearing instruction in the addressing instruction packet in addition to the respective device identification address. Wherein each of the devices clears the default identification code of each of the devices from the addressing instruction packet according to the identification code clearing instruction after receiving the addressing instruction packet, sets the respective device identification address in the addressing instruction packet as the unique identification code of each of the devices, thereby accomplishing the resetting of the unique identification code of each of the devices.

[0021] In an embodiment, the addressing instruction packet received by each of the devices has N bit values. P of the N bit values in the addressing instruction packet represent the identification code clearing instruction of each of the devices, where N and P are suitable integer values.

[0022] In an embodiment, the addressing instruction packet has a pulse width modulation signal. Part of the waveforms of the pulse width modulation signal have duty cycles representing the P bit values of the identification code clearing instruction. The duty cycles of each of the waveforms of the pulse width modulation signal fall within a first duty cycle range representing the bit value "0". The duty cycles of each of the waveforms of the pulse width modulation signal fall within a second duty cycle range representing the bit value "1".

[0023] As mentioned above, the present application provides a single-wire multi-device serial addressing system. The present application provides a single-wire multi-device serial addressing system. The single-wire multi-device serial addressing system of the present application does not set up multiple frequency signal transmission lines between multiple devices and a controller, but only uses the original data transmission line, so that each of the multiple devices serially connected to each other can be effectively addressed under the condition of saving line cost. After effective addressing, the controller can transmit a packet to give instructions to the multiple devices after addressing the multiple devices, and each device can operate according to the instructions given by the controller.

[0024] In order to enable a further understanding of the features and technical contents of the present application, please refer to the following detailed description of the present application and the accompanying drawings. However, the accompanying drawings provided are only for reference and illustration, and are not intended to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A block diagram of a single-wire multi-device serial addressing system of an embodiment of the present application.

[0026] Figure 2 A schematic diagram of multiple devices of a single-wire multi-device serial addressing system of an embodiment of the present application, all of which have not been addressed.

[0027] Figure 3 A schematic diagram of multiple devices of a single-wire multi-device serial addressing system of an embodiment of the present application, only the first of which has been addressed.

[0028] Figure 4 A schematic diagram of an addressing instruction packet when only the first of multiple devices of a single-wire multi-device serial addressing system of an embodiment of the present application has been addressed.

[0029] Figure 5 A schematic diagram of multiple devices of a single-wire multi-device serial addressing system of an embodiment of the present application, the first and second of which have been addressed.

[0030] Figure 6 A schematic diagram of an addressing instruction packet when the first and second of multiple devices of a single-wire multi-device serial addressing system of an embodiment of the present application have been addressed.

[0031] Figure 7 A schematic diagram of multiple devices of a single-wire multi-device serial addressing system of an embodiment of the present application, all of which have been addressed.

[0032] Figure 8 A schematic diagram of multiple bit values in an addressing instruction packet transmitted between multiple devices of a single-wire multi-device serial addressing system of an embodiment of the present application.

[0033] Figure 9A timing diagram showing the duty cycle of a pulse width modulation signal representing a corresponding device identification address in an addressing instruction packet transmitted between devices of a single-wire multi-device serial addressing system according to embodiments of the present invention. DETAILED DESCRIPTION

[0034] The present invention is described herein with reference to specific embodiments thereof which are presented as examples in order to provide a thorough description for those skilled in the art to understand the advantages and effects of the present invention. The present invention can be carried out or applied by other different embodiments, and the details in the present specification can be modified and changed in various ways based on different viewpoints and applications without departing from the spirit and scope of the present invention. In addition, the drawings of the present invention are merely simple schematic illustrations and not actual size depictions, and it is hereby declared in advance. The following embodiments will further describe the related technical contents of the present invention in detail, but the disclosed contents are not intended to limit the protection scope of the present invention. In addition, the term "or" used herein can include a combination of any one or more of the associated listed items as possible.

[0035] Please refer to Figures 1 to 3 , Figure 5 and Figure 7 , wherein Figure 2 is a schematic diagram of a single-wire multi-device serial addressing system according to embodiments of the present invention in which none of the devices have been addressed, Figure 3 is a schematic diagram of a single-wire multi-device serial addressing system according to embodiments of the present invention in which only the first device has been addressed, Figure 5 is a schematic diagram of a single-wire multi-device serial addressing system according to embodiments of the present invention in which the first and second devices have been addressed, and Figure 7 is a schematic diagram of a single-wire multi-device serial addressing system according to embodiments of the present invention in which all of the devices have been addressed.

[0036] A single-wire multi-device serial addressing system according to embodiments of the present invention includes a plurality of devices (such as, but not limited to, a plurality of devices 101-103 as shown in Figure 1 ) and a controller 900.

[0037] For example, each or any one or more of the plurality of devices included in a single-wire multi-device serial addressing system according to embodiments of the present invention can be a light emitting device, each of which can include one or more light emitting components such as light emitting diodes, but the present invention is not limited thereto. It should be understood that the number and type of devices and the number of (light emitting) components within each device can be adjusted according to actual needs.

[0038] As shown in Figure 1As shown, the plurality of devices 101-103 are arranged in sequence and are connected in series. For the convenience of description, the first device 101 in the plurality of devices 101-103 is defined as the first device 101, and the last device 103 in the plurality of devices 101-103 is defined as the last device 103.

[0039] The input end DI of the first device 101 is connected to the output end of the controller 900. The input end DI of the device 102 is connected to the output end DO of the first device 101, and the input end DI of the last device 103 is connected to the output end DO of the device 102. The output end DO of the last device 103 is connected to the input end of the controller 900.

[0040] As shown in FIG. 1, the plurality of devices 101-103 are not yet addressed. At this time, the unique identification code ID of each device 101-103 or the corresponding device address can be internally set as a default identification code FF. The default identification code FF of each of the plurality of devices 101-103 can be different from each other. Figure 1 Figure 2 As shown in FIG. 1, the output end DO of each device 101-103 that is not outputting an address instruction packet to the next device 101-103 or the controller 900 can be in an off state.

[0041] As shown in FIG. 1, the output end DO of each device 101-103 that is not outputting an address instruction packet to the next device 101-103 or the controller 900 can be in an off state. Figure 2

[0042] If the controller 900 wants to address the plurality of devices 101-103, the output end of the controller 900 can output an address instruction packet to the input end DI of the first device 101.

[0043] When the input end DI of the first device 101 receives an address instruction packet from the output end of the controller 900, the first device 101 sets the unique identification code ID of the first device 101 according to a corresponding device identification address in the address instruction packet received from the controller 900.

[0044] In detail, the first device 101 can set the unique identification code ID of the first device 101 to be the same as the corresponding device identification address in the address instruction packet received from the controller 900. Alternatively, the first device 101 counts up the corresponding device identification address in the address instruction packet received from the controller 900 once to increase the corresponding device identification address by one, and sets the counted corresponding device identification address as the unique identification code ID of the first device 101.

[0045] The first device 101 can adjust the corresponding device identification address in the address instruction packet received from the controller 900. After the first device 101 adjusts the corresponding device identification address in the address instruction packet, the output end DO of the first device 101 is connected to the input end DI of the device 102. Figures 2 to 3 ​​The first device 101 switches from the closed state to the open state to output the adjusted addressing instruction packet with the counted corresponding device identification address "02" to the input end DI of the next device 102.

[0046] For example, the first device 101 replaces a default identification code FF in the first device 101 with a corresponding device identification address "00" in the addressing instruction packet received from the controller 900 as the unique identification code ID of the first device 101, thus completing the resetting of the unique identification code ID of the first device 101. Figure 3 The "01" shown is substituted for Figure 2 The default identification code FF in the first device 101 shown is set as the unique identification code ID of the first device 101, thus completing the resetting of the unique identification code ID of the first device 101. In addition, the first device 101 can count up the corresponding device identification address in the addressing instruction packet received from the controller 900 once to increase the value of the corresponding device identification address by one, for example, the corresponding device identification address value +1 is formed as Figure 5 The "02" shown is output to the next device 102 as an addressing instruction packet with the counted corresponding device identification address.

[0047] Alternatively, the first device 101 counts up the corresponding device identification address "00" in the addressing instruction packet received from the controller 900 once to increase the value of the corresponding device identification address by one, for example, the corresponding device identification address value "00" +1 is formed as "01", and the counted corresponding device identification address "01" is set as the unique identification code ID of the first device 101. Further, the first device 101 counts up the unique identification code ID of the first device 101 once to increase the value of the corresponding device identification address by one, for example Figure 2 The "02" shown is output to the next device 102 as an addressing instruction packet with the counted corresponding device identification address "02". Figure 5 The "02" shown is output to the next device 102 as an addressing instruction packet with the counted corresponding device identification address "02".

[0048] When the input end DI of the device 102, which is the second device in the sequence among the plurality of devices 101 to 103, receives an addressing instruction packet from the output end DO of the first device 101, the device 102 sets the unique identification code ID of the device 102 according to a corresponding device identification address in the addressing instruction packet received from the first device 101.

[0049] For example, the device 102 replaces a default identification code FF in the device 102 with a corresponding device identification address "02" in the addressing instruction packet received from the first device 101 as the unique identification code ID of the device 102, thus completing the resetting of the unique identification code ID of the device 102. Figure 5 The "02" shown is output to the next device 102 as an addressing instruction packet with the counted corresponding device identification address "02".

[0050] The device 102 can adjust a corresponding device identification address in the addressing instruction packet received from the previous device 101. After the device 102 adjusts the corresponding device identification address in the addressing instruction packet received from the previous device 101, the output terminal DO of the device 102 switches from the off state to the on state, as shown in FIG. 3, to output the adjusted addressing instruction packet to the input terminal DI of the next device 103. Figures 3 to 5

[0051] For example, the device 102 counts up the unique identification code ID of the device 102 once to increase the value of the corresponding device identification address by one, such as "02" + 1 = "03", and outputs an addressing instruction packet with the counted corresponding device identification address "03" to the next device 103.

[0052] When the input terminal DI of the last device 103 in the plurality of devices 101-103 receives an addressing instruction packet from the output terminal DO of the previous device 102, the last device 103 sets the unique identification code ID of the last device 103 according to a corresponding device identification address in the addressing instruction packet received from the previous device 102.

[0053] For example, the last device 103 replaces a default identification code FF with a corresponding device identification address "03" in the addressing instruction packet received from the previous device 102, as shown in FIG. 4, as the unique identification code ID of the last device 103, thus completing the resetting of the unique identification code ID of the last device 103. Figure 7

[0054] After the last device 103 sets the unique identification code ID of the last device 103, the output terminal DO of the last device 103 can switch from the off state to the on state, as shown in FIG. 5, to directly transmit the addressing instruction packet received from the device 102 to the controller 900. Alternatively, the last device 103 adjusts the addressing instruction packet received from the device 102, and the output terminal DO of the last device 103 can switch from the off state to the on state, as shown in FIG. 6, to output the adjusted addressing instruction packet to the input terminal DI of the controller 900. Figures 5 to 7 Figures 5 to 7

[0055] The output terminals DO of the plurality of devices 101-103 can sequentially switch from the off state to the on state in the order of the plurality of devices 101-103, as described above, and the plurality of devices 101-103 sequentially complete the addressing in the order of the plurality of devices 101-103.

[0056] ​​​​The controller 900 compares the value of the corresponding device identification address of the addressing instruction packet outputted by the controller 900 to the first device 101 with the value of the corresponding device identification address of the addressing instruction packet received by the controller 900 from the last device 103, so as to determine the corresponding device identification address of each of the devices 101-103 and the arrangement order and number of the devices 101-103.

[0057] Referring to Figures 1 to 7 wherein Figure 4 Fig. 1 is a schematic diagram of an addressing instruction packet when only the first device of the single-wire multi-device serial addressing system has been addressed, according to an embodiment of the present application, Figure 6 Fig. 2 is a schematic diagram of an addressing instruction packet when the first device and the second device of the single-wire multi-device serial addressing system have been addressed, according to an embodiment of the present application.

[0058] The input terminal DI of the first device 101 receives a corresponding device identification address in addition to the unique identification code ID(l) of the first device 101 in the addressing instruction packet received from the controller 900, as shown in Figure 4 Fig. 1, and the input terminal DI of the first device 101 receives a corresponding device identification address in addition to the unique identification code ID(l) of the first device 101 in the addressing instruction packet received from the controller 900, as shown in

[0059] When the first device 101 receives an addressing instruction packet from the controller 900 with a identification code clearing instruction, the first device 101 clears a default identification code FF of the first device 101 from the addressing instruction packet according to the identification code clearing instruction. The first device 101 sets a corresponding device identification address (e.g., the value after counting up as described above) in the addressing instruction packet as the unique identification code ID(l) of the first device 101, so as to complete resetting of the unique identification code ID(l) of the first device 101.

[0060] The output terminal DO of the first device 101 outputs a corresponding device identification address in addition to the unique identification code ID(2) of the next device 102 in the addressing instruction packet outputted to the input terminal DI of the next device 102, as shown in Figure 4 Fig. 2, and the output terminal DO of the first device 101 outputs a corresponding device identification address in addition to the unique identification code ID(2) of the next device 102 in the addressing instruction packet outputted to the input terminal DI of the next device 102, as shown in

[0061] When the device 102 receives an addressing instruction packet from the first device 101 with a identification code clearing instruction, the device 102 clears a default identification code FF of the device 102 from the addressing instruction packet according to the identification code clearing instruction. The device 102 sets a corresponding device identification address (e.g., the value after counting up as described above) in the addressing instruction packet as the unique identification code ID(2) of the device 102, so as to complete resetting of the unique identification code ID(2) of the device 102.

[0062] The output DO of device 102 is output to the input DI of the next device 103 in an addressing instruction packet, such as... Figure 6 In addition to a corresponding device identification address having a unique identification code ID (3) representing the next device 103, the device may also have an identification code clearing instruction CMD.

[0063] When device 103 receives an addressing instruction packet from the previous device 102 containing an identifier clearing instruction, device 103 clears a default identifier FF from the addressing instruction packet according to this identifier clearing instruction. Device 103 sets a corresponding device identification address (such as the value after counting up as described above) in this addressing instruction packet as the unique identifier ID (3) of device 103, thus completing the reset of the unique identifier ID (3) of device 103.

[0064] Please see Figures 1 to 8 ,in Figure 8 This is a schematic diagram of multiple bit values ​​in an addressing instruction packet transmitted between multiple devices in a single-wire multi-device serial addressing system according to an embodiment of the present invention.

[0065] like Figure 7 The addressing instruction packet received by each of the plurality of devices 101 to 103 shown may have N bit values, for example, but not limited to, such as Figure 8 The bit values ​​shown are b0 to b19, wherein M of the N bit values ​​in the addressing instruction packet represent a corresponding device identification address of each of the plurality of devices 101 to 103, where N and M are appropriate integer values.

[0066] The first device 101 can set a unique identification code ID (1) based on M of the N bit values ​​in an addressing instruction packet received from the controller 900. In addition, the first device 101 adjusts M of the N bit values ​​in an addressing instruction packet received from the controller 900 and outputs the addressing instruction packet with the adjusted M bit values ​​to the next device 102.

[0067] For example, the first device 101 sets its unique identifier ID(1) (e.g., bit value "01") to be the same as a corresponding device identification address (e.g., ...) within an addressing instruction packet received from the controller 900. Figure 8 (The bit value "01" is shown). In addition, the first device 101 counts up one time from a corresponding device identification address (e.g., bit value "01") in an addressing instruction packet received from the controller 900 to increment the value of the corresponding device identification address by one time, and outputs an addressing instruction packet with a counted corresponding device identification address (e.g., bit value "10") to the next device 102.

[0068] Alternatively, the first device 101 counts up the corresponding device identification address (e.g., bit value "00") in an addressing instruction packet received from the controller 900 by one to increase the value of the corresponding device identification address by one, sets the corresponding device identification address (e.g., bit value "01") after the counting as the unique identification code ID(l) of the first device 101. Further, the first device 101 counts up the unique identification code ID(l) of the first device 101 by one to increase the value of the corresponding device identification address by one, for example, as shown in the table below. Figure 8 Further, the first device 101 counts up the unique identification code ID(l) of the first device 101 by one to increase the value of the corresponding device identification address by one, for example, as shown in the table below. Figure 2 Further, the first device 101 counts up the unique identification code ID(l) of the first device 101 by one to increase the value of the corresponding device identification address by one, for example, as shown in the table below.

[0069] The second device 102 in order among the plurality of devices 101 to 103 sets the unique identification code ID(2) of the device 102 in accordance with the M bit values among the N bit values in an addressing instruction packet received from the first device 101. In addition, the device 102 adjusts the M bit values among the N bit values in an addressing instruction packet received from the first device 101, and outputs the addressing instruction packet having the adjusted M bit values to the next device 103.

[0070] For example, the device 102 sets the unique identification code ID(2) of the device 102 to be the same as a corresponding device identification address (e.g., bit value "10") in an addressing instruction packet received from the first device 101. In addition, the device 102 counts up the corresponding device identification address in an addressing instruction packet received from the first device 101 by one to increase the value of the corresponding device identification address by one, and outputs an addressing instruction packet having the corresponding device identification address (e.g., bit value "11") after the counting to the next device 103.

[0071] The third device 103 in order among the plurality of devices 101 to 103 sets the unique identification code ID(3) of the device 103 in accordance with the M bit values among the N bit values in an addressing instruction packet received from the second device 102 in order among the plurality of devices 101 to 103. For example, the device 103 sets the unique identification code ID(3) of the device 103 to be the same as a corresponding device identification address (e.g., bit value "11") in an addressing instruction packet received from the previous device 102.

[0072] The device 103 adjusts M bit values among N bit values in an addressing instruction packet received from the first device 101, and outputs the addressing instruction packet with the adjusted M bit values to the controller 900. In practice, the device 103 can also not adjust M bit values among N bit values in an addressing instruction packet received from the device 102, and directly output the addressing instruction packet received from the device 102 to the controller 900.

[0073] The controller 900 can compare a corresponding device identification address bit value of an addressing instruction packet output by the controller 900 to the first device 101 with a corresponding device identification address bit value of an addressing instruction packet received by the controller 900 from the last device 103, to determine the corresponding device identification address of each of the devices 101-103, and the arrangement order and number of the devices 101-103. In this way, the devices 101-103 complete the addressing.

[0074] After the above-mentioned addressing operation is performed, the controller 900 can output a control instruction packet with a plurality of bit values representing unique identification codes ID of the devices 101-103, operation control data, and control instructions, and sequentially transmit the control instruction packet to the devices 101-103. Each of the devices 101-103 can identify the plurality of bit values in the received control instruction packet, to determine the control instructions and operation control data in the control instruction packet, and the like, which are used to control the operation of which device among the devices 101-103. Each of the devices 101-103 operates according to the control instructions and operation control data in the control instruction packet used to control its own operation.

[0075] Please refer to Figures 1 to 9 , wherein Figure 9 is a schematic diagram of the duty cycle of a pulse width modulation signal representing a corresponding device identification address in an addressing instruction packet transmitted between the devices of the single-wire multi-device serial addressing system according to an embodiment of the present application.

[0076] The addressing instruction packet received by each of the devices 101-103 can have a pulse width modulation signal with a plurality of waveforms. The duty cycles of at least some of the plurality of waveforms of the pulse width modulation signal represent M bit values of a corresponding device identification address, respectively.

[0077] The duty cycles of other ones of the plurality of waveforms of the pulse width modulation signal in the addressing instruction packet received by each of the devices 101-103 can represent P bit values of an identification code clearing instruction, respectively.

[0078] For example, as Figure 9As shown, the duty cycle of each waveform of the pulse width modulation signal not greater than a first duty cycle (for example, but not limited to 25%) represents the bit value "0", and the duty cycle of each waveform of the pulse width modulation signal not less than a second duty cycle (for example, but not limited to 75%) represents the bit value "1".

[0079] Alternatively, the duty cycle of each waveform of the pulse width modulation signal equal to a first duty cycle represents the bit value "0", and the duty cycle of each waveform of the pulse width modulation signal not less than a second duty cycle represents the bit value "1".

[0080] Alternatively, the duty cycle of each waveform of the pulse width modulation signal falls within a first duty cycle range represents the bit value "0", and the duty cycle of each waveform of the pulse width modulation signal not less than a second duty cycle range represents the bit value "1".

[0081] In summary, the present application provides a single-wire multi-device serial addressing system. The single-wire multi-device serial addressing system of the present application does not set up multiple frequency signal transmission lines between multiple devices and a controller, but only uses the original data transmission line, so that under the condition of saving line cost, each of the multiple devices serially connected to each other can still be effectively addressed. After effective addressing, the controller can transmit a packet to issue an instruction to the multiple devices after addressing the multiple devices, and each device can operate according to the instruction issued by the controller to itself.

[0082] The above disclosed content is only the preferred feasible embodiment of the present application, and is not limited to the claims of the present application, so that any equivalent technical changes made according to the content of the specification and drawings of the present application are included in the claims of the present application.

Claims

1. A single-wire multi-device serial addressing system, characterized in that, The single-wire multi-device serial addressing system includes: Controller; and Multiple devices are arranged in sequence. The device that is first in the sequence is defined as the first device, and the device that is last in the sequence is defined as the last device. The input terminal of the first device is connected to the output terminal of the controller. The input terminals of each of the other devices are connected to the output terminal of the previous device. The output terminal of the last device is connected to the input terminal of the controller. Wherein, the input terminal of the first device receives an addressing instruction packet from the output terminal of the controller, the first device sets a unique identification code for the first device based on a corresponding device identification address in the addressing instruction packet received from the controller, the first device adjusts the corresponding device identification address in the addressing instruction packet, and outputs the adjusted addressing instruction packet to the next device. In this process, the input terminals of each of the other devices besides the first device receive the addressing instruction packet from the output terminal of the previous device, and each of the other devices besides the first device determines its own unique identification code based on the corresponding device identification address in the received addressing instruction packet. Among them, each of the devices other than the first device and the last device adjusts the corresponding device identification address in the addressing instruction packet received from the previous device, and outputs the adjusted addressing instruction packet to the next device. The last device may directly output the addressing instruction packet received from the previous device to the controller, or adjust the addressing instruction packet and output the adjusted addressing instruction packet to the controller. The addressing instruction packet received by each of the aforementioned devices includes a pulse width modulation signal. Each of the multiple waveforms of the pulse width modulation signal has a working period. The working period of the pulse width modulation signal that is not greater than a first working period represents a bit value "0", and the working period of the pulse width modulation signal that is not less than a second working period represents a bit value "1". Wherein, the M working cycles of the M waveforms in the plurality of waveforms of the pulse width modulation signal respectively represent the M bit values ​​of the corresponding device identification address, wherein M is an integer value; Wherein, P of the P waveforms in the pulse width modulation signal, and P of the working cycles of the waveforms, respectively represent P bit values ​​of an identification code clearing instruction, where P is an integer value; Wherein, when the addressing instruction packet received by the input terminal of the first device from the controller has P bit values ​​representing the identification code clearing instruction, the first device clears the default identification code of the first device according to the identification code clearing instruction; Wherein, when each of the other devices, other than the first device, receives an addressing instruction packet from the device that is preceding it, which contains P bits representing the identification code clearing instruction, the other devices clear the default identification code within themselves according to the identification code clearing instruction.

2. The single-line multi-device serial addressing system according to claim 1, characterized in that, The controller compares the addressing instruction packet output to the first device with the addressing instruction packet received by the controller from the last device to determine the corresponding device identification address of each of the plurality of devices and the arrangement order and number of the plurality of devices.

3. The single-line multi-device serial addressing system according to claim 1, characterized in that, The outputs of the devices that are not currently outputting the addressing instruction packet to the next device or the controller are in a closed state.

4. The single-line multi-device serial addressing system according to claim 3, characterized in that, After each of the devices other than the last device adjusts the corresponding device identification address in the addressing instruction packet, the output of each of the devices other than the last device switches from the closed state to the open state to output the adjusted addressing instruction packet to the input of the next device.

5. The single-line multi-device serial addressing system according to claim 4, characterized in that, After the last device adjusts the corresponding device identification address in the addressing instruction packet, the output of the last device switches from the closed state to the open state to output the adjusted addressing instruction packet to the input of the controller; The output terminals of the plurality of devices are sequentially switched from the closed state to the open state according to the arrangement order of the plurality of devices.

6. The single-line multi-device serial addressing system according to claim 1, characterized in that, Each of the aforementioned devices sets its own unique identification code to be the same as the corresponding device identification address in the received addressing instruction packet.

7. The single-line multi-device serial addressing system according to claim 1, characterized in that, Each device counts up one position of the corresponding device identification address in the received addressing instruction packet to increment the corresponding device identification address by one position, and sets the counted corresponding device identification address as its own unique identification code.

8. The single-line multi-device serial addressing system according to claim 1, characterized in that, The first device counts upwards from the M bits representing the unique identifier of the first device within the addressing instruction packet received from the controller to increase the size of the M bits of the unique identifier of the first device, and outputs the counted addressing instruction packet to the next device.

9. The single-line multi-device serial addressing system according to claim 8, characterized in that, Each of the devices other than the first device counts upwards from the M bits of the unique identifier representing the previous device itself in the addressing instruction packet received from the previous device. Each of the devices other than the first device and the last device outputs the counted addressing instruction packet to the next device. The last device outputs the counted addressing instruction packet to the controller.

10. The single-wire multi-device serial addressing system according to claim 1, characterized in that, Each of the aforementioned devices includes one or more light-emitting components.

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