Battery pack equalization system, equalization control circuit and working method thereof

Abstract

A battery pack equalization system, its equalization control circuit and working method are disclosed. The equalization control circuit is configured as a daisy chain architecture together with other equalization control circuits. The battery pack divides a plurality of single batteries connected in series into a plurality of battery groups, wherein the single batteries belonging to the end of each battery group are shared by adjacent battery groups. The equalization control circuit comprises: a first battery terminal coupled to the negative electrode of No. 1 battery in the corresponding battery group; a second battery terminal to an n+1 battery terminal, which are respectively coupled to the positive electrodes of No. 1 to No. n batteries connected in series in the corresponding battery group in turn, wherein n is an integer greater than or equal to 3; a digital input terminal receiving an equalization control signal with a digital coded pulse sequence; and a high-side transfer terminal transferring the received equalization control signal to the digital input terminal of the next equalization control circuit in the daisy chain architecture.

Description

Technical Field

[0001] This invention relates to an electronic circuit, and more particularly, to a battery pack balancing system, a balancing control circuit for balancing a battery pack, and a method for operating the balancing control circuit in a battery pack balancing system. Background Technology

[0002] High-voltage battery packs typically consist of a large number of individual cells connected in series to achieve the required voltage level. Differences in charge state, impedance, and temperature characteristics among the individual cells can lead to imbalances between them.

[0003] Such high-voltage battery packs require technologies to communicate with stacked battery packs to meet the different balancing and communication needs of existing electric bicycles, electric motorcycles, electric vehicles, and energy storage battery stacks. Summary of the Invention

[0004] To address one or more problems in the prior art, the present invention aims to provide a battery pack balancing system, a balancing control circuit, and a method for operating the balancing control circuit in the battery pack balancing system. This system meets the balancing requirements of stacked battery packs while saving on communication hardware costs, and offers excellent flexibility and scalability.

[0005] According to one embodiment of the present invention, an equalization control circuit for equalizing a battery pack is proposed, configured in a daisy-chain architecture together with other equalization control circuits. The battery pack divides multiple series-connected individual cells into multiple battery groups, wherein the individual cells at the end of each battery group are shared by adjacent battery groups. The equalization control circuit includes: a first battery terminal coupled to the negative terminal of cell 1 in the corresponding battery group; a second battery terminal to the (n+1)th battery terminal, respectively coupled to the positive terminals of cells 1 to n connected in series in the corresponding battery group, where n is an integer greater than or equal to 3; a digital input terminal for receiving an equalization control signal having a digitally coded pulse sequence; and a high-side transmission terminal configured to transmit the received equalization control signal to the digital input terminal of the next equalization control circuit in the daisy-chain architecture.

[0006] According to another embodiment of the present invention, a battery pack equalization system is also proposed, comprising: a battery pack, wherein multiple individual cells connected in series are divided into m battery groups, where m is an integer greater than or equal to 2, wherein individual cells belonging to the end of each battery group are shared by adjacent battery groups; m equalization control circuits configured in a daisy-chain architecture, corresponding one-to-one with the m battery groups, wherein each equalization control circuit includes: a first battery terminal coupled to the negative terminal of battery number 1 in the corresponding battery group; a second battery terminal to the (n+1)th battery terminal, respectively coupled to the positive terminals of batteries number 1 to n in the corresponding battery group, where n is an integer greater than or equal to 3; a digital input terminal for receiving an equalization control signal having a digitally coded pulse sequence; and a high-side transmission terminal for transmitting the received equalization control signal to the digital input terminal of the next equalization control circuit in the daisy-chain architecture.

[0007] According to another embodiment of the present invention, a method for operating an equalization control circuit in a battery pack equalization system is also proposed. This equalization control circuit, together with other equalization control circuits, is configured in a daisy-chain architecture. The battery pack divides k series-connected individual cells into multiple battery groups, each battery group containing n series-connected individual cells, where n is an integer greater than or equal to 3 and less than k. Individual cells belonging to the end of each battery group are shared by adjacent battery groups. The method includes: coupling a first battery terminal of the equalization control circuit to the negative terminal of cell number 1 in the corresponding battery group; sequentially coupling the second to (n+1)th battery terminals of the equalization control circuit to the positive terminals of cells number 1 to n in the corresponding battery group; receiving and sharing an equalization control signal with a digitally coded pulse sequence at the digital input terminal of the equalization control circuit; and transmitting the received equalization control signal via the high-side transmission terminal of the equalization control circuit to the digital input terminal of the next equalization control circuit in the daisy-chain architecture. Attached Figure Description

[0008] Figure 1 This is a circuit block diagram of a battery pack balancing system 100 according to an embodiment of the present invention;

[0009] Figure 2 The timing requirements of the equalization control signal BCTRL according to an embodiment of the present invention;

[0010] Figure 3 This is a data transmission structure for the equalization control signal BCTRL according to an embodiment of the present invention;

[0011] Figure 4 This is a circuit schematic diagram of a battery pack balancing system 100A according to an embodiment of the present invention;

[0012] Figure 5This is a circuit schematic diagram of a battery pack balancing system 100B according to an embodiment of the present invention.

[0013] Figure 6 This is a schematic diagram of an equalization control circuit IC for equalizing a battery pack according to an embodiment of the present invention.

[0014] Figure 7 A flowchart of a method 700 for performing battery pack balancing by an balancing control circuit according to an embodiment of the present invention. Detailed Implementation

[0015] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0016] Throughout this specification, references to “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it can be a direct connection or coupling to the other element or there may be intermediate elements. Conversely, when an element is referred to as “directly connected to” or “directly coupled to” another element, there are no intermediate elements. The same reference numerals indicate the same elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0017] Figure 1 This is a circuit block diagram of a battery pack balancing system 100 according to an embodiment of the present invention. Figure 1As shown, the battery pack system 100 includes a battery pack 101, a sampling unit 102, a system controller 103, and m equalization control circuits IC1 to ICm configured in a daisy-chain architecture. The battery pack 101 has a plurality of individual cells connected in series between the positive terminal B+ and the negative terminal B- of the battery pack. The battery pack 101 divides these individual cells into m battery groups 10_1 to 10_m, wherein the individual cells belonging to the end of each battery group are shared by adjacent battery groups.

[0018] exist Figure 1 In the illustrated embodiment, each battery group comprises n batteries connected in series: battery 1, battery 2, ..., battery n, where n is an integer greater than or equal to 3. Figure 1 As shown, battery n, located at the end of battery group 10_1, is shared as battery 1 by the adjacent battery group 10_2. Similarly, battery n, located at the end of battery group 10_2, is also shared as battery 1 by the adjacent battery group 10_3. In other words, both battery 1 and battery n at the end of battery group 10_2 are shared by the adjacent battery groups.

[0019] exist Figure 1 In the illustrated embodiment, sampling unit 102 is connected to each individual cell in battery pack 101 to collect voltage information for each individual cell. System controller 103 is connected to sampling unit 102 to receive and monitor the voltage of each individual cell, determine its state within the entire battery pack 101, and automatically provide equalization control signal BCTRL to meet equalization requirements. The equalization requirements referred to herein include equalization requirements within each battery pack and equalization requirements between different battery packs.

[0020] Each of the equalization control circuits IC1 to ICm is configured as an integrated circuit, forming a structure as follows: Figure 1 The diagram shows a daisy-chain architecture where equalization control circuits IC1 and ICm are stacked sequentially. Equalization control circuits IC1 to ICm correspond one-to-one with m battery groups 10_1 to 10_m to equalize battery group 101. In one embodiment, the equalization control circuit controls energy transfer within the corresponding battery group; for example, it controls the transfer of energy from the highest-voltage cell in the corresponding battery group to other cells in the corresponding battery group, or it controls the transfer of energy from other cells in the corresponding battery group to the lowest-voltage cell in the corresponding battery group. In another embodiment, the equalization control circuit controls the discharge of battery groups with relatively higher voltages and the charging of battery groups with relatively lower voltages until all battery groups are equalized.

[0021] Each equalization control circuit includes multiple terminals. For example... Figure 1As shown, the equalization control circuit IC1 has multiple terminals including a first battery terminal GND, second battery terminals C1 to nth battery terminals Cn, n+1th battery terminal V+, a digital input terminal CTRL, and a high-side transmission terminal UP. The first battery terminal GND is coupled to the negative terminal of battery number 1 in the corresponding battery group (10_1). The second battery terminals C1 to nth battery terminals Cn are sequentially coupled to the positive terminals of batteries number 1 to n-1 in the corresponding battery group (10_1), and the n+1th battery terminal V+ is coupled to the positive terminal of battery number n.

[0022] Continue as Figure 1 As shown, the equalization control circuit IC1 is located on the lowest side of the daisy-chain architecture. Its first battery terminal GND is coupled to the negative terminal B- of the battery pack, and its digital input terminal CTRL is connected to the system controller 103 via the isolation circuit 104 to receive the equalization control signal BCTRL provided by the system controller 103. Its high-side transmission terminal UP transmits the received equalization control signal BCTRL to the digital input terminal CTRL of the next equalization control circuit (IC2) in the daisy-chain architecture. In one embodiment, the isolation circuit 104 may include an optocoupler, a transformer, a capacitive isolation device, or any other suitable electrical isolation device.

[0023] The first battery terminal GND of the equalization control circuit IC2 is coupled to the negative terminal of battery No. 1 in battery group 10_2 (i.e. battery No. n in battery group 10_1). Its second battery terminal C1 to the nth battery terminal Cn are coupled to the positive terminals of batteries No. 1 to No. n-1 in battery group 10_2, respectively. The (n+1)th battery terminal V+ is coupled to the positive terminal of battery No. n.

[0024] Continue as Figure 1 As shown, the digital input terminal CTRL of the equalization control circuit IC2 is coupled to the high-side transmission terminal UP of the preceding equalization control circuit (IC1) in the daisy-chain architecture to receive the equalization control signal BCTRL. Its high-side transmission terminal UP transmits the equalization control signal BCTRL to the digital input terminal CTRL of the following equalization control circuit (IC3) in the daisy-chain architecture.

[0025] like Figure 1 As shown, the equalization control circuit ICm is located on the highest side of the daisy chain architecture, and its (n+1)th battery terminal V+ is coupled to the positive terminal B+ of the battery pack.

[0026] In other embodiments, the number of individual cells in different battery groups can be different. For example, the battery group 10_m closest to the positive terminal B+ of the battery pack may include d individual cells, where d is an integer greater than or equal to 3 and less than n, and adjacent battery groups still share the individual cells located at the ends. In one embodiment, if the battery group 10_m includes 3 individual cells, the fourth battery terminal C3 to the (n+1)th battery terminal are all coupled to the positive terminal of battery number 3, while keeping the connections of the other battery terminals unchanged.

[0027] When any equalization request occurs, the system controller 103 outputs an equalization control signal BCTRL with a digitally coded pulse sequence to the digital input terminal CTRL of the equalization control circuit IC1 located at the lowest side of the daisy chain architecture. Subsequently, the equalization control signal BCTRL is passed sequentially to the higher-side equalization control circuits IC2 to ICm in the daisy chain architecture via the high-side transmission terminal UP of the equalization control circuit IC1. The equalization control circuits IC2 to ICm receive the equalization control signal BCTRL at their respective digital input terminals CTRL, and then transmit the received equalization control signal BCTRL to the digital input terminal CTRL of the next equalization control circuit in the daisy chain architecture via the high-side transmission terminal UP, until it reaches the equalization control circuit ICm located at the highest side.

[0028] Continue as Figure 1 As shown, each equalization control circuit further includes a single-wire interface circuit 11 and a pulse transmission circuit 12. In one embodiment, the single-wire interface circuit 11 is coupled to the digital input terminal CTRL, receives an equalization control signal BCTRL with a digitally encoded pulse sequence, and generates and stores control data based on the number of pulses in the digitally encoded pulse sequence to control the equalization control circuit. The pulse transmission circuit 12 is configured to transmit the equalization control signal BCTRL received at the digital input terminal CTRL to the high-side transmission terminal UP. The high-side transmission terminal UP of the equalization control circuit IC1 transmits the equalization control signal BCTRL to the digital input terminal CTRL of the next equalization control circuit (IC2) in the daisy-chain architecture.

[0029] In one embodiment, the pulse transmission circuit 12 includes, as shown below: Figure 1 The inverter INV and switch M1 are shown. The inverter INV has an input terminal and an output terminal. The input terminal is coupled to the digital input terminal CTRL to receive the equalization control signal BCTRL, and the output terminal is coupled to the control terminal of switch M1. The first terminal of switch M1 is coupled to the high-side transmit terminal UP, and the second terminal is coupled to reference ground. Figure 1As shown, the pulse transmission circuit 12 transmits and shares the equalization control signal BCTRL received at the digital input terminal CTRL to the high-side transmission terminal UP. Subsequently, the equalization control signal BCTRL is transmitted and shared to the digital input terminal CTRL of the next equalization control circuit in the daisy-chain architecture.

[0030] According to one embodiment of the present invention, under the control of the equalization control signal BCTRL, the equalization control circuits IC1 to ICm discharge individual cells with relatively higher voltages and charge individual cells with relatively lower voltages until all individual cells are balanced. According to another embodiment of the present invention, under the control of the equalization control signal BCTRL, the equalization control circuits IC1 to ICm discharge groups of cells with relatively higher voltages and charge groups of cells with relatively lower voltages until all groups of cells are balanced.

[0031] Figure 2 This describes the timing requirements of the equalization control signal BCTRL according to an embodiment of the present invention. Figure 2 As shown, when no transmission is in progress, both the digital input terminal CTRL and the high-side transmission terminal UP are in an idle state, and the equalization control signal BCTRL is controlled by... Figure 1 The external pull-up resistor RH is shown to pull the signal high. It should be noted that at the start of the transmission, the equalization control circuits IC1 to ICm in the daisy-chain architecture are all in an idle state. The system controller 103 sends a signal with an initial duration t. INT A low-level signal is used as a start condition. For example, a low-level signal not lower than 50µs and not higher than 500ms indicates a start condition, marking the beginning of a communication. After receiving the start condition, the equalization control circuits IC1-ICm begin receiving the equalization control signal BCTRL, which has a digitally coded pulse sequence. Then, the system controller 103 sends the equalization control signal BCTRL. The data transmission of the equalization control signal BCTRL is in pulse units, according to... Figure 3 The prescribed data transmission structure will be explained in detail later.

[0032] The equalization control circuits IC1 to ICm receive the data encoded pulse sequence and store it for a preset time t. STORE Internal storage to Figure 1 In the single-wire interface circuit 11 shown, after the equalization control signal BCTRL is sent, the system controller 103 sends the termination condition. Upon receiving the termination condition, the digital input terminals CTRL of the equalization control circuits IC1 to ICm are activated via... Figure 1 The external pull-up resistor RH is shown to pull the device high. This high level is maintained for a duration equal to the off-time t. OFF The digital input terminal CTRL and the high-side transmission terminal UP return to the idle state. For example... Figure 2As shown, the digital pulse codes of the equalization control signal BCTRL transmitted on the digital input terminal CTRL and the high-side transmission terminal UP are basically the same, with only a slight system delay T. PROP .

[0033] Figure 3 This is a data transmission structure for the equalization control signal BCTRL according to an embodiment of the present invention. For example... Figure 3 As shown, the equalization control signal BCTRL switches between logic low and logic high levels. Digitally encoded pulses can be used to provide data and / or timing information.

[0034] exist Figure 3 In the illustrated embodiment, the digitally encoded pulse sequence of the equalization control signal BCTRL includes: an address encoding pulse (ADDR), a read / write identifier pulse, and a command encoding pulse. The read / write identifier pulse and the command encoding pulse are collectively labeled "Command." Each equalization control circuit in the daisy-chain architecture is assigned a unique address for communication with the system controller 103. Each equalization control circuit is configured to identify whether its own set address matches the address code contained in the address encoding pulse (ADDR) of the equalization control signal BCTRL. The read / write identifier pulse instructs the equalization control circuit corresponding to that address code to operate in write mode or read mode. The command encoding pulse instructs the operation of the equalization control circuit corresponding to that address code to meet the equalization requirements of the battery pack.

[0035] Figure 4 This is a circuit diagram of a battery pack balancing system 100A according to an embodiment of the present invention. Figure 4 In the embodiment shown, the battery pack system 100A includes a battery pack 101A, a sampling unit 102, a system controller 103, and m equalization control circuits IC1 to ICm configured in a daisy-chain architecture.

[0036] Battery pack 101A has k individual cells connected in series between the positive terminal B+ and the negative terminal B-. Battery pack 101A divides the k individual cells into m battery groups 10A_1 to 10A_m, where individual cells belonging to the end of each battery group are shared by adjacent battery groups. Figure 4 In the illustrated embodiment, battery group 10A_1 includes five batteries of sizes 1 to 5 connected in series. Battery group 10A_2 includes five batteries of sizes 5 to 9 connected in series. Battery group 10A_3 includes five batteries of sizes 9 to 13 connected in series. Battery group 10A_m includes five batteries of sizes k-4, k-3, ..., k connected in series. Figure 5As shown, battery group 10A_1 shares battery No. 5 with the adjacent battery group 10A_2, and battery group 10A_2 shares battery No. 9 with the adjacent battery group 10A_3. That is to say, the No. 5 and No. 9 batteries located at the ends of battery group 10_2 are shared by the adjacent battery groups.

[0037] exist Figure 4 In the illustrated embodiment, sampling unit 102 is used to collect voltage information of each individual cell. System controller 103 is connected to sampling unit 102, receives and monitors the voltage of each series-connected individual cell, determines its state in the entire battery pack 101A, and automatically provides equalization control signal BCTRL to meet the equalization requirements of battery pack 101A.

[0038] Each of the equalization control circuits IC1 to ICm is configured as an integrated circuit, forming a structure as follows: Figure 4 The daisy-chain architecture is shown. The equalization control circuits IC1 to ICm correspond one-to-one with the m battery groups 10A_1 to 10A_m. For example... Figure 4 As shown, each equalization control circuit includes a single-wire interface circuit 11, a pulse transmission circuit 12, multiple conduction paths 14, a pair of switches consisting of a high-side switch QH and a low-side switch QL, and multiple terminals.

[0039] For example, the equalization control circuit IC1 has multiple terminals including a first battery terminal GND, second battery terminals C1 to C4, a sixth battery terminal V+, a digital input terminal CTRL, a high-side transfer terminal UP, an address configuration terminal ADDR1, a first power terminal P1, and a second power terminal P2. Figure 4 As shown, the first battery terminal GND is coupled to the negative terminal of battery number 1 in battery group 10A_1. The second battery terminals C1 to C4 are sequentially coupled to the positive terminals of batteries number 1 to 4 in battery group 10A_1, respectively, and the sixth battery terminal V+ is coupled to the positive terminal of battery number 5. The address configuration terminal ADDR1 is configured to connect to an external resistor R. ADDR The equalization control circuit sets its own unique address to enable communication with the system controller 103. Those skilled in the art will understand that in other embodiments, the equalization control circuit may also set its own address in other well-known ways.

[0040] Continue as Figure 4 As shown, the first power terminal P1 is coupled to the second power terminal P2 via inductor L1. A pair of switches (a high-side switch QH and a low-side switch QL connected in series) is coupled between the sixth battery terminal and the first battery terminal. The middle node of the switch pair is coupled to the second power terminal P2. Figure 4 As shown, the switching transistors are coupled together with the inductor L1 to form the energy conversion unit 13.

[0041] According to an embodiment of the present invention, for a battery group having n series-connected individual cells, the plurality of conduction paths 14 include n-1 switches S1 to S(n-1). Figure 4 In the illustrated embodiment, multiple conduction paths 14 selectively couple the first power terminal P1 to one of the second battery terminals C1 through the fifth battery terminal C4. Figure 4 In the illustrated embodiment, the plurality of conduction paths 14 include four switches S1 to S4 to provide electrical connections between the first power terminal P1 and the battery terminal (one of C1 to C4), respectively.

[0042] The system controller 103 communicates with the equalization control circuits IC1 to ICm in the daisy-chain architecture via the equalization control signal BCTRL. The equalization control signal BCTRL is issued from the system controller 103 and sequentially passed to each equalization control circuit in the daisy-chain architecture. Each equalization control circuit's digital input terminal CTRL receives and shares the equalization control signal BCTRL and decodes the address encoding pulse contained in the equalization control signal BCTRL. When the equalization control circuit recognizes that the address encoding matches its own set address, it selects one of the multiple conduction paths 14 to conduct based on the command encoding of the equalization control signal BCTRL, and simultaneously guides the switching operation of the switching transistor pairs in the energy conversion unit 13 (e.g., boost or buck operation) to perform equalization control on the battery pack 101.

[0043] Specifically, Figure 4 The single-wire interface circuit 11 shown is coupled to the digital input terminal CTRL, receives the equalization control signal BCTRL, and generates control data based on the number of pulses in the equalization control signal BCTRL, and performs equalization control based on the control data. In one embodiment, the address-matched equalization control circuit switches one of switches S1 to S4 between fully on and fully off states based on the command encoding of the equalization control signal BCTRL.

[0044] In one embodiment, taking the equalization control circuit IC1 as an example, for a battery group having n sequentially connected individual cells, the first power terminal P1 is time-divisionally coupled to the positive terminal of the first target battery or the negative terminal of the second target battery. The first target battery is the individual cell with the highest voltage among batteries numbered 1 to n-1, and the second target battery is the individual cell with the highest voltage among batteries numbered 2 to n. In one embodiment, the first power terminal P1 is coupled to the positive terminal of the first target battery during a first duration t1, and the energy transfer unit 13 operates in boost mode. During a second duration t2, it is coupled to the negative terminal of the second target battery, and the energy transfer unit 13 operates in buck mode.

[0045] In another embodiment, balancing between the two battery packs can also be achieved. For example, when balancing is required between battery packs 10A_1 and 10A_2, the system controller 103 outputs balancing control signals BCTRL that match the addresses of balancing control circuits IC1 and IC2, respectively. Balancing control circuit IC1 activates switch S4 based on the balancing control signal BCTRL, and balancing control circuit IC2 activates switch S1 based on the balancing control signal BCTRL. Further, if the voltage of battery pack 10A_1 exceeds a preset value of the voltage of battery pack 10A_2, the energy transfer units 13 of both balancing control circuits IC1 and IC2 operate in boost mode. If the voltage of battery pack 10A_2 exceeds a preset value of the voltage of battery pack 10A_1, the energy transfer units 13 of both balancing control circuits IC1 and IC2 operate in buck mode.

[0046] According to embodiments of the present invention, the balancing control circuits IC1 to ICm constituting the daisy-chain architecture perform active balancing, enabling rapid balancing of large currents within and between battery groups. Compared to passive balancing, active balancing significantly reduces the time required, thus improving balancing efficiency. This balancing method further extends the battery pack's discharge time to the load, improves discharge efficiency, extends battery pack lifespan, and ultimately achieves energy conservation and emission reduction.

[0047] Figure 5 This is a circuit diagram of a battery pack balancing system 100B according to an embodiment of the present invention. Figure 5 As shown, the battery pack system 100B includes a battery pack 101B, a system controller 103, and four equalization control circuits IC1 to IC4 configured in a daisy-chain architecture. The battery pack 101B has a number of individual cells connected in series between the positive terminal B+ and the negative terminal B-. The battery pack 101B divides these individual cells into four battery groups 10B_1 to 10B_4, where individual cells belonging to the end of each battery group are shared by adjacent battery groups. Figure 5 In the illustrated embodiment, each battery group comprises n batteries connected in series: battery 1, battery 2, ..., battery n, where n is an integer greater than or equal to 3. Figure 5 As shown, battery number n at the end of battery group 10B_1 is shared as battery number 1 by the adjacent battery group 10B_2, and battery number n at the end of battery group 10B_2 is also shared as battery number 1 by the adjacent battery group 10B_3. In other words, both battery number 1 and battery number n at the end of battery group 10B_2 are shared by the adjacent battery groups.

[0048] exist Figure 5In the illustrated embodiment, the system controller 103 communicates with four equalization control circuits IC1 to IC4 configured in a daisy-chain architecture. It provides an equalization control signal BCTRL based on the voltage information of each individual battery cell and determines whether to generate an alarm message based on the status feedback signal FBS. The number of pulses in the status feedback signal FBS represents the operating status of the equalization control circuit.

[0049] exist Figure 5 In the illustrated embodiment, each equalization control circuit, in addition to a single-bus interface circuit 11 and a pulse transmission circuit 12, also includes a status transmission circuit 15 and multiple terminals. These multiple terminals include a first battery terminal GND, second battery terminals C1 to the nth battery terminals Cn, the (n+1)th battery terminal V+, a digital input terminal CTRL, a high-side transmission terminal UP, a status report terminal STAT, and a low-side transmission terminal DOWN. Figure 5 In the illustrated embodiment, the energy transfer unit 13 and the plurality of conduction paths 14 are omitted for clarity.

[0050] exist Figure 5 In the illustrated embodiment, a single-wire interface circuit 11 is coupled to the digital input terminal CTRL to receive an equalization control signal BCTRL with a digitally coded pulse sequence. Control data is generated and stored based on the number of pulses in the digitally coded pulse sequence for equalization control. Figure 5 As shown, the equalization control signal BCTRL is sequentially transmitted to the equalization control circuit located on the higher side of the daisy chain architecture via the high-side transmission terminal UP and the digital input terminal CTRL, and finally to the equalization control circuit IC4 on the highest side.

[0051] like Figure 5 As shown, the transmission paths of the state feedback signal FBS and the equalization control signal BCTRL are exactly opposite, and they are transmitted along the equalization control circuit ICm toward the equalization control circuit IC1.

[0052] In one embodiment, in the equalization control circuit IC2, when a read / write flag pulse indicating the read mode is received, the single-wire interface circuit 11 generates a status feedback signal FBS0 to report the current operating status of the equalization control circuit (IC2). Further, the low-side transmit terminal DOWN is coupled to the status report terminal STAT of the next equalization control circuit (IC3) in the daisy-chain architecture to receive the status feedback signal. The status transmit circuit 15 transmits the received status feedback signal FBS1 to the status report terminal STAT of the current equalization control circuit (IC2). The status feedback signal FBS1 is passed from the high side to the low side of the daisy-chain architecture until it finally reaches the system controller 103. The system controller 103 reads information through the status report terminal STAT of the equalization control circuit IC1 located at the lowest side of the daisy-chain architecture, providing high flexibility and monitorability.

[0053] Specifically, the status transmission circuit 15 includes first and second transmission paths. The first transmission path is used to transmit the upper-level status feedback signal FBS0, representing the status of the current equalization control circuit, to the status report terminal STAT; the second transmission path is used to transmit the status feedback signal (the status feedback signal FBS1, reflecting the operating status of the equalization control circuit located on the high side) received from the low-side transmission terminal DOWN to the status report terminal STAT of the current equalization control circuit.

[0054] exist Figure 5 In the illustrated embodiment, the status transmission circuit 15 includes a comparator COMP, a bias voltage source VB, an OR gate OR1, and a switch M2. The bias voltage source VB has a power supply terminal and an output terminal, wherein the power supply terminal is coupled to the positive terminal of the n-cell battery, and the output terminal is coupled to the non-inverting input of the comparator COMP. The inverting input of the comparator COMP is coupled to the low-side transmission terminal DOWN. The OR gate OR1 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to a single-wire interface circuit 11 to receive a status feedback signal FBS0 representing the current operating state of the equalization control circuit, and the second input terminal is coupled to the output of the comparator COMP to receive a status feedback signal FBS1 representing the operating state of the high-side equalization control circuit. The output of the OR gate OR1 is coupled to the control terminal of the switch M2, providing the status feedback signal FBS to the low-side transmission terminal DWON of the previous equalization control circuit in the daisy-chain architecture via the status report terminal STAT.

[0055] On one hand, when a read / write flag pulse indicating the read mode is received, the single-wire interface circuit 11 generates a status feedback signal FBS0 indicating the current equalization control circuit, and transmits it to the control terminal of switch M2 via the first input of OR gate OR1, so as to transmit the status feedback signal FBS0 to the status report terminal STAT. On the other hand, the low-side transmission terminal DOWN is coupled to the status report terminal STAT of the next equalization control circuit in the daisy-chain architecture, so as to transmit the status feedback signal (i.e., FBS1) from the high-side equalization control circuit via the second input of OR gate circuit OR1 to the control terminal of switch M2, to the status report terminal STAT of the current equalization control circuit, and finally to the system controller 103.

[0056] Figure 6 This is a schematic diagram of an equalization control circuit IC for a battery pack equalization system according to an embodiment of the present invention. Figure 6As shown, battery group 10C includes batteries numbered 1 to 5 connected in series. The equalization control circuit IC includes a single-wire interface circuit 11 as described above, a pulse transmission circuit 12, a pair of switches consisting of a high-side switch QH and a low-side switch QL, multiple conduction paths 14A, a status transmission circuit 15, and multiple terminals.

[0057] The equalization control circuit IC has multiple terminals, including a ground terminal GND coupled to the negative terminal of battery 1, terminals C2 to C4 coupled to the negative terminals of batteries 2 to 5 respectively, a terminal V+ coupled to the positive terminal of battery 5, a second power terminal P2 coupled to the intermediate node of the switching transistor pair, a first power terminal P1 coupled to the second power terminal P2 via an external inductor L1, a digital input terminal CTRL, a high-side transmission terminal UP, a status report terminal STAT, and a low-side transmission terminal DOWN. The switching transistor pair and inductor L1 constitute energy conversion unit 13.

[0058] exist Figure 6 In the illustrated embodiment, the first power terminal P1 is time-divisionally coupled to either the positive terminal of the first target battery or the negative terminal of the second target battery. The first target battery is the lowest voltage cell among batteries of size 1 to 4, and the second target battery is the lowest voltage cell among batteries of size 2 to 5. Specifically, when the first power terminal P1 is coupled to the positive terminal of the first target battery, the energy transfer unit 13 is configured to operate in buck mode. When the first power terminal P1 is coupled to the negative terminal of the second target battery, the energy transfer unit 13 is configured to operate in boost mode.

[0059] like Figure 6 As shown, the multiple conduction paths 14A include four switches S1 to S4 to provide electrical connections between the second terminal of the first inductor L1 and the positive terminal of the first target battery. In one embodiment, each of the switches S1 to S4 includes two N-channel MOSFETs connected in anti-phase series. Figure 6 In the embodiment shown, switch S4, which can be coupled to the negative terminal of battery 5, and switch S1, which can be coupled to the positive terminal of battery 1, each include a unidirectional switch, while S3 and S2 each include two bidirectional switches connected in series in opposite phases.

[0060] Figure 7 This is a flowchart of a battery pack balancing method 700 performed by a balancing control circuit according to an embodiment of the present invention. The balancing control circuit, together with other balancing control circuits, is configured in a daisy-chain architecture. The battery pack divides k series-connected individual cells into multiple battery groups. Each battery group contains n series-connected individual cells, where n is an integer greater than or equal to 3 and less than k. Individual cells at the end of each battery group are shared by adjacent battery groups. The operating method 700 includes steps 701 to 703.

[0061] In step 701, the first battery terminal of the equalization control circuit is coupled to the negative terminal of battery No. 1 in the corresponding battery group, and the second battery terminal to the (n+1)th battery terminal of the equalization control circuit are sequentially coupled to the positive terminals of batteries No. 1 to No. n connected in series in the corresponding battery group.

[0062] In step 702, each equalization control circuit receives and shares an equalization control signal with a digitally coded pulse sequence at its digital input terminal. In one embodiment, the digital pulse sequence includes an address-coded pulse, a read / write flag pulse, and a command-coded pulse. The equalization control circuit identifies whether its own set address matches the address code. The read / write flag pulse is configured to instruct the equalization control circuit to operate in write or read mode. The command-coded pulse is configured to instruct the operation of the equalization control circuit corresponding to the address code to meet equalization requirements.

[0063] In step 703, the received equalization control signal is transmitted to the digital input terminal of the next equalization control circuit in the daisy-chain architecture via the high-side transmission terminal of the equalization control circuit.

[0064] In one embodiment, the battery pack balancing method 700 further includes: coupling an inductor between a first power terminal and a second power terminal of the balancing control circuit; using a pair of switches coupled between the positive terminal of battery n and the negative terminal of battery 1, the intermediate node of the switch pair being coupled to the second power terminal; and, upon detecting that the self-set address of the balancing control circuit matches the address code, configuring the first power terminal to be selectively coupled to one of the second to nth battery terminals based on the command code in the balancing control signal, and configuring the switching operation of the switch pair to meet the balancing requirements.

[0065] In one embodiment, the battery pack balancing operation method 700 further includes: generating a status feedback signal at the status reporting terminal of the balancing control circuit to report the operating status of the balancing control circuit when a read / write flag pulse indicates a read mode. In one embodiment, the operation method 700 further includes coupling a low-side transmit terminal of the balancing control circuit to the status reporting terminal of a subsequent balancing control circuit in a daisy-chain architecture to receive the status feedback signal; and transmitting the received status feedback signal via a status transmission circuit to the status reporting terminal of the balancing control circuit, and finally to a system controller.

[0066] In the specification or claims, related terms such as "first" and "second" may merely distinguish one entity or action from another, without necessarily implying any relationship or order between these entities or actions. Numerical orders such as "first," "second," and "third" merely refer to different individuals among a plurality and do not imply any order or sequence, unless specifically defined in the claim language. The order of the text in any claim does not imply that the processing steps must be performed in a provisional or logical order according to such an order, unless specifically specified in the claim language. Without departing from the scope of the invention, these processing steps may be interchanged in any order, provided that such interchange does not contradict the claim language and does not result in logical absurdity.

[0067] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A balancing control circuit for balancing a battery pack, configured in a daisy-chain architecture along with other balancing control circuits, wherein the battery pack divides multiple series-connected individual cells into multiple battery groups, wherein individual cells belonging to the end of each battery group are shared by adjacent battery groups, the balancing control circuit comprising: The first battery terminal is coupled to the negative terminal of battery number 1 in the corresponding battery group; The second battery terminal to the (n+1)th battery terminal are respectively coupled to the positive terminals of batteries 1 to n connected in series in the corresponding battery group, where n is an integer greater than or equal to 3. The nth battery terminal and the (n+1)th battery terminal of the equalization control circuit are also respectively coupled to the first battery terminal and the second battery terminal of the next equalization control circuit in the daisy chain architecture. The first power terminal is coupled to the second power terminal via an inductor; n-1 conduction paths are configured to selectively couple the first power terminal to one of the second to the nth battery terminals; A pair of switching transistors is coupled between the (n+1)th battery terminal and the first battery terminal, wherein the middle node of the pair of switching transistors is coupled to the second power terminal. Digital input terminals receive equalization control signals with digitally coded pulse sequences; The high-side transmission terminal is configured to transmit the received equalization control signal to the digital input terminal of the next equalization control circuit in the daisy-chain architecture; and Batteries numbered 1 to n constitute the first sub-battery group in a plurality of battery groups, and batteries numbered n to 2n-1 constitute the second sub-battery group in a plurality of battery groups. When equalization is required between the first battery group and the second battery group, the equalization control circuit, based on the received equalization control signal, couples the first power terminal to the nth battery terminal and simultaneously guides the switching operation of the switching transistor pair. Furthermore, the next equalization control circuit, based on the equalization control signal, couples the first power terminal of the next equalization control circuit to the second battery terminal of the next equalization control circuit and simultaneously guides the switching operation of the switching transistor pair of the next equalization control circuit.

2. The equalization control circuit as claimed in claim 1, wherein the digital input terminal is connected to a system controller via an isolation circuit to receive the equalization control signal.

3. The equalization control circuit of claim 1, wherein the digital input terminal is coupled to the high-side transmit terminal of the preceding equalization control circuit in the daisy-chain architecture to receive the equalization control signal.

4. The equalization control circuit as described in claim 1, further comprising: The pulse transmission circuit transmits the equalization control signal received from the digital input terminal to the high-side transmission terminal.

5. The equalization control circuit as described in claim 1, wherein the digitally coded pulse sequence comprises: The address encoding pulse allows the equalization control circuit to identify whether its own set address matches the address encoding. The read / write indicator pulse instructs the equalization control circuit to operate in write or read mode; and The command-encoded pulse guides the operation of the equalization control circuit corresponding to the address code to meet the equalization requirements.

6. The equalization control circuit as described in claim 5, wherein when the equalization control circuit identifies that its own set address matches the address code, it guides the switching operation of the switch pair based on the command code of the equalization control signal, and simultaneously guides the selection of the n-1 conduction paths.

7. The equalization control circuit of claim 5, further comprising a status reporting terminal, wherein when the read / write flag pulse indicates a read mode, the equalization control circuit provides a status feedback signal at the status reporting terminal to report the operating status of the equalization control circuit.

8. The equalization control circuit as described in claim 7, further comprising: The low-side transmission terminal is coupled to the status report terminal of the next equalization control circuit in the daisy-chain architecture to receive status feedback signals. as well as The status transmission circuit is configured to transmit the status feedback signal to the status report terminal.

9. A battery pack balancing system, comprising: A battery pack is a series-connected battery cell group divided into m battery groups, where m is an integer greater than or equal to 2. The battery cells at the end of each battery group are shared by the adjacent battery groups. There are m equalization control circuits configured in a daisy-chain architecture, each corresponding one-to-one with one of the m battery groups. Each equalization control circuit includes: The first battery terminal is coupled to the negative terminal of battery number 1 in the corresponding battery group; The second battery terminal to the (n+1)th battery terminal are sequentially coupled to the positive terminals of batteries 1 to n in the corresponding battery group, where n is an integer greater than or equal to 3. The nth and (n+1)th battery terminals of the equalization control circuit are also coupled to the first and second battery terminals of the next equalization control circuit in the daisy chain architecture. The first power terminal is coupled to the second power terminal via an inductor; n-1 conduction paths are configured to selectively couple the first power terminal to one of the second to the nth battery terminals; A pair of switching transistors is coupled between the (n+1)th battery terminal and the first battery terminal, wherein the middle node of the pair of switching transistors is coupled to the second power terminal. Digital input terminals receive equalization control signals with digitally coded pulse sequences; The high-side transmission terminal transmits the received equalization control signal to the digital input terminal of the next equalization control circuit in the daisy-chain architecture; and Batteries numbered 1 to n constitute the first sub-battery group in a plurality of battery groups, and batteries numbered n to 2n-1 constitute the second sub-battery group in a plurality of battery groups. When the first battery group and the second battery group need to be balanced, the balancing control circuit, based on the balancing control signal, couples the first power terminal to the nth battery terminal and guides the switching operation of the switching transistor pair. Furthermore, the next balancing control circuit, based on the balancing control signal, couples the first power terminal of the next balancing control circuit to the second battery terminal of the next balancing control circuit and guides the switching operation of the switching transistor pair of the next balancing control circuit.

10. The system of claim 9, wherein the digital input terminals of each equalization control circuit share the equalization control signal.

11. The system of claim 9, wherein a system controller sends the equalization control signal to the digital input terminal of the equalization control circuit located at the lowest side of the daisy-chain architecture.

12. The system of claim 9, wherein the digitally coded pulse sequence comprises: Address encoding pulse, each equalization control circuit identifies whether its own set address matches the address encoding; The read / write indicator pulse instructs the equalization control circuit to operate in write or read mode; and The command-encoded pulse instructs the operation of the equalization control circuit corresponding to that address code to meet the equalization requirements.

13. The system of claim 12, wherein each equalization control circuit, upon recognizing that the address code matches its own set address, guides the switching operation of the switch pair based on the command code of the equalization control signal, and simultaneously guides the selection of the n-1 conduction paths.

14. The system of claim 12, wherein each equalization control circuit further includes a status reporting terminal, wherein when a read / write flag pulse indicates a read mode, the equalization control circuit generates a status feedback signal at the status reporting terminal to report the operating status of the equalization control circuit.

15. The system of claim 14, wherein each equalization control circuit further comprises: The low-side transmission terminal is coupled to the status report terminal of the next equalization control circuit in the daisy-chain architecture to receive status feedback signals. as well as The status transmission circuit is configured to transmit the status feedback signal to the status report terminal.

16. A method for operating an equalization control circuit in a battery pack equalization system, the equalization control circuit being configured in a daisy-chain architecture with other equalization control circuits, wherein the battery pack divides k series-connected individual cells into multiple battery groups, each battery group containing n series-connected individual cells, where n is an integer greater than or equal to 3 and less than k, wherein the individual cells at the end of each battery group are shared by adjacent battery groups, the method comprising: The first battery terminal of the equalization control circuit is coupled to the negative terminal of battery No. 1 in the corresponding battery group, and the second battery terminal to the (n+1)th battery terminal of the equalization control circuit are sequentially coupled to the positive terminals of batteries No. 1 to No. n connected in series in the corresponding battery group. The nth battery terminal of the equalization control circuit is coupled to the first battery terminal of the next equalization control circuit in the daisy chain architecture, and the (n+1)th battery terminal of the equalization control circuit is coupled to the second battery terminal of the next equalization control circuit. An inductor is coupled between the first power terminal and the second power terminal of the equalization control circuit; One of the n-1 conduction paths of the equalization control circuit is turned on to selectively couple the first power terminal to one of the second to nth battery terminals of the equalization control circuit; A pair of switches is used, which is coupled between the (n+1)th battery terminal and the first battery terminal of the equalization control circuit, with the middle node of the switch pair coupled to the second power terminal of the equalization control circuit. The equalization control circuit receives and shares equalization control signals with digitally coded pulse sequences at its digital input terminals; The received equalization control signal is transmitted to the digital input terminal of the next equalization control circuit in the daisy-chain architecture via the high-side transmission terminal of the equalization control circuit. Batteries numbered 1 to n constitute the first sub-battery group in the multiple battery groups, and batteries numbered n to 2n-1 constitute the second sub-battery group in the multiple battery groups. as well as When equalization is required between the first battery group and the second battery group, the first power terminal of the equalization control circuit is coupled to the nth battery terminal of the equalization control circuit based on the equalization control signal, and the switching operation of the switching transistor pair of the equalization control circuit is guided. Furthermore, based on the equalization control signal, the first power terminal of the subsequent equalization control circuit is coupled to the second battery terminal of the subsequent equalization control circuit, and the switching operation of the switching transistor pair of the subsequent equalization control circuit is guided.

17. The method of operation as claimed in claim 16, wherein the digitally coded pulse sequence comprises: The address encoding pulse allows the equalization control circuit to identify whether its own set address matches the address encoding. The read / write indicator pulse instructs the equalization control circuit to operate in write or read mode; and The command-encoded pulse instructs the operation of the equalization control circuit corresponding to that address code to meet the equalization requirements.

18. The method of operation as described in claim 17, wherein when the self-set address of the equalization control circuit is identified to match the address code, based on the command code in the equalization control signal, the first power terminal is configured to be selectively coupled to one of the second to nth battery terminals, and the switching operation of the switch pair is configured to meet the equalization requirements.

19. The working method of claim 17, further comprising: When the read / write flag pulse indicates read mode, a status feedback signal is generated at the status report terminal of the equalization control circuit to report the operating status of the equalization control circuit.

20. The working method of claim 19, further comprising: The low-side transmit terminal of the equalization control circuit is coupled to the status report terminal of the next equalization control circuit in the daisy chain architecture to receive status feedback signals. as well as The received status feedback signal is also transmitted to the status report terminal of the equalization control circuit via the status transmission circuit, and finally transmitted to a system controller.

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