Storage unit, memory and preparation method thereof

Abstract

The present disclosure relates to a memory cell, a memory and a method for preparing the same. The memory cell includes a transistor and a capacitor. The transistor includes a semiconductor layer, a first gate and a second gate. The semiconductor layer includes a first portion extending along a first direction, and a second portion and a third portion respectively connected to both ends of the first portion and extending along a second direction; the second direction intersects with the first direction, and a side of the second portion facing away from the third portion is electrically connected to a bit line. The first gate and the second gate are respectively located on opposite sides of the first portion in the second direction. The capacitor is located on a side of the third portion facing away from the second portion and is electrically connected to the third portion. The present disclosure is conducive to improving the storage density, storage capacity, electrical performance and reliability of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a storage unit, a memory and a preparation method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of a number of memory cells arranged in an array. The memory cell may adopt a 1T1C architecture, for example, comprising a transistor and a capacitor.

[0003] Currently, with the increasing demand for memory capacity, memory cells are being arranged in three dimensions. However, the scalability issues and complex manufacturing processes of 1T1C architecture memory cells can easily degrade the electrical performance of memory cells when the size is further reduced, making it difficult to further reduce the size of memory cells while maintaining their electrical performance. Summary of the Invention

[0004] Based on this, the embodiments of the present disclosure provide a memory cell, a memory and a method for manufacturing the same, so as to improve the storage density, storage capacity, electrical performance and reliability of the memory.

[0005] In one aspect, an embodiment of the present disclosure provides a memory cell including a transistor and a capacitor.

[0006] The transistor includes: a semiconductor layer, a first gate and a second gate; wherein the semiconductor layer includes a first portion extending along a first direction, and a second portion and a third portion respectively connected to both ends of the first portion and extending along a second direction; the second direction intersects with the first direction, and a side of the second portion facing away from the third portion is electrically connected to a bit line; the first gate and the second gate are respectively located on opposite sides of the first portion in the second direction.

[0007] The capacitor is located on a side of the third portion facing away from the second portion and is electrically connected to the third portion.

[0008] According to some embodiments, one of the first gate and the second gate includes a first sub-gate and a second sub-gate that are stacked in a direction away from the first portion and made of different materials.

[0009] According to some embodiments, the first sub-gate is a polysilicon gate, and the second sub-gate and the other of the first gate and the second gate are metal gates.

[0010] According to some embodiments, the second portion and the third portion are located on the same side of the first portion. The first gate is located within the space enclosed by the first, second, and third portions and is electrically connected to the first word line. The second gate is located on a side of the first portion facing away from the second and third portions along the second direction and includes a first sub-gate and a second sub-gate. The second sub-gate is electrically connected to the second word line.

[0011] According to some embodiments, the memory cell further includes: a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is located between the first gate and the first portion. The second gate dielectric layer is located between the first sub-gate and the first portion. The second gate dielectric layer has a thickness greater than that of the first gate dielectric layer along the second direction.

[0012] According to some embodiments, the bit line extends along the second direction. The capacitor protrudes from the third portion along the second direction toward the side where the second gate is located. The memory cell further includes: a first isolation structure, a second isolation structure, and a third isolation structure. The first isolation structure is located between the first gate and the second portion, and between the first gate and the third portion. The second isolation structure is located between the second gate and the bit line, and between the second gate and the capacitor. The third isolation structure is located on the same side of the first gate, the third portion, the capacitor, and the first isolation structure between the first gate and the third portion, and is in contact with and connected to the first isolation structure between the first gate and the second portion.

[0013] According to some embodiments, along the second direction, a length of the second portion is greater than a length of the third portion.

[0014] On the other hand, embodiments of the present disclosure further provide a memory device comprising: at least one memory cell as described in any of the above embodiments, at least one bit line, at least one first word line, and at least one second word line. The bit line extends along a second direction and is electrically connected to a corresponding second portion of the memory cell. The first word line extends along a third direction and is electrically connected to a corresponding first gate of the memory cell. The second word line extends along a third direction and is electrically connected to a corresponding second gate of the memory cell. The third direction intersects with both the first and second directions.

[0015] According to some embodiments, there are multiple storage units, and two storage units arranged adjacent to each other in the second direction constitute a repeating unit. In the same repeating unit, the two storage units are mirror-symmetrical to each other, and the second portions of the two storage units are opposite and connected to form an integral structure.

[0016] According to some embodiments, a memory cell includes: a first isolation structure located between a first gate and a second portion, and between the first gate and a third portion; and a third isolation structure located on the same side of the first gate, the third portion, the capacitor, and the first isolation structure between the first gate and the third portion, and in contact with and connected to the first isolation structure between the first gate and the second portion. In a single repeating unit, the first isolation structures located between the first gate and the second portion of two memory cells face each other and are connected as a single unit; and the third isolation structures of the two memory cells face each other and are connected as a single unit.

[0017] On the other hand, an embodiment of the present disclosure further provides a method for preparing a memory, comprising the following steps.

[0018] A stacked structure is formed, wherein the stacked structure includes a plurality of first sacrificial layers and a plurality of second sacrificial layers that are alternately stacked.

[0019] The stack structure is etched along a stacking direction of the first sacrificial layer and the second sacrificial layer to form a first receiving hole.

[0020] A semiconductor layer is formed on the inner side wall of the second sacrificial layer in the first receiving hole; the semiconductor layer includes a first portion extending along a first direction, and a second portion and a third portion respectively connected to both ends of the first portion and extending along a second direction; the second direction intersects the first direction.

[0021] A first gate is formed on a side of the first portion away from the inner sidewall of the second sacrificial layer.

[0022] The stacked structure at a side of the first portion away from the first gate is etched, and a second gate is formed at a side of the first portion away from the first gate.

[0023] The second sacrificial layer located on a side of the second portion facing away from the third portion is removed to form a bit line accommodating groove.

[0024] A bit line is formed in the bit line receiving groove, and the bit line is electrically connected to the second portion.

[0025] The second sacrificial layer located on a side of the third portion facing away from the second portion is removed to form a capacitor accommodating groove.

[0026] A capacitor is formed in the capacitor receiving groove, and the capacitor is electrically connected to the third part.

[0027] According to some embodiments, forming a semiconductor layer on the inner sidewall of the second sacrificial layer in the first receiving hole includes the following steps.

[0028] A semiconductor material layer is formed on the hole wall of the first receiving hole.

[0029] The outer sidewall of the first sacrificial layer extending along the second direction is etched until the semiconductor material layer is exposed.

[0030] The semiconductor material layer is etched based on the removal area of ​​the first sacrificial layer extending along the second direction to remove the semiconductor material layer extending along the second direction between adjacent second sacrificial layers to form an initial semiconductor layer.

[0031] The outer sidewall of the first sacrificial layer extending along the first direction is etched until the initial semiconductor layer is exposed.

[0032] The initial semiconductor layer is etched based on the removal area of ​​the first sacrificial layer extending along the first direction to remove the initial semiconductor layer extending along the first direction between adjacent second sacrificial layers, forming semiconductor layers respectively located on the inner sidewalls of each second sacrificial layer.

[0033] According to some embodiments, the method for preparing the memory further includes the following steps.

[0034] Before forming the semiconductor material layer on the hole wall of the first receiving hole, a first dielectric material layer is formed on the hole wall of the first receiving hole; wherein the semiconductor material layer is formed on the surface of the first dielectric material layer away from the hole wall of the first receiving hole.

[0035] While forming the semiconductor layer on the inner sidewall of the second sacrificial layer, the first dielectric material layer is etched to form a second gate dielectric layer between the inner sidewall of the second sacrificial layer and the semiconductor layer.

[0036] According to some embodiments, before etching the outer sidewall of the first sacrificial layer extending along the second direction until the semiconductor material layer is exposed, the method further includes the following steps.

[0037] A second dielectric material layer is formed to cover the semiconductor material layer and fill the first receiving hole.

[0038] The second dielectric material layer and the stacked structure and semiconductor material layer located on one side of the second dielectric material layer are etched along the stacking direction of the first sacrificial layer and the second sacrificial layer to form a first isolation trench extending along the first direction, and the remaining second dielectric material layer constitutes an initial first isolation structure.

[0039] A third isolation structure is formed in the first isolation trench.

[0040] Correspondingly, forming the first gate on a side of the first portion away from the inner sidewall of the second sacrificial layer includes the following steps.

[0041] The initial first isolation structure is etched along the stacking direction of the first sacrificial layer and the second sacrificial layer to form a second accommodating hole and a first isolation structure located on opposite sides of the second accommodating hole in the first direction, and the semiconductor material layer and the third isolation structure located on opposite sides of the second accommodating hole in the second direction are exposed.

[0042] A first gate dielectric layer is conformally formed on the hole wall of the second receiving hole.

[0043] A first gate covering the first gate dielectric layer and filling the second receiving hole and a first word line correspondingly connected to the first gate are formed.

[0044] According to some embodiments, the method for preparing the memory further includes the following steps.

[0045] After etching the semiconductor material layer based on the removed area of ​​the first sacrificial layer extending along the second direction to form an initial semiconductor layer, the removed area of ​​the first sacrificial layer extending along the second direction and the etched area of ​​the semiconductor material layer are backfilled with the first insulating material.

[0046] After etching the initial semiconductor layer based on the removed area of ​​the first sacrificial layer extending along the first direction to form a semiconductor layer, the removed area of ​​the first sacrificial layer extending along the first direction and the etched area of ​​the initial semiconductor layer are backfilled with a second insulating material.

[0047] Correspondingly, the etching of the stacked structure on the side of the first portion away from the first gate and forming the second gate on the side of the first portion away from the first gate further includes the following steps.

[0048] Along the stacking direction of the first sacrificial layer and the second sacrificial layer, the first part of the second sacrificial layer and the second insulating material on the side away from the first gate is etched to form a second isolation groove extending along the second direction and spaced apart in the first direction, and the outer side wall of the corresponding end of the first part and part of the first insulating material are exposed in the second isolation groove.

[0049] A second isolation structure is formed in the second isolation trench.

[0050] Along the stacking direction of the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the second insulating material in the gap between adjacent second isolation grooves in the first direction are etched to form a third accommodating hole, and the second isolation structure on the opposite sides of the third accommodating hole in the first direction is exposed, while retaining part of the second sacrificial layer in the gap between adjacent second isolation grooves to form a first sub-gate.

[0051] A second sub-gate covering the first sub-gate and a second word line correspondingly connected to the second sub-gate are formed in the third receiving hole; wherein the second gate includes the first sub-gate and the second sub-gate.

[0052] According to some embodiments, the removal of the second sacrificial layer located on the side of the second part away from the third part to form a bit line accommodating groove also includes: on the side of the second part away from the third part, etching the outer side wall of the second sacrificial layer extending along the second direction until the second isolation structure and the outer side wall of the second part are exposed to form the bit line accommodating groove.

[0053] Correspondingly, the step of forming the bit line in the bit line receiving groove further includes: filling the bit line receiving groove with metal material to form the bit line.

[0054] The embodiments of the present disclosure may or may have at least the following advantages:

[0055] In an embodiment of the present disclosure, the semiconductor layer of the transistor is configured to include a first portion extending along a first direction, and a second portion and a third portion connected to both ends of the first portion and extending along a second direction, so that the side of the second portion facing away from the third portion is electrically connected to the bit line, and the side of the third portion facing away from the second portion is electrically connected to the capacitor, and a first gate and a second gate are respectively provided on two opposite sides of the first portion in the second direction. In this way, the transistor adopts the aforementioned structure, which not only helps to improve the space utilization of the area where the transistor is located, thereby effectively reducing the planar area of ​​a single memory cell, but also helps to increase the contact area between the transistor and the bit line by extending the length of the second portion in the semiconductor layer, and to increase the contact area between the transistor and the capacitor by extending the length of the third portion in the semiconductor layer, thereby effectively reducing the contact resistance. In addition, the embodiment of the present disclosure provides the first gate and the second gate on two opposite sides of the first portion of the semiconductor layer in the second direction, which also helps to increase the thickness of the semiconductor layer, especially the first portion, to avoid transistor leakage, thereby improving the reliability of the transistor.

[0056] From the above, the storage unit provided by the embodiment of the present disclosure can not only occupy a smaller planar area to improve the storage density and storage capacity of the memory, but also ensure that the storage unit has better electrical performance and reliability, thereby improving the electrical performance and reliability of the memory.

[0057] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0059] Figure 1 is a schematic structural diagram of a storage unit provided in some embodiments;

[0060] Figure 2 for Figure 1 An electrical characteristic curve diagram of a transistor in the memory cell shown;

[0061] Figure 3 is a schematic structural diagram of another storage unit provided in some embodiments;

[0062] Figure 4 for Figure 3 A schematic diagram of the three-dimensional structure of the storage unit shown;

[0063] Figure 5 A schematic structural diagram of a memory provided in some embodiments;

[0064] Figure 6 A schematic top view of another memory provided in some embodiments in the XY plane;

[0065] Figure 7 A schematic flow chart of a method for preparing a memory provided in some embodiments;

[0066] Figure 8 for Figure 7 A schematic flow chart of step S300 in the method for preparing the memory shown;

[0067] Figure 9 for Figure 7 A schematic flow chart of another step S300 in the method for preparing the memory shown;

[0068] Figure 10 for Figure 7 A schematic flow chart of step S400 in the method for preparing the memory shown;

[0069] Figure 11 for Figure 7 A schematic flow chart of step S500 in the method for preparing the memory shown;

[0070] Figure 12 A schematic structural diagram of a structure obtained after forming a stacked structure provided in some embodiments;

[0071] Figure 13 A schematic structural diagram of a structure obtained after forming a first receiving hole provided in some embodiments;

[0072] Figure 14 A schematic structural diagram of a structure obtained after forming a first dielectric material layer provided in some embodiments;

[0073] Figure 15 A schematic structural diagram of a structure obtained after forming a semiconductor material layer provided in some embodiments;

[0074] Figure 16 A schematic structural diagram of a structure obtained after forming a second dielectric material layer provided in some embodiments;

[0075] Figure 17 A schematic structural diagram of a structure obtained after forming a first isolation trench provided in some embodiments;

[0076] Figure 18 A schematic structural diagram of a structure obtained after forming a third isolation structure provided in some embodiments;

[0077] Figure 19 A schematic structural diagram of a structure obtained after forming a second accommodating hole and a first isolation structure provided in some embodiments;

[0078] Figure 20 A schematic structural diagram of a structure obtained after forming a first gate dielectric layer provided in some embodiments;

[0079] Figure 21 A schematic structural diagram of a structure obtained after forming a first gate and a first word line provided in some embodiments;

[0080] Figure 22 A schematic structural diagram of a structure obtained by etching the outer sidewall of the first sacrificial layer extending along the second direction until the semiconductor material layer is exposed, provided in some embodiments;

[0081] Figure 23 A schematic structural diagram of a structure obtained after forming an initial semiconductor layer provided in some embodiments;

[0082] Figure 24 A schematic structural diagram of a structure obtained after backfilling with a first insulating material provided in some embodiments;

[0083] Figure 25 A schematic structural diagram of a structure obtained by etching an outer sidewall of a first sacrificial layer extending along a first direction until an initial semiconductor layer is exposed, provided in some embodiments;

[0084] Figure 26 A schematic structural diagram of a structure obtained after forming a semiconductor layer provided in some embodiments;

[0085] Figure 27 A schematic structural diagram of a structure obtained after backfilling with a second insulating material provided in some embodiments;

[0086] Figure 28 A schematic structural diagram of a structure obtained after forming a second isolation trench provided in some embodiments;

[0087] Figure 29 A schematic structural diagram of a structure obtained after forming a second isolation structure provided in some embodiments;

[0088] Figure 30A schematic structural diagram of a structure obtained after forming a third accommodating hole provided in some embodiments;

[0089] Figure 31 is a schematic structural diagram of a structure obtained after forming a second gate and a second word line provided in some embodiments;

[0090] Figure 32 A schematic structural diagram of a structure obtained after forming a bit line accommodating groove provided in some embodiments;

[0091] Figure 33 A schematic structural diagram of a structure obtained after forming a bit line provided in some embodiments;

[0092] Figure 34 A schematic structural diagram of another structure obtained after forming a bit line provided in some embodiments;

[0093] Figure 35 A schematic structural diagram of a structure obtained after forming a capacitor receiving groove provided in some embodiments;

[0094] Figure 36 A schematic structural diagram of a structure obtained after forming a capacitor provided in some embodiments;

[0095] Figure 37 Schematic diagram of the cross-sectional structure of a capacitor in the XZ plane provided in some embodiments.

[0096] Description of reference numerals:

[0097] U-memory unit, M-repeating unit; 1-transistor, 2-capacitor, 3-first isolation structure, 4-second isolation structure, 5-third isolation structure; 01-gate, 02-gate oxide layer; 11-semiconductor layer, 12-first gate, 13-second gate, 14-first gate dielectric layer, 15-second gate dielectric layer; first part, 112-second part, 113-third part; 131-first sub-gate, 132-second sub-gate; WL-word line, WL1-first word line, WL2-second word line, BL-bit line;

[0098] N-stack structure, L1-first sacrificial layer, L2-second sacrificial layer, L3-protective layer, 150-first dielectric material layer, 110-semiconductor material layer, 30-second dielectric material layer, 3A-initial first isolation structure, 11A-initial semiconductor layer, 61-first insulating material, 62-second insulating material, 21-first electrode, 22-dielectric layer, 23-second electrode, H1-first accommodating hole, H2-second accommodating hole, H3-second accommodating hole, G1-first isolation groove, G2-second isolation groove, G3-bit line accommodating groove, G4-capacitor accommodating groove. DETAILED DESCRIPTION

[0099] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0100] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0101] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "electrically connected to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion without departing from the teachings of the present disclosure.

[0102] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0103] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Embodiments of the present disclosure should not be limited to the specific shapes of the regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Accordingly, the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0104] In the current DRAM manufacturing process, the memory cell 6F is mostly used. 2 A manufacturing method for arranged and buried wordlines. Because further reducing the size of memory cells becomes very difficult with this method, as the demand for memory storage capacity continues to increase, memory cells have begun to be arranged in three dimensions. However, due to the scalability issues of memory cells in DRAM and the complexity of their process, further reducing the size of memory cells can easily degrade their electrical performance, making it difficult to further reduce the size of memory cells while ensuring their electrical performance.

[0105] In some embodiments, see Figure 1 Figure (a) and (b) in , where Figure 1 Figure (a) shows a three-dimensional structure of a storage unit. Figure 1 Figure (b) is Figure 1 Figure (a) shows a top view of a memory cell. The memory cell adopts a 1T1C architecture, which includes a transistor 1 and a capacitor 2.

[0106] For example, transistor 1 includes a gate 01 integrally connected to a word line WL, and a gate oxide layer 02 and a semiconductor layer 11 sequentially surrounding gate 01. Two opposing outer walls of semiconductor layer 11 in a first direction (e.g., the X direction) are respectively connected to a bit line BL and capacitor 2. Word line WL extends in a vertical direction (e.g., the Z direction). Furthermore, the portion of semiconductor layer 11 connected to bit line BL is the source, and the portion connected to capacitor 2 is the drain.

[0107] From the above, as the characteristic size of transistor 1 decreases, Figure 1 After the leakage test of the transistor 1 of the memory cell shown in FIG. 1 is performed, the electrical characteristic curve of the transistor 1 can be obtained as shown in FIG. Figure 2 As shown. Figure 2 As shown in FIG, the transistor 1 adopts the above structure and will have a gate-induced drain leakage (GIDL) effect; that is, when the gate voltage is zero or negative, if the drain voltage is positive, leakage current is likely to be generated. Figure 2 In the current curve I 11 is the drain current curve of transistor 1 in the off state when the drain voltage is 1V, and the current curve I 12 The drain current curve of transistor 1 in the off state when the drain voltage is 0.05V, the current curve I 21 is the drain current curve of transistor 1 in the on state when the drain voltage is 1V, and the current curve I 12This is the drain current curve of transistor 1 in the on state when the drain voltage is 0.05V. 11 And the current curve I 12 It can be seen that when the gate voltage is -0.5V, the drain voltage is 0.05V, but when the transistor 1 is in the off state, the drain current increases significantly, which is close to 2×10 -07 A.

[0108] From the above, the embodiments of the present disclosure provide a storage unit and a memory, which are beneficial to reducing the planar occupied area of ​​the storage unit to improve the storage density and storage capacity of the memory, and are also beneficial to ensuring that the storage unit has better electrical performance and reliability to improve the electrical performance and reliability of the memory.

[0109] See also Figure 3 and Figure 4 Some embodiments of the present disclosure provide a storage unit that can be applied to a memory, especially a DRAM.

[0110] like Figure 3 and Figure 4 As shown in , the memory cell U includes: a transistor 1 and a capacitor 2. The transistor 1 includes: a semiconductor layer 11, a first gate 12 and a second gate 13. The semiconductor layer 11 includes a first portion 111 extending along a first direction (e.g., the X direction), and a second portion 112 and a third portion 113 respectively connected to both ends of the first portion 111 and extending along a second direction (e.g., the Y direction). The second direction (e.g., the Y direction) and the first direction (e.g., the X direction) intersect, for example, are orthogonal. In addition, the side of the second portion 112 facing away from the third portion 113 is electrically connected to the bit line BL. The first gate 12 and the second gate 13 are respectively located on opposite sides of the first portion 111 in the second direction (e.g., the Y direction). The capacitor 2 is located on a side of the third portion 113 facing away from the second portion 112 and is electrically connected to the third portion 113.

[0111] Here, the first portion 111 of the semiconductor layer 11 can serve as the channel region of the transistor 1 to form a channel current under the control of the gate voltage of the first gate 12 and the second gate 13. The second portion 112 of the semiconductor layer 11 is connected to the bit line BL, and the second portion 112 can be, for example, a source. The third portion 113 of the semiconductor layer 11 is connected to the capacitor 2, and the third portion 113 can be, for example, a drain.

[0112] In the disclosed embodiment, the semiconductor layer 11 of the transistor 1 is configured to include a first portion 111 extending in a first direction (e.g., the X direction), and a second portion 112 and a third portion 113 connected to both ends of the first portion 111 and extending in a second direction (e.g., the Y direction). The second portion 112 is electrically connected to the bit line BL on a side facing away from the third portion 113, and the third portion 113 is electrically connected to the capacitor 2 on a side facing away from the second portion 112. A first gate 12 and a second gate 13 are provided on opposite sides of the first portion 111 in the second direction (e.g., the Y direction). Thus, the transistor 1 employing the aforementioned structure not only improves the space utilization of the region where the transistor 1 is located, thereby effectively reducing the planar area of ​​a single memory cell U, but also increases the contact area between the transistor 1 (e.g., the source) and the bit line BL by extending the length of the second portion 112 in the semiconductor layer 11, and increases the contact area between the transistor 1 (e.g., the drain) and the capacitor 2 by extending the length of the third portion 113 in the semiconductor layer 11, thereby effectively reducing contact resistance.

[0113] Moreover, in the embodiment of the present disclosure, a first gate 12 and a second gate 13 are respectively provided on opposite sides of the first part 111 of the semiconductor layer 11 in the second direction (for example, the Y direction), which is also beneficial to increase the thickness of the semiconductor layer 11, especially the first part 111, to avoid leakage of the transistor 1, thereby improving the reliability of the transistor 1.

[0114] From the above, the memory unit U provided in the embodiment of the present disclosure can not only occupy a smaller plane area to improve the storage density and storage capacity of the memory, but also ensure that the memory unit U has better electrical performance and reliability, thereby improving the electrical performance and reliability of the memory.

[0115] It is understood that the first portion 111, the second portion 112, and the third portion 113 of the semiconductor layer 11 can be an integral structure so as to be formed simultaneously. Furthermore, in some embodiments, the semiconductor layer 11 includes, but is not limited to, an indium gallium zinc oxide film layer (i.e., an IGZO film layer). Thus, based on the excellent anti-leakage characteristics, low cost, and simple process of the IGZO film layer, the anti-leakage characteristics of the transistor 1 can be correspondingly improved, and the production cost of the memory cell U can be reduced, the process of the memory cell U can be simplified, and production efficiency can be improved.

[0116] In some embodiments, see Figure 3 and Figure 4, the second portion 112 and the third portion 113 of the semiconductor layer 11 are located on the same side of the first portion 111. In this way, the second portion 112 and the third portion 113 of the semiconductor layer 11 can form a continuous three-sided space with the first portion 111 at both ends of the first portion 111. Correspondingly, the first gate 12 is located in the space surrounded by the first portion 111, the second portion 112 and the third portion 113 of the semiconductor layer 11, and is electrically connected to the first word line WL1. The second gate 13 is located on the side of the first portion 111 away from the second portion 112 and the third portion 113 along the second direction (for example, the Y direction), and includes a first sub-gate 131 and a second sub-gate 132. The second sub-gate 132 is electrically connected to the second word line WL2.

[0117] For example, the first word line WL1 can extend along a third direction (e.g., the Z direction), which is perpendicular to the intersection of the first and second directions. The first gate 12 and the first word line WL1 are integrally formed. Similarly, the second word line WL2 can also extend along the third direction (e.g., the Z direction), and the second sub-gate 132 of the second gate 13 and the second word line WL2 are integrally formed.

[0118] In some embodiments, please refer to Figure 3 and Figure 4 The bit line BL extends along the second direction (eg, direction Y). Accordingly, along the second direction (eg, direction Y), the length of the second portion 112 of the semiconductor layer 11 is greater than the length of the third portion 113 .

[0119] In the embodiment of the present disclosure, the second portion 112 of the semiconductor layer 11 is electrically connected to the bit line BL, and the length of the second portion 112 is greater than the length of the third portion 113, which helps to ensure that the second portion 112 can have a larger contact area with the bit line BL along the extension direction of the bit line BL, so as to further reduce the contact resistance between the transistor 1 (for example, the source) and the bit line BL.

[0120] In some embodiments, the bit line BL is formed of a conductive material, including but not limited to silicon-based materials, metal-based materials, or combinations thereof. For example, the bit line BL may be made of polysilicon, metal, metal nitride, metal silicide, or combinations thereof. For example, the bit line BL may be a single-layer structure of tungsten, titanium nitride, or polysilicon, or a stacked-layer structure of titanium nitride, tungsten, or the like.

[0121] It should be added that, in some embodiments, see Figure 3 One of the first gate 12 and the second gate 13 includes a first sub-gate 131 and a second sub-gate 132 that are stacked in a direction away from the first portion 111 and made of different materials. Figure 3In the figure, the second gate 13 is illustrated as including the first sub-gate 131 and the second sub-gate 132 , but the present invention is not limited thereto.

[0122] In some embodiments, the first sub-gate 131 is a polysilicon gate, and the second sub-gate 132 and the other of the first gate 12 and the second gate 13 are metal gates.

[0123] In some examples, such as Figure 3 As shown in FIG, the second gate 13 includes a first sub-gate 131 and a second sub-gate 132. The first gate 12 and the second sub-gate 132 are metal gates.

[0124] For example, the metal gate includes, but is not limited to, a single structure of tungsten or copper having excellent conductivity, and may also include a stacked structure of metal and metal, or metal and metal compound. For example, the metal gate includes a stacked structure of titanium nitride and tungsten.

[0125] Please continue reading Figure 3 and Figure 4 In some embodiments, the memory cell U further includes: a first gate dielectric layer 14 and a second gate dielectric layer 15. The first gate dielectric layer 14 is located between the first gate 12 and the first portion 111 of the semiconductor layer 11. The second gate dielectric layer 15 is located between the first sub-gate 131 of the second gate 13 and the first portion 111 of the semiconductor layer 11. In the second direction (e.g., the Y direction), the thickness of the second gate dielectric layer 15 is greater than the thickness of the first gate dielectric layer 14.

[0126] Here, the thickness values ​​of the second gate dielectric layer 15 and the first gate dielectric layer 14 can be set to match each other as required, but the thickness of the second gate dielectric layer 15 must be greater than that of the first gate dielectric layer 14 as a restriction.

[0127] For example, Figure 3 As shown in the figure, the first gate dielectric layer 14 is coated on the sidewalls of the first gate 12 along the circumference of the first gate 12; that is, the first gate dielectric layer 14 can coat the sidewalls of the first gate 12 extending along the first direction (e.g., X direction) and the second direction (e.g., Y direction), respectively.

[0128] For example, the second gate dielectric layer 15 is disposed parallel to the second gate 13, and the second gate dielectric layer 15 and the second gate 13 may have the same length in a first direction (e.g., the X direction). For further example, the orthographic projection of the second gate dielectric layer 15 along the second direction (e.g., the Y direction) substantially coincides with the orthographic projection of the first sub-gate 131 in the second gate 13 in the second direction (e.g., the Y direction).

[0129] For example, the materials of the first gate dielectric layer 14 and the second gate dielectric layer 15 may be the same or different.

[0130] In some examples, the material of the first gate dielectric layer 14 and / or the second gate dielectric layer 15 includes, but is not limited to, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-K dielectric material, ferroelectric material, antiferroelectric material, or a combination thereof. K represents a dielectric constant, and the dielectric constant of the high-K dielectric material is, for example, greater than or equal to 3.9, and may be, for example, 20.

[0131] In some examples, the high-K dielectric material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3).

[0132] For example, the material of the first gate dielectric layer 14 and / or the second gate dielectric layer 15 may be silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), zinc oxide (ZnO), zirconium oxide (ZrO 2 ) or hafnium oxide (HfO 2 ).

[0133] For example, the material of the second gate dielectric layer 15 is polysilicon oxide.

[0134] In some of the above embodiments, the second gate dielectric layer 15 is located between the first sub-gate 131 of the second gate 13 and the first portion 111 of the semiconductor layer 11. Compared with the first gate dielectric layer 14, the second gate dielectric layer 15 has a larger thickness, which can compensate for the oxygen vacancies in the first portion 111 (for example, the channel region) of the semiconductor layer 11 to a certain extent, especially in the embodiment where the second gate dielectric layer 15 is formed of polysilicon oxide, thereby helping to improve the reliability of the transistor 1.

[0135] In some embodiments, please refer to Figure 3 and Figure 4 The bit line BL extends along a second direction (e.g., the Y direction). The capacitor 2 protrudes from the third portion 113 of the semiconductor layer 11 along the second direction (e.g., the Y direction) toward the side where the second gate 13 is located. The memory cell U further includes a first isolation structure 3, a second isolation structure 4, and a third isolation structure 5.

[0136] The first isolation structure 3 is located between the first gate 12 and the second portion 112 of the semiconductor layer 11, and between the first gate 12 and the third portion 113 of the semiconductor layer 11. For example, the portion of the first isolation structure 3 located between the first gate 12 and the second portion 112 of the semiconductor layer 11, and the portion of the first isolation structure 3 located between the first gate 12 and the third portion 113 of the semiconductor layer 11, both extend along the second direction (e.g., the Y direction) and cover the corresponding sidewalls of the first gate dielectric layer 14 along the second direction (e.g., the Y direction).

[0137] The second isolation structure 4 is located between the second gate 13 and the bit line BL, and between the second gate 13 and the capacitor 2. For example, the portion of the second isolation structure 4 located between the second gate 13 and the bit line BL, and the portion of the second isolation structure 4 located between the second gate 13 and the capacitor 2, both extend along the second direction (e.g., the Y direction) and cover the sidewalls of the corresponding second gate dielectric layer 15 along the second direction (e.g., the Y direction).

[0138] The third isolation structure 5 is located on the same side of the first isolation structure 3 between the first gate 12 and the third portion 113 of the semiconductor layer 11, the capacitor 2, and the first isolation structure 3 between the first gate 12 and the third portion 113, and is in contact with and connected to the first isolation structure 3 between the first gate 12 and the second portion 112 of the semiconductor layer 11. For example, the third isolation structure 5 extends along a first direction (e.g., the X direction) and covers corresponding sidewalls of the first isolation structure 3 between the first gate 12 and the second portion 112 of the semiconductor layer 11 along the second direction (e.g., the Y direction), corresponding sidewalls of the first gate dielectric layer 14 along the first direction (e.g., the X direction), corresponding sidewalls of the first isolation structure 3 between the first gate 12 and the third portion 113 along the first direction (e.g., the X direction), corresponding sidewalls of the third portion 113 of the semiconductor layer 11 along the first direction (e.g., the X direction), and corresponding sidewalls of the capacitor 2 along the first direction (e.g., the X direction).

[0139] In the embodiment of the present disclosure, the aforementioned first isolation structure 3 , second isolation structure 4 and third isolation structure 5 are used to effectively eliminate the GIDL effect of the transistor 1 , thereby improving the electrical performance and reliability of the transistor 1 .

[0140] It should be noted that the first isolation structure 3, the second isolation structure 4, and the third isolation structure 5 are formed of insulating materials and may be single-layer structures or stacked-layer structures. Furthermore, the insulating materials used for the first isolation structure 3, the second isolation structure 4, and the third isolation structure 5 may be the same or different. For example, the insulating materials may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0141] In some embodiments, capacitor 2 can have a structure in which a first electrode, a dielectric layer, and a second electrode are stacked in sequence. For example, capacitor 2 is a metal-insulator-metal (MIM) capacitor; that is, both the first electrode and the second electrode are formed of metal materials. The dielectric layer (insulator) can be formed of silicon oxide, silicon nitride, a high-K dielectric material, or a combination thereof. The first electrode of capacitor 2 is electrically connected to the third portion 113 of semiconductor layer 11.

[0142] Some embodiments of the present disclosure also provide a memory as an application device of the storage unit in some of the above embodiments. The memory also has the technical advantages of the above storage unit. Figure 5 and Figure 6 The memory includes: at least one memory unit U as described in any of the above embodiments, at least one bit line BL, at least one first word line WL1 and at least one second word line WL2.

[0143] like Figure 5 and Figure 6 As shown in FIG, the bit line BL extends along a second direction (e.g., the Y direction) and is electrically connected to the second portion 112 of the semiconductor layer 11 in the memory cell U. The first word line WL1 extends along a third direction (e.g., the Z direction) and is electrically connected to the first gate 12 in the memory cell U. The second word line WL2 extends along a third direction (e.g., the Z direction) and is electrically connected to the second gate 13 in the memory cell U. The third direction (e.g., the Z direction) intersects with the first direction (e.g., the X direction) and the second direction (e.g., the Y direction).

[0144] For example, the third direction (eg, Z direction) is orthogonal to the first direction (eg, X direction) and the second direction (eg, Y direction).

[0145] In some embodiments, please refer to Figure 5 and Figure 6 The number of memory units U can be multiple, and two memory units U arranged adjacent to each other in the second direction (e.g., the Y direction) can constitute a repeating unit M. In the same repeating unit M, the two memory units U are mirror-symmetric to each other, and the second portions 112 of the semiconductor layers 11 in the two memory units U are opposite and can be connected to form an integrated structure.

[0146] Here, if Figure 6 As shown in FIG, the mirror-symmetric center line OO′ of two memory cells U in the same repeating unit M extends along the first direction (eg, the X direction), and may, for example, pass through the geometric center of the third isolation structure 5 .

[0147] In some embodiments, please refer to Figure 5 and Figure 6 In the same repeating unit M, the first isolation structures 3 between the first gate 12 and the second portion 112 of the two memory cells U are opposite and connected as an integral structure, and the third isolation structures 5 of the two memory cells U are opposite and connected as an integral structure. Thus, the two memory cells U in the same repeating unit M can be considered to share the same third isolation structure 5.

[0148] In some embodiments, see Figure 6, there are multiple repeating units M, and the multiple repeating units M can be arranged in rows along a first direction (for example, the X direction) and arranged in columns along a second direction (for example, the Y direction); wherein, the memory cells U in two adjacent columns of repeating units M can share the same bit line BL, and the two adjacent columns of repeating units M are symmetrically distributed with the bit line BL as the center.

[0149] Also, see Figure 5 In some embodiments, multiple repeating units M may be stacked along a third direction (e.g., the Z direction) to achieve three-dimensional stacking of memory cells U. In this way, the first word line WL1 and the second word line WL2 may be respectively connected to corresponding gates of the memory cells U in their extending directions.

[0150] Some embodiments of the present disclosure also provide a memory manufacturing method for manufacturing the memory described in some of the aforementioned embodiments. This manufacturing method also possesses the technical advantages of the aforementioned memories. Furthermore, the memory manufacturing method provided by the embodiments of the present disclosure reduces the difficulty of the process, is easy to implement, and also helps improve the production efficiency and yield of the memory.

[0151] See also Figure 7 , the preparation method of the memory includes the following steps S100 to S900.

[0152] S100 , forming a stack structure, where the stack structure includes a plurality of first sacrificial layers and a plurality of second sacrificial layers alternately stacked.

[0153] S200 , etching the stack structure along the stacking direction of the first sacrificial layer and the second sacrificial layer to form a first receiving hole.

[0154] S300, forming a semiconductor layer on the inner side wall of the second sacrificial layer in the first receiving hole; the semiconductor layer includes a first portion extending along the first direction, and a second portion and a third portion respectively connected to both ends of the first portion and extending along the second direction; the second direction intersects the first direction.

[0155] S400 , forming a first gate on a side of the first portion away from an inner sidewall of the second sacrificial layer.

[0156] S500 , etching the stacked structure on a side of the first portion away from the first gate, and forming a second gate on a side of the first portion away from the first gate.

[0157] S600 , removing the second sacrificial layer located on a side of the second portion away from the third portion to form a bit line accommodating groove.

[0158] S700 , forming a bit line in the bit line receiving groove, and electrically connecting the bit line to the second portion.

[0159] S800 , removing the second sacrificial layer located on a side of the third portion facing away from the second portion to form a capacitor accommodating groove.

[0160] S900 , forming a capacitor in the capacitor receiving groove, and electrically connecting the capacitor to the third portion.

[0161] In some embodiments, see Figure 8 In step S300 , a semiconductor layer is formed on the inner sidewall of the second sacrificial layer in the first receiving hole, including the following steps S310 to S350 .

[0162] S310 , forming a semiconductor material layer on the hole wall of the first receiving hole.

[0163] S320 , etching the outer sidewall of the first sacrificial layer extending along the second direction until the semiconductor material layer is exposed.

[0164] S330 , etching the semiconductor material layer based on the removal area of ​​the first sacrificial layer extending along the second direction to remove the semiconductor material layer extending along the second direction between adjacent second sacrificial layers to form an initial semiconductor layer.

[0165] S340 , etching the outer sidewall of the first sacrificial layer extending along the first direction until the initial semiconductor layer is exposed.

[0166] S350 , etching the initial semiconductor layer based on the removal area of ​​the first sacrificial layer extending along the first direction to remove the initial semiconductor layer extending along the first direction between adjacent second sacrificial layers, forming semiconductor layers respectively located on the inner sidewalls of each second sacrificial layer.

[0167] In some embodiments, see Figure 9 The method for preparing the memory further includes the following steps S301 and S351.

[0168] S301 , before forming a semiconductor material layer on the hole wall of the first receiving hole in step S310 , a first dielectric material layer is formed on the hole wall of the first receiving hole.

[0169] Accordingly, in step S310 , a semiconductor material layer is formed on a surface of the first dielectric material layer away from the wall of the first receiving hole.

[0170] S351 , while forming a semiconductor layer on the inner sidewall of the second sacrificial layer, the first dielectric material layer is etched to form a second gate dielectric layer between the inner sidewall of the second sacrificial layer and the semiconductor layer.

[0171] In some examples, the second gate dielectric layer formed in step S351 may be an initial second gate dielectric layer; and after etching to form a second isolation trench in the subsequent step S510 , a second gate dielectric layer of a final structure may be obtained.

[0172] In some embodiments, please refer to Figure 9 Before performing step S320 to etch the outer sidewall of the first sacrificial layer extending along the second direction until the semiconductor material layer is exposed, the method further includes the following steps S311 to S313.

[0173] S311 , forming a second dielectric material layer covering the semiconductor material layer and filling the first receiving hole.

[0174] S312, etching the second dielectric material layer and the stacking structure and semiconductor material layer located on one side of the second dielectric material layer along the stacking direction of the first sacrificial layer and the second sacrificial layer to form a first isolation groove extending along the first direction, and making the remaining second dielectric material layer constitute an initial first isolation structure.

[0175] S313 , forming a third isolation structure in the first isolation trench.

[0176] Accordingly, see Figure 10 In step S400, a first gate is formed on a side of the first portion away from the inner sidewall of the second sacrificial layer, including the following steps S410 to S430.

[0177] S410, etching the initial first isolation structure along the stacking direction of the first sacrificial layer and the second sacrificial layer to form a second accommodating hole and a first isolation structure located on opposite sides of the second accommodating hole in the first direction, and exposing the semiconductor material layer and the third isolation structure located on opposite sides of the second accommodating hole in the second direction.

[0178] S420 , conformally forming a first gate dielectric layer on the hole wall of the second receiving hole.

[0179] S430 , forming a first gate covering the first gate dielectric layer and filling the second receiving hole and a first word line correspondingly connected to the first gate.

[0180] In some embodiments, please refer to Figure 9 The method for preparing the memory further includes the following steps S331 and S352.

[0181] S331, in step S330, the semiconductor material layer is etched based on the removed area of ​​the first sacrificial layer extending along the second direction to form an initial semiconductor layer, and then the first insulating material is backfilled in the removed area of ​​the first sacrificial layer extending along the second direction and the etched area of ​​the semiconductor material layer.

[0182] S352, in step S350, the initial semiconductor layer is etched based on the removed area of ​​the first sacrificial layer extending along the first direction. After the semiconductor layer is formed, the removed area of ​​the first sacrificial layer extending along the first direction and the etched area of ​​the initial semiconductor layer are backfilled with a second insulating material.

[0183] Accordingly, see Figure 11 In step S500, the stacked structure of the first portion away from the first gate is etched, and the second gate is formed on the side of the first portion away from the first gate, and the following steps S510 to S540 are also included.

[0184] S510, along the stacking direction of the first sacrificial layer and the second sacrificial layer, etching the first portion of the second sacrificial layer and the second insulating material away from the first gate, forming a second isolation groove extending along the second direction and spaced apart in the first direction, and exposing the outer side wall of the corresponding end portion of the first portion and a portion of the first insulating material in the second isolation groove.

[0185] S520 , forming a second isolation structure in the second isolation trench.

[0186] S530, along the stacking direction of the first sacrificial layer and the second sacrificial layer, the second sacrificial layer and the second insulating material in the interval between adjacent second isolation grooves in the first direction are etched to form a third accommodating hole, and the second isolation structure on opposite sides of the third accommodating hole in the first direction is exposed, while retaining part of the second sacrificial layer in the interval between adjacent second isolation grooves to form a first sub-gate.

[0187] S540 , forming a second sub-gate covering the first sub-gate and a second word line correspondingly connected to the second sub-gate in the third receiving hole; wherein the second gate includes the first sub-gate and the second sub-gate.

[0188] In some embodiments, step S600 removes the second sacrificial layer located on the side of the second part away from the third part to form a bit line accommodating groove, and also includes: on the side of the second part away from the third part, etching the outer wall of the second sacrificial layer extending along the second direction until the second isolation structure and the outer wall of the second part are exposed to form a bit line accommodating groove.

[0189] Accordingly, the step S700 of forming the bit line in the bit line receiving groove further includes: filling the bit line receiving groove with a metal material to form the bit line.

[0190] Furthermore, in some embodiments, the step S600 of removing the second sacrificial layer located on a side of the second portion facing away from the third portion to form a bit line accommodating groove further includes: etching an outer sidewall of the second sacrificial layer located on the same side as the second gate and extending along the first direction until the second sacrificial layer between corresponding second isolation structures and the second sacrificial layer between corresponding second portions in adjacent columns of memory cells are removed, thereby forming the bit line accommodating groove. Accordingly, the step S700 of forming the bit line in the bit line accommodating groove further includes: filling the bit line accommodating groove with a metal material to form a bit line shared by adjacent columns of memory cells.

[0191] In some embodiments, step S800 removes the second sacrificial layer located on the side of the third part away from the second part to form a capacitor accommodating groove, and also includes: on the side of the third part away from the second part, etching the outer wall of the second sacrificial layer extending along the second direction until the second isolation structure and the outer wall of the third part are exposed to form a capacitor accommodating groove.

[0192] Here, in the embodiment where the third isolation structure is formed, the capacitor receiving groove also exposes the third isolation structure.

[0193] For example, forming a capacitor in the capacitor receiving groove in step S900 includes the following steps.

[0194] S910 , forming a first electrode conformally covering a wall of a capacitor receiving groove.

[0195] S920 , forming a dielectric layer conformally covering the first electrode.

[0196] S930 , forming a second electrode filling the capacitor receiving groove on a surface of the dielectric layer away from the first electrode.

[0197] It should be understood that although the above Figures 7 to 11 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figures 7 to 11 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0198] In order to more clearly illustrate the preparation method of the memory in some of the above embodiments, the following Figures 12 to 37 Understand some embodiments of the present disclosure.

[0199] In step S100, refer to Figure 12 , forming a stacked structure N, which includes a plurality of first sacrificial layers L1 and a plurality of second sacrificial layers L2 that are alternately stacked.

[0200] Here, it is understandable that Figure 12 Only one stacking structure N is used as an example. When the stacking structure N is formed, it can be formed before the substrate ( Figure 12Multiple first sacrificial material layers and multiple second sacrificial material layers are alternately stacked on a substrate (not shown), and then the multiple first sacrificial material layers and the multiple second sacrificial material layers are patterned to form a plurality of stacked structures N arranged in an array, so that corresponding memory cells U are prepared based on each stacked structure N. In addition, the number of stacked layers of the first sacrificial layers L1 and the second sacrificial layers L2 in the stacked structure N can match the storage requirements of the memory cell U in a third direction (e.g., the Z direction).

[0201] For example, the alternating stacking of the first sacrificial layer L1 and the second sacrificial layer L2 in the stacked structure N may start with the first sacrificial layer L1 and end with the second sacrificial layer L2. However, this is not limited to the above. For example, the alternating stacking of the first sacrificial layer L1 and the second sacrificial layer L2 may start with the second sacrificial layer L2 and end with the first sacrificial layer L1; or the alternating stacking of the first sacrificial layer L1 and the second sacrificial layer L2 may start with the first sacrificial layer L1 and end with the first sacrificial layer L1, etc., all of which are permitted.

[0202] In some examples, the first sacrificial layer L1 includes, but is not limited to, a silicon oxide layer.

[0203] In some examples, the second sacrificial layer L2 includes, but is not limited to, a polysilicon layer.

[0204] For further example, the second sacrificial layer L2 is a heavily doped polysilicon layer, for example, a P-type heavily doped polysilicon layer. The doping concentration of the P-type doping element in the second sacrificial layer L2 can be 1E20 / cm 3 ~1E21 / cm 3 The P-type doping elements include, for example, Group III elements, such as boron.

[0205] Here, the second sacrificial layer L2 is a heavily doped polysilicon layer, which is beneficial for increasing the threshold voltage of the transistor 1 after the first sub-gate 131 of the second gate 13 is subsequently formed based on the second sacrificial layer L2.

[0206] In some examples, taking the first sacrificial layer L1 as the starting layer and the second sacrificial layer L2 as the ending layer in the stacked structure N as an example, the stacked structure N may further include a protective layer L3 covering the top second sacrificial layer L2. The protective layer L3 may be, for example, a hard mask layer, including but not limited to a silicon nitride layer.

[0207] In step S200, refer to Figure 13 The stack structure N is etched along the stacking direction of the first sacrificial layer L1 and the second sacrificial layer L2 (ie, the third direction, such as the Z direction) to form a first receiving hole H1.

[0208] Here, the first receiving hole H1 is used to define the formation position of the semiconductor layer 11 in the memory unit U. In the example where the second portion 112 of the semiconductor layer 11 in the same repeating unit M is opposite and has an integral structure, the first receiving hole H1 can be used to directly define the formation position of the semiconductor layer 11 in the repeating unit M.

[0209] For example, the cross-sectional shape of the first accommodating hole H1 includes, but is not limited to, a rectangle. The cross-sectional shape of the first accommodating hole H1 refers to a cross-sectional shape of the first accommodating hole H1 in the XY plane.

[0210] In step S300, refer to Figure 3 and Figures 14 to 27 A semiconductor layer 11 is formed on the inner sidewall of the second sacrificial layer L2 within the first receiving hole H1. The semiconductor layer 11 includes a first portion 111 extending along a first direction (e.g., the X direction), and a second portion 112 and a third portion 113 connected to both ends of the first portion 111 and extending along a second direction (e.g., the Y direction). The second direction (e.g., the Y direction) and the first direction (e.g., the X direction) intersect, for example, are orthogonal.

[0211] In some examples, step S300 may include steps S301 to S352.

[0212] In step S301, please refer to Figure 14 Before forming the semiconductor material layer on the hole wall of the first receiving hole H1 in step S310 , a first dielectric material layer 150 is formed on the hole wall of the first receiving hole H.

[0213] By way of example, the first dielectric material layer 150 includes, but is not limited to, silicon oxide.

[0214] Here, it can be understood that in the embodiment where the first sacrificial layer L1 is a silicon oxide layer, the first dielectric material layer 150 may be formed only on the sidewalls (ie, inner sidewalls) of the second sacrificial layer L2 located within the first receiving hole H1 .

[0215] For example, a thermal oxidation process is performed on the inner sidewall of the second sacrificial layer L2 in the first receiving hole H1. The second sacrificial layer L2 is a polysilicon layer, and the first dielectric material layer 150 can be a polysilicon oxide layer.

[0216] In other examples, the first dielectric material layer 150 can be formed by a deposition process to cover the hole wall of the first receiving hole H1. The first dielectric material layer 150 can be formed of materials such as aluminum oxide (Al2O3), zinc oxide (ZnO), zirconium oxide (ZrO2), or hafnium oxide (HfO2).

[0217] In step S310, refer to Figure 15 , a semiconductor material layer 110 is formed on the hole wall of the first receiving hole H1.

[0218] After the first dielectric material layer 150 is formed on the wall of the first receiving hole H1 , the semiconductor material layer 110 is formed on the surface of the first dielectric material layer 150 away from the wall of the first receiving hole H1 .

[0219] By way of example, the semiconductor material layer 110 includes, but is not limited to, an IGZO layer.

[0220] In step S311, refer to Figure 16 , forming a second dielectric material layer 30 covering the semiconductor material layer 110 and filling the first receiving hole H1.

[0221] By way of example, the second dielectric material layer 30 includes but is not limited to a silicon oxide layer.

[0222] For example, the top surface of the second dielectric material layer 30 is flush with the top surface of the protection layer L3 in the stacked structure N.

[0223] In step S312, refer to Figure 17 The second dielectric material layer 30 and the stacked structure N and the semiconductor material layer 110 located on one side of the second dielectric material layer 30 are etched along the stacking direction of the first sacrificial layer L1 and the second sacrificial layer L2 (i.e., the third direction, such as the Z direction) to form a first isolation trench G1 extending along the first direction (e.g., the X direction), and the remaining second dielectric material layer 30 constitutes an initial first isolation structure 3A.

[0224] Here, the first isolation trench G1 may be used to define a formation position of the third isolation structure 5 between adjacent transistors 1 in the same repeating unit M.

[0225] In step S313, refer to Figure 18 , a third isolation structure 5 is formed in the first isolation trench G1.

[0226] For example, the third isolation structure 5 and the second dielectric material layer 30 are made of different materials.

[0227] By way of example, the third isolation structure 5 is formed of silicon nitride material.

[0228] In step S400, refer to Figures 19 to 21 , step S400 may include steps S410 to S430.

[0229] In step S410, refer to Figure 19 The initial first isolation structure 3A is etched along the stacking direction of the first sacrificial layer L1 and the second sacrificial layer L2 (i.e., the third direction, such as the Z direction) to form the second accommodating hole H2 and the first isolation structure 3 located on opposite sides of the second accommodating hole H2 in the first direction (e.g., the X direction), and the semiconductor material layer 110 and the third isolation structure 5 located on opposite sides of the second accommodating hole H2 in the second direction (e.g., the Y direction) are exposed.

[0230] Here, the second receiving hole H2 is used to define the formation positions of the first gate 12 and the first word line WL1 .

[0231] For example, the cross-sectional shape of the second receiving hole H2 includes, but is not limited to, a rectangle, a circle, or an ellipse, etc. The cross-sectional shape of the second receiving hole H2 refers to the cross-sectional shape of the second receiving hole H2 in the XY plane.

[0232] In step S420, refer to Figure 20 , a first gate dielectric layer 14 is conformally formed on the hole wall of the second receiving hole H2.

[0233] For example, the first gate dielectric layer 14 is formed by a deposition process, which includes but is not limited to an atomic layer deposition process.

[0234] For example, the material of the first gate dielectric layer 14 includes, but is not limited to, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-K dielectric material, ferroelectric material, antiferroelectric material, or a combination thereof.

[0235] In step S430, refer to Figure 21 , forming a first gate 12 covering the first gate dielectric layer 14 and filling the second receiving hole H2 and a first word line WL1 correspondingly connected to the first gate 12 .

[0236] For example, the first gate 12 and the first word line WL1 are formed of a metal material, such as tungsten or copper, and are an integrated structure.

[0237] For example, the first gate 12 and the first word line WL1 may also be a stacked structure of metal and metal, or metal and metal compound. For example, the first gate 12 and the first word line WL1 are a stacked structure of titanium nitride and tungsten.

[0238] In step S320, refer to Figure 22 , the outer sidewall of the first sacrificial layer L1 extending along the second direction (eg, the Y direction) is etched until the semiconductor material layer 110 is exposed.

[0239] For example, the first sacrificial layer L1 may be etched using a lateral etching process.

[0240] In step S330, refer to Figure 23 The semiconductor material layer 110 is etched based on the removal area extending along the second direction (for example, the Y direction) of the first sacrificial layer L1 to remove the semiconductor material layer 110 extending along the second direction (for example, the Y direction) between adjacent second sacrificial layers L2 to form an initial semiconductor layer 11A.

[0241] Here, the first gate dielectric layer 14 extending along the second direction (eg, the Y direction) between adjacent second sacrificial layers L2 may serve as an etching stopper layer for the semiconductor material layer 110 .

[0242] In step S331, refer to Figure 24 The first insulating material 61 is backfilled in the removed area of ​​the first sacrificial layer L1 extending along the second direction (eg, the Y direction) and the etched area of ​​the semiconductor material layer 110 .

[0243] Illustratively, the first insulating material 61 is different from the material of the first sacrificial layer L1 .

[0244] By way of example, the first insulating material 61 includes, but is not limited to, silicon nitride material.

[0245] In step S340, refer to Figure 25 , the outer sidewall of the first sacrificial layer L1 extending along the first direction (eg, the X direction) is etched until the initial semiconductor layer 11A is exposed.

[0246] For example, the first sacrificial layer L1 may be etched using a lateral etching process.

[0247] It can be understood that after executing step S340 , each first sacrificial layer L1 in the stacked structure N has been effectively removed without any residue.

[0248] In step S350, refer to Figure 26 The initial semiconductor layer 11A is etched based on the removal area extending along the first direction (for example, the X direction) of the first sacrificial layer L1 to remove the initial semiconductor layer 11A extending along the first direction (for example, the X direction) between adjacent second sacrificial layers L2, thereby forming semiconductor layers 11 respectively located on the inner side walls of each second sacrificial layer L2.

[0249] At this point, the semiconductor layer 11 of each memory cell in the embodiment of the present disclosure has been prepared. The relevant structure of the semiconductor layer 11 can be found in the relevant descriptions in some of the aforementioned embodiments and will not be described in detail here.

[0250] In some embodiments, the first dielectric material layer 150 also covers the inner sidewall of the first sacrificial layer L1 in the first receiving hole H1. Figure 26 While forming the semiconductor layer 11 on the inner sidewall of the second sacrificial layer L2 , the first dielectric material layer 150 is etched to form a second gate dielectric layer 15 between the inner sidewall of the second sacrificial layer L2 and the semiconductor layer 11 .

[0251] Here, etching of the first dielectric material layer 150 on the inner sidewalls of the first sacrificial layer L1 can be performed twice, matching the etching of the semiconductor material layer 110 and the initial semiconductor layer 11A. Furthermore, etching of the first dielectric material layer 150 on the inner sidewalls of the first sacrificial layer L1 is performed prior to etching the corresponding regions of the semiconductor material layer 110 and the initial semiconductor layer 11A, thereby exposing the corresponding regions of the semiconductor material layer 110 and the initial semiconductor layer 11A.

[0252] In some examples, the second gate dielectric layer 15 formed in step S351 may be an initial second gate dielectric layer; and after etching to form a second isolation trench in the subsequent step S510 , a final second gate dielectric layer 15 may be obtained.

[0253] In step S352, refer to Figure 27 The second insulating material 62 is backfilled in the removed area of ​​the first sacrificial layer L1 extending along the first direction (eg, the X direction) and the etched area of ​​the initial semiconductor layer 11A.

[0254] For example, the second insulating material 62 and the first insulating material 61 are made of different materials.

[0255] By way of example, the second insulating material 62 includes, but is not limited to, silicon oxide material.

[0256] In step S500, refer to Figures 28 to 30 , the stacked structure N on the side of the first portion 111 of the semiconductor layer 11 away from the first gate 12 is etched, and the second gate 13 is formed on the side of the first portion 111 away from the first gate 12 .

[0257] In some examples, step S500 may include steps S510 to S540.

[0258] In step S510, refer to Figure 28 , along the stacking direction of the first sacrificial layer L1 and the second sacrificial layer L2 (i.e., the third direction, such as the Z direction), the second sacrificial layer L2 and the second insulating material 62 on the side of the first portion 111 in the semiconductor layer 11 away from the first gate 12 are etched to form second isolation grooves G2 extending along the second direction (e.g., the Y direction) and spaced apart in the first direction (e.g., the X direction), and the outer side walls of the corresponding ends of the first portion 111 and part of the first insulating material 61 are exposed in the second isolation grooves G2.

[0259] Here, the intervals between adjacent second isolation trenches G2 in the first direction (eg, the X direction) are used to define the formation positions of the second gate 13 and the second word line WL2 .

[0260] In step S520, refer to Figure 29 , forming a second isolation structure 4 in the second isolation trench G2.

[0261] For example, the material of the second isolation structure 4 is the same as the first insulating material 61 .

[0262] By way of example, the material of the second isolation structure 4 includes, but is not limited to, silicon nitride material.

[0263] In step S530, refer to Figure 30, along the stacking direction of the first sacrificial layer L1 and the second sacrificial layer L2 (i.e., the third direction, such as the Z direction), the second sacrificial layer L2 and the second insulating material 62 in the interval between adjacent second isolation trenches G2 in the first direction (e.g., the X direction) are etched to form a third accommodating hole H3, and the second isolation structure 4 on opposite sides of the third accommodating hole H3 in the first direction (e.g., the X direction) is exposed, while retaining a portion of the second sacrificial layer L2 in the interval between adjacent second isolation trenches G2 to form the first sub-gate 131.

[0264] Illustratively, the first sub-gate 131 is a polysilicon gate.

[0265] In step S540, refer to Figure 31 A second sub-gate 132 covering the first sub-gate 131 and a second word line WL2 correspondingly connected to the second sub-gate 132 are formed in the third receiving hole H3 .

[0266] Thus, the second gate 13 includes a first sub-gate 131 and a second sub-gate 132 .

[0267] For example, the second sub-gate 132 and the second word line WL2 are formed of a metal material, such as tungsten or copper, and are an integrated structure.

[0268] In step S600, refer to Figure 32 , the second sacrificial layer L2 located on the side of the second portion 112 of the semiconductor layer 11 away from the third portion 113 is removed to form a bit line accommodating groove G3.

[0269] Here, the bit line accommodating groove G3 can be formed by etching the outer wall of the second sacrificial layer L2 extending along the second direction (for example, the Y direction) on the side of the second part 112 of the semiconductor layer 11 away from the third part 113 until the second isolation structure 4 and the outer wall of the second part 112 are exposed.

[0270] For example, the second sacrificial layer L2 may be etched using a lateral etching process.

[0271] In step S700, refer to Figure 33 , a bit line BL is formed in the bit line receiving groove G3 , and the bit line BL is electrically connected to the second portion 112 of the semiconductor layer 11 .

[0272] For example, the materials forming the bit lines BL include, but are not limited to, silicon-based materials, metal-based materials, or combinations thereof. For example, the material of the bit lines BL includes polysilicon, metal, metal nitride, metal silicide, or combinations thereof. For example, the bit lines BL may have a single-layer structure of tungsten, titanium nitride, or polysilicon, or a stacked-layer structure of titanium nitride, tungsten, or the like.

[0273] For example, the bit line BL is formed by filling the bit line receiving groove G4 with a metal material, such as tungsten or copper.

[0274] It is worth mentioning that in some embodiments, see Figure 6 and Figure 34 , multiple memory cells U are arranged in columns along the second direction (eg, Y direction); wherein two columns of memory cells U can share the same bit line BL and are symmetrically distributed around the bit line BL. Accordingly, the stacking structure N can be as follows Figure 34 As shown in .

[0275] Based on this, when the aforementioned step S600 is specifically performed, the following method can be adopted: the outer wall of the second sacrificial layer L2 located on the same side of the second gate 13 and extending along the first direction (for example, the X direction) is etched until the second sacrificial layer L2 between the corresponding second isolation structures 4 in adjacent column storage cells U and the second sacrificial layer L2 between the corresponding second parts 112 are both removed, thereby forming a bit line accommodating groove G3.

[0276] In step S800, refer to Figure 35 , the second sacrificial layer L2 located on the side of the third portion 113 of the semiconductor layer 11 away from the second portion 112 is removed to form a capacitor accommodating groove G4.

[0277] Here, the capacitor accommodating groove G4 can be formed on the side of the third portion 113 of the semiconductor layer 11 away from the second portion 112 by etching the outer wall of the second sacrificial layer L2 extending along the second direction (for example, the Y direction) until the second isolation structure 4 and the outer wall of the third portion 113 are exposed.

[0278] For example, the second sacrificial layer L2 may be etched using a lateral etching process.

[0279] In addition, in the embodiment where the third isolation structure 5 is formed, the capacitor receiving groove G5 also exposes the third isolation structure 5 .

[0280] In step S900, refer to Figure 36 , a capacitor 2 is formed in the capacitor receiving groove G4 , and the capacitor 2 is electrically connected to the third portion 113 of the semiconductor layer 11 .

[0281] It can be understood that the manufacturing process of the capacitor 2 may be different depending on the structure of the matching capacitor 2.

[0282] In some embodiments, the structure of capacitor 2 is as follows Figure 37 As shown, it includes a stacked first electrode 21, a dielectric layer 22, and a second electrode 23. Accordingly, step S900 may include the following steps S910 to S930.

[0283] In step S910 , a first electrode 21 is formed to conformally cover the wall of the capacitor receiving groove G4 , so that the first electrode 21 can be in contact with and connected to the third portion 113 of the semiconductor layer 11 .

[0284] In step S920 , a dielectric layer 22 is formed to conformally cover the first electrode 21 .

[0285] For example, the dielectric layer 22 may be formed of silicon oxide, silicon nitride, a high-K dielectric material, or a combination thereof.

[0286] In step S930 , a second electrode 23 is formed on the surface of the dielectric layer 22 away from the first electrode 21 to fill the capacitor receiving groove G4 .

[0287] For example, the first electrode 21 and the second electrode 23 can be formed of metal materials, respectively. Furthermore, the materials of the first electrode 21 and the second electrode 23 can be the same or different.

[0288] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0289] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0290] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, and all such variations and improvements fall within the scope of protection of the present disclosure.

Claims

1. A storage unit, characterized in that: include: A transistor comprising: a semiconductor layer, a first gate, and a second gate; the semiconductor layer comprising a first portion extending along a first direction, and a second portion and a third portion respectively connected to both ends of the first portion and extending along a second direction; the second direction intersects the first direction, and a side of the second portion facing away from the third portion is electrically connected to a bit line; the first gate and the second gate are respectively located on opposite sides of the first portion in the second direction; a capacitor, located on a side of the third portion facing away from the second portion and electrically connected to the third portion; One of the first gate and the second gate includes a first sub-gate and a second sub-gate stacked in a direction away from the first portion and made of different materials.

2. The storage unit according to claim 1, wherein The first sub-gate is a polysilicon gate; The second sub-gate and the other of the first gate and the second gate are metal gates.

3. The storage unit according to claim 1 or 2, characterized in that The second portion and the third portion are located on the same side of the first portion; The first gate is located in a space enclosed by the first portion, the second portion, and the third portion, and is electrically connected to the first word line; The second gate is located on a side of the first portion away from the second portion and the third portion along the second direction, and includes the first sub-gate and the second sub-gate; the second sub-gate is electrically connected to the second word line.

4. The storage unit according to claim 3, wherein: Also includes: a first gate dielectric layer, located between the first gate and the first portion; a second gate dielectric layer, located between the first sub-gate and the first portion; Wherein, along the second direction, the thickness of the second gate dielectric layer is greater than the thickness of the first gate dielectric layer.

5. The storage unit according to claim 3, wherein: The bit line extends along the second direction; the capacitor protrudes from the third portion along the second direction toward the side where the second gate is located; The storage unit further includes: a first isolation structure located between the first gate and the second portion, and between the first gate and the third portion; a second isolation structure located between the second gate and the bit line, and between the second gate and the capacitor; The third isolation structure is located on the same side of the first gate, the third portion, the capacitor, and the first isolation structure between the first gate and the third portion, and is in contact with and connected to the first isolation structure between the first gate and the second portion. The storage unit according to claim 1 , wherein: Along the second direction, a length of the second portion is greater than a length of the third portion.

7. A memory, characterized in that: include: At least one storage unit according to any one of claims 1 to 6; at least one bit line; The bit line extends along the second direction and is electrically connected to the second portion of the memory cell; at least one first word line; The first word line extends along a third direction and is electrically connected to the first gate of the memory cell; at least one second word line; The second word line extends along the third direction and is electrically connected to the second gate of the memory cell; The third direction intersects with each of the first direction and the second direction.

8. The memory according to claim 7, wherein: There are multiple storage units, and two storage units arranged adjacent to each other in the second direction constitute a repeating unit; In the same repeating unit, the two storage units are mirror-symmetrical to each other, and the second parts of the two storage units are opposite to each other and connected to form an integral structure.

9. The memory according to claim 8, wherein: The memory cell includes: a first isolation structure located between the first gate and the second portion and between the first gate and the third portion; a third isolation structure located on the same side of the first isolation structure as the first gate, the third portion, the capacitor, and the first gate and the third portion, and in contact with and connected to the first isolation structure between the first gate and the second portion; In the same repeating unit, the first isolation structures between the first gate and the second portion of the two storage cells are opposite to each other and connected as an integral structure; the third isolation structures of the two storage cells are opposite to each other and connected as an integral structure.

10. A method for preparing a memory, characterized in that: include: forming a stacked structure comprising a plurality of first sacrificial layers and a plurality of second sacrificial layers alternately stacked; Etching the stack structure along the stacking direction of the first sacrificial layer and the second sacrificial layer to form a first receiving hole; forming a semiconductor layer on an inner sidewall of the second sacrificial layer in the first receiving hole; the semiconductor layer including a first portion extending along a first direction, and a second portion and a third portion connected to both ends of the first portion and extending along a second direction; the second direction intersecting the first direction; forming a first gate on a side of the first portion away from an inner sidewall of the second sacrificial layer; Etching the stacked structure on a side of the first portion facing away from the first gate, and forming a second gate on a side of the first portion facing away from the first gate; removing the second sacrificial layer located on a side of the second portion facing away from the third portion to form a bit line accommodating groove; forming a bit line in the bit line receiving groove and electrically connecting the bit line to the second portion; removing the second sacrificial layer located on a side of the third portion facing away from the second portion to form a capacitor accommodating groove; A capacitor is formed in the capacitor receiving groove, and the capacitor is electrically connected to the third portion.

11. The method for preparing a memory according to claim 10, wherein: The step of forming a semiconductor layer on the inner sidewall of the second sacrificial layer in the first receiving hole includes: forming a semiconductor material layer on the hole wall of the first receiving hole; Etching the outer sidewall of the first sacrificial layer extending along the second direction until the semiconductor material layer is exposed; etching the semiconductor material layer based on the removal area of ​​the first sacrificial layer extending along the second direction to remove the semiconductor material layer extending along the second direction between adjacent second sacrificial layers to form an initial semiconductor layer; Etching the outer sidewall of the first sacrificial layer extending along the first direction until the initial semiconductor layer is exposed; The initial semiconductor layer is etched based on the removal area of ​​the first sacrificial layer extending along the first direction to remove the initial semiconductor layer extending along the first direction between adjacent second sacrificial layers to form the semiconductor layers respectively located on the inner sidewalls of each second sacrificial layer.

12. The method for preparing a memory according to claim 11, wherein: Also includes: Before forming the semiconductor material layer on the hole wall of the first receiving hole, forming a first dielectric material layer on the hole wall of the first receiving hole; wherein the semiconductor material layer is formed on a surface of the first dielectric material layer away from the hole wall of the first receiving hole; While forming the semiconductor layer on the inner sidewall of the second sacrificial layer, the first dielectric material layer is etched to form a second gate dielectric layer between the inner sidewall of the second sacrificial layer and the semiconductor layer.

13. The method for preparing a memory according to claim 11, wherein: The method further includes etching the outer sidewall of the first sacrificial layer extending along the second direction until the semiconductor material layer is exposed: forming a second dielectric material layer covering the semiconductor material layer and filling the first receiving hole; Etching the second dielectric material layer and the stacked structure and the semiconductor material layer located on one side of the second dielectric material layer along the stacking direction of the first sacrificial layer and the second sacrificial layer to form a first isolation trench extending along the first direction, and making the remaining second dielectric material layer constitute an initial first isolation structure; forming a third isolation structure in the first isolation trench; The step of forming a first gate on a side of the first portion away from an inner sidewall of the second sacrificial layer comprises: Etching the initial first isolation structure along the stacking direction of the first sacrificial layer and the second sacrificial layer to form a second accommodating hole and the first isolation structures located on opposite sides of the second accommodating hole in the first direction, and exposing the semiconductor material layer and the third isolation structure located on opposite sides of the second accommodating hole in the second direction; Conformally forming a first gate dielectric layer on the wall of the second receiving hole; The first gate covering the first gate dielectric layer and filling the second receiving hole and a first word line correspondingly connected to the first gate are formed.

14. The method for preparing a memory according to any one of claims 11 to 13, wherein: Also includes: After etching the semiconductor material layer based on the removed area of ​​the first sacrificial layer extending along the second direction to form the initial semiconductor layer, backfilling the removed area of ​​the first sacrificial layer extending along the second direction and the etched area of ​​the semiconductor material layer with a first insulating material; After etching the initial semiconductor layer based on the removed region of the first sacrificial layer extending along the first direction to form the semiconductor layer, backfilling the removed region of the first sacrificial layer extending along the first direction and the etched region of the initial semiconductor layer with a second insulating material; The etching of the stacked structure on a side of the first portion facing away from the first gate and forming a second gate on a side of the first portion facing away from the first gate further includes: Etching the second sacrificial layer and the second insulating material on a side of the first portion facing away from the first gate along the stacking direction of the first sacrificial layer and the second sacrificial layer to form second isolation trenches extending along the second direction and spaced apart in the first direction, and exposing outer sidewalls of corresponding ends of the first portion and a portion of the first insulating material in the second isolation trenches; forming a second isolation structure in the second isolation trench; Etching the second sacrificial layer and the second insulating material in the space between adjacent second isolation trenches in the first direction along the stacking direction of the first sacrificial layer and the second sacrificial layer to form a third accommodating hole, exposing the second isolation structure on opposite sides of the third accommodating hole in the first direction, while retaining a portion of the second sacrificial layer in the space between adjacent second isolation trenches to form a first sub-gate; A second sub-gate covering the first sub-gate and a second word line correspondingly connected to the second sub-gate are formed in the third receiving hole; wherein the second gate includes the first sub-gate and the second sub-gate.

15. The method for preparing a memory according to claim 14, wherein: The step of removing the second sacrificial layer on a side of the second portion away from the third portion to form a bit line accommodating groove further comprises: etching an outer sidewall of the second sacrificial layer extending along the second direction on a side of the second portion away from the third portion until the second isolation structure and the outer sidewall of the second portion are exposed to form the bit line accommodating groove; The forming of the bit line in the bit line receiving groove further includes: filling the bit line receiving groove with a metal material to form the bit line.

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