Display substrate and display device

Abstract

The embodiment of the invention provides a display substrate and a display device, relates to the technical field of display, and is used for leading out a set data line from a display area to a binding area through a first fan-out line and a second fan-out line so as to reduce the frame width of one side of the binding area of the display substrate. The display substrate comprises a plurality of pixel circuits, a plurality of data lines, a first fan-out line and a second fan-out line, wherein the first fan-out line and the second fan-out line are arranged in a display area. At least one of the data lines is a set data line, and the second fan-out line is closer to the middle line, in the second direction, of the binding area than the set data line. And one column of pixel circuits is electrically connected with one data line. One end of the first fan-out line is electrically connected with the set data line, and the other end is electrically connected with the second fan-out line. And the second fan-out lines pass through the pixel circuits of the two adjacent sub-pixels in the set pixels corresponding to the second fan-out lines, or pass through the outer sides of the pixel circuits located on the outer sides in the set pixels corresponding to the second fan-out lines, and extend to the binding area. The display substrate is used for displaying images.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) display devices have gradually become one of the mainstream products in the display field due to their excellent performance such as self-luminescence, high contrast, wide viewing angle, fast response speed, can be used for flexible panels, wide operating temperature range, simple structure and process. OLED display substrates can be widely used in terminal products such as smartphones, tablets, TVs and wearable devices (such as watches). Among them, high pixel density (Pixels Per Inch, PPI) and narrow frame are currently an important development direction of OLED display devices. Summary of the invention

[0003] The purpose of the embodiments of the present disclosure is to provide a display substrate and a display device, which are used to lead the data lines of the parts of the display area close to the two ends of the binding area from the display area to the binding area through the first fan-out line and the second fan-out line, thereby reducing the border width on one side of the binding area of ​​the display substrate.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, a display substrate is provided. The display substrate has a display area and a binding area, and the binding area is located on one side of the display area along a second direction. The display substrate includes: a plurality of pixel circuits, a plurality of data lines, and a first fan-out line and a second fan-out line arranged in the display area. At least one of the plurality of data lines is a set data line, and the second fan-out line is closer to the midline of the binding area along the second direction than the set data line.

[0006] A plurality of pixel circuits are arranged in a plurality of rows and columns, a row of pixel circuits is arranged along a first direction, a column of pixel circuits is arranged along a second direction, and the first direction and the second direction intersect. A data line extends along the second direction, and a column of pixel circuits is electrically connected to a data line. A first fan-out line extends along the first direction, and a second fan-out line extends along the second direction. One end of the first fan-out line is electrically connected to a set data line, and the other end is electrically connected to the second fan-out line.

[0007] Wherein, the display substrate includes a plurality of pixels, each pixel includes at least three sub-pixels, and each sub-pixel includes a pixel circuit; at least one of the plurality of pixels is a setting pixel, and one setting pixel is correspondingly provided with at least one second fan-out line, and the second fan-out line passes between the pixel circuits of two adjacent sub-pixels in the corresponding setting pixel, or passes from the outside of the pixel circuit located on the outside of the corresponding setting pixel, and extends to the binding area.

[0008] In the above display substrate, a part of the data lines included in the display substrate directly extends to the binding area, and the other part is led out to the binding area through the first fan-out line and the second fan-out line, and the data lines are all led out from the display area, so that the data lines do not need to occupy the space on one side of the binding area, and the border width on the binding area side of the display substrate is reduced. At the same time, by setting the first fan-out line and the second fan-out line, the number of signal lines for transmitting data signals in the display area is increased, and the density of the signal lines for transmitting data signals is increased, so that the overall resistance of the signal lines for transmitting data signals is reduced, which is conducive to achieving the transmission stability and reliability of the data signal.

[0009] In some embodiments, the display substrate further includes: a first voltage signal line extending along the second direction. A set pixel is correspondingly provided with at least one first voltage signal line, and the first voltage signal line passes between pixel circuits of two adjacent sub-pixels in the corresponding set pixel, or passes from the outside of the pixel circuit located on the outside of the corresponding set pixel.

[0010] In some embodiments, among at least one second fan-out line and at least one first voltage signal line corresponding to a pixel, a second fan-out line passes between pixel circuits of a pair of adjacent sub-pixels, and a first voltage signal line passes between pixel circuits of another pair of adjacent sub-pixels.

[0011] In some embodiments, a pixel includes three sub-pixels. A second fan-out line and a first voltage signal line are set corresponding to the pixel, the second fan-out line passes between pixel circuits of a pair of adjacent sub-pixels among the three sub-pixels, and the first voltage signal line passes between pixel circuits of another pair of adjacent sub-pixels among the three sub-pixels.

[0012] In some embodiments, among the second fan-out lines and the first voltage signal lines corresponding to the set pixels, one first voltage signal line and one second fan-out line pass between pixel circuits of the same pair of adjacent sub-pixels.

[0013] In some embodiments, a pixel includes three sub-pixels. A second fan-out line and a first voltage signal line are set corresponding to the pixel, and the second fan-out line and the first voltage signal line pass between pixel circuits of the same pair of adjacent sub-pixels in the three sub-pixels.

[0014] In some embodiments, the second fan-out line is provided with a second break, and the second break divides the second fan-out line into an effective part and a redundant part. One end of the effective part of the second fan-out line is electrically connected to the first fan-out line, and the other end extends to the binding area. The display substrate also includes: a first connection portion, and the first voltage signal line and the redundant part of the second fan-out line are electrically connected through the first connection portion.

[0015] In some embodiments, the first voltage signal line and the second fan-out line passing through the pixel circuits of the same pair of adjacent sub-pixels are arranged adjacent to each other, and the first voltage signal line, the second fan-out line and the first connecting portion are arranged in the same layer and are integrally formed.

[0016] In some embodiments, the first fan-out line is provided with a first break, and the first break divides the first fan-out line into an effective part and a redundant part. One end of the effective part of the first fan-out line is electrically connected to the set data line, and the other end is electrically connected to the effective part of the second fan-out line. The display substrate also includes: a second connection part, one end of the second connection part is electrically connected to the redundant part of the first fan-out line; along the thickness direction of the display substrate, a via is provided between the second connection part and the redundant part of the second fan-out line, and the other end of the second connection part is electrically connected to the redundant part of the second fan-out line through the via.

[0017] In some embodiments, the second connection portion and the redundant portion of the first fan-out line are disposed in the same layer and are integrally formed.

[0018] In some embodiments, the display substrate further includes: a plurality of reference voltage signal lines extending along the second direction, and a column of pixel circuits is electrically connected to a reference voltage signal line. In two adjacent columns of pixel circuits, the reference voltage signal line connected to one column of pixel circuits and the data line connected to the other column of pixel circuits are arranged close to each other. The second fan-out line is arranged between the reference voltage signal line and the data line that are arranged close to each other.

[0019] In some embodiments, the first voltage signal line of the display substrate is disposed between the reference voltage signal line and the data line which are disposed close to each other.

[0020] In some embodiments, the display substrate further comprises: a substrate, a semiconductor layer disposed on the substrate, and a plurality of auxiliary reference voltage signal lines disposed on a side of the semiconductor layer away from the substrate. The auxiliary reference voltage signal lines extend along a first direction and are electrically connected to the reference voltage signal lines. The first fan-out line is disposed on a side of the auxiliary reference voltage signal line away from the substrate; in an orthographic projection onto the substrate, the first fan-out line overlaps with the auxiliary reference voltage signal line and partially overlaps with the semiconductor layer.

[0021] In some embodiments, the display substrate further includes: a plurality of second voltage signal lines extending along the second direction, and a column of pixel circuits is electrically connected to a second voltage signal line. The film layer where the plurality of second voltage signal lines are located is located on a side of the film layer where the first fan-out line is located away from the substrate, and in an orthographic projection onto the substrate, the second voltage signal line covers the first break of the first fan-out line.

[0022] In some embodiments, the display substrate further includes: a multi-layer source-drain conductive layer. A pair of adjacent source-drain conductive layers in the multi-layer source-drain conductive layer are respectively a first set source-drain conductive layer and a second set source-drain conductive layer, and the first set source-drain conductive layer is closer to the substrate than the second set source-drain conductive layer. The first fan-out line is provided in the first set source-drain conductive layer, and the data line and the second fan-out line are provided in the second set source-drain conductive layer.

[0023] In some embodiments, the display substrate further includes: a gate signal line, an enable signal line, an auxiliary first voltage signal line, and an auxiliary second voltage signal line, all extending along the first direction. The pixel circuit is electrically connected to the gate signal line and the enable signal line; the auxiliary first voltage signal line is electrically connected to the first voltage signal line, and the auxiliary second voltage signal line is electrically connected to the second voltage signal line.

[0024] The first set source-drain conductive layer is provided with at least one of a gate signal line, an enable signal line, an auxiliary first voltage signal line, and an auxiliary second voltage signal line. In the orthographic projection to the substrate, at least one of the gate signal line, the enable signal line, the auxiliary first voltage signal line, and the auxiliary second voltage signal line covers the second break of the second fan-out line.

[0025] In some embodiments, the first voltage signal line, the second voltage signal line and the reference voltage signal line of the display substrate are all disposed in the second set source-drain conductive layer.

[0026] In some embodiments, the display substrate further includes: a first gate layer and a second gate layer. The semiconductor layer, the first gate layer and the second gate layer of the display substrate are sequentially arranged in a direction away from the substrate and are located between the substrate and the multi-layer source and drain conductive layer. The auxiliary reference voltage signal line of the display substrate is arranged on the second gate layer.

[0027] In some embodiments, the multi-layer source-drain conductive layer includes a first source-drain conductive layer and a second source-drain conductive layer, the first source-drain conductive layer is a first set source-drain conductive layer, and the second source-drain conductive layer is a second set source-drain conductive layer.

[0028] In some embodiments, the multi-layer source-drain conductive layer includes a first source-drain conductive layer, a second source-drain conductive layer and a third source-drain conductive layer, the first source-drain conductive layer is a first set source-drain conductive layer, and the second source-drain conductive layer is a second set source-drain conductive layer.

[0029] In some embodiments, the multi-layer source-drain conductive layer includes a first source-drain conductive layer, a second source-drain conductive layer and a third source-drain conductive layer, the second source-drain conductive layer is a first set source-drain conductive layer, and the third source-drain conductive layer is a second set source-drain conductive layer.

[0030] In some embodiments, the set data line is further away from the center line of the binding area along the second direction than other data lines in the plurality of data lines. The set data line is entirely located in the display area, and ends of other data lines extend to the binding area.

[0031] In another aspect, a display device is provided, comprising: a display substrate as described in any one of the above embodiments, and a circuit board, the circuit board being electrically connected to the display substrate.

[0032] The above-mentioned display device has the same structure and beneficial technical effects as the display substrate provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0034] Figure 1 is a structural diagram of a display device according to some embodiments;

[0035] Figure 2 is another structural diagram of a display device according to some embodiments;

[0036] Figure 3 is a structural diagram of a pixel circuit according to some embodiments;

[0037] Figure 4 is a structural diagram of a pixel circuit according to some other embodiments;

[0038] Figure 5 is a partial enlarged structural diagram of a display area AA of a display substrate according to some embodiments;

[0039] Figure 6 Based on Figure 5 An enlarged structural diagram of region D in FIG.

[0040] Figure 7 Based on Figure 5 An enlarged structural diagram of region F in FIG.

[0041] Figure 8 A structural diagram of a first source-drain conductive layer to a second source-drain conductive layer of a display substrate according to some embodiments;

[0042] Fig. 9The first source-drain conductive layer of the display substrate according to some embodiments is Figure 8 An enlarged structural diagram of region E in FIG.

[0043] Fig.10 The second source-drain conductive layer of the display substrate according to some embodiments is Figure 8 An enlarged structural diagram of region E in FIG.

[0044] Fig.11 is an equivalent circuit diagram of a pixel circuit according to some embodiments;

[0045] Fig.12 is a cross-sectional structural diagram of a display substrate according to some embodiments;

[0046] Fig.13 is a structural diagram of a semiconductor layer of a display substrate according to some embodiments;

[0047] Fig.14 is a structural diagram of a display substrate from a semiconductor layer to a second gate layer according to some embodiments;

[0048] Fig.15 FIG. 4 is a structural diagram of a display substrate from a semiconductor layer to a first source-drain conductive layer according to some embodiments. DETAILED DESCRIPTION

[0049] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0050] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0051] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0052] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0053] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0054] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0055] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [a stated condition or event] is detected" are optionally interpreted to mean "upon determining that" or "in response to determining that" or "upon detecting [a stated condition or event]" or "in response to detecting [a stated condition or event]," depending on the context.

[0056] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0057] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0058] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0059] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0060] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0061] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0062] In the embodiments of the present disclosure, Figure 1 and Figure 2 FIG. 1 is a plan view of the structure of the display device 1000. In order to clearly describe the connection between the display substrate 100 and the circuit board 200, Figure 2 In the figure, the circuit board 200 is shown on the same side of the display area AA of the display substrate 100. It should be noted that in the finally formed display substrate 100, the circuit board 200 is bent to the other side.

[0063] In order to clearly describe the relative position relationship between the second fan-out line FIP2 and the first voltage signal line VSS and the pixel circuit 10, Figure 3 and Figure 4 Only a part of the pixel circuit 10 of the display substrate 100 is shown in the structure diagram. The number of pixel circuits 10 included in the actual display substrate 100 is not limited to that shown in the figure. Meanwhile, the film layer structure included in the display substrate 100 includes but is not limited to the film layer structure shown in the figure.

[0064] In order to clearly describe the transmission path of the data signal between the set data line DL1, the first fan-out line FIP1 and the second fan-out line FIP2, Figure 5 FIG. 4 shows a partial enlarged view of the display area AA, Figure 5 The direction indicated by the vertical arrow in FIG. 1 is the transmission path of the data signal transmitted through the second fan-out line FIP2 in the binding area BB. Figure 5 The direction indicated by the horizontal arrow in the figure is the transmission path of the data signal transmitted from the second fan-out line FIP2 to the first fan-out line FIP1. Figure 5 Three transmission paths of data signals of the set data line DL1 are identified. Figure 6 for Figure 5 The enlarged structure diagram of area D in Figure 7 for Figure 5 Enlarged structural diagram of area F in FIG.

[0065] In order to clearly describe the connection between the redundant part FIP12 of the first fan-out line FIP1 and the redundant part FIP22 of the second fan-out line FIP2 and the first voltage signal line VSS, Figure 8 Only the structure diagram of the first source-drain conductive layer to the second source-drain conductive layer is shown. Fig. 9 The first source-drain conductive layer is Figure 8 The enlarged structure diagram of area E in Fig.10 The second source-drain conductive layer is based on Figure 8 Enlarged structural diagram of area E in FIG.

[0066] Fig.11 is an equivalent circuit diagram of a pixel circuit according to some embodiments. Fig.12 is a cross-sectional structural diagram of a display substrate according to some embodiments.

[0067] Fig.13 FIG. 4 is a planar structural diagram of a semiconductor layer of a display substrate according to some embodiments. Fig.14 FIG. 4 is a structural diagram of a display substrate from a semiconductor layer to a second gate layer according to some embodiments. Fig.15 FIG. 4 is a structural diagram of a display substrate from a semiconductor layer to a first source-drain conductive layer according to some embodiments.

[0068] It should be noted that in order to clearly describe the pattern design of each film layer structure and the corresponding relationship between each film layer, Figures 3 to 10 ,and Figures 13 to 15 Only an enlarged structural schematic diagram of a partial area corresponding to some sub-pixels in each film layer structure of the display substrate is shown. The actual film layer structure of the display substrate 100 may also include other film layer structures, and the pattern design of each film layer structure includes but is not limited to that shown in the figure, and may also include other designs.

[0069] In order to clearly describe the connection between the functional film layers, Figure 3 , Figure 4 , Figures 6 to 8 , Fig.14 and Fig.15 The insulating dielectric layer ILD and the first planarization layer 61 shown in the figure are vias on the insulating dielectric layer ILD and the first planarization layer 61. In the actual film layer structure, the insulating dielectric layer ILD and the first planarization layer 61 are the film layers that entirely cover the display substrate 100, and vias are set on the insulating dielectric layer ILD and the first planarization layer 61 at the positions shown in the figure, so that the parts that need to be electrically connected between the second gate layer 32 and the first source-drain conductive layer 41, and between the first source-drain conductive layer 41 and the second source-drain conductive layer 42 can be connected correspondingly through the vias.

[0070] like Figure 1As shown, some embodiments of the present disclosure provide a display device 1000. The display device 1000 may be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is expected that the embodiments may be implemented in or associated with a variety of electronic devices, including but not limited to televisions, mobile phones, wearable devices, PDAs (Personal Digital Assistants), AR (Augmented Reality) devices, VR (Virtual Reality) devices, handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, clocks, calculators, television monitors, flat panel displays, computer monitors, in-vehicle displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc. For example, as Figure 1 As shown, the display device 1000 may be a mobile phone.

[0071] From the perspective of the light-emitting type of the display device 1000, the display device 1000 may be an OLED (Organic Light-Emitting Diode, or Organic Electroluminescence Display, organic light-emitting semiconductor) display device, a QLED (Quantum Dot Light Emitting Diodes, quantum dot electroluminescent diode) display device, an MLED (Mini Light Emitting Diodes, or Micro Light Emitting Diodes, micro light-emitting diode) display device, etc. From the perspective of the form of the display device 1000, the display device 1000 may be a flat display device, a curved display device, or a foldable display device, etc. From the perspective of the shape of the display device 1000, the display device 1000 may be rectangular or circular, etc. There is no limitation on this, and an adaptive design can be performed according to actual needs.

[0072] Some embodiments of the present disclosure are schematically described below using a rectangular and planar organic light emitting diode display device as an example, but the implementation methods of the present disclosure include but are not limited to this, and any other display device may also be considered as long as the same technical concept is applied.

[0073] In some embodiments, Figure 2 As shown, the display device 1000 includes a display substrate 100 and a circuit board 200. The circuit board 200 is electrically connected to the display substrate 100.

[0074] Exemplarily, the circuit board 200 is configured to transmit a driving signal to the display substrate 100 to drive the display substrate 100 to realize image display.

[0075] Exemplarily, the circuit board 200 may include a TCON (Timing Controller), a power management chip DC / DC, an adjustable resistor divider circuit (generating Vcom), and other driving circuits. The circuit board 200 may also include other circuit structures, which are not listed here one by one.

[0076] In some embodiments, the display device 1000 may further include an under-screen camera and an under-screen fingerprint sensor, so that the display device 1000 can realize various functions such as taking photos, recording videos, fingerprint recognition or face recognition, etc. There is no limitation to this, and an adaptive design can be performed according to actual needs.

[0077] In some embodiments, Figure 2 As shown, the display substrate 100 has a display area AA and a peripheral area AN at least located on one side of the display area AA along the second direction Y. The display substrate 100 includes a plurality of pixels P disposed in the display area AA, and each pixel P includes at least three sub-pixels P(x).

[0078] Exemplarily, the plurality of pixels P are arranged in a plurality of rows and columns.

[0079] For example, Figure 2 As shown, the display area AA is an area on the display substrate 100 for displaying images, the sub-pixel P(x) is the smallest light-emitting unit on the display substrate 100, and the sub-pixel P(x) is used to display images.

[0080] In some examples, multiple sub-pixels P(x) emit light of the same color, and the display substrate 100 may further include a color filter layer disposed on the light-emitting side of the multiple sub-pixels P(x), that is, the display substrate 100 adopts a COE (CF On Encapsulation) structure.

[0081] For example, multiple sub-pixels P(x) all emit light of colors such as white light, red light, green light or blue light. In this case, the colored light emitted by the sub-pixel P(x) remains the same color light after passing through the color filter layer, or is converted into other color light for emission. Therefore, when multiple sub-pixels P(x) emit the same color light, the display substrate 100 can achieve multi-color light output.

[0082] In other examples, multiple sub-pixels P(x) emit light of different colors. For example, multiple sub-pixels P(x) include red sub-pixels that emit red light, green sub-pixels that emit green light, and blue sub-pixels that emit blue light, thereby realizing multi-color light output of the display substrate 100.

[0083] It should be noted that each pixel P includes at least three sub-pixels P(x), that is, each pixel P may include three, four or more sub-pixels P(x), and the multiple sub-pixels P(x) included in each pixel P may be a row, a column or a group of sub-pixels P(x), and a group of sub-pixels P(x) may be a plurality of sub-pixels P(x) adjacent to each other, and the adjacent plurality of sub-pixels P(x) are arranged in a row, a column, an L-shape, a rectangle or a diamond, etc.

[0084] Meanwhile, the light emitting areas of the multiple sub-pixels P(x) included in each pixel P may be the same or different. The above is only an exemplary description and is not intended to limit the present disclosure. The specific adaptive design can be carried out according to actual needs.

[0085] The following description is made by taking the case where a plurality of sub-pixels P(x) included in each pixel P are arranged in a row along the first direction X as an example.

[0086] In some embodiments, Figure 2 As shown, the peripheral area AN is arranged around the display area AA. The gate driving circuit (such as Gate on Array, GOA for short), control signal lines (such as clock signal lines, power supply voltage signal lines, etc.) and binding driver chips (such as Source Driver IC, source driver chips) can be arranged in the peripheral area AN. The functions of the peripheral area AN include but are not limited to the above.

[0087] For example, Figure 2 As shown, the peripheral area AN includes a binding area BB, which is located on one side of the display area AA along the second direction Y. The binding area BB is adjacent to one side edge of the display area AA, and the binding area BB is adjacent to the lower side edge of the display area AA. The display substrate 100 is connected to an external driver in the binding area BB.

[0088] For example, the binding area BB is configured to lead out the signal lines (such as the data line DL, the first voltage signal line VSS and the reference voltage signal line VRef1, etc.) and bind them to the driving circuit board (such as the circuit board 200) or the driving chip. That is, the binding area BB is located on the side of the display substrate 100 for binding the driving circuit board or the driving chip.

[0089] In some embodiments, Figure 2As shown, the display substrate 100 includes: a plurality of pixel circuits 10 and a plurality of light-emitting devices 20. The plurality of pixel circuits 10 are arranged in a plurality of rows and columns, a row of pixel circuits 10 is arranged along a first direction X, and each row of pixel circuits 10 includes a plurality of pixel circuits 10 arranged at intervals along the first direction X; a column of pixel circuits 10 is arranged along a second direction Y, and each column of pixel circuits 10 includes a plurality of pixel circuits 10 arranged at intervals along the second direction Y. In other words, the first direction X is the row direction in which the plurality of pixel circuits 10 are arranged, and the second direction Y is the column direction in which the plurality of pixel circuits 10 are arranged. The first direction X and the second direction Y intersect.

[0090] Exemplarily, the first direction X is perpendicular to the second direction Y.

[0091] Exemplarily, each pixel circuit 10 is connected to a light emitting device 20 , and the pixel circuit 10 is configured to drive the light emitting device 20 connected thereto to emit light.

[0092] Exemplarily, the light-emitting device 20 includes, but is not limited to, OLED (Organic Light-Emitting Diode), Mini LED (Mini Light-Emitting Diode), Micro LED (Micro Light-Emitting Diode), and the like.

[0093] In some embodiments, Figure 2 and Figure 3 As shown, the display substrate 100 further includes: a plurality of data lines DL, a first fan-out line FIP1 and a second fan-out line FIP2. The data lines DL extend along the second direction Y, and a column of pixel circuits 10 is electrically connected to one data line DL. At least one of the plurality of data lines DL is a set data line DL1, and the second fan-out line FIP2 is closer to the center line of the binding area BB along the second direction Y than the set data line DL1.

[0094] The first fan-out line FIP1 and the second fan-out line FIP2 are provided in the display area AA, the first fan-out line FIP1 extends along the first direction X, and the second fan-out line FIP2 extends along the second direction Y. One end of the first fan-out line FIP1 is electrically connected to the setting data line DL1 , and the other end is electrically connected to the second fan-out line FIP2 .

[0095] Among them, Figure 2As shown, at least one of the multiple pixels P is a setting pixel PP, and one setting pixel PP is correspondingly provided with at least one second fan-out line FIP2. The second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP, or passes from the outside of the pixel circuit 10 located on the outside of the corresponding setting pixel PP, and extends to the binding area BB.

[0096] In some embodiments, Figure 2 As shown, compared with other data lines DL in the plurality of data lines DL, the set data line DL1 is further away from the center line of the binding area BB along the second direction Y. The set data line DL1 is entirely located in the display area AA, and the ends of other data lines DL extend to the binding area BB.

[0097] For example, Figure 2 As shown, the data line DL may include a first data line DL1 and a second data line DL2, wherein the first data line DL1 is a setting data line DL1. The setting data line DL1 is located in the display area AA and does not extend to the binding area BB; the second fan-out line FIP2 and the second data line DL2 extend to the binding area BB. The setting data line DL1, the first fan-out line FIP1 and the second fan-out line FIP2 are sequentially connected, and each first fan-out line FIP1 is respectively connected to a setting data line DL1 and a

[0098] The second fan-out line FIP2 is electrically connected.

[0099] In other words, the second data line DL2 directly extends to the binding area BB, and the data line DL1 is set as the data line DL in the display substrate 100 that needs to be led out to the binding area BB through the first fan-out line FIP1 and the second fan-out line FIP2 in sequence. This setting method can be called FIP (Fanout In Pixel, fan-out in pixel).

[0100] like Figure 2 As shown, the border width of one side of the display substrate 100 for binding the driver is, for example Figure 2 The width of the portion of the peripheral area AN below the display area AA is d1, and the size of the binding area BB along the second direction Y is d2, d1 ≥ d2. With such a design, the size d1 of the side of the peripheral area AN where the binding area BB is set can be reduced, which is conducive to achieving a narrow frame of the display device 1000.

[0101] By inserting the second fan-out line FIP2 in the pixel P or between adjacent pixels P, the set data line DL1 is led out to the binding area BB through the first fan-out line FIP1 and the second fan-out line FIP2, the number of signal lines for transmitting data signals in the display area AA is increased, and the density of signal lines for transmitting data signals is increased, so that the overall resistance of the signal lines for transmitting data signals is reduced, which is conducive to achieving the transmission stability and reliability of the data signal. At the same time, the newly added second fan-out line FIP2 is inserted between adjacent pixel circuits 10, respectively, to ensure the uniformity of the film structure of the display substrate 100, thereby ensuring the display effect of the display substrate 100.

[0102] For example, Figure 2 As shown, the pixel PP is set to include, for example, three sub-pixels P(x) arranged in sequence along the first direction X, for example, from Figure 2 From the left side to the right side in FIG, there are the first sub-pixel PP(1), the second sub-pixel PP(2), and the third sub-pixel PP(3).

[0103] In some examples, such as Figure 2 As shown, a second fan-out line FIP2 is correspondingly provided for a setting pixel PP in the display substrate 100 . The second fan-out line FIP2 passes through the outer side of the pixel circuit 10 located on the outer side of the corresponding setting pixel PP and extends to the binding area BB.

[0104] For example, the second fan-out line FIP2 passes through a side of the pixel circuit 10 of the first sub-pixel PP( 1 ) away from the pixel circuit 10 of the second sub-pixel PP( 2 ) and extends to the bonding area BB.

[0105] For another example, the second fan-out line FIP2 passes through a side of the pixel circuit 10 of the third sub-pixel PP(3) away from the pixel circuit 10 of the second sub-pixel PP(2), and extends to the bonding area BB.

[0106] In other examples, such as Figure 3 As shown, a second fan-out line FIP2 is correspondingly provided for a setting pixel PP in the display substrate 100 . The second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP and extends to the binding area BB.

[0107] For example, the second fan-out line FIP2 passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2), and extends to the bonding area BB; or Figure 3 As shown, the second fan-out line FIP2 passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3), and extends to the bonding area BB.

[0108] In some other examples, two second fan-out lines FIP2 are correspondingly arranged for one setting pixel PP in the display substrate 100 . The second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP and extends to the binding area BB.

[0109] For example, one second fan-out line FIP2 passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2), and extends to the binding area BB; another second fan-out line FIP2 passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3), and extends to the binding area BB.

[0110] In some other examples, a setting pixel PP in the display substrate 100 is correspondingly provided with three setting data lines DL1 and a second fan-out line FIP2, and the second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP and extends to the binding area BB.

[0111] For example, a second fan-out line FIP2 passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2), and extends to the binding area BB; another second fan-out line FIP2 passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3), and extends to the binding area BB; another second fan-out line FIP2 passes from the outside of the pixel circuit 10 located on the outside in the corresponding set pixel PP, and extends to the binding area BB.

[0112] In some other examples, four second fan-out lines FIP2 are correspondingly arranged for a set pixel PP in the display substrate 100, wherein, along the first direction X, the first second fan-out line FIP2 passes from the side of the pixel circuit 10 of the first sub-pixel PP(1) away from the second sub-pixel PP(2), and extends to the binding area BB; the second second fan-out line FIP2 passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2), and extends to the binding area BB; the third second fan-out line FIP2 passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3), and extends to the binding area BB; the fourth second fan-out line FIP2 passes from the side of the pixel circuit 10 of the third sub-pixel PP(3) away from the second sub-pixel PP(2), and extends to the binding area BB.

[0113] It can be understood that, when the setting pixel PP includes three sub-pixels P(x), and both sides of the setting pixel PP along the first direction X are adjacent to other pixels P, one or two second fan-out lines FIP2 may be included between two adjacent pixels P (one of which is the setting pixel PP). When two adjacent pixels P are both setting pixels PP, and the number of second fan-out lines FIP2 corresponding to one setting pixel PP is less than or equal to the number of sub-pixels P(x) included in the setting pixel PP, wherein a second fan-out line FIP2 corresponding to the first setting pixel PP is located between the two setting pixels PP, any one of the second fan-out lines FIP2 corresponding to the second setting pixel PP may be located between the two setting pixels PP, or between the sub-pixels P(x) in the second setting pixel PP, or on the side of the second setting pixel PP away from the first setting pixel PP.

[0114] By setting the first fan-out line FIP and the second fan-out line FIP2, the data line DL corresponding to at least a part of the multiple sub-pixels P(x) included in the pixel PP is led out from the display area AA to the binding area BB through the second fan-out line FIP2 instead of being led out from the peripheral area AN to the binding area BB, thereby reducing the wiring area of ​​the data line DL in the peripheral area AN and reducing the dimension d1 of the side of the peripheral area AN where the binding area BB is set along the second direction Y, thereby achieving a narrow frame of the display device 1000.

[0115] It should be noted that the outer side of the pixel circuit 10 located on the outer side of the setting pixel PP refers to between the setting pixel PP and another pixel P adjacent to the setting pixel PP, and the other pixel P may also be the setting pixel PP.

[0116] The above is only an exemplary description and is not intended to limit the present disclosure. Each set pixel PP may also include four, five or more sub-pixels P(x). In some examples, the number of second fan-out lines FIP2 corresponding to each set pixel PP is less than or equal to the number of sub-pixels P(x) included therein, and the second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding set pixel PP, or passes from the outside of the pixel circuit 10 located on the outside of the corresponding set pixel PP, and extends to the binding area BB. In other examples, the number of second fan-out lines FIP2 corresponding to each set pixel PP is greater than the number of sub-pixels P(x) included therein, and a portion of the second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding set pixel PP, and another portion passes from the outside of the pixel circuit 10 located on the outside of the corresponding set pixel PP, and extends to the binding area BB.

[0117] For example, Figure 2 As shown, the data line DL needs to extend to the binding area BB and be bound and connected to a driver (such as a driver circuit board or a driver chip, etc.) in the binding area BB. The driver transmits a data signal to the data line DL so that the pixel circuit 10 can drive the light-emitting device 20 to emit light.

[0118] like Figure 2 As shown, along the first direction X, the size of the binding area BB is, for example, smaller than the size of the display area AA, and along the second direction Y, the binding area BB may be arranged opposite to the middle area of ​​the display area AA. The data lines DL located at the edges of both sides of the display area AA along the first direction X are set data lines DL1 (first data lines DL1), and the data lines DL located in the middle area of ​​the display area AA along the first direction X are second data lines DL2.

[0119] In some embodiments, the display substrate does not include the first fan-out line FIP1 and the second fan-out line FIP2, and an end of the data line DL1 close to the binding area BB is set to extend toward the peripheral area AN and converge toward the binding area BB. Figure 2 In the display substrate 100, along the first direction X, the size of the binding area BB is smaller than the size of the display area AA. In this way, the portion of the data line DL1 located in the peripheral area AN and extending into the binding area BB will occupy the space in the peripheral area AN, so that the portion of the peripheral area AN on the side where the binding area BB is set is larger in the second direction Y, and the border width of the side of the display substrate 100 used for binding the driver is larger.

[0120] In other embodiments, Figure 2 As shown, along the second direction Y, the second data line DL2 is arranged opposite to the binding area BB, and the setting data line DL1 is located on both sides of the second data line DL2 along the first direction X. In this way, along the first direction X, the first data line DL1 located on both sides of the binding area BB is led out to the binding area BB through the first fan-out line FIP1 and the second fan-out line FIP2, and the second data line DL2 arranged opposite to the binding area BB is directly led out to the binding area BB.

[0121] Use Figure 2 In the design shown, multiple data lines DL (set data line DL1 and second data line DL2) are led out from the display area AA to the binding area BB. The data lines DL do not occupy the space in the peripheral area AN, which is beneficial to reducing the size d2 of the part of the peripheral area AN on one side of the binding area BB, thereby realizing a narrow frame of the display device 1000.

[0122] It should be noted that in the display substrate 100, the number of binding areas BB can be multiple. For example, in a large-size display device (such as a TV or a computer, etc.), the display substrate 100 may include multiple binding areas BB, and the data lines DL arranged relative to the binding areas BB along the second direction Y can be considered as the second data lines DL2, and the remaining data lines DL can be considered as the first data lines DL1 (set data lines DL1). Of course, the way of distinguishing the first data lines DL1 and the second data lines DL2 is not limited to this, and the first data lines DL1 and the second data lines DL2 can also be arranged in different areas as needed.

[0123] In some embodiments, Figure 3 As shown, the display substrate 100 further includes: a first voltage signal line VSS extending along the second direction Y. At least one first voltage signal line VSS is correspondingly provided for one setting pixel PP, and the first voltage signal line VSS passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP, or passes from the outside of the pixel circuit 10 located on the outside of the corresponding setting pixel PP.

[0124] The following description takes the case where the pixel PP includes a first sub-pixel PP(1), a second sub-pixel PP(2) and a third sub-pixel PP(3) sequentially arranged along the first direction X as an example.

[0125] In some examples, a first voltage signal line VSS is correspondingly disposed to a setting pixel PP in the display substrate 100 , and the first voltage signal line VSS passes through the outside of the pixel circuit 10 located outside of the corresponding setting pixel PP.

[0126] For example, the first voltage signal line VSS passes through a side of the pixel circuit 10 of the first sub-pixel PP( 1 ) away from the pixel circuit 10 of the second sub-pixel PP( 2 ).

[0127] For another example, the first voltage signal line VSS passes through a side of the pixel circuit 10 of the third sub-pixel PP( 3 ) away from the pixel circuit 10 of the second sub-pixel PP( 2 ).

[0128] In other examples, such as Figure 3 As shown, a setting pixel PP in the display substrate 100 is correspondingly provided with a first voltage signal line VSS, and the first voltage signal line VSS passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP.

[0129] For example, Figure 3As shown, the first voltage signal line VSS passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2); or, the first voltage signal line VSS passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3).

[0130] In some other examples, two first voltage signal lines VSS are correspondingly provided to one setting pixel PP in the display substrate 100 , and the first voltage signal line VSS passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP.

[0131] For example, a first voltage signal line VSS passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2); another first voltage signal line VSS passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3).

[0132] In some further examples, three first voltage signal lines VSS are correspondingly provided for one setting pixel PP in the display substrate 100 , and the first voltage signal line VSS passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP.

[0133] For example, a first voltage signal line VSS passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2); another first voltage signal line VSS passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3); and another first voltage signal line VSS passes from the outside of the pixel circuit 10 located on the outside in the corresponding set pixel PP.

[0134] In some other examples, four first voltage signal lines VSS are correspondingly arranged for a set pixel PP in the display substrate 100, wherein, along the first direction X, the first first voltage signal line VSS passes from a side of the pixel circuit 10 of the first sub-pixel PP(1) away from the second sub-pixel PP(2); the second first voltage signal line VSS passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2); the third first voltage signal line VSS passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3); and the fourth first voltage signal line VSS passes from a side of the pixel circuit 10 of the third sub-pixel PP(3) away from the second sub-pixel PP(2).

[0135] It can be understood that, when the setting pixel PP includes three sub-pixels P(x), and both sides of the setting pixel PP along the first direction X are adjacent to other pixels P, one or two first voltage signal lines VSS may be included between two adjacent pixels P (one of which is the setting pixel PP). When two adjacent pixels P are both setting pixels PP, and the number of first voltage signal lines VSS corresponding to the setting pixel PP is less than or equal to the number of sub-pixels P(x) included in the setting pixel PP, wherein a first voltage signal line VSS corresponding to the first setting pixel PP is located between the two setting pixels PP, any one of the first voltage signal lines VSS corresponding to the second setting pixel PP may be located between the two setting pixels PP, or between the sub-pixels P(x) in the second setting pixel PP, or on the side of the second setting pixel PP away from the first setting pixel PP.

[0136] By inserting the first voltage signal line VSS in the setting pixel PP, or between the setting pixel PP and the pixel P adjacent to it (or another setting pixel PP), the number of wiring lines of the first voltage signal line VSS in the display area AA is increased, and the density of the first voltage signal line VSS in the display area AA is increased, thereby reducing the overall resistance of the first voltage signal line VSS, which is beneficial to reducing the voltage drop of the first voltage signal line VSS and ensuring the transmission stability and reliability of the first voltage signal.

[0137] In some embodiments, Figure 3 As shown, among the at least one second fan-out line FIP2 and the at least one first voltage signal line VSS corresponding to the pixel PP, a second fan-out line FIP2 passes between the pixel circuits 10 of a pair of adjacent sub-pixels P(x), and a first voltage signal line VSS passes between the pixel circuits 10 of another pair of adjacent sub-pixels P(x).

[0138] By inserting the second fan-out line FIP2 and the first voltage signal line VSS between the pixel circuits 10 of adjacent sub-pixels P(x) within the set pixel PP, the density of signal lines for transmitting the first voltage signal and the data signal within the display area AA is increased, thereby reducing the overall resistance of the first voltage signal line VSS and the data line DL, which is beneficial to reducing the voltage drop of the first voltage signal line VSS and the data line DL, and ensuring the transmission stability and reliability of the first voltage signal and the data signal.

[0139] For example, Figure 3As shown, each pixel P includes three sub-pixels P(x). A second fan-out line FIP2 and a first voltage signal line VSS are provided corresponding to the set pixel PP, the second fan-out line FIP2 passes through the pixel circuits 10 of a pair of adjacent sub-pixels P(x) among the three sub-pixels P(x), and the first voltage signal line VSS passes through the pixel circuits 10 of another pair of adjacent sub-pixels P(x) among the three sub-pixels P(x).

[0140] For example, Figure 3 As shown, the set pixel PP includes a first sub-pixel P(1), a second sub-pixel P(2) and a third sub-pixel P(3) arranged in sequence along the first direction X. The first voltage signal line VSS passes between the pixel circuits 10 of the first sub-pixel P(1) and the second sub-pixel P(2), and the second fan-out line FIP2 passes between the pixel circuits 10 of the second sub-pixel P(2) and the third sub-pixel P(3), and extends to the binding area BB.

[0141] It should be noted that, in the case where each pixel P includes three sub-pixels P(x), the second fan-out line FIP2 may pass between the pixel circuits 10 of the first sub-pixel P(1) and the second sub-pixel P(2) and extend to the binding area BB; the first voltage signal line VSS may pass between the pixel circuits 10 of the second sub-pixel P(2) and the third sub-pixel P(3).

[0142] In some embodiments, Figure 4 As shown, among the second fan-out lines FIP2 and the first voltage signal lines VSS corresponding to the pixel PP, one first voltage signal line VSS and one second fan-out line FIP2 pass between the pixel circuits 10 of the same pair of adjacent sub-pixels P(x).

[0143] Exemplarily, the pixel circuit 10 includes, for example, a plurality of TFTs (Thin Film Transistors), at least one capacitor, and at least one connection node. Part of the connection nodes (e.g. Fig.11 The fifth node N5 shown in FIG. 1 plays a key role in the operation of the pixel circuit 10. The specific structure of the pixel circuit 10 is described later and will not be described here.

[0144] By setting a first voltage signal line VSS corresponding to the set pixel PP and a second fan-out line FIP2 to pass through the pixel circuits 10 of the same pair of adjacent sub-pixels P(x), the wiring density of the signal line for transmitting the first voltage signal in the display area AA is increased, the resistance of the signal line for transmitting the first voltage signal in the display area AA is reduced, and the voltage drop of the first voltage signal is reduced.

[0145] At the same time, the first voltage signal line VSS serves as a constant voltage signal line, which can play a signal shielding effect, thereby preventing the data signal transmitted by the second fan-out line FIP2 passing through the pixel circuits 10 of adjacent sub-pixels P(x) from generating signal crosstalk with the nodes within the pixel circuit 10, thereby ensuring the normal operation of the pixel circuit 10.

[0146] For example, Figure 4 As shown, the pixel P includes three sub-pixels P(x). The pixel PP is set to be correspondingly provided with a second fan-out line FIP2 and a first voltage signal line VSS, and the second fan-out line FIP2 and the first voltage signal line VSS pass through the pixel circuits 10 of the same pair of adjacent sub-pixels P(x) among the three sub-pixels P(x).

[0147] For example, Figure 4 As shown, the pixel PP is set to include a first sub-pixel P(1), a second sub-pixel P(2) and a third sub-pixel P(3) arranged in sequence along the first direction X. The first voltage signal line VSS and the second fan-out line FIP2 both pass between the pixel circuits 10 of the first sub-pixel P(1) and the second sub-pixel P(2).

[0148] It should be noted that, when each pixel P includes three sub-pixels P(x), the first voltage signal line VSS and the second fan-out line FIP2 may also pass between the pixel circuits 10 of the second sub-pixel P(2) and the third sub-pixel P(3).

[0149] In some embodiments, Figure 6 As shown, the second fan-out line FIP2 is provided with a second break DK2, which divides the second fan-out line FIP2 into an effective part FIP21 and a redundant part FIP22. One end of the effective part FIP21 of the second fan-out line FIP2 is electrically connected to the first fan-out line FIP1, and the other end extends to the bonding area BB.

[0150] For example, Figure 6 As shown, the second break DK2 divides the second fan-out line FIP2 into an effective part FIP21 and a redundant part FIP22 which are electrically insulated from each other, see Figure 2 and Figure 5 , one end of the effective portion FIP21 of the second fan-out line FIP2 (eg Figure 2 The first fan-out line FIP1 is electrically connected to the binding area BB through the effective part FIP21 of the second fan-out line FIP2 and the lower end shown in FIG. 1 , and the other end is connected to the first fan-out line FIP1. The side of the effective part FIP21 of the second fan-out line FIP2 away from the binding area BB is electrically insulated from the redundant part FIP22 of the second fan-out line FIP2. That is, the first fan-out line FIP1 is electrically connected to the effective part FIP21 of the second fan-out line FIP2, and extends to the binding area BB through the effective part FIP21 of the second fan-out line FIP2.

[0151] The second fan-out line FIP2 is divided into an effective part FIP21 and a redundant part FIP22 which are electrically insulated from each other through the second break DK2. The data signal is emitted from the driver bound in the binding area BB, and is transmitted to the corresponding sub-pixel P(x) in sequence through the effective part FIP21 of the second fan-out line FIP2, the first fan-out line FIP1 and the set data line DL1. In this way, the transmission path of the data signal does not pass through the redundant part FIP22 of the second fan-out line FIP2, which is beneficial to shortening the transmission path of the data signal on the second fan-out line FIP2, thereby reducing the voltage drop of the data signal during the transmission process on the second fan-out line FIP2, preventing signal distortion caused by the voltage drop, and ensuring the accuracy of data signal transmission.

[0152] It should be noted that the redundant part FIP22 of the second fan-out line FIP2 may be configured not to transmit signals, or configured to transmit signals other than data signals.

[0153] In some embodiments, Figure 8 and Fig.10 As shown, the display substrate 100 further includes a first connection portion LJ1, through which the first voltage signal line VSS and the redundant portion FIP22 of the second fan-out line FIP2 are electrically connected. The redundant portion FIP22 of the second fan-out line FIP2 is configured to transmit a first voltage signal.

[0154] The redundant part FIP22 of the second fan-out line FIP2 is connected to the first voltage signal line VSS through the first connection part LJ1, thereby increasing the wiring area of ​​the first voltage signal line VSS in the display area AA, so that the density of the first voltage signal line VSS in the display area AA is increased, which is beneficial to reducing the resistance of the first voltage signal line VSS, and further reducing the voltage drop of the first voltage signal line VSS.

[0155] In some embodiments, Figure 4 , Figure 8 and Fig.10 As shown, the first voltage signal line VSS and the second fan-out line FIP2 passing through the pixel circuits 10 of the same pair of adjacent sub-pixels P(x) are arranged adjacent to each other, and the first voltage signal line VSS, the second fan-out line FIP2 and the first connecting portion LJ1 are arranged in the same layer and are integrally formed.

[0156] For example, in the preparation process of the display substrate 100, a conductive structure layer is first formed by a sputtering process, and then the conductive structure layer is patterned by an etching process, so as to form the connected first voltage signal line VSS, the first connection part LJ1 and the second fan-out line FIP2. In this way, the first voltage signal line VSS, the second fan-out line FIP2 and the first connection part LJ1 are formed at the same time in the same preparation step, and the first voltage signal line VSS, the first connection part LJ1 and the second fan-out line FIP2 are connected to each other as an integrated structure, and there is no need to set up other structures to connect the three. While adding the first connection part LJ1 and the second fan-out line FIP2, there is no need to increase the preparation process steps of the display substrate 100, which is conducive to reducing production costs.

[0157] It should be noted that the preparation process of the first voltage signal line VSS, the first connection portion LJ1 and the second fan-out line FIP2 may also adopt other methods, which are only exemplary descriptions and are not intended to limit the present disclosure.

[0158] In some embodiments, Figure 6 As shown, the first fan-out line FIP1 is provided with a first break DK1, which divides the first fan-out line FIP1 into an effective part FIP11 and a redundant part FIP12. One end of the effective part 11 of the first fan-out line FIP1 is electrically connected to the set data line DL1, and the other end is electrically connected to the effective part FIP21 of the second fan-out line FIP2.

[0159] For example, Figure 6 As shown, the first break DK1 divides the first fan-out line FIP1 into an effective part FIP11 and a redundant part FIP12 which are electrically insulated from each other, see Figure 2 and Figure 5 , one end of the effective portion FIP11 of the first fan-out line FIP1 (eg Figure 2 The first fan-out line FIP1 has a first active portion FIP21 and a second active portion FIP221, and the second fan-out line FIP2 extends to the binding area BB, and the other end is connected to the second fan-out line FIP2. The side of the active portion FIP21 of the first fan-out line FIP1 away from the binding area BB is electrically insulated from the redundant portion FIP12 of the first fan-out line FIP1. That is, the active portion FIP11 of the first fan-out line FIP1 is electrically connected to the active portion FIP21 of the second fan-out line FIP2, and extends to the binding area BB through the active portion FIP21 of the second fan-out line FIP2.

[0160] The first fan-out line FIP1 is divided into an effective part FIP11 and a redundant part FIP12 which are electrically insulated from each other through the first break DK1. The data signal is emitted from the driver bound in the binding area BB, and is transmitted to the corresponding sub-pixel P(x) in sequence through the effective part FIP21 of the second fan-out line FIP2, the effective part FIP11 of the first fan-out line FIP1 and the set data line DL1. In this way, the transmission path of the data signal does not pass through the redundant part FIP22 of the second fan-out line FIP2 and the redundant part FIP12 of the first fan-out line FIP1, which is beneficial to shortening the transmission path of the data signal on the first fan-out line FIP1 and the second fan-out line FIP2, thereby reducing the voltage drop of the data signal during the transmission process on the first fan-out line FIP1 and then the second fan-out line FIP2, preventing signal distortion caused by the voltage drop, and ensuring the accuracy of data signal transmission.

[0161] In some embodiments, Figure 8 and Fig. 9 As shown, the display substrate 100 further includes: a second connection portion LJ2. Along the thickness direction of the display substrate 100, a via K is provided between the second connection portion LJ2 and the redundant portion FIP22 of the second fan-out line FIP2, one end of the second connection portion LJ2 is electrically connected to the redundant portion FIP12 of the first fan-out line FIP1, and the other end of the second connection portion LJ2 is electrically connected to the redundant portion FIP22 of the second fan-out line FIP2 through the via K.

[0162] Exemplarily, the first fan-out line FIP1 and the second fan-out line FIP2 are located in different film layer structures, that is, along the thickness direction of the display substrate 100 , the film layer structures where the first fan-out line FIP1 and the second fan-out line FIP2 are located are at different distances from the display substrate 100 .

[0163] An insulating spacer layer, such as a planarization layer 6, may be further included between the first fan-out line FIP1 and the second fan-out line FIP2. The first fan-out line FIP1 and the second fan-out line FIP2 are electrically insulated from each other. A via K is provided on the planarization layer 6 corresponding to a portion between the redundant portion FIP22 of the second fan-out line FIP2 and one end close to the second connection portion LJ2, so that one end of the second connection portion LJ2 is connected to the redundant portion FIP22 of the second fan-out line FIP2 through the via K. In this way, the redundant portion FIP12 of the first fan-out line FIP1 is connected to the redundant portion FIP22 of the second fan-out line FIP2 through the second connection portion LJ2, thereby increasing the wiring area of ​​the first voltage signal line VSS in the display area AA, thereby increasing the density of the first voltage signal line VSS in the display area AA, and the redundant portion FIP12 of the first fan-out line FIP1 is provided in parallel with the redundant portion FIP22 of the second fan-out line FIP2, thereby reducing the resistance of the first voltage signal line VSS, thereby reducing the voltage drop of the first voltage signal line VSS.

[0164] In some embodiments, Fig. 9 As shown, the second connection portion LJ2 and the redundant portion FIP12 of the first fan-out line FIP1 are arranged in the same layer and are integrally formed.

[0165] For example, in the preparation process of the display substrate 100, a conductive structure layer is first formed by a sputtering process, and then, for example, the conductive structure layer is patterned by an etching process, so as to form the redundant part FIP12 and the second connection part LJ2 of the first fan-out line FIP1 that are connected. In this way, the redundant part FIP12 and the second connection part LJ2 of the first fan-out line FIP1 are formed at the same time in the same preparation step, and the second connection part LJ2 and the redundant part FIP12 of the first fan-out line FIP1 are an integral structure connected to each other, and there is no need to set up other structures to connect the two. While the redundant part FIP12 and the second connection part LJ2 of the first fan-out line FIP1 are added, there is no need to increase the preparation process steps of the display substrate 100, which is conducive to reducing production costs.

[0166] It should be noted that the redundant part FIP12 of the first fan-out line FIP1 and the second connection part LJ2 may also be prepared by other methods, which are only illustrative and not intended to limit the present disclosure.

[0167] In some embodiments, Figure 3 and Figure 4 As shown, the display substrate 100 further includes: a plurality of reference voltage signal lines VRef1. The reference voltage signal line VRef1 extends along the second direction Y, and a column of pixel circuits 10 is electrically connected to a reference voltage signal line VRef1. In two adjacent columns of pixel circuits 10, the reference voltage signal line VRef1 connected to one column of pixel circuits 10 and the data line DL connected to the other column of pixel circuits 10 are arranged close to each other. The second fan-out line FIP2 is arranged between the reference voltage signal line VRef1 and the data line DL which are arranged close to each other.

[0168] For example, Figure 3 and Figure 4 As shown, each column of pixel circuits 10 is electrically connected to a data line DL and a reference voltage signal line VRef1, respectively. A column of pixel circuits 10 extends along the second direction Y, and the data line DL and the reference voltage signal line VRef1 correspondingly connected to the column of pixel circuits 10 are located on both sides of the pixel circuit 10 along the first direction X. A second fan-out line FIP2 is inserted into two adjacent columns of pixel circuits 10 to lead the set data line DL1 from the display area AA to the binding area BB.

[0169] In some embodiments, Figure 3 and Figure 4As shown, the first voltage signal line VSS of the display substrate 100 is disposed between the reference voltage signal line VRef1 and the data line DL which are disposed close to each other.

[0170] For example, Figure 3 and Figure 4 As shown, the data line DL and the reference voltage signal line VRef1 corresponding to a column of pixel circuits 10 are located on both sides of the pixel circuit 10 along the first direction X. A first voltage signal line VSS is inserted into two adjacent columns of pixel circuits 10, which increases the density of the first voltage signal lines VSS in the display area AA, thereby reducing the overall resistance of the first voltage signal lines VSS, which is beneficial to reducing the voltage drop of the first voltage signal lines VSS, and ensuring the transmission stability and reliability of the first voltage signal.

[0171] In some embodiments, Fig.11 As shown, the pixel circuit 10 includes a plurality of transistors TFT and at least one capacitor.

[0172] Exemplarily, the pixel circuit 10 may be a "3T1C" circuit, a "7T1C" circuit, an "8T1C" circuit, or a "9T2C" circuit, etc., wherein "T" refers to a TFT, and the number before "T" refers to the number of TFTs; "C" refers to a capacitor, and the number before "C" refers to the number of capacitors. In the embodiments of the present disclosure, the pixel circuit 10 is a "9T2C" circuit as an example for schematic description, but the embodiments of the present disclosure are not limited thereto, and any other pixel circuit 10 may also be considered as long as the same technical concept is applied.

[0173] For example, Fig.11 , which is an equivalent circuit diagram of a pixel circuit 10 in a 9T2C mode. In this case, the pixel circuit 10 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1 and a second capacitor C2, and signal lines electrically connected to the pixel circuit 10 (e.g., a data signal line DL, a first enable signal line EM1, a second enable signal line EM2, an initialization signal line Vinit, a first voltage signal line VSS, a second voltage signal line VDD, etc.).

[0174] For example, Fig.11 As shown, each pixel circuit 10 is correspondingly connected to three gate signal lines GL, namely a first gate signal line GL1 , a second gate signal line GL2 , and a third gate signal line GL3 .

[0175] A gate of the first transistor T1 is electrically connected to the third gate signal line GL3 , a first electrode of the first transistor T1 is electrically connected to the first initialization signal line Vinit1 , and a second electrode of the first transistor T1 is electrically connected to the first node N1 .

[0176] A gate of the second transistor T2 is electrically connected to the second gate signal line GL2 , a first electrode of the second transistor T2 is electrically connected to the first node N1 , and a second electrode of the second transistor T2 is electrically connected to the third node N3 .

[0177] A gate of the third transistor T3 is electrically connected to the first node N1 , a first electrode of the third transistor T3 is electrically connected to the second node N2 , and a second electrode of the third transistor T3 is electrically connected to the third node N3 .

[0178] A gate of the fourth transistor T4 is electrically connected to the first gate signal line GL1 , a first electrode of the fourth transistor T4 is electrically connected to the data signal line DL, and a second electrode of the fourth transistor T4 is electrically connected to the fifth node N5 .

[0179] A gate of the fifth transistor T5 is electrically connected to the first enable signal line EM1 , a first electrode of the fifth transistor T5 is electrically connected to the second voltage signal line VDD, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2 .

[0180] A gate of the sixth transistor T6 is electrically connected to the second enable signal line EM2 , a first electrode of the sixth transistor T6 is electrically connected to the third node N3 , and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4 .

[0181] A gate of the seventh transistor T7 is electrically connected to the scan signal line Scan, a first electrode of the seventh transistor T7 is electrically connected to the second initialization signal line Vinit2, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4.

[0182] A gate of the eighth transistor T8 is electrically connected to the scan signal line Scan, a first electrode of the eighth transistor T8 is electrically connected to the second reference voltage signal line VRef2, and a second electrode of the eighth transistor T8 is electrically connected to the second node N2.

[0183] A gate of the ninth transistor T9 is electrically connected to the second gate signal line GL2 , a first electrode of the ninth transistor T9 is electrically connected to the first reference voltage signal line VRef1 , and a second electrode of the ninth transistor T9 is electrically connected to the fifth node N5 .

[0184] The first plate C11 of the first capacitor C1 is electrically connected to the fifth node N5, and the second plate C12 of the first capacitor C1 is electrically connected to the first node N1.

[0185] The first plate C21 of the second capacitor C2 is electrically connected to the fifth node N5, and the second plate C22 of the second capacitor C2 is electrically connected to the second voltage signal line VDD.

[0186] The fifth node N5 is electrically connected to the first capacitor C1 and the second capacitor C2, and a voltage change of the fifth node N5 may cause a change in the storage voltages of the first capacitor C1 and the second capacitor C2.

[0187] In some embodiments, Fig.12 As shown, the display substrate 100 includes a substrate 1, a semiconductor layer 2, a multi-layer gate layer 3 and a multi-layer source-drain conductive layer 4. The multi-layer source-drain conductive layer 4 can be collectively referred to as a functional film layer in the display substrate 100, each functional film layer has a set conductive pattern, and adjacent functional film layers are separated by an insulating film layer structure.

[0188] Exemplarily, the substrate 1 may be a rigid substrate, the material of which includes but is not limited to glass. Alternatively, the substrate 1 may be a flexible substrate, the material of which includes but is not limited to any one of PI (Polyimide), PC (Polycarbonate) or PVC (Polyvinyl Chloride).

[0189] For example, Fig.12 and Fig.13 As shown, the semiconductor layer 2 includes an active layer pattern. Fig.13 As shown, the active layer pattern includes an active layer 21 of each transistor TFT.

[0190] In some examples, the thin film transistor TFT may be a low temperature polysilicon thin film transistor, that is, the semiconductor layer 2 is made of low temperature polysilicon.

[0191] In some other examples, the thin film transistor TFT may also be an oxide thin film transistor, that is, the semiconductor layer 2 is made of metal oxide, such as indium gallium zinc oxide or indium gallium tin oxide.

[0192] In some embodiments, Fig.12 As shown, the multi-layer gate layer 3 includes a first gate layer 31 and a second gate layer 32 which are sequentially arranged from one side of the substrate 1 .

[0193] For example, Fig.14 As shown, the first gate layer 31 includes a first gate conductive pattern, the first gate conductive pattern overlaps with the orthographic projection of the active layer pattern on the substrate 1, and the overlapping portion of the first gate conductive pattern and the active layer pattern serves as the gate of each transistor TFT.

[0194] In some examples, such as Fig.14As shown, the first gate conductive pattern includes a scan signal line Scan extending along a first direction X, and the scan signal line Scan is configured to transmit a scan signal to the transistor TFT.

[0195] In some embodiments, Fig.12 and Fig.14 As shown, the second gate layer 32 includes a second gate conductive pattern, and the second gate conductive pattern includes an auxiliary reference voltage signal line VRef11.

[0196] For example, Fig.14 As shown, the auxiliary reference voltage signal line VRef11 extends along the first direction X and is connected to the reference voltage signal line VRef1.

[0197] For example, Fig.14 As shown, the second gate conductive pattern includes a plurality of signal lines extending along the first direction X, such as an auxiliary reference voltage signal line VRef11, a second reference voltage signal line VRef2, a first initialization signal line Vinit1, a second enable signal line EM2, and a repair signal line Repair. The first initialization signal line Vinit1 is configured to transmit an initialization signal to the transistor TFT. The second enable signal line EM2 is configured to transmit a light emitting control signal to the transistor TFT.

[0198] In some embodiments, Fig.12 As shown, the display substrate 100 further includes a multi-layer gate insulating layer 5 . The multi-layer gate insulating layer 5 includes a first gate insulating layer 51 disposed between the semiconductor layer 2 and the first gate layer 1 , and a second gate insulating layer 52 disposed between the first gate layer 31 and the second gate layer 32 .

[0199] In some embodiments, Fig.14 As shown, the first gate conductive pattern includes a first plate pattern, and the first plate pattern includes a first plate (e.g., a first plate C11 of the first capacitor C1, and a first plate C21 of the second capacitor C2) of each pixel circuit 10. The second gate layer 32 also includes a second plate pattern, and the second plate pattern includes a second plate (e.g., a second plate C12 of the first capacitor C1, and a second plate C22 of the second capacitor C2) of the capacitor of each pixel circuit 10.

[0200] like Fig.14 As shown, the first plate pattern and the second plate pattern overlap in their orthographic projections on the substrate 1. The second plate C12 of the first capacitor C1 overlaps with the first plate C11 to form the first capacitor C1, and the second plate C22 of the second capacitor C2 overlaps with the first plate C21 to form the second capacitor C2.

[0201] In some embodiments, Figure 3 , Figure 4 and Fig.12 As shown, a pair of adjacent source-drain conductive layers 4 in the multi-layer source-drain conductive layer 4 are respectively a first set source-drain conductive layer and a second set source-drain conductive layer, and the first set source-drain conductive layer is closer to the substrate 1 than the second set source-drain conductive layer. The first fan-out line FIP1 is arranged in the first set source-drain conductive layer, and the data line DL and the second fan-out line FIP2 are arranged in the second set source-drain conductive layer.

[0202] For example, Fig.15 As shown, an insulating dielectric layer ILD is provided between the second gate layer 32 and the first source-drain conductive layer 41, the second gate layer 32 is electrically insulated from the first source-drain conductive layer 41, a via is provided on the insulating dielectric layer ILD, and the second gate conductive pattern in the second gate layer 32 and the part of the first conductive pattern in the first source-drain conductive layer 41 that needs to be connected are electrically connected through the via on the insulating dielectric layer ILD.

[0203] Exemplarily, an insulating spacer layer (e.g., a planarization layer 6) is further provided between the first set source-drain conductive layer and the second set source-drain conductive layer, the first set source-drain conductive layer and the second set source-drain conductive layer are electrically insulated, a via is provided on the insulating spacer layer, and the parts of the first set source-drain conductive layer and the second set source-drain conductive layer that need to be connected can be electrically connected through the via on the insulating spacer layer. One end of the first fan-out line FIP1 is connected to the set data line DL1 through a via, and the other end is connected to the second fan-out line FIP2 through another via.

[0204] The first set source-drain conductive layer includes a first fan-out line FIP1 extending along a first direction X, and may also include other signal lines extending along the first direction X. The second set source-drain conductive layer includes a second fan-out line FIP2 and a data line DL extending along a second direction Y, and may also include other signal lines extending along the second direction Y. With such a design, the multiple signal lines included in each source-drain conductive layer may all extend in the same direction, simplifying the structure of the conductive pattern inside, thereby simplifying the preparation process of the source-drain conductive layer.

[0205] At the same time, the data lines DL (set data lines DL1) located on both sides of the display area AA along the first direction X can be led out from the display area AA to the binding area BB through the first fan-out line FIP1 and the second fan-out line FIP2, thereby reducing the width of the peripheral area AN of the display substrate 100 on the side of the binding area BB, thereby reducing the border width of the side of the display device 1000 used to bind the driver.

[0206] like Fig.14 and Fig.15As shown, the first fan-out line FIP1 is disposed in the first set source-drain conductive layer, and the auxiliary reference voltage signal line VRef11 is located in the second gate layer 32. In the thickness direction along the display substrate 100, the auxiliary reference voltage signal line VRef11 is located above the fifth node N5, and the first fan-out line FIP1 is located above the auxiliary reference voltage signal line VRef11. That is, the auxiliary reference voltage signal line VRef11 is located between the fifth node N5 and the first fan-out line FIP1.

[0207] The auxiliary reference voltage signal line VRef11 is configured to transmit a reference voltage signal, and the auxiliary reference voltage signal is a constant voltage signal. In this way, the auxiliary reference voltage line VRef11 between the fifth node N5 and the first fan-out line FIP1 can play a shielding effect, preventing signal crosstalk between the data signal transmitted on the first fan-out line FIP and the fifth node N5, thereby ensuring the normal operation of the pixel circuit 10.

[0208] In some embodiments, Figure 3 and Figure 4 As shown, the multi-layer source-drain conductive layer 4 includes a first source-drain conductive layer 41 and a second source-drain conductive layer 42 . The first source-drain conductive layer 41 is a first set source-drain conductive layer, and the second source-drain conductive layer 42 is a second set source-drain conductive layer.

[0209] Exemplarily, the first fan-out line FIP1 is disposed on the first source-drain conductive layer 41 , and the data line DL and the second fan-out line FIP2 are disposed on the second source-drain conductive layer 42 .

[0210] For example, Fig.15 As shown, the first source-drain conductive layer 41 includes a first source-drain conductive pattern, and the first source-drain conductive pattern includes a source 411 and a drain 412 of each transistor TFT. The source 411 and the drain 412 may be identical in structure, so the source 411 and the drain 412 of the transistor TFT may be interchangeable.

[0211] For example, Fig.15 As shown, the first source-drain conductive pattern further includes a first gate line GL1, a second gate line GL2, a third gate line GL3, a first fan-out line FIP1, an auxiliary second voltage signal line DIP, an auxiliary first voltage signal line SIP and a first enable signal line EM1 extending along the first direction X. The first enable signal line EM1 is configured to transmit a light emitting control signal to the transistor TFT.

[0212] See also Fig.14 and Fig.15 The second electrode plate C22 of the second capacitor C2 is provided with an opening, and the first source-drain conductive layer 41 also includes a connecting line LX, one end of the connecting line LX is connected to the first electrode plate C21 of the second capacitor C2 through the opening, and the other end is connected to Fig.14The fifth node N5 in the dotted box is connected.

[0213] See also Fig.14 and Fig.15 In the thickness direction of the display substrate 100, the auxiliary reference voltage signal line VRef11 is located above the fifth node N5, and the first fan-out line FIP1 is located above the auxiliary reference voltage signal line VRef11. That is, the auxiliary reference voltage signal line VRef11 is located between the fifth node N5 and the first fan-out line FIP1.

[0214] The auxiliary reference voltage signal line VRef11 is configured to transmit a reference voltage signal, and the auxiliary reference voltage signal is a constant voltage signal. In this way, the auxiliary reference voltage line VRef11 between the fifth node N5 and the first fan-out line FIP1 can play a shielding effect, preventing signal crosstalk between the data signal transmitted on the first fan-out line FIP and the fifth node N5, thereby ensuring the normal operation of the pixel circuit 10.

[0215] For example, Fig.12 As shown, the display substrate 100 further includes: a multi-layer planarization layer 6, and the multi-layer planarization layer 6 includes a first planarization layer 61 and a second planarization layer 62. The first planarization layer 61 is arranged between the first source-drain conductive layer 41 and the second source-drain conductive layer 42, and the second planarization layer 62 is arranged on a side of the second source-drain conductive layer 42 away from the first source-drain conductive layer 41.

[0216] In some embodiments, Figure 3 and Figure 4 As shown, the second source-drain conductive layer 42 includes a data line DL extending along the second direction Y, a first voltage signal line VSS, a second voltage signal line VDD, a second fan-out line FIP2 and a reference voltage signal line VRef1.

[0217] For example, Figure 8 As shown, a plurality of vias are provided on the first planarization layer 61, and the first voltage signal line VSS is electrically connected to the auxiliary first voltage signal line SIP through the vias on the first planarization layer 61, thereby increasing the number of signal lines for transmitting the first voltage signal in the display area AA without increasing the film layer structure, increasing the wiring density of the signal lines for transmitting the first voltage signal in the display area AA, and reducing the resistance of the first voltage signal line VSS.

[0218] For example, Figure 8As shown, the second voltage signal line VDD is electrically connected to the auxiliary first voltage signal line DIP through the via hole on the first planarization layer 61, thereby increasing the number of signal lines for transmitting the second voltage signal in the display area AA without increasing the film layer structure, increasing the wiring density of the signal lines for transmitting the second voltage signal in the display area AA, and reducing the resistance of the second voltage signal line VDD.

[0219] In some embodiments, the multi-layer source-drain conductive layer 4 includes a first source-drain conductive layer 41 , a second source-drain conductive layer 42 and a third source-drain conductive layer 43 , the first source-drain conductive layer 41 is a first set source-drain conductive layer, and the second source-drain conductive layer 42 is a second set source-drain conductive layer.

[0220] Exemplarily, the first fan-out line FIP1 is disposed on the first source-drain conductive layer 41 , and the data line DL and the second fan-out line FIP2 are disposed on the second source-drain conductive layer 42 .

[0221] For example, Fig.12 As shown, the multi-layer planarization layer 6 further includes a third planarization layer 63 , which is disposed on a side of the third source-drain conductive layer 43 away from the second source-drain conductive layer 42 .

[0222] In some embodiments, the multi-layer source-drain conductive layer 4 includes a first source-drain conductive layer 41 , a second source-drain conductive layer 42 and a third source-drain conductive layer 43 , the second source-drain conductive layer 42 is a first set source-drain conductive layer, and the third source-drain conductive layer 43 is a second set source-drain conductive layer.

[0223] Exemplarily, the second source-drain conductive layer 42 is the first set source-drain conductive layer, and the third source-drain conductive layer 43 is the second set source-drain conductive layer. The first fan-out line FIP1 is disposed in the second source-drain conductive layer 42 , and the data line DL and the second fan-out line FIP2 are disposed in the third source-drain conductive layer 43 .

[0224] It should be noted that the display substrate 100 may include two semiconductor layers, wherein the material of one semiconductor layer includes, for example, low-temperature polysilicon, and the material of the other semiconductor layer includes, for example, metal oxide, and the active layers of the multiple transistors TFT included in the pixel circuit 10 are respectively located in the two semiconductor layers. In this way, the multiple transistors TFT included in the pixel circuit 10 include some low-temperature polysilicon thin film transistors and some oxide thin film transistors.

[0225] In some embodiments, Fig.14 and Fig.15As shown, the display substrate 100 further includes: a plurality of auxiliary reference voltage signal lines VRef11 disposed on a side of the semiconductor layer 2 away from the substrate 1. The auxiliary reference voltage signal line VRef11 extends along a first direction X and is electrically connected to the reference voltage signal line VRef1. Among them, the first fan-out line FIP1 is disposed on a side of the auxiliary reference voltage signal line VRef11 away from the substrate 1. In an orthographic projection onto the substrate 1, the first fan-out line FIP1 overlaps with the auxiliary reference voltage signal line VRef11 and overlaps with part of the semiconductor layer 2.

[0226] In the thickness direction of the display substrate 100, the auxiliary reference voltage signal line VRef11 is located above the fifth node N5, and the first fan-out line FIP1 is located above the auxiliary reference voltage signal line VRef11. That is, the auxiliary reference voltage signal line VRef11 is located between the fifth node N5 and the first fan-out line FIP1, so that the auxiliary reference voltage signal transmitted by the auxiliary reference voltage signal line VRef11 is a constant voltage signal, which can play a shielding effect, prevent the data signal transmitted on the first fan-out line FIP from generating signal crosstalk with the fifth node N5, and ensure the normal operation of the pixel circuit 10.

[0227] It should be noted that the first fan-out line FIP1 extends along the first direction X, and a shielding structure is provided between the first fan-out line FIP1 and the fifth node N5 of a row of pixel circuits 10 adjacent thereto, so as to prevent signal crosstalk between the data signal transmitted by the first fan-out line FIP1 and the fifth node N5 of the pixel circuit 10. The shielding structure may be an auxiliary reference voltage signal line VRef11 located between the first fan-out line FIP1 and the fifth node N5 along the thickness direction of the display substrate 100, or may be other signal lines that transmit constant voltage signals.

[0228] In some embodiments, Figure 6 and Figure 7 As shown, the display substrate 100 further includes: a plurality of second voltage signal lines VDD. The second voltage signal lines VDD extend along the second direction Y, and a column of pixel circuits 10 is electrically connected to a second voltage signal line VDD.

[0229] The film layer where the plurality of second voltage signal lines VDD are located is located on the side of the film layer where the first fan-out line FIP1 is located away from the substrate 1 . In the orthographic projection to the substrate 1 , the second voltage signal line VDD covers the first break DK1 of the first fan-out line FIP1 .

[0230] For example, Figure 6 and Figure 7As shown, the first fan-out line FIP1 is located at the first source-drain conductive layer 41, and the second voltage signal line VDD is located at the second source-drain conductive layer 42. The orthographic projection of the first break DK1 on the first fan-out line FIP1 on the display substrate 100 falls within the range of the orthographic projection of the second voltage signal line VDD on the display substrate 100, that is, the first break DK1 is blocked by the second voltage signal line VDD, and when ambient light from the side of the substrate 1 away from the first source-drain conductive layer 41 is emitted toward the substrate 1, the part of the ambient light emitted toward the first fan-out line FIP1 where the break DK1 is not set can be blocked and reflected by the first fan-out line FIP1, and the part of the ambient light emitted toward the first break DK1 can be blocked and reflected by the second voltage signal line VDD, thereby reducing the difference in light reflectivity of the first source-drain conductive layer 41 at the first break DK1 and at the place where the first break DK1 is not set, and effectively weakening the screen-off mura phenomenon caused by the first break DK1.

[0231] Exemplarily, the number of the second breaks DK2 on the second fan-out line FIP2 is greater than or equal to the number of the first breaks DK1 on the first fan-out line FIP1.

[0232] In some examples, such as Figure 5 , Figure 6 and Figure 7 As shown, in the first fan-out line FIP1 and the second fan-out line FIP2 connected to the data line DL1, the number of the second breaks DK2 on the second fan-out line FIP2 is half the number of the first breaks DK1 on the first fan-out line FIP1. For example, two first breaks DK1 are provided on each first fan-out line FIP1, and one second break DK2 is provided on each second fan-out line FIP2.

[0233] In other examples, in a first fan-out line FIP1 and a second fan-out line FIP2 connected to the data line DL1, the number of second breaks DK2 on the second fan-out line FIP2 is equal to the number of first breaks DK1 on the first fan-out line FIP1. For example, each first fan-out line FIP1 is provided with a first break DK1, and each second fan-out line FIP2 is provided with a second break DK2.

[0234] Understandably, see Figure 3 and Figure 5The length of the first fan-out line FIP1 along the first direction X is, for example, the same or substantially the same as the length of the display area AA along the first direction X, and the length of the second fan-out line FIP1 along the second direction Y is, for example, the same or substantially the same as the length of the display area AA along the second direction Y. One end of the effective portion FIP21 of the second fan-out line FIP2 extends to the binding area BB, and the other end extends toward the display area AA along the second direction Y and is connected to one end of the effective portion FIP11 of the first fan-out line FIP1. The other end of the effective portion FIP11 of the first fan-out line FIP1 is connected to a setting data line DL1.

[0235] When no other signal line is disposed between the setting data line DL1 and the boundary of the display area AA extending along the second direction Y, a first break DK1 may be disposed on the first fan-out line FIP1 connected to the setting data line DL1 .

[0236] When other signal lines such as the first voltage line VSS or the second voltage line VDD are provided between the setting data line DL1 and the boundary extending along the second direction Y of the display area AA, two first breaks DK1 may be provided on the first fan-out line FIP1 connected to the setting data line DL1, and the two first breaks DK1 are respectively provided on both sides of the setting data line DL1 along the first direction X. In this way, the first fan-out line FIP1 has two redundant parts FIP12, and the two redundant parts FIP12 may be respectively connected to two signal lines (such as the first voltage signal line VSS or the second voltage signal line VDD, etc.), so as to increase the wiring density of the signal lines connected thereto in the display area AA, thereby reducing the resistance of the signal lines connected thereto.

[0237] The specific design of the breaks on the first fan-out line FIP1 and the second fan-out line FIP2 can be adaptively designed according to actual needs, which is only an exemplary description here and is not intended to limit the present disclosure.

[0238] In some embodiments, Figure 3 , Figure 4 and Figure 6 As shown, the display substrate 100 further includes: a gate signal line GL1, an enable signal line EM, an auxiliary first voltage signal line SIP, and an auxiliary second voltage signal line DIP, all extending along the first direction X. The pixel circuit 10 is electrically connected to the gate signal line GL1 and the enable signal line EM. The auxiliary first voltage signal line SIP is electrically connected to the first voltage signal line VSS, and the auxiliary second voltage signal line DIP is electrically connected to the second voltage signal line VDD.

[0239] The first set source-drain conductive layer is provided with at least one of the gate signal line GL1, the enable signal line EM, the auxiliary first voltage signal line SIP and the auxiliary second voltage signal line DIP. In the orthographic projection to the substrate 1, at least one of the gate signal line GL1, the enable signal line EM, the auxiliary first voltage signal line SIP and the auxiliary second voltage signal line DIP covers the second break DK2 of the second fan-out line FIP2.

[0240] Exemplarily, the enable signal line EM includes a first enable signal line EM1 and a second enable signal line EM2. The pixel circuit 10 is electrically connected to the first enable signal line EM1 and the second enable signal line EM2.

[0241] In the case where the display substrate 100 includes two source-drain conductive layers 4, the first set source-drain conductive layer is the first source-drain conductive layer 41. In the case where the display substrate 100 includes three source-drain conductive layers 4, the first set source-drain conductive layer is the first source-drain conductive layer 41 or the second source-drain conductive layer 42. The first set source-drain conductive layer is the first source-drain conductive layer 41, and the second set source-drain conductive layer is the second source-drain conductive layer 42.

[0242] At least one of the gate signal line GL1, the enable signal line EM, the auxiliary first voltage signal line SIP and the auxiliary second voltage signal line DIP is located in the first set source-drain conductive layer, the second fan-out line FIP2 is located in the second set source-drain conductive layer, and the first set source-drain conductive layer is located between the second set source-drain conductive layer and the substrate 1. In this way, when at least one of the gate signal line GL1, the enable signal line EM, the auxiliary first voltage signal line SIP and the auxiliary second voltage signal line DIP in the first set source-drain conductive layer covers the second break DK2 of the second fan-out line FIP2, it can achieve a signal shielding effect, thereby avoiding the data signal transmitted by the second fan-out line FIP2 passing through the pixel circuits 10 of adjacent sub-pixels P(x) from generating signal crosstalk with the nodes in the pixel circuit 10, thereby ensuring the normal operation of the pixel circuit 10.

[0243] like Figure 6 As shown, the transverse signal line in the first source-drain conductive layer 41 overlapping the second break DK2 may be at least one of the gate signal line GL1 , the enable signal line EM, the auxiliary first voltage signal line SIP or the auxiliary second voltage signal line DIP.

[0244] In some embodiments, Fig.12 and Fig.15 As shown, the first voltage signal line VSS, the second voltage signal line VDD and the reference voltage signal line VRef1 of the display substrate 100 are all disposed in the second set source-drain conductive layer.

[0245] The first voltage signal line VSS, the second voltage signal line VDD and the reference voltage signal line VRef1 in the second set source-drain conductive layer can block the first break DK1 on the first fan-out line FIP1 in the first set source-drain conductive layer to prevent the data signal transmitted by the first fan-out line FIP1 from generating signal crosstalk between the first break DK1 position and the node in the pixel circuit 10, thereby ensuring the normal operation of the pixel circuit 10.

[0246] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, comprising a display area and a binding area, wherein the binding area is located on one side of the display area along a second direction; The display substrate comprises: A plurality of pixel circuits, wherein the plurality of pixel circuits are arranged in a plurality of rows and columns, wherein a row of pixel circuits is arranged along a first direction, and a column of pixel circuits is arranged along a second direction, and the first direction and the second direction intersect; a plurality of data lines, the data lines extending along the second direction, a column of pixel circuits being electrically connected to one of the data lines; A first fan-out line and a second fan-out line are provided in the display area; the first fan-out line extends along the first direction, and the second fan-out line extends along the second direction; at least one of the plurality of data lines is a setting data line, and the second fan-out line is closer to a center line of the binding area along the second direction than the setting data line; one end of the first fan-out line is electrically connected to the setting data line, and the other end is electrically connected to the second fan-out line; Wherein, the display substrate comprises a plurality of pixels, each pixel comprises at least three sub-pixels, and each sub-pixel comprises one pixel circuit; At least one of the multiple pixels is a setting pixel, and one of the setting pixels is correspondingly provided with at least one second fan-out line, and the second fan-out line passes between pixel circuits of two adjacent sub-pixels in the corresponding setting pixel, or passes from the outside of the pixel circuit located on the outside of the corresponding setting pixel, and extends to the binding area.

2. The display substrate according to claim 1, wherein: The display substrate further comprises: A first voltage signal line extends along the second direction; one of the set pixels is correspondingly provided with at least one of the first voltage signal lines, and the first voltage signal line passes between pixel circuits of two adjacent sub-pixels in the corresponding set pixel, or passes from the outside of the pixel circuit located on the outside of the corresponding set pixel.

3. The display substrate according to claim 2, wherein: Among the at least one second fan-out line and at least one first voltage signal line corresponding to the set pixel, one second fan-out line passes between pixel circuits of a pair of adjacent sub-pixels, and one first voltage signal line passes between pixel circuits of another pair of adjacent sub-pixels.

4. The display substrate according to claim 3, wherein: The pixel includes three sub-pixels; The setting pixel is correspondingly provided with a second fan-out line and a first voltage signal line, the second fan-out line passes between pixel circuits of a pair of adjacent sub-pixels among the three sub-pixels, and the first voltage signal line passes between pixel circuits of another pair of adjacent sub-pixels among the three sub-pixels.

5. The display substrate according to claim 2, wherein: Among the second fan-out lines and the first voltage signal lines corresponding to the setting pixel, one first voltage signal line and one second fan-out line pass between pixel circuits of the same pair of adjacent sub-pixels.

6. The display substrate according to claim 5, wherein: The pixel includes three sub-pixels; The setting pixel is correspondingly provided with one of the second fan-out lines and one of the first voltage signal lines, and the second fan-out line and the first voltage signal line pass between pixel circuits of a same pair of adjacent sub-pixels among the three sub-pixels.

7. The display substrate according to claim 5, wherein: The second fan-out line is provided with a second break, and the second break divides the second fan-out line into a valid part and a redundant part; one end of the valid part of the second fan-out line is electrically connected to the first fan-out line, and the other end extends to the binding area; The display substrate further includes a first connection portion, through which the first voltage signal line and a redundant portion of the second fan-out line are electrically connected.

8. The display substrate according to claim 7, wherein: The first voltage signal line and the second fan-out line passing through the pixel circuits of the same pair of adjacent sub-pixels are arranged adjacent to each other, and the first voltage signal line, the second fan-out line and the first connecting portion are arranged in the same layer and are integrally formed.

9. The display substrate according to claim 7, wherein: The first fan-out line is provided with a first break, and the first break divides the first fan-out line into a valid part and a redundant part; one end of the valid part of the first fan-out line is electrically connected to the set data line, and the other end is electrically connected to the valid part of the second fan-out line; The display substrate further includes: a second connection portion, one end of which is electrically connected to a redundant portion of the first fan-out line; A via hole is provided between the second connection portion and the redundant portion of the second fan-out line along the thickness direction of the display substrate, and the other end of the second connection portion is electrically connected to the redundant portion of the second fan-out line through the via hole.

10. The display substrate according to claim 9, wherein: The second connection portion and the redundant portion of the first fan-out line are arranged in the same layer and are integrally formed.

11. The display substrate according to any one of claims 1 to 10, wherein: The display substrate further comprises: A plurality of reference voltage signal lines, wherein the reference voltage signal lines extend along the second direction, and one column of pixel circuits is electrically connected to one of the reference voltage signal lines; in two adjacent columns of pixel circuits, the reference voltage signal line connected to one column of pixel circuits and the data line connected to the other column of pixel circuits are arranged close to each other; Wherein, the second fan-out line is arranged between the reference voltage signal line and the data line which are arranged close to each other.

12. The display substrate according to claim 11, wherein: The first voltage signal line of the display substrate is arranged between the reference voltage signal line and the data line which are arranged close to each other.

13. The display substrate according to claim 11, wherein: The display substrate further comprises: substrate; a semiconductor layer disposed on the substrate; A plurality of auxiliary reference voltage signal lines are provided on a side of the semiconductor layer away from the substrate, the auxiliary reference voltage signal lines extend along the first direction and are electrically connected to the reference voltage signal lines; The first fan-out line is arranged on a side of the auxiliary reference voltage signal line away from the substrate; in an orthographic projection onto the substrate, the first fan-out line overlaps with the auxiliary reference voltage signal line and partially overlaps with the semiconductor layer.

14. The display substrate according to any one of claims 1 to 10, wherein: The display substrate further comprises: a plurality of second voltage signal lines, wherein the second voltage signal lines extend along the second direction, and a column of pixel circuits is electrically connected to one of the second voltage signal lines; The film layer where the plurality of second voltage signal lines are located is located on a side of the film layer where the first fan-out line is located away from the substrate, and in an orthographic projection onto the substrate, the second voltage signal line covers the first break of the first fan-out line.

15. The display substrate according to any one of claims 1 to 10, wherein: The display substrate further comprises: A plurality of source-drain conductive layers, wherein a pair of adjacent source-drain conductive layers in the plurality of source-drain conductive layers are respectively a first set source-drain conductive layer and a second set source-drain conductive layer, and the first set source-drain conductive layer is closer to the substrate than the second set source-drain conductive layer; The first fan-out line is arranged in the first set source-drain conductive layer, and the data line and the second fan-out line are arranged in the second set source-drain conductive layer.

16. The display substrate according to claim 15, wherein: The display substrate further comprises: a gate signal line, an enable signal line, an auxiliary first voltage signal line and an auxiliary second voltage signal line, all extending along the first direction; the pixel circuit is electrically connected to the gate signal line and the enable signal line; the auxiliary first voltage signal line is electrically connected to the first voltage signal line, and the auxiliary second voltage signal line is electrically connected to the second voltage signal line; The first set source-drain conductive layer is provided with at least one of the gate signal line, the enable signal line, the auxiliary first voltage signal line and the auxiliary second voltage signal line; in the orthographic projection onto the substrate, at least one of the gate signal line, the enable signal line, the auxiliary first voltage signal line and the auxiliary second voltage signal line covers the second break of the second fan-out line.

17. The display substrate according to claim 15, wherein: The first voltage signal line, the second voltage signal line and the reference voltage signal line of the display substrate are all arranged on the second set source-drain conductive layer.

18. The display substrate according to claim 15, wherein: The display substrate further comprises: a first gate layer and a second gate layer; the semiconductor layer of the display substrate, the first gate layer and the second gate layer are sequentially arranged in a direction away from the substrate and are located between the substrate and the multi-layer source-drain conductive layer; The auxiliary reference voltage signal line of the display substrate is arranged on the second gate layer.

19. The display substrate according to claim 15, wherein: The multi-layer source-drain conductive layer includes a first source-drain conductive layer and a second source-drain conductive layer, the first source-drain conductive layer is the first set source-drain conductive layer, and the second source-drain conductive layer is the second set source-drain conductive layer; or, The multi-layer source-drain conductive layer includes a first source-drain conductive layer, a second source-drain conductive layer and a third source-drain conductive layer, the first source-drain conductive layer is the first set source-drain conductive layer, and the second source-drain conductive layer is the second set source-drain conductive layer; or, The multi-layer source-drain conductive layer includes a first source-drain conductive layer, a second source-drain conductive layer and a third source-drain conductive layer, the second source-drain conductive layer is the first set source-drain conductive layer, and the third source-drain conductive layer is the second set source-drain conductive layer.

20. The display substrate according to any one of claims 1 to 10, wherein: Compared with other data lines in the plurality of data lines, the set data line is farther away from a center line of the binding area along the second direction; the set data line is entirely located in the display area, and ends of the other data lines extend to the binding area.

21. A display device, comprising: The display substrate according to any one of claims 1 to 20; A circuit board is electrically connected to the display substrate.

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