Shifting register, scanning driving circuit and display device

Abstract

The invention relates to the technical field of display, in particular to a shifting register, a scanning driving circuit and a display device. The shift register comprises a first input circuit, a first output circuit, a second input circuit, a second output circuit and a second control circuit, the second control circuit is electrically connected with the first node, the second node, a fifth voltage end, a second clock signal end and the control end, and the second control circuit is configured to be electrically connected with the first output circuit. Under the control of the signal of the second node, the second clock signal and the signal of the control end, when the first output circuit is switched on, the electric connection between the first node and the fifth voltage end is cut off, and when the second output circuit is switched on, the signal of the fifth voltage end is written into the first node.

Description

Shift register, scan drive circuit and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register, a scan drive circuit, and a display device. Background Art

[0002] The scan drive circuit is an important auxiliary circuit in a display device. The scan drive circuit includes a plurality of shift registers. During operation, the output end of the shift register is prone to output instability.

[0003] Summary of the Invention

[0004] In one aspect, the present disclosure provides a shift register, comprising:

[0005] a first input circuit electrically connected to the start signal terminal, the first node, and the first clock signal terminal, wherein the first input circuit is configured to write the signal of the start signal terminal into the first node under the control of the first clock signal of the first clock signal terminal;

[0006] a first output circuit electrically connected to the first node, an output terminal, and a first voltage terminal, wherein the first output circuit is configured to write a signal from the first voltage terminal to the output terminal when the first output circuit is turned on under control of a signal from the first node;

[0007] a second input circuit electrically connected to the first node, the second node, the second voltage terminal, and the first clock signal terminal, the second input circuit being configured to write the first clock signal to the second node under control of a signal from the first node, and to write a signal from the second voltage terminal to the second node under control of the first clock signal;

[0008] a second output circuit electrically connected to the fourth voltage terminal, the second node, and the output terminal, the second output circuit being configured to write the signal of the fourth voltage terminal into the output terminal when the second output circuit is turned on under the control of the signal of the fourth node;

[0009] The second control circuit is electrically connected to the first node, the second node, the fifth voltage terminal, the second clock signal terminal and the control terminal. The second control circuit is configured to, under the control of the signal of the second node, the second clock signal and the signal of the control terminal, disconnect the electrical connection between the first node and the fifth voltage terminal when the first output circuit is turned on, and write the signal of the fifth voltage terminal into the first node when the second output circuit is turned on.

[0010] In some embodiments, a first control circuit is further included, which is electrically connected to the first node, the second node, the fourth node, the second clock signal terminal, and the third voltage terminal. The first control circuit is configured to write the second clock signal to the fourth node under the control of the signal of the second node and the second clock signal of the second clock signal terminal, and to write the signal of the third voltage terminal to the fourth node under the control of the signal of the first node.

[0011] In some embodiments, the second control circuit includes a first subcircuit and a second subcircuit connected in series between the fifth voltage terminal and the first node.

[0012] The second sub-circuit is electrically connected to the control terminal, and the second sub-circuit is configured to be disconnected when the first output circuit is turned on, and to be turned on when the second output circuit is turned on;

[0013] The first sub-circuit is electrically connected to the second node and the second clock signal terminal. The first sub-circuit is configured to cooperate with the second sub-circuit to write the signal of the fifth voltage terminal into the first node when it is turned on under the control of the signal of the second node and the second clock signal of the second clock signal terminal.

[0014] In some embodiments, the first sub-circuit includes a fourth transistor and a fifth transistor, wherein the control electrode of the fourth transistor is electrically connected to the second clock signal terminal, and the first electrode of the fourth transistor is electrically connected to the first node; the control electrode of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is electrically connected to the fifth voltage terminal;

[0015] The second sub-circuit is electrically connected between the fourth transistor and the fifth transistor, or between the fourth transistor and the first node, or between the fifth transistor and the fifth voltage terminal.

[0016] In some embodiments, the second sub-circuit includes an eleventh transistor, wherein the control electrode of the eleventh transistor is electrically connected to the control terminal.

[0017] a first electrode of the eleventh transistor is electrically connected to the first node, and a second electrode of the eleventh transistor is electrically connected to the first electrode of the fourth transistor;

[0018] Alternatively, the first electrode of the eleventh transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the eleventh transistor is electrically connected to the first electrode of the fifth transistor;

[0019] Alternatively, the first electrode of the eleventh transistor is electrically connected to the second electrode of the fifth transistor, and the second electrode of the eleventh transistor is electrically connected to the fifth voltage terminal.

[0020] In some embodiments, the control terminal is electrically connected to the fourth node.

[0021] In some embodiments, the first input circuit includes a first transistor, a first electrode of the first transistor is electrically connected to the start signal terminal, a second electrode of the first transistor is electrically connected to the first node, and a control electrode of the first transistor is electrically connected to the first clock signal terminal.

[0022] In some embodiments, the first output circuit includes a tenth transistor, a first electrode of the tenth transistor is electrically connected to the output terminal, a second electrode of the tenth transistor is electrically connected to the first voltage terminal, and a control electrode of the tenth transistor is electrically connected to the first node.

[0023] In some embodiments, the transistors in the shift register are all N-type transistors.

[0024] In some embodiments, the first output circuit further includes a first capacitor, one plate of the first capacitor is electrically connected to the first node, and the other plate of the first capacitor is electrically connected to the output end.

[0025] In some embodiments, the second input circuit includes:

[0026] a second transistor, having a control electrode electrically connected to the first node, a first electrode electrically connected to the second node, and a second electrode electrically connected to the first clock signal terminal;

[0027] The third transistor has a control electrode electrically connected to the first clock signal terminal, a first electrode electrically connected to the second node, and a second electrode electrically connected to the second voltage terminal.

[0028] In some embodiments, the first control circuit includes:

[0029] a sixth transistor, having a control electrode electrically connected to the second node, a first electrode electrically connected to the fifth node, and a second electrode electrically connected to the second clock signal terminal;

[0030] a seventh transistor, having a control electrode electrically connected to the second clock signal terminal, a first electrode electrically connected to the fourth node, and a second electrode electrically connected to the fifth node;

[0031] an eighth transistor, having a control electrode electrically connected to the first node, a first electrode electrically connected to the fourth node, and a second electrode electrically connected to the third voltage terminal;

[0032] A second capacitor has one plate electrically connected to the first node, and another plate electrically connected to the fifth node.

[0033] In some embodiments, the second output circuit includes:

[0034] a ninth transistor, having a control electrode electrically connected to the fourth node, a first electrode electrically connected to the output terminal, and a second electrode electrically connected to the fourth voltage terminal;

[0035] A third capacitor, wherein one plate is electrically connected to the fourth node, and the other plate is electrically connected to the fourth voltage terminal.

[0036] In some embodiments, the first voltage terminal and the second voltage terminal are configured to be electrically connected to the same signal terminal.

[0037] In some embodiments, the third voltage terminal, the fourth voltage terminal, and the fifth voltage terminal are configured to be electrically connected to the same signal terminal.

[0038] On the other hand, a scan driving circuit is provided, comprising a plurality of the shift registers described above, wherein the plurality of shift registers are cascaded.

[0039] On the other hand, a display device is provided, comprising a plurality of pixel driving circuits and the scanning driving circuit, wherein the pixel driving circuit comprises a plurality of transistors, and the output end of the shift register in the scanning driving circuit is electrically connected to the control electrode of the transistor to provide an enable signal.

[0040] In another aspect, a display panel is provided, comprising:

[0041] substrate;

[0042] a semiconductor layer comprising a first semiconductor strip and a second semiconductor strip, wherein the first semiconductor strip comprises an active layer of a fourth transistor and a fifth transistor, and the second semiconductor strip comprises an active layer of an eleventh transistor;

[0043] a first conductive layer comprising a first conductive strip, a second conductive strip, and a third conductive strip, wherein the first conductive strip comprises a gate of the fourth transistor, the second conductive strip comprises gates of the fifth and sixth transistors, and one plate of the second capacitor, and the third conductive strip comprises a gate of the eleventh transistor, a gate of the ninth transistor, and one plate of the third capacitor;

[0044] The second conductive layer includes a first bridge line, and the first bridge line is electrically connected to the first semiconductor strip and the second semiconductor strip through a via.

[0045] In some embodiments, the first semiconductor strip includes a first region and a second region, the first region is the active layer of the fourth transistor, and the second region is the active layer of the fifth transistor; the first bridge wire is connected to an end of the first region away from the second region through a via, or the first bridge wire is connected to an end of the second region away from the first region through a via.

[0046] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0048] FIG1 schematically shows a front view structure of a display device;

[0049] FIG2 schematically shows a schematic diagram of a display panel;

[0050] FIG3 schematically shows a circuit diagram of a pixel driving circuit;

[0051] FIG4 is a circuit diagram of a shift register in the related art;

[0052] FIG5 is a timing diagram of the operation of the shift register shown in FIG4 ;

[0053] FIG6 is a potential diagram of each node during operation of the shift register shown in FIG4 ;

[0054] FIG7 schematically shows a structural block diagram of a shift register;

[0055] FIG8 schematically shows a block diagram of another structure of a shift register;

[0056] FIG9 schematically shows a structural block diagram of yet another shift register;

[0057] FIG10 schematically shows a circuit diagram of a shift register;

[0058] FIG11 schematically shows a circuit diagram of another shift register;

[0059] FIG12 schematically shows a circuit diagram of yet another shift register;

[0060] FIG13 schematically shows a timing diagram of each signal terminal in the shift register shown in FIG10 to FIG12;

[0061] FIG. 14 schematically shows a potential diagram of the shift register shown in FIG. 12 during operation.

[0062] FIG15 schematically shows a layout of a shift register;

[0063] FIG. 16 schematically shows a layout of a first semiconductor strip. Specific embodiments

[0064] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0065] In the circuits provided in the embodiments of the present disclosure, a "node" does not refer to an actual component, but rather to a junction point of related electrical connections in a circuit diagram. That is, these nodes are nodes formed by equivalent junction points of related electrical connections in the circuit diagram.

[0066] FIG1 schematically illustrates a front view structure of a display device. As shown in FIG1 , some embodiments of the present disclosure provide a display device 100, which can be any device that displays either moving (e.g., video) or fixed (e.g., still images) and whether text or images. For example, the display device 100 can be a mobile phone, a wireless device, a personal data assistant (PDA), a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a camcorder, a game console, a watch, a clock, a calculator, a television monitor, a flat-panel display, a computer monitor, a car display (e.g., an odometer display, etc.), a navigator, a cockpit controller and / or display, a display of a camera view (e.g., a display of a rearview camera in a vehicle), an electronic photo, an electronic billboard or sign, a projector, a building structure, a packaging, and an aesthetic structure (e.g., a display of an image of a piece of jewelry), etc. FIG1 illustrates the display device 100 as a mobile phone as an example.

[0067] The display device 100 includes a display panel 110. The display panel 110 may be a liquid crystal display panel (LCD); the display panel 110 may also be an electroluminescent display panel or a photoluminescent display panel. If the display panel 110 is an electroluminescent display panel, the electroluminescent display panel may be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) display panel. If the display panel 110 is a photoluminescent display panel, the photoluminescent display device may be a quantum dot photoluminescent display panel.

[0068] Some embodiments of the present disclosure are described by taking the display panel 110 as an organic light-emitting diode (OLED) display panel as an example.

[0069] FIG2 schematically shows a schematic diagram of a display panel. As shown in FIG2 , the display panel 110 includes a substrate 111 and a plurality of sub-pixels P, a plurality of gate lines, and a plurality of data lines arranged on one side of the substrate 111 .

[0070] The substrate 111 may be a rigid substrate or a flexible substrate, and may be selected according to actual needs.

[0071] Exemplarily, the substrate 111 is a rigid substrate, such as a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0072] Exemplarily, the substrate 111 may be a flexible substrate, such as a PET (Polyethyleneterephthalate) substrate, a PEN (Polyethylenenaphthalate twoformic acid glycol ester) substrate, or a PI (Polyimide) substrate.

[0073] The display panel 110 may have a display area AA and a non-display area NA electrically connected to the display area AA. The non-display area NA may be located on one, two, or three sides of the display area AA, or the non-display area NA may be disposed around the display area AA. A plurality of sub-pixels P, a plurality of gate lines, and a plurality of data lines may be located within the display area AA.

[0074] For example, the plurality of sub-pixels P may be arranged in an array. For example, the plurality of sub-pixels P may be arranged in an array to form a plurality of sub-pixel rows and a plurality of sub-pixel columns, wherein the plurality of sub-pixels P in a sub-pixel row are arranged along a first direction X, and the plurality of sub-pixels P in a sub-pixel column are arranged along a second direction Y.

[0075] The first direction X and the second direction Y intersect each other. The angle between the first direction X and the second direction Y can be set according to actual needs. For example, the angle between the first direction X and the second direction Y can be 85°, 88°, 90°, 92°, or 95°.

[0076] The sub-pixel P may include a pixel driving circuit and a light-emitting device electrically connected to the pixel driving circuit. When the display panel 110 is in operation, the light-emitting device may emit light under the drive of the pixel driving circuit.

[0077] Figure 3 schematically illustrates a circuit diagram of a pixel driver circuit. As shown in Figure 3, the pixel driver circuit includes an emission control terminal EM, a data signal terminal Data, a data write control terminal Gate, and a reset control terminal Reset. These terminals EM, Data, Gate, and Reset of the pixel driver circuit can receive signals and, under their control, drive the light-emitting device OLED to emit light.

[0078] FIG3 shows a pixel driving circuit with a 7T1C structure as an example. In actual applications, the pixel driving circuit may also have other structures such as 4T1C, 6T1C, 6T2C, 7T2C, and 8T2C. The embodiments of the present disclosure do not limit the structure of the pixel driving circuit. Wherein, T represents a transistor, and the number before T represents the number of transistors. C represents a capacitor, and the number before C represents the number of capacitors.

[0079] Exemplarily, multiple pixel driving circuits in the same sub-pixel column can be electrically connected to the same data line, and multiple pixel driving circuits in the same sub-pixel row can be electrically connected to the same gate line. For example, the gate lines include a first gate line, a second gate line, and a third gate line, the first gate line is electrically connected to the light-emitting control terminal EM of the pixel driving circuit in the same sub-pixel row, the second gate line is electrically connected to the data write control terminal Gate of the pixel driving circuit in the same sub-pixel row, and the third gate line is electrically connected to the reset control terminal Reset of the pixel driving circuit in the same sub-pixel row. The number of gate lines electrically connected to the multiple pixel driving circuits in the same sub-pixel row can be set according to the structure of the pixel driving circuit.

[0080] A scan drive circuit is also provided on one side of the substrate 111. The scan drive circuit includes multiple cascaded shift registers 112, each of which includes an output terminal. When the scan drive circuit is in operation, the multiple cascaded shift registers 112 output control signals step by step through the output terminals. The output terminals of the shift registers 112 can be electrically connected to the gate lines, so that the shift registers 112 provide control signals to the pixel drive circuit through the gate lines.

[0081] The output terminal of the shift register 112 can be electrically connected to at least one of the light-emitting control terminal EM, the data writing control terminal Gate, and the reset control terminal Reset of the pixel driving circuit via a gate line. In the disclosed embodiment, only the example of the output terminal of the shift register 112 being electrically connected to the light-emitting control terminal EM of the pixel driving circuit via a gate line is used for description.

[0082] Exemplarily, the scan driving circuit is disposed in the non-display area NA. Of course, in actual applications, in order to reduce the frame size of the display panel 110, at least part of the structure of the scan driving circuit can also be disposed in the display area AA.

[0083] FIG4 is a circuit diagram of a shift register in the related art. The transistors shown in FIG4 are all N-type transistors. A high-level signal is input to the Vgh terminal, and the level is Vg. A low-level signal is input to the Vgl terminal. The threshold voltages of t1 and t10 are both Vth. FIG5 is an operating timing diagram of the shift register shown in FIG4 . The timing signal marked as Stv is input to the Stv terminal in FIG4 , the timing signal marked as Ck is input to each Ck terminal in FIG4 , the timing signal marked as Cb is input to each Cb terminal in FIG4 , and the timing signal marked as Eout is the timing signal output from the output terminal Eout in FIG4 . When Stv is a high-level signal, the level is equal to the level of Vg and Vgh. FIG6 and FIG7 are potential diagrams of each node during the operation of the shift register shown in FIG4 .

[0084] The working process of the shift register in the related art is described in detail below with reference to FIG. 4 to FIG. 7 .

[0085] Phase A: A low-level signal is applied to Stv, a high-level signal is applied to Ck, and a low-level signal is applied to Cb. t1 is activated by a high-level signal from Ck and writes the low-level signal from Stv to node n1. t2, t8, and t10 are activated by a low-level signal from n1, resulting in no conduction between Vgh and Eout. t3 is activated by a high-level signal from Ck and writes the high-level signal from Vgh to node n2. t5 is activated by a high-level signal from n2 and writes the low-level signal from Vgl to node n3. t4 is activated by a low-level signal from Cb and deletes the connection between n3 and n1. t6 is activated by a high-level signal from n2 and writes the low-level signal from Cb to node n5, simultaneously charging capacitor c1, which is electrically connected between n2 and n5. t7 is activated by a low-level signal from Cb, causing node n4 to float. t9 is closed under the control of the signal from node n4, and there is no conduction between Vgl and Eout. Therefore, there is no conduction between Eout and Vgl or Vhg, and Eout is floating.

[0086] Phase B: A low-level signal is applied to Stv, a low-level signal is applied to Ck, and a high-level signal is applied to Cb. T1 and t3 are closed by the low-level signal from Ck, resulting in no conduction between Stv and node n1, and no conduction between Vgh and node n2. Node n2 maintains a high-level signal due to capacitor C1. T5 is opened by the high-level signal from node n2, and T4 is opened by the high-level signal from Cb. Conductive conduction occurs between Vgl and node n1, and the low-level signal from Vgl is written to node n1. T2, T8, and T10 are closed by the low-level signal from node n1, resulting in no conduction between Vgh and Eout. T6 is opened by the high-level signal from node n2, and T7 is opened by the high-level signal from Cb. Conductive conduction occurs between Cb and node n4, and the high-level signal from Cb is written to node n4, simultaneously charging capacitor C2, which is electrically connected between Vgl and node n4. t9 is turned on under the control of the high-level signal of the n4 node, the Vgl terminal and the Eout terminal are connected, the low-level signal of the Vgl terminal is written to the Eout terminal, and the shift register outputs a low-level signal.

[0087] Phase C: A low-level signal is applied to Stv, a high-level signal is applied to Ck, and a low-level signal is applied to Cb. t1 is enabled by the high-level signal at Ck, and the low-level signal at Stv is written to node n1 via t1. t2, t8, and t10 are disabled by the low-level signal at n1, resulting in no conduction between Vgh and Eout. t3 is enabled by the high-level signal at Ck, and the high-level signal at Vgh is written to node n2 via t3. t5 is enabled by the high-level signal at n2, and the low-level signal at Vgl is written to node n3. t4 is disabled by the low-level signal at Cb, resulting in no conduction between nodes n3 and n1. t6 is enabled by the high-level signal at n2, and the low-level signal at Cb is written to node n5 via t6, simultaneously charging capacitor c1, which is electrically connected between nodes n2 and n5. During t7, a low-level signal from Cb is applied to turn off the connection between n5 and n4. Capacitor C2 maintains a high-level signal at n4. During t9, a high-level signal from n4 is applied to turn on the connection between Vgl and Eout, and the shift register outputs a low-level signal through Eout.

[0088] Phase D: A high-level signal is applied to Stv, a low-level signal is applied to Ck, and a high-level signal is applied to Cb. t1 and t3 are closed by the low-level signal at Ck. Node n2 maintains a high-level signal due to capacitor C1. t5 is opened by the high-level signal at n2, and t4 is opened by the high-level signal at Cb. Current conduction occurs between Vgl and n1, and the low-level signal at Vgl is written to n1. t2, t8, and t10 are closed by the low-level signal at n1, and current is lost between Vgh and Eout. t6 is opened by the high-level signal at n2, and t7 is opened by the high-level signal at Cb. Current conduction occurs between Cb and n4, and the high-level signal at Cb is written to n4. t9 is opened by the high-level signal at n4, and current conduction occurs between Vgl and Eout. The low-level signal at Vgl is written to Eout, and the shift register outputs a low-level signal through Eout.

[0089] Phase E: A high-level signal is applied to the Stv terminal, a high-level signal is applied to the Ck terminal, and a low-level signal is applied to the Cb terminal. t1 is turned on by the high-level signal from the Ck terminal, and the high-level signal from the Stv terminal is written to the n1 node through t1. Due to the characteristics of transistor t1, the voltage at node n1 is the voltage Vh at the Stv terminal minus the threshold voltage Vth of t1, i.e., the voltage at node n1 is Vh - Vth. t10 is turned on by the high-level signal from node n1, and conduction is established between the Vgh terminal and the Eout terminal, with the high-level signal from the Vgh terminal being written to the Eout terminal. Furthermore, because t10 itself forms a capacitor Cgs, Cgs is equivalent to one plate electrically connected to the n1 node and the other plate electrically connected to the Eout terminal. When the high-level signal from the Vgh terminal is written to the Eout terminal, the voltage at the Eout terminal increases. Due to the coupling effect of capacitor Cgs, the voltage at node n1 increases, and after increasing, it becomes greater than the voltage at the Stv terminal. At the same time, t3 is turned on by a high-level signal at Ck, and a high-level signal at Vgh is written to node n2. t5 is turned on by a high-level signal at n2, and a low-level signal at Vgl is written to node n3 via t5. t4 is turned off by a low-level signal at Cb, resulting in no conduction between n3 and n1. t6 is turned on by a high-level signal at n2, and a low-level signal at Cb is written to node n5 via t6, simultaneously charging capacitor C1. t7 is turned off by a low-level signal at Cb, resulting in no conduction between n5 and n4. t8 is turned on by a high-level signal at n1, and a low-level signal at Vgl is written to node n4 via t8. t9 is turned off by a low-level signal at n4, resulting in no conduction between Vgl and Eout. The shift register outputs a high-level signal via Eout.

[0090] Phase F: A high-level signal is applied to Stv, a low-level signal is applied to Ck, and a high-level signal is applied to Cb. t1 and t3 are closed by the low-level signal from Ck. t4 is opened by the high-level signal from Cb, turning on nodes n1 and n3. Part of the charge from node n1 is written to node n3, causing the voltage level at node n1 to decrease. Because t10 forms a capacitor Cgs, the capacitor Cgs maintains a high-level signal at node n1. t2 is opened by the high-level signal from node n1, and the low-level signal from Ck is written to node n2 via t2. t5 is closed by the low-level signal from node n2, causing no conduction between node n3 and Vgl. Because no conduction between node n3 and Vgl occurs, the charge from node n3 is not released to Vgl, preventing the voltage level at node n1 from continuously decreasing. The high-level signal from node n1 can still control t10 to turn on, and the high-level signal from Vgh is written to Eout via t10. At the same time, t8 is turned on by a high-level signal at n1, and the low-level signal at Vgl is written to n4 through t8. T9 is turned off by a low-level signal at n4, and there is no conduction between Vgl and Eout. The shift register outputs a high-level signal through Eout.

[0091] Phase G: A high-level signal is applied to the Stv terminal, a high-level signal is applied to the Ck terminal, and a low-level signal is applied to the Cb terminal. Compared to Phase E, since the voltage level at node n1 is higher than that at the Stv terminal in Phase G, the source of t1 is electrically connected to the Stv terminal, and the drain of t1 is electrically connected to the n1 node. At this time, Vgs at t1 is the high-level signal at the Ck terminal minus the high-level signal at the Stv terminal, which is less than the threshold voltage of t1 (for example, the high-level signal at the Ck terminal is equal to the high-level signal at the Stv terminal, and Vgs is equal to 0). Therefore, t1 is closed, and there is no conduction between Stv and node n1. Furthermore, t3 is turned on by the high-level signal at the Ck terminal, and the high-level signal at the Vgh terminal is written to node n2 through t3. T5 is turned on by the high-level signal at node n2, and conduction is achieved between Vgl and node n3. The charge written to node n3 in Phase F is released through Vgl.

[0092] Within a display frame of the display panel, Phases F and G alternate. During Phase F, some of the charge at node n1 is written to node n3, causing the potential at node n1 to decrease. During Phase G, node n3 and the Vgl terminal are conductive, allowing the charge written to node n3 to be released to the Vgl terminal. As Phases F and G alternate, the potential at node n1 continues to decrease. That is, the potential at node n1 decreases each time Phases F and G alternate.

[0093] If the shift register needs to stably output a high-level signal Vg through the Eout terminal, the potential of the n1 node must be greater than the sum of Vg and the threshold voltage Vth of t10. When phases F and G alternate, the potential of the n1 node continues to decrease, and when the potential of the n1 node becomes less than the sum of Vg and the threshold voltage Vth of t10, t10 is likely to turn off, causing the Eout terminal to float, which can easily lead to defects in the shift register output due to disturbances from other signals.

[0094] Moreover, even if t1 is turned on to make the Stv terminal and the n1 node conductive, when compensating the potential of the n1 node, due to the characteristics of the t1 transistor, the potential of the n1 node after compensation is equal to the high-level signal Vg of the Stv terminal minus the threshold voltage Vth of t1, that is, the potential of the n1 node is Vg-Vth, which is still less than Vg+Vth, and t10 cannot be guaranteed to be turned on.

[0095] To solve the above problem, some embodiments of the present disclosure provide a shift register that can prevent the problem of floating output terminal of t10 due to a decrease in the control electrode potential of t10 transistor.

[0096] FIG8 schematically shows a structural block diagram of a shift register. As shown in FIG8 , the shift register includes a first input circuit 10 , a first output circuit 20 , a second input circuit 30 , a second output circuit 50 and a second control circuit 60 .

[0097] The first input circuit 10 is electrically connected to the start signal terminal STV, the first node N1, and the first clock signal terminal CK. The first input circuit 10 is configured to write the signal of the start signal terminal STV into the first node N1 under the control of the first clock signal of the first clock signal terminal CK.

[0098] For example, when the first clock signal is a high-level signal, the first input circuit 10 is turned on, and the signal at the start signal terminal STV is written into the first node N1 through the first input circuit 10. At this time, when the signal at the start signal terminal STV is a high-level signal, the first node N1 is a high-level signal; when the signal at the start signal terminal STV is a low-level signal, the first node N1 is a low-level signal.

[0099] In practical applications, the scan driving circuit may further include a start signal line, which may be electrically connected to the start signal terminal STV, so that the start signal terminal STV obtains the start signal in the start signal line.

[0100] Illustratively, when the scan driving circuit includes multiple cascaded shift registers, the start signal terminal STV of the first shift register is electrically connected to the start signal line, and the start signal terminal STV of the next shift register is electrically connected to the output terminal EOUT of the previous shift register.

[0101] Exemplarily, the scan driving circuit may further include a plurality of clock signal lines, and the first clock signal terminal CK is electrically connected to one of the clock signal lines to obtain a first clock signal in the clock signal line.

[0102] The first output circuit 20 is electrically connected to the first node N1, the output terminal EOUT, and the first voltage terminal V1. The first output circuit 20 is configured to write the signal of the first voltage terminal V1 to the output terminal EOUT when it is turned on under the control of the signal of the first node N1.

[0103] For example, when the signal at the first node N1 is a high-level signal, the first output circuit 20 is turned on, and the signal at the first voltage terminal V1 is written to the output terminal EOUT through the first output circuit 20. When the signal at the first node N1 is a low-level signal, the first output circuit 20 is turned off, and there is no electrical connection between the first voltage terminal V1 and the output terminal EOUT.

[0104] The output terminal EOUT is used to be electrically connected to the gate line GL. The first voltage terminal V1 can be fed with a constant high-level signal.

[0105] The second input circuit 30 is electrically connected to the first node N1, the second node N2, the second voltage terminal V2, and the first clock signal terminal CK. The second input circuit 30 is configured to write the first clock signal to the second node N2 under the control of the signal at the first node N1, and to write the signal at the second voltage terminal V2 to the second node N2 under the control of the first clock signal.

[0106] For example, when the signal at the first node N1 is a high-level signal, the second input circuit 30 is turned on, and the first clock signal is written to the second node N2 through the second input circuit 30. When the first clock signal is a high-level signal, the second input circuit 30 is turned on, and the signal at the second voltage terminal V2 is written to the second node N2 through the second input circuit 30.

[0107] The second voltage terminal V2 can be connected to a constant high-level signal. For example, the first voltage terminal V1 and the second voltage terminal V2 are electrically connected to the same signal terminal, so that the first voltage terminal V1 and the second voltage terminal V2 are connected to the same high-level signal.

[0108] The second output circuit 50 is electrically connected to the fourth voltage terminal V4, the second node N2, and the output terminal EOUT. The second output circuit 50 is configured to write the signal of the fourth voltage terminal V4 to the output terminal EOUT when it is turned on under the control of the signal of the second node N2.

[0109] The fourth voltage terminal V4 can be supplied with a constant low-level signal. For example, the fourth voltage terminal V4 and the third voltage terminal V3 can be electrically connected to the same signal terminal, so that the same low-level signal can be supplied to the fourth voltage terminal V4 and the third voltage terminal V3. For example, a VGL line is further provided on the substrate, and a constant low-level signal is supplied to the VGL line. The fourth voltage terminal V4 and the third voltage terminal V3 are electrically connected to the VGL line at the same time.

[0110] The second control circuit 60 is electrically connected to the first node N1, the second node N2, the fifth voltage terminal V5, the second clock signal terminal CB, and the control terminal C. The second control circuit 60 is configured to, under the control of the signal of the second node N2, the second clock signal, and the signal of the control terminal C, disconnect the electrical connection between the first node N1 and the fifth voltage terminal V5 when the first output circuit 20 is turned on, and write the signal of the fifth voltage terminal V5 into the first node N1 when the second output circuit 50 is turned on.

[0111] For example, when the signal at the control terminal C is a low-level signal, the second control circuit 60 is not conductive, resulting in no conduction between the first node N1 and the fifth voltage terminal V5. When the signal at the control terminal C, the signal at the second node N2, and the second clock signal are all high-level signals, the second control circuit 60 is conductive, and the signal at the fifth voltage terminal V5 is written to the first node N1 through the second control circuit 60.

[0112] The fifth voltage terminal V5 can be connected to a constant low-level signal. For example, the fifth voltage terminal V5, the fourth voltage terminal V4, and the third voltage terminal V3 can be electrically connected to the same signal terminal. For example, the fifth voltage terminal V5, the fourth voltage terminal V4, and the third voltage terminal V3 are all electrically connected to the VGL line.

[0113] The shift register provided in the embodiment of the present disclosure can disconnect the electrical connection between the first node N1 and the fifth voltage terminal V5 through the second control circuit 60 when the first output circuit 20 is turned on, thereby preventing the charge of the first node N1 from being released to the fifth voltage terminal V5, that is, preventing the first output circuit 20 from being unable to continue to be turned on due to a drop in the potential of the first node N1.

[0114] The shift register may further include a first control circuit 40, which is electrically connected to the first node N1, the second node N2, the fourth node N4, the second clock signal terminal CB, and the third voltage terminal V3. The first control circuit 40 is configured to write the second clock signal to the fourth node N4 under the control of the signal at the second node N2 and the second clock signal at the second clock signal terminal CB, and to write the signal at the third voltage terminal V3 to the fourth node N4 under the control of the signal at the first node N1.

[0115] For example, when the signal at the second node N2 and the second clock signal are both high-level signals, the first control circuit 40 is turned on, and the second clock signal is written into the fourth node N4 via the first control circuit 40. When the signal at the first node N1 is high-level signal, the first control circuit 40 is turned on, and the signal at the third voltage terminal V3 is written into the fourth node N4 via the first control circuit 40.

[0116] The third voltage terminal V3 can be fed with a constant low-level signal.

[0117] Figure 9 schematically shows a block diagram of another shift register. Figure 10 schematically shows a block diagram of yet another shift register. As shown in Figures 9 and 10, the second control circuit 60 may include a first sub-circuit 61 and a second sub-circuit 62 connected in series between the fifth voltage terminal V5 and the first node N1.

[0118] The second sub-circuit 62 is configured to be disconnected when the first output circuit 20 is turned on, and to be turned on when the second output circuit 50 is turned on. The first sub-circuit 61 is electrically connected to the second node N2 and the second clock signal terminal CB. When the first sub-circuit 61 is turned on under the control of the signal at the second node N2 and the second clock signal, it is configured to cooperate with the second sub-circuit 62 to write the signal of the fifth voltage terminal V5 to the first node N1.

[0119] For example, when the signal at the second node N2 and the second clock signal are both high-level signals, the first sub-circuit 61 is turned on, and when the second output circuit 50 is turned on, the second sub-circuit 62 is turned on. The first sub-circuit 61 and the second sub-circuit 62 are turned on simultaneously, allowing the signal at the fifth voltage terminal V5 to be written to the first node N1 via the first sub-circuit 61 and the second sub-circuit 62. When the first output circuit 20 is turned on, the second sub-circuit 62 is turned off, disconnecting the fifth voltage terminal V5 from the first node N1.

[0120] The first sub-circuit 61 and the second sub-circuit 62 are connected in series between the fifth voltage terminal V5 and the first node N1, which means that when both the first sub-circuit 61 and the second sub-circuit 62 are turned on, the fifth voltage terminal V5 and the first node N1 are conductive, and when the second sub-circuit 62 is not conductive, the fifth voltage terminal V5 and the first node N1 are not conductive.

[0121] Exemplarily, the first subcircuit 61 and the second subcircuit 62 may be connected in series between the fifth voltage terminal V5 and the first node N1 as shown in FIG. 9 , and the second subcircuit 62 is located between the first subcircuit 61 and the first node.

[0122] Exemplarily, the first subcircuit 61 and the second subcircuit 62 may be connected in series between the fifth voltage terminal V5 and the first node N1 as shown in FIG. 10 , with the first subcircuit 61 located between the second subcircuit 62 and the first node.

[0123] Of course, the first sub-circuit 61 and the second sub-circuit 62 can also be connected in series in other ways, as long as when the second sub-circuit 62 is not conductive, there is no conductivity between the fifth voltage terminal V5 and the first node N1. For example, the second sub-circuit 62 is located within the first sub-circuit 61, and when the second sub-circuit 62 is not conductive, the first sub-circuit 61 is also not conductive.

[0124] By providing the second sub-circuit 62 in the second control circuit 60, and by making the second sub-circuit 62 non-conductive when the first output circuit 20 is conductive, the charge of the first node N1 will not be released to the fifth voltage terminal through the first sub-circuit 61 during the conductive process of the first output circuit 20, so that the first output circuit 20 can remain in the conductive state, thereby preventing output defects from occurring at the output terminal EOUT.

[0125] Figure 11 schematically shows a circuit diagram of a shift register, Figure 12 schematically shows a circuit diagram of another shift register, and Figure 13 schematically shows a circuit diagram of yet another shift register. As shown in Figures 11 to 13, the shift register includes a plurality of transistors, the first pole of each transistor being one of the source and drain of the transistor, and the second pole being the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first pole and the second pole of the transistor in the embodiments of the present disclosure can be structurally indistinguishable. The control pole of the transistor can be the gate of the transistor, and the gate is used to control the turning on or off of the transistor. In the shift registers provided in some embodiments of the present disclosure, only the example of each transistor being an N-type transistor is used for illustration.

[0126] As shown in Figures 11 to 13, the first sub-circuit 61 may include a fourth transistor T4 and a fifth transistor T5, the control electrode of the fourth transistor T4 is electrically connected to the second clock signal terminal CB, and the first electrode of the fourth transistor T4 is electrically connected to the first node N1; the control electrode of the fifth transistor T5 is electrically connected to the second node N2, the first electrode of the fifth transistor T5 is electrically connected to the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5 is electrically connected to the fifth voltage terminal V5.

[0127] The first electrode of the fifth transistor T5 and the second electrode of the fourth transistor T4 may be electrically connected directly or through the second sub-circuit 62. When the first electrode of the fifth transistor T5 and the second electrode of the fourth transistor T4 are electrically connected directly, the second sub-circuit 62 may be electrically connected between the fifth transistor T5 and the fifth voltage terminal V5, or between the fourth transistor T4 and the first node N1. When the first electrode of the fifth transistor T5 and the second electrode of the fourth transistor T4 are electrically connected through the second sub-circuit 62, the first electrode of the fifth transistor T5 is electrically connected to the second sub-circuit 62, and the second electrode of the fourth transistor T4 is electrically connected to the second sub-circuit 62.

[0128] For example, when the first output circuit 20 is turned on, the second sub-circuit 62 is not turned on, so that there is no conduction between the fifth voltage terminal V5 and the first node N1, and the charge of the N1 node will not be released to the fifth voltage terminal V5, that is, the potential of the N1 node will not continue to decrease, so that the first output circuit 20 can continue to be turned on under the control of the signal of the first node N1, preventing output defects from occurring in the shift register.

[0129] 11 to 13 , the second sub-circuit 62 may include an eleventh transistor T11 , the control electrode of the eleventh transistor T11 is electrically connected to the control terminal C, and the signal from the control terminal C controls the turning on or off of the eleventh transistor T11 .

[0130] Exemplarily, as shown in FIG11 , a first electrode of the eleventh transistor T11 is electrically connected to the first node N1 , and a second electrode of the eleventh transistor T11 is electrically connected to a first electrode of the fourth transistor T4 .

[0131] Exemplarily, as shown in FIG12 , the first electrode of the eleventh transistor T11 is electrically connected to the second electrode of the fifth transistor T5 , and the second electrode of the eleventh transistor T1 is electrically connected to the fifth voltage terminal V5 .

[0132] Exemplarily, as shown in FIG13 , the first electrode of the eleventh transistor T11 is electrically connected to the second electrode of the fourth transistor T4 , and the second electrode of the eleventh transistor T11 is electrically connected to the first electrode of the fifth transistor T5 .

[0133] For example, when the first output circuit 20 is turned on, the signal at the control terminal C is a low-level signal, and the eleventh transistor T11 is turned off. At this time, there is no conduction between the fifth voltage terminal V5 and the first node N1, and the charge of the N1 node will not be released to the fifth voltage terminal V5, that is, the potential of the N1 node will not continue to decrease, so that the first output circuit 20 can continue to be turned on under the control of the signal at the first node N1, thereby preventing output defects from occurring in the shift register.

[0134] The control terminal C can be electrically connected to the fourth node N4. That is, the control electrode of the eleventh transistor T11 is electrically connected to the fourth node N4. When the signal at the fourth node N4 is a low-level signal, the eleventh transistor T11 is turned off, and when the signal at the fourth node N4 is a high-level signal, the eleventh transistor T11 is turned on.

[0135] The first input circuit 10 may include a first transistor T1 , a first electrode of the first transistor T1 being electrically connected to the start signal terminal STV, a second electrode of the first transistor T1 being electrically connected to the first node N1 , and a control electrode of the first transistor T1 being electrically connected to the first clock signal terminal CK.

[0136] For example, when the first clock signal is a high-level signal, the first transistor T1 is turned on, and the signal at the start signal terminal STV is written into the first node N1 through the first transistor T1.

[0137] The first output circuit 20 may include a tenth transistor T10 , a first electrode of the tenth transistor T10 being electrically connected to the output terminal EOUT, a second electrode of the tenth transistor T10 being electrically connected to the first voltage terminal V1 , and a control electrode of the tenth transistor T10 being electrically connected to the first node N1 .

[0138] For example, when the signal at the first node N1 is a high-level signal, the tenth transistor T10 is turned on, and the signal at the first voltage terminal V1 is written into the output terminal EOUT through the tenth transistor T10 .

[0139] The first output circuit 20 may further include a first capacitor, one of the plates of the first capacitor being electrically connected to the first node N1, and the other plate of the first capacitor being electrically connected to the output terminal EOUT. When the first node N1 is connected to the start signal terminal STV and a high-level signal is written to it, the first capacitor can be charged simultaneously. When the first node N1 is disconnected from the start signal terminal STV, the first node N1 can maintain a high-level signal under the action of the first capacitor. Furthermore, when a high-level signal is written to the output terminal EOUT, the potential of the first node N1 can be increased due to the coupling effect of the first capacitor.

[0140] The second input circuit 30 may include a second transistor T2 and a third transistor T3 .

[0141] The control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the second node N2, and the second electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK. The control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the second voltage terminal V2.

[0142] For example, when the signal at the first node N1 is high, the second transistor T2 is turned on, and the first clock signal is written to the second node N2 through the second transistor T2. When the first clock signal is high, the third transistor T3 is turned on, and the signal at the second voltage terminal V2 is written to the second node N2 through the third transistor T3.

[0143] The first control circuit 40 may include a sixth transistor T6 , a seventh transistor T7 , an eighth transistor T8 , and a second capacitor C2 .

[0144] A control electrode of the sixth transistor T6 is electrically connected to the second node N2, a first electrode of the sixth transistor T6 is electrically connected to the fifth node N5, and a second electrode of the sixth transistor T6 is electrically connected to the second clock signal terminal CB. A control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, a first electrode of the seventh transistor T7 is electrically connected to the fourth node N4, and a second electrode of the seventh transistor T7 is electrically connected to the fifth node N5. A control electrode of the eighth transistor T8 is electrically connected to the first node N1, a first electrode of the eighth transistor T8 is electrically connected to the fourth node N4, and a second electrode of the eighth transistor T8 is electrically connected to the third voltage terminal V3. One plate of the second capacitor C2 is electrically connected to the first node N1, and the other plate is electrically connected to the fifth node N5.

[0145] For example, when the second node N2 and the second clock signal are both high-level signals, the sixth transistor T6 and the seventh transistor T7 are turned on, and the second clock signal is written into the fourth node N4 through the sixth transistor and the seventh transistor. When the signal at the first node N1 is high-level, the eighth transistor T8 is turned on, and the low-level signal at the third voltage terminal V3 is written into the fourth node N4 through the eighth transistor.

[0146] The second output circuit 50 may include a ninth transistor T9 and a third capacitor C3 .

[0147] A control electrode of the ninth transistor T9 is electrically connected to the fourth node N4, a first electrode of the ninth transistor T9 is electrically connected to the output terminal EOUT, and a second electrode of the ninth transistor T9 is electrically connected to the fourth voltage terminal V4. One plate of the third capacitor C3 is electrically connected to the fourth node N4, and the other plate is electrically connected to the fourth voltage terminal V4.

[0148] For example, when the signal at the fourth node N4 is high, the ninth transistor T9 turns on, and the low-level signal at the fourth voltage terminal V4 is written to the output terminal EOUT via the ninth transistor T9. Simultaneously, when a high-level signal is written to the fourth node N4, the third capacitor C3 is charged. When the fourth node N4 is floating, the fourth node N4 can maintain a high-level signal due to the action of the third capacitor C3.

[0149] Figure 14 schematically shows a signal timing diagram of each signal terminal in the shift register, and Figure 15 schematically shows a potential diagram during the operation of the shift register. The operation process of the shift register shown in Figure 13 will be described in detail below in conjunction with Figures 14 and 15.

[0150] Phase A: A low-level signal is applied to the start signal terminal STV, a high-level signal is applied to the first clock signal terminal CK, and a low-level signal is applied to the second clock signal terminal CB. The first transistor T1 is turned on by the high-level signal of the first clock signal terminal CK and writes the low-level signal of the start signal terminal STV to the first node N1. The second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off by the low-level signal of the first node N1, and no conduction occurs between the first voltage terminal V1 and the output terminal EOUT. The third transistor T3 is turned on by the high-level signal of the first clock signal terminal CK and writes the high-level signal of the second voltage terminal V2 to the second node N2. The fifth transistor T5 is turned on by the high-level signal of the second node N2 and writes the low-level signal of the fifth voltage terminal V5 to the sixth node N6. The fourth transistor T4 is turned off by the low-level signal of the second clock signal terminal CB, and no conduction occurs between the third node N3 and the first node N1. The sixth transistor T6 is turned on under the control of the high-level signal at the second node N2. The sixth transistor T6 writes the low-level signal from the second clock signal terminal CB to the fifth node N5, and simultaneously charges the second capacitor C2 electrically connected between the second node N2 and the fifth node N5. The seventh transistor T7 is turned off under the control of the low-level signal from the second clock signal terminal CB, causing the fourth node N4 to float. The eleventh transistor T11 is turned off, and the third node N3 and the sixth node N6 are not conductive. The ninth transistor T9 is turned off under the control of the signal at the fourth node N4, and there is no conduction between the fourth voltage terminal V4 and the output terminal EOUT. Therefore, there is no conduction between the output terminal EOUT and the fourth voltage terminal V4 and the first voltage terminal V1, and the output terminal EOUT is floating.

[0151] Phase B: A low-level signal is applied to the start signal terminal STV, a low-level signal is applied to the first clock signal terminal CK, and a high-level signal is applied to the second clock signal terminal CB. The first transistor T1 and the third transistor T3 are turned off by the low-level signal from the first clock signal terminal CK. There is no conduction between the start signal terminal STV and the first node N1, and there is no conduction between the second voltage terminal V2 and the second node N2. The second node N2 maintains a high-level signal due to the action of the second capacitor C2. The sixth transistor T6 is turned on by the high-level signal from the second node N2, and the seventh transistor T7 is turned on by the high-level signal from the second clock signal terminal CB. Conductive conduction occurs between the second clock signal terminal CB and the fourth node N4. The high-level signal from the second clock signal terminal CB is written to the fourth node N4, and the third capacitor C3, which is electrically connected between the third voltage terminal V3 and the fourth node N4, is charged. The fifth transistor T5 is turned on by a high-level signal at the second node N2, conducting the fifth voltage terminal V5 and the sixth node N6. The fourth transistor T4 is turned on by a high-level signal at the second clock signal terminal CB, conducting the third node N3 and the first node N1. The eleventh transistor T11 is turned on by a high-level signal at the fourth node N4, conducting the third node N3 and the sixth node N6, thereby establishing electrical conduction between the fifth voltage terminal V5 and the first node N1. The low-level signal at the fifth voltage terminal V5 is written to the first node N1. The second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off by a low-level signal at the first node N1, disabling electrical conduction between the first voltage terminal V1 and the output terminal EOUT. The ninth transistor T9 is turned on by a high-level signal at the fourth node N4, conducting electrical conduction between the fourth voltage terminal V4 and the output terminal EOUT. The low-level signal at the fourth voltage terminal V4 is written to the output terminal EOUT, and the shift register outputs a low-level signal.

[0152] Phase C: A low-level signal is applied to the start signal terminal STV, a high-level signal is applied to the first clock signal terminal CK, and a low-level signal is applied to the second clock signal terminal CB. The first transistor T1 is turned on by the high-level signal from the first clock signal terminal CK, and the low-level signal from the start signal terminal STV is written to the first node N1 via the first transistor T1. The second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off by the low-level signal from the first node N1, and no conduction occurs between the first voltage terminal V1 and the output terminal EOUT. The third transistor T3 is turned on by the high-level signal from the first clock signal terminal CK, and the high-level signal from the second voltage terminal V2 is written to the second node N2 via the third transistor T3. The sixth transistor T6 is turned on by the high-level signal from the second node N2, and the low-level signal from the second clock signal terminal CB is written to the fifth node N5 via the sixth transistor T6, simultaneously charging the second capacitor C2 electrically connected between the second node N2 and the fifth node N5. The seventh transistor T7 is turned off by the low-level signal from the second clock signal terminal CB, and no conduction occurs between the fifth node N5 and the fourth node N4. The fourth node N4 maintains a high-level signal under the action of the third capacitor C3. The eleventh transistor T11 is turned on by the high-level signal at the fourth node N4, and the sixth node N6 and the third node N3 are conductive. The fifth transistor T5 is turned on by the high-level signal at the second node N2, and the fifth voltage terminal V5 and the sixth node N6 are conductive. The fifth transistor T5 writes the low-level signal of the fifth voltage terminal V5 to the third node N3. The fourth transistor T4 is turned off by the low-level signal at the second clock signal terminal CB, and the third node N3 and the first node N1 are not conductive. The ninth transistor T9 is turned on by the high-level signal at the fourth node N4, and the fourth voltage terminal V4 and the output terminal EOUT are conductive, and the shift register outputs a low-level signal through the output terminal EOUT.

[0153] Phase D: A high-level signal is applied to the start signal terminal STV, a low-level signal is applied to the first clock signal terminal CK, and a high-level signal is applied to the second clock signal terminal CB. The first transistor T1 and the third transistor T3 are turned off by the low-level signal at the first clock signal terminal CK. The second node N2 maintains a high-level signal due to the action of the second capacitor C2. The sixth transistor T6 is turned on by the high-level signal at the second node N2, and the seventh transistor T7 is turned on by the high-level signal at the second clock signal terminal CB. Conductive conduction occurs between the second clock signal terminal CB and the fourth node N4, and the high-level signal at the second clock signal terminal CB is written to the fourth node N4. The eleventh transistor is turned on by the high-level signal at the fourth node N4, and the fifth transistor T5 is turned on by the high-level signal at the second node N2. The fourth transistor T4 is turned on by the high-level signal at the second clock signal terminal CB, and conductive conduction occurs between the fifth voltage terminal V5 and the first node N1. The low-level signal at the fifth voltage terminal V5 is written to the first node N1. The second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off under the control of the low-level signal at the first node N1, and no conduction occurs between the first voltage terminal V1 and the output terminal EOUT. The ninth transistor T9 is turned on under the control of the high-level signal at the fourth node N4, and conduction occurs between the fourth voltage terminal V4 and the output terminal EOUT. The low-level signal at the fourth voltage terminal V4 is written to the output terminal EOUT, and the shift register outputs a low-level signal through the output terminal EOUT.

[0154] Phase E: A high-level signal is applied to the start signal terminal STV, a high-level signal is applied to the first clock signal terminal CK, and a low-level signal is applied to the second clock signal terminal CB. The first transistor T1 is turned on by the high-level signal from the first clock signal terminal CK, and the high-level signal from the start signal terminal STV is written to the first node N1 via the first transistor T1. Due to the characteristics of the first transistor T1, the voltage at the first node N1 is the voltage Vh at the start signal terminal STV minus the threshold voltage Vth of the first transistor T1, i.e., the voltage at the first node N1 is Vh - Vth. The tenth transistor T10 is turned on by the high-level signal from the first node N1, conducting current between the first voltage terminal V1 and the output terminal EOUT, and the high-level signal from the first voltage terminal V1 is written to the output terminal EOUT. Furthermore, because the tenth transistor T10 itself forms a capacitor Cgs, Cgs is equivalent to having one plate electrically connected to the first node N1 and the other plate electrically connected to the output terminal EOUT. When a high-level signal from the first voltage terminal V1 is written to the output terminal EOUT, the level of the output terminal EOUT increases. Due to the coupling effect of the capacitor Cgs, the level of the first node N1 increases and becomes greater than the level of the start signal terminal STV. Simultaneously, the third transistor T3 is turned on by the high-level signal from the first clock signal terminal CK, and the high-level signal from the second voltage terminal V2 is written to the second node N2. The fifth transistor T5 is turned on by the high-level signal from the second node N2, and the low-level signal from the fifth voltage terminal V5 is written to the sixth node N6 via the fifth transistor T5. The eighth transistor T8 is turned on by the high-level signal from the first node N1, and the low-level signal from the third voltage terminal V3 is written to the fourth node N4 via the eighth transistor T8. The eleventh transistor T11 is turned off by the low-level signal from the fourth node N4, and the sixth node N6 and the third node N3 are not conductive. The fourth transistor T4 is turned off under the control of the low-level signal of the second clock signal terminal CB, and no conduction occurs between the third node N3 and the first node N1. The sixth transistor T6 is turned on under the control of the high-level signal of the second node N2. The low-level signal of the second clock signal terminal CB is written to the fifth node N5 through the sixth transistor T6, and the second capacitor C2 is charged. The seventh transistor T7 is turned off under the control of the low-level signal of the second clock signal terminal CB, and no conduction occurs between the fifth node N5 and the fourth node N4. The ninth transistor T9 is turned off under the control of the low-level signal of the fourth node N4, and no conduction occurs between the fourth voltage terminal V4 and the output terminal EOUT. The shift register outputs a high-level signal through the output terminal EOUT.

[0155] Phase F: A high-level signal is applied to the start signal terminal STV, a low-level signal is applied to the first clock signal terminal CK, and a high-level signal is applied to the second clock signal terminal CB. The first transistor T1 and the third transistor T3 are turned off by the low-level signal from the first clock signal terminal CK. The fourth transistor T4 is turned on by the high-level signal from the second clock signal terminal CB, conducting the first node N1 and the third node N3. Part of the charge from the first node N1 is written to the N3 node, causing the level of the first node N1 to decrease. Because the tenth transistor T10 forms a capacitor Cgs, the capacitor Cgs maintains a high-level signal at the first node N1. The second transistor T2 is turned on by the high-level signal from the first node N1, and the low-level signal from the first clock signal terminal CK is written to the second node N2 via the second transistor T2. The fifth transistor T5 is turned off by the low-level signal from the second node N2, and no conduction occurs between the sixth node N6 and the fifth voltage terminal. Simultaneously, the eighth transistor T8 is turned on by the high-level signal from the first node N1, and the low-level signal from the third voltage terminal V3 is written to the fourth node N4 via the eighth transistor T8. The eleventh transistor T11 is turned off under the control of the low-level signal at the fourth node N4, and the sixth node N6 and the third node N3 are disconnected. Due to the lack of conduction between the third node N3 and the fifth voltage terminal V5, the charge at the third node N3 is not released to the fifth voltage terminal V5, so that the level of the first node N1 does not continue to decrease. The high-level signal at the first node N1 can still control the tenth transistor T10 to turn on, and the high-level signal at the first voltage terminal V1 is written to the output terminal EOUT through the tenth transistor T10. The ninth transistor T9 is turned off under the control of the low-level signal at the fourth node N4, and there is no conduction between the fourth voltage terminal V4 and the output terminal EOUT. The shift register outputs a high-level signal through the output terminal EOUT.

[0156] Phase G: A high-level signal is applied to the start signal terminal STV, a high-level signal is applied to the first clock signal terminal CK, and a low-level signal is applied to the second clock signal terminal CB. Compared to Phase E, since the level of the first node N1 is higher than the level of the start signal terminal STV in Phase G, the source of the first transistor T1 is electrically connected to the start signal terminal STV, and the drain of the first transistor T1 is electrically connected to the first node N1. At this time, the Vgs of the first transistor T1 is the high-level signal of the first clock signal terminal CK minus the high-level signal of the start signal terminal STV, which is less than the threshold voltage of the first transistor T1 (for example, when the high-level signal of the first clock signal terminal CK is equal to the high-level signal of the start signal terminal STV, Vgs is equal to 0). The first transistor T1 is turned off, and there is no conduction between the start signal terminal STV and the first node N1. Furthermore, the third transistor T3 is turned on by the high-level signal of the first clock signal terminal CK, and the high-level signal of the second voltage terminal V2 is written to the second node N2 via the third transistor T3. The fifth transistor T5 is turned on by the high-level signal of the second node N2, and conduction is established between the fifth voltage terminal V5 and the sixth node N6. Since the eighth transistor T8 is turned on by the high-level signal of the first node N1, the low-level signal of the third voltage terminal V3 is written to the fourth node N4 via the eighth transistor T8. The eleventh transistor T11 is turned off by the low-level signal of the fourth node N4, and conduction is not established between the third node N3 and the sixth node N6. Therefore, the charge written to the third node N3 in phase F cannot be released via the fifth voltage terminal V5.

[0157] Within a display frame of the display panel, phases F and G alternate. During phase F, a portion of the charge at the first node N1 is written to the third node N3, causing the potential of the first node N1 to decrease. During phase G, since the eleventh transistor T11 is turned off, the third node N3 and the sixth node N6 are not conductive, that is, the third node N3 and the fifth voltage terminal V5 are not conductive, and the charge written to the third node N3 cannot be released to the fifth voltage terminal V5. When phases F and G alternate, the potential of the first node N1 does not continue to decrease, allowing the first node N1 to maintain a high potential. This reduces the risk of the tenth transistor T10 being shut down due to the decrease in the potential of the first node N1, allowing the output terminal EOUT to output stably.

[0158] The operation process of the shift register shown in Figures 11 and 12 is similar to the operation process of the shift register shown in Figure 13. Both can achieve the following: when the tenth transistor is turned on to output a high-level signal at the output terminal EOUT, the signal at the fourth node N4 is a low-level signal. Under the control of the low-level signal at the fourth node N4, the eleventh transistor 11 remains turned off, so that the fifth voltage terminal V5 and the first node N1 remain disconnected, and the charge at the first node N1 cannot be released to the fifth voltage terminal V5, so that the first node N1 can maintain a high-level signal. In turn, the tenth transistor T10 is turned on under the control of the high-level signal at the first node N1, so that the shift register can output a high-level signal at the first voltage terminal V1. Moreover, when the ninth transistor T9 is turned on, the signal of the fourth node N4 is a high-level signal, and the eleventh transistor T11 remains turned on under the control of the high-level signal of the fourth node N4, so that the fourth transistor T4 and the fifth transistor T5 are turned on in cooperation with the signal of the second node N2 and the second clock signal, so that the low-level signal of the fifth voltage terminal V5 is written into the first node N1, and the tenth transistor T10 remains turned off under the control of the low-level signal of the first node N1.

[0159] FIG15 schematically shows a layout of a shift register, and FIG16 schematically shows a layout of a first semiconductor strip.

[0160] As shown in FIG15 , the display panel includes a semiconductor layer, a first conductive layer, and a second conductive layer disposed on one side of a substrate.

[0161] The semiconductor layer includes a first semiconductor strip 11 and a second semiconductor strip 12 . The first semiconductor strip 11 includes the active layer of the fourth transistor T4 and the fifth transistor T5 . The second semiconductor strip 12 includes the active layer of the eleventh transistor T11 .

[0162] The first conductive layer includes a first conductive strip 21, a second conductive strip 22, and a third conductive strip 23. The first conductive strip 21 includes the gate of the fourth transistor T4, the second conductive strip 22 includes the gates of the fifth transistor T5 and the sixth transistor T6, and one plate of the second capacitor C2, and the third conductive strip 23 includes the gate of the eleventh transistor T11, the gate of the ninth transistor T9, and one plate of the third capacitor C3.

[0163] The second conductive layer includes a first bridge line 31 , which is electrically connected to the first semiconductor strip 11 and the second semiconductor strip 12 through a via.

[0164] The first bridge line 31 electrically connects the first semiconductor strip 11 and the second semiconductor strip 12 through a via, so that the first semiconductor strip 11 and the second semiconductor strip 12 are electrically connected. The first semiconductor strip 11 includes the active layer of the fourth transistor T4 and the fifth transistor T5, and the second semiconductor strip 12 includes the active layer of the eleventh transistor T11. That is, the fourth transistor T4, the fifth transistor T5, and the eleventh transistor T11 are connected in series.

[0165] Exemplarily, the semiconductor layer further includes a third semiconductor strip 13, which includes the active layer of the ninth transistor T9. The second conductive layer further includes a second bridge line 32, which is electrically connected to the active layer of the ninth transistor T9 and the second semiconductor strip 12 via a via. The active layer of the ninth transistor T9 is electrically connected to a second voltage line, which can receive a low-level signal. When the eleventh transistor T11 is turned off, the fourth transistor T4 and the fifth transistor T5 can be disconnected from the second voltage line, thereby preventing the charge at the first node from being released into the second voltage line through the fourth transistor T4, the fifth transistor T5, and the eleventh transistor T11.

[0166] As shown in FIG16 , the first semiconductor strip includes a first region 11 a and a second region 11 b. The first region 11 a is the active layer of the fourth transistor T4, and the second region 11 b is the active layer of the fifth transistor T5. The first bridge line 31 is connected to an end of the first region 11 a away from the second region 11 b through a via, or the first bridge line 31 is connected to an end of the second region 11 b away from the first region 11 a through a via.

[0167] When the first bridge line 31 is connected to the end of the first region 11a away from the second region 11b through a via, the eleventh transistor T11 is connected between the fourth transistor T4 and the first node N1; when the first bridge line 31 is connected to the end of the second region 11b away from the first region 11a through a via, the eleventh transistor T11 is connected between the second voltage line and the fifth transistor T5.

[0168] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0169] References herein to "one embodiment," "an embodiment," or "one or more embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Furthermore, please note that instances of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0170] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0171] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present disclosure may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0172] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A shift register, characterized in that: include: A first input circuit is electrically connected to the start signal terminal, the first node, and the first clock signal terminal, wherein the first input circuit is configured to write the signal of the start signal terminal into the first node under the control of the first clock signal of the first clock signal terminal; a first output circuit electrically connected to the first node, the output terminal, and the first voltage terminal, wherein the first output circuit is configured to write the signal of the first voltage terminal into the output terminal when the first output circuit is turned on under the control of the signal of the first node; a second input circuit, electrically connected to the first node, the second node, the second voltage terminal, and the first clock signal terminal, wherein the second input circuit is configured to write the first clock signal into the second node under the control of the signal of the first node, and to write the signal of the second voltage terminal into the second node under the control of the first clock signal; a second output circuit electrically connected to the fourth voltage terminal, the second node, and the output terminal, wherein the second output circuit is configured to write the signal of the fourth voltage terminal into the output terminal when the second output circuit is turned on under the control of the signal of the second node; The second control circuit is electrically connected to the first node, the second node, the fifth voltage terminal, the second clock signal terminal and the control terminal. The second control circuit is configured to, under the control of the signal of the second node, the second clock signal and the signal of the control terminal, disconnect the electrical connection between the first node and the fifth voltage terminal when the first output circuit is turned on, and write the signal of the fifth voltage terminal into the first node when the second output circuit is turned on.

2. The shift register according to claim 1, wherein: It also includes a first control circuit, which is electrically connected to the first node, the second node, the fourth node, the second clock signal terminal, and the third voltage terminal. The first control circuit is configured to write the second clock signal to the fourth node under the control of the signal of the second node and the second clock signal of the second clock signal terminal, and to write the signal of the third voltage terminal to the fourth node under the control of the signal of the first node.

3. The shift register according to claim 1, wherein: The second control circuit includes a first subcircuit and a second subcircuit connected in series between the fifth voltage terminal and the first node, The second sub-circuit is electrically connected to the control end, and the second sub-circuit is configured to, under the control of the signal of the control end, be disconnected when the first output circuit is turned on, and be disconnected when the second output circuit is turned on. The circuit is conducting when it is on; The first sub-circuit is electrically connected to the second node and the second clock signal terminal. The first sub-circuit is configured to cooperate with the second sub-circuit to write the signal of the fifth voltage terminal to the first node when the first sub-circuit is turned on under the control of the signal of the second node and the second clock signal of the second clock signal terminal.

4. The shift register according to claim 3, wherein: The first subcircuit includes a fourth transistor and a fifth transistor, wherein the control electrode of the fourth transistor is electrically connected to the second clock signal terminal, and the first electrode of the fourth transistor is electrically connected to the first node; the control electrode of the fifth transistor is electrically connected to the second node, the first electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is electrically connected to the fifth voltage terminal; The second sub-circuit is electrically connected between the fourth transistor and the fifth transistor, or between the fourth transistor and the first node, or between the fifth transistor and the fifth voltage terminal.

5. The shift register according to claim 4, wherein: The second sub-circuit includes an eleventh transistor, wherein a control electrode of the eleventh transistor is electrically connected to the control terminal. A first electrode of the eleventh transistor is electrically connected to the first node, and a second electrode of the eleventh transistor is electrically connected to a first electrode of the fourth transistor; Or, the first electrode of the eleventh transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the eleventh transistor is electrically connected to the first electrode of the fifth transistor; Alternatively, the first electrode of the eleventh transistor is electrically connected to the second electrode of the fifth transistor, and the second electrode of the eleventh transistor is electrically connected to the fifth voltage terminal.

6. The shift register according to any one of claims 1 to 5, wherein: The control end is electrically connected to the fourth node.

7. The shift register according to any one of claims 1 to 6, wherein: The first input circuit includes a first transistor, a first electrode of the first transistor is electrically connected to the start signal terminal, a second electrode of the first transistor is electrically connected to the first node, and a control electrode of the first transistor is electrically connected to the first clock signal terminal.

8. The shift register according to any one of claims 1 to 7, wherein: The first output circuit includes a tenth transistor, a first electrode of the tenth transistor is electrically connected to the output terminal, a second electrode of the tenth transistor is electrically connected to the first voltage terminal, and a control electrode of the tenth transistor is electrically connected to the first node.

9. The shift register according to claim 8, wherein:

10. The shift register according to claim 8, wherein: The first output circuit further includes a first capacitor, one of the plates of the first capacitor is electrically connected to the first node, and the other plate of the first capacitor is electrically connected to the output end.

11. The shift register according to any one of claims 1 to 10, wherein: The second input circuit comprises: a second transistor, a control electrode electrically connected to the first node, a first electrode electrically connected to the second node, and a second electrode electrically connected to the first clock signal terminal; The third transistor has a control electrode electrically connected to the first clock signal terminal, a first electrode electrically connected to the second node, and a second electrode electrically connected to the second voltage terminal.

12. The shift register according to claim 6, wherein: The first control circuit comprises: a sixth transistor, a control electrode electrically connected to the second node, a first electrode electrically connected to the fifth node, and a second electrode electrically connected to the second clock signal terminal; a seventh transistor, a control electrode electrically connected to the second clock signal terminal, a first electrode electrically connected to the fourth node, and a second electrode electrically connected to the fifth node; an eighth transistor, a control electrode electrically connected to the first node, a first electrode electrically connected to the fourth node, and a second electrode electrically connected to the third voltage terminal; A second capacitor, wherein one plate is electrically connected to the first node, and the other plate is electrically connected to the fifth node.

13. The shift register according to any one of claims 1 to 12, wherein: The second output circuit comprises: a ninth transistor, having a control electrode electrically connected to the fourth node, a first electrode electrically connected to the output terminal, and a second electrode electrically connected to the fourth voltage terminal; A third capacitor, wherein one plate is electrically connected to the fourth node, and another plate is electrically connected to the fourth voltage terminal.

14. The shift register according to any one of claims 1 to 13, wherein: The first voltage terminal and the second voltage terminal are configured to be electrically connected to the same signal terminal.

15. The shift register according to any one of claims 1 to 13, wherein: The third voltage terminal, the fourth voltage terminal, and the fifth voltage terminal are configured to be electrically connected to the same signal terminal.

16. A scanning driving circuit, characterized in that: The invention comprises a plurality of shift registers according to any one of claims 1 to 15, wherein the plurality of shift registers are cascaded.

17. A display device, characterized in that: It comprises a plurality of pixel driving circuits and a scanning driving circuit as claimed in claim 16, wherein the pixel driving circuit comprises a plurality of transistors, and the output end of the shift register in the scanning driving circuit is electrically connected to the control electrode of the transistor to provide an enable signal.

18. A display panel, characterized in that: include: substrate; A semiconductor layer, comprising a first semiconductor strip and a second semiconductor strip, wherein the first semiconductor strip comprises an active layer of a fourth transistor and a fifth transistor, and the second semiconductor strip comprises an active layer of an eleventh transistor; a first conductive layer, comprising a first conductive strip, a second conductive strip and a third conductive strip, wherein the first conductive strip comprises a gate of a fourth transistor, the second conductive strip comprises gates of the fifth transistor and the sixth transistor and one of the plates of the second capacitor, and the third conductive strip comprises a gate of an eleventh transistor, a gate of a ninth transistor and one of the plates of the third capacitor; The second conductive layer includes a first bridge line, and the first bridge line is electrically connected to the first semiconductor strip and the second semiconductor strip through a via hole.

19. The display panel according to claim 18, wherein: The first semiconductor strip includes a first region and a second region, the first region is an active layer of the fourth transistor, and the second region is an active layer of the fifth transistor; the first bridge wire is connected to an end of the first region away from the second region through a via, or the first bridge wire is connected to an end of the second region away from the first region through a via.

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