Display driving circuit, driving method of display panel and display device

Abstract

The invention discloses a display driving circuit, a driving method of a display panel (20) and a display device, and belongs to the technical field of display. The display driving circuit comprises a first display driving circuit (11), a second display driving circuit (12), a power supply circuit (13) and a time sequence control circuit (14). When the time sequence control circuit (14) is in an initialized state, the first display driving circuit (11) closes the plurality of pixels (P1) through the second display driving circuit (12), so that the phenomenon of splash screen of the display panel (20) under the control of an uncertain signal output by the time sequence control circuit (14) is avoided; moreover, when the time sequence control circuit (14) is in a state after the initialization state is ended, the plurality of pixels (P1) are driven by the second display driving circuit (12), so that the display panel (20) displays normally, and the display effect of the display device is improved.

Description

Display driving circuit, display panel driving method and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display driving circuit, a driving method for a display panel, and a display device. Background Art

[0002] A display device generally includes a display driver circuit, a gate driver circuit, and multiple rows of pixels. The display driver circuit is electrically connected to the gate driver circuit, which is in turn electrically connected to the multiple rows of pixels. The display driver circuit is configured to send a drive signal to the gate driver circuit, causing the gate driver circuit to scan the multiple rows of pixels row by row.

[0003] A display driver circuit includes a timing controller (TCON), a source driver circuit (SIC), and a power supply circuit. The power supply circuit is electrically connected to the timing controller and the source driver circuit, respectively, for supplying power to the timing controller and the source driver circuit. The source driver circuit is electrically connected to the timing controller and the gate driver circuit, respectively, for controlling the gate driver circuit based on timing signals output by the timing controller. The source driver circuit is also configured to provide drive signals to multiple pixels based on power provided by the power supply circuit.

[0004] However, the start-up time of the timing control circuit and the source driving circuit in the above display driving circuit is quite different, resulting in a poor display effect of the display device.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a display driving circuit, a display panel driving method, and a display device. The technical solution is as follows:

[0007] According to one aspect of the present application, a display driving circuit is provided. The display driving circuit is used for a display panel, the display panel including a plurality of pixels, and the display driving circuit includes:

[0008] a first display driving circuit, a second display driving circuit, a power supply circuit, and a timing control circuit;

[0009] The first display driving circuit is electrically connected to the power supply circuit and the timing control circuit respectively, the power supply circuit is used to send a first power supply signal to the first display driving circuit, and the timing control circuit is used to send a communication flag signal to the first display driving circuit;

[0010] The first display driving circuit is electrically connected to the second display driving circuit, and the first display driving circuit is configured to send a first control signal to the second display driving circuit when the level of the first power signal jumps from the first level to the second level, and send a second control signal to the second display driving circuit when the level of the communication flag signal jumps from the third level to the fourth level;

[0011] The second display driving circuit is electrically connected to the plurality of pixels, and is configured to turn off the plurality of pixels based on the first control signal and drive the plurality of pixels based on the second control signal.

[0012] Optionally, the first display driving circuit includes a comparison circuit and a source driving chip, and the comparison circuit is electrically connected to the power supply circuit and the source driving chip respectively;

[0013] The comparison circuit is configured to generate a first indication signal when detecting that the level of the first power signal output by the power circuit reaches the second level, and output the first indication signal to the source driver chip;

[0014] The source driver chip is configured to send a first control signal to the second display driver circuit based on the first indication signal.

[0015] Optionally, the first display driving circuit includes a comparison circuit and a source driving chip, and the comparison circuit is electrically connected to the timing control circuit and the source driving chip respectively;

[0016] The comparison circuit is configured to generate a second indication signal when detecting that the level of the communication flag signal output by the timing control circuit reaches a fourth level, and output the second indication signal to the source driver chip;

[0017] The source driver chip is configured to send a second control signal to the second display driver circuit based on the second indication signal.

[0018] Optionally, the timing control circuit is further configured to send a first driving timing signal to the first display driving circuit;

[0019] The first display driving circuit is used to stop sending the first control signal to the second display driving circuit when the level of the communication flag signal changes from the third level to the fourth level, and send a second driving timing signal to the second display driving circuit according to the first driving timing signal, wherein the high level amplitude of the second driving timing signal is greater than the high level amplitude of the first driving timing signal, and the second driving timing signal is the second control signal.

[0020] Optionally, the power supply circuit includes a first power supply circuit and a second power supply circuit;

[0021] The first power supply circuit is coupled to the first display driving circuit, the first power supply circuit is configured to send an analog power supply signal to the first display driving circuit, and the first display driving circuit is configured to send data signals to the plurality of pixels based on the analog power supply signal;

[0022] The second power supply circuit is electrically connected to the plurality of pixels, and the second power supply circuit is used to send a driving power signal to the plurality of pixels;

[0023] The plurality of pixels are configured to emit light based on the data signal and the driving power signal.

[0024] Optionally, the first control signal has the same level as the analog power signal.

[0025] Optionally, the pixel includes a light emitting device and a first transistor;

[0026] The second display driving circuit is electrically connected to the gate of the first transistor, the first electrode of the first transistor is electrically connected to the first display driving circuit terminal, and the second electrode of the first transistor is electrically connected to the second power supply circuit.

[0027] Optionally, the second level is greater than the first level, and the fourth level is greater than the third level.

[0028] According to another aspect of the present application, a method for driving a display panel is provided, which is applied to the first display driving circuit included in the display driving circuit described above, and the method includes:

[0029] In response to the first power signal sent by the power circuit jumping from a first level to a second level, sending a first control signal to the second display driving circuit;

[0030] In response to the communication flag signal sent by the timing control circuit jumping from the third level to the fourth level, sending a second control signal to the second display driving circuit;

[0031] The first control signal is used to instruct the second display driving circuit to control the plurality of pixels to be turned off, and the second control signal is used to instruct the second display driving circuit to drive the plurality of pixels.

[0032] Optionally, in response to the first power signal sent by the power circuit jumping from a first level to a second level, sending a first control signal to the second display driving circuit includes:

[0033] monitoring whether the transmission communication flag signal sent by the power supply circuit jumps from the first level to the second level;

[0034] generating a first indication signal in response to the level of the first power signal sent by the power circuit reaching the second level;

[0035] A first control signal is sent to the second display driving circuit based on the first indication signal.

[0036] Optionally, in response to the communication flag signal sent by the timing control circuit jumping from the third level to the fourth level, sending the second control signal to the second display driving circuit includes:

[0037] monitoring whether the transmission communication flag signal output by the timing control circuit jumps from the third level to the fourth level;

[0038] generating a second indication signal in response to the level of the transmission communication flag signal output by the timing control circuit reaching the fourth level;

[0039] A second control signal is sent to the second display driving circuit based on the second indication signal.

[0040] Optionally, the sending a second control signal to the second display driving circuit based on the second indication signal includes:

[0041] Based on the second indication signal, receiving a first driving timing signal sent by the timing control circuit;

[0042] A second driving timing signal is sent to the second display driving circuit according to the first driving timing signal, wherein the high level amplitude of the second driving timing signal is greater than the high level amplitude of the first driving timing signal.

[0043] According to another aspect of the present application, a display device is provided, comprising a display panel and a display driving circuit, wherein the display driving circuit is electrically connected to the display panel, and the display driving circuit is the display driving circuit of the above-mentioned display panel.

[0044] According to another aspect of the present application, a computer program product or computer program is provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the above-described display panel driving method.

[0045] The beneficial effects of the technical solutions provided in the embodiments of the present application include at least:

[0046] A display driver circuit is provided, comprising a first display driver circuit, a second display driver circuit, a power supply circuit, and a timing control circuit. The first display driver circuit can turn off multiple pixels in a display panel through the second display driver circuit when the level of a first power supply signal reaches a second level; the first display driver circuit can also drive multiple pixels in the display panel through the second display driver circuit when the level of a communication flag signal reaches a fourth level. In this way, the first display driver circuit can turn off multiple pixels through the second display driver circuit when the timing control circuit is in an initialization state, thereby avoiding the screen flickering phenomenon of the display panel under the control of the uncertain signal output by the timing control circuit; and when the timing control circuit is in an initialization state or in a state after initialization, the second display driver circuit can drive multiple pixels so that the display panel displays normally, thereby solving the problem of poor display effect of the display device in the related art and improving the display effect of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0048] FIG1 is a schematic structural diagram of a display driving circuit provided in an embodiment of the present application;

[0049] FIG2 is a schematic structural diagram of another display driving circuit provided in an embodiment of the present application;

[0050] FIG3 is a power-on timing diagram of a display driving circuit in the related art;

[0051] FIG4 is a power-on timing diagram of a display driving circuit provided in an embodiment of the present application;

[0052] FIG5 is a schematic structural diagram of a pixel driving circuit provided in an embodiment of the present application;

[0053] FIG6 is a schematic structural diagram of a level conversion circuit provided in an embodiment of the present application;

[0054] FIG7 is a power-on timing diagram of a level conversion circuit provided in an embodiment of the present application;

[0055] FIG8 is a schematic structural diagram of a first display driving circuit provided in an embodiment of the present application;

[0056] FIG9 is a flow chart of a method for driving a display panel according to an embodiment of the present application;

[0057] FIG10 is a flowchart of another display panel driving method provided in an embodiment of the present application;

[0058] FIG11 is a schematic structural diagram of a display device provided in an embodiment of the present application.

[0059] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0060] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0061] Currently, in active-matrix organic light-emitting diode (AMOLED) display products, a gate driver circuit can be used to scan and drive multiple rows of pixels (pixels) included in a display panel (panel) row by row, allowing the display panel to complete the display. Because the gate driver circuit is currently integrated on the array substrate included in the display panel, it can also be called an array substrate row driver (GOA) circuit. For example, the gate driver circuit can be electrically connected to a display driver circuit disposed on the periphery of the display panel and can be electrically connected to multiple rows of pixels via multiple gate lines in a one-to-one correspondence. The gate driver circuit can be used to receive multiple drive signals transmitted by the display driver circuit and, driven by these multiple drive signals, sequentially apply a turn-on voltage or a turn-off voltage to the multiple gate lines to control the operation of the pixel circuits in the pixels. This allows the multiple rows of pixel circuits to be turned on row by row. The pixel circuit can further transmit a light-emitting drive voltage to the light-emitting elements in the pixels to drive the light-emitting elements to emit light, that is, to illuminate the light-emitting elements. The turn-on voltage and turn-off voltage can be referred to as gate drive signals. It can also be determined that the turning on or off of the pixel circuit in each row of pixels is mainly achieved by the turn-on voltage or turn-off voltage applied by the gate driving circuit to the gate line electrically connected to it. The turn-on voltage can also be called the row turn-on voltage.

[0062] The display driver circuit includes a timing control circuit, a source driver circuit, and a power supply circuit. The power supply circuit is electrically connected to the timing control circuit and the source driver circuit, respectively, for supplying power to the timing control circuit and the source driver circuit, respectively. The source driver circuit is electrically connected to the timing control circuit and the gate driver circuit, respectively, for controlling the gate driver circuit according to a timing signal output by the timing control circuit. The source driver circuit is also configured to provide drive signals to multiple pixels based on power provided by the power supply circuit.

[0063] However, the startup times of the timing control circuit and the source driver circuit in the above-mentioned display driver circuit differ significantly. That is, after the power supply circuit powers on the timing control circuit and the source driver circuit, the timing control circuit undergoes a period of initialization. During this initialization process, the timing control circuit is unable to normally output timing control signals to the source driver circuit, resulting in the source driver circuit being unable to control the gate driver circuit. At this time, the source driver circuit may send an uncertain signal to the gate driver circuit. The uncertain signal includes a disordered high-level signal or a low-level signal, causing the gate driver circuit to be uncontrollable and the pixels electrically connected to the gate driver circuit to be in an abnormal operating state. This causes the current display image of the display panel to flicker, resulting in a poor display effect of the display device.

[0064] The embodiments of the present application provide a display driving circuit, a display panel driving method, and a display device, which can solve the problems existing in the related art.

[0065] FIG1 is a schematic diagram of the structure of a display driver circuit 10 provided in an embodiment of the present application. Referring to FIG1 , the display driver circuit 10 can be used in a display panel 20, which can include a plurality of pixels p1. The display driver circuit 10 can include a first display driver circuit 11, a second display driver circuit 12, a power supply circuit 13, and a timing control circuit 14. The first display driver circuit 11 can include a source driver circuit, and the second display driver circuit 12 can include a gate driver circuit.

[0066] The first display driver circuit 11 can be electrically connected to the power supply circuit 13 and the timing control circuit 14, respectively. The power supply circuit 13 can be used to send a first power signal to the first display driver circuit 11. The first power signal can be an analog power signal (AVDD). The first display driver circuit 11 can send a data signal (Vdate) to the plurality of pixels p1 based on the analog power signal (AVDD). The timing control circuit 14 can be used to send a communication flag signal (BCLD) to the first display driver circuit 11. The communication flag signal (BCLD) is a flag bit that indicates that the communication between the timing control circuit 14 and the first display driver circuit 11 is normal. That is, when the communication flag signal (BCLD) is at a high level, it indicates that the timing control circuit 14 can send a normal timing control signal to the source driver circuit.

[0067] The first display driving circuit 11 can be electrically connected to the second display driving circuit 12. The first display driving circuit 11 is used to send a first control signal to the second display driving circuit 12 when the level of the first power supply signal jumps from the first level to the second level. The second display driving circuit 12 is electrically connected to multiple pixels p1. The second display driving circuit 12 is used to turn off the multiple pixels p1 based on the first control signal.

[0068] Since the level of the first power signal jumps from the first level to the second level, it can be indicated that the power supply circuit 13 has currently sent the first power signal to the first display driver circuit 11, and the first display driver circuit 11 can send a data signal (Vdate) to multiple pixels p1 based on the first power signal. At this time, the second display driver circuit 112 is in an uncontrollable state, and the second display driver circuit 12 may send a low-level signal or a high-level signal to the multiple pixels p1. The high-level signal and the low-level signal can be one of a shutdown signal and an open signal, respectively. When the second display driver circuit 12 sends an open signal to the multiple pixels p1, the multiple pixels p1 can emit light under the action of the open signal and the data signal (Vdate), causing the display panel 20 to experience screen flicker. Therefore, the first display driver circuit 11 can send a first control signal to the second display driver circuit 12, so that the second display driver circuit 12 can send a close signal to the multiple pixels p1 according to the first control signal to close the multiple pixels p1, so that the display panel 20 is in a black screen state.

[0069] Furthermore, the first display driver circuit 11 is further configured to send a second control signal to the second display driver circuit 12 when the level of the communication flag signal jumps from the third level to the fourth level, and the second display driver circuit 12 is configured to drive multiple pixels p1 based on the second control signal. When the level of the first power supply signal jumps from the third level to the fourth level, it can indicate that the timing control circuit 14 is currently initialized and the timing control circuit 14 can send a normal timing control signal to the first display driver circuit 11. At this time, the first display driver circuit 11 can send a data signal (Vdate) to multiple pixels p1 based on the first power supply signal. Thus, the first display driver circuit 11 can send a second control signal to the second display driver circuit 12, and the second display driver circuit 12 can send a drive signal (the drive signal may include a sequential on signal and an off signal) to the multiple pixels p1 according to the second control signal to drive the multiple pixels p1 to emit light normally, so that the display panel 20 is in a normal display state.

[0070] In summary, the embodiments of the present application provide a display driver circuit comprising a first display driver circuit, a second display driver circuit, a power supply circuit, and a timing control circuit. The first display driver circuit can turn off multiple pixels in the display panel through the second display driver circuit when the level of the first power supply signal reaches the second level; the first display driver circuit can also drive multiple pixels in the display panel through the second display driver circuit when the level of the communication flag signal reaches the fourth level. In this way, the first display driver circuit can turn off multiple pixels through the second display driver circuit when the timing control circuit is in the initialization state, thereby avoiding the display panel from flickering under the control of the uncertain signal output by the timing control circuit; and when the timing control circuit is in the initialization state or in a state after the initialization is completed, the second display driver circuit can drive multiple pixels so that the display panel displays normally, which can solve the problem of poor display effect of the display device in the related art and improve the display effect of the display device.

[0071] It should be noted that the first level and the second level in the embodiment of the present application can be two levels with different amplitudes, and the third level and the fourth level can be two levels with different amplitudes. The embodiment of the present application does not limit the specific amplitudes of the first level, the second level, the third level and the fourth level.

[0072] FIG2 is a schematic diagram of the structure of another display driver circuit 10 provided in an embodiment of the present application. Referring to FIG2 , in an optional embodiment, the timing control circuit 14 may also be configured to send a first drive timing signal to the first display driver circuit 11. The first display driver circuit 11 may be configured to stop sending the first control signal to the second display driver circuit 12 when the level of the communication flag signal changes from the third level to the fourth level, and to send a second drive timing signal to the second display driver circuit 12 based on the first drive timing signal. The high-level amplitude of the second drive timing signal is greater than the high-level amplitude of the first drive timing signal, and the second drive timing signal may be a second control signal.

[0073] That is, the timing control circuit 14 can be used to send a first drive timing signal and display data to the first display driver circuit 11, and the first drive timing signal can be gate drive timing data. The first display driver circuit 11 can be used to send a second drive timing signal to the second display driver circuit 12 according to the first drive timing signal, and the second drive timing signal can be a gate drive timing signal. The first display driver circuit 11 can also send display drive data to the display panel 20. The first drive timing signal may include configuration information of the gate drive timing signal, and the configuration information includes at least one of a duty cycle, a rising edge slope, a high level amplitude, a frequency, and a signal duration. In an embodiment of the present application, the first drive timing signal may include a light-emitting control signal (EMGOA) and a gate control signal (GATEGOA), wherein the light-emitting control signal (EMGOA) may include a first start signal (ESTV) and a first clock signal (ECB and ECK), and the gate control signal (GATEGOA) may include a second start signal (GSTV) and a second clock signal (GCB and GCK).

[0074] The first display driver circuit 11 may include a voltage conversion (Level Shift; abbreviated as: LS) ​​circuit and a source driver chip 113. The voltage conversion circuit 111 may be integrated into the source driver chip 113. The input end of the voltage conversion circuit 111 may be electrically connected to the timing control circuit 14, and the output end of the voltage conversion circuit 111 may be electrically connected to the second display driver circuit 12. The first display driver circuit 11 may convert display data into an analog voltage and transmit it to the display panel 20. The first display driver circuit 11 may also boost the voltage of the first drive timing signal through the voltage conversion circuit 111 and transmit it to the display panel 20.

[0075] FIG3 is a power-on timing diagram of a display driver circuit 10 in the related art, and FIG4 is a power-on timing diagram of a display driver circuit 10 provided in an embodiment of the present application. Please refer to FIG2, FIG3 and FIG4. Optionally, the power supply circuit 13 may include a first power supply circuit 131 (PMIC) and a second power supply circuit 132 (ELIC). The first power supply circuit 131 is electrically connected to the first display driver circuit 11, and the first power supply circuit 131 is used to transmit an analog power signal (AVDD) to the first display driver circuit 11, and the first display driver circuit 11 is used to transmit a data signal (Vdata) to multiple pixels p1 based on the analog power signal (AVDD). The second power supply circuit 132 is electrically connected to the multiple pixels p1, and the second power supply circuit 132 is used to transmit a driving power signal (ELVDD) to the multiple pixels p1. Multiple pixels p1 can be used to emit light based on the data signal (Vdata) and the driving power signal (ELVDD).

[0076] The first power supply circuit 131 can also provide a device interface power supply (VDDIO) to the first display driving circuit 11 and the timing control circuit 14, and provide a high-level output signal (VGH), a low-level output signal (VGL), a first reference voltage (VGMP), a second reference voltage (VGSP), a first initial signal (Vint1; abbreviated: V1) and a second initial signal (Vint2; abbreviated: V2) to the first display driving circuit 11.

[0077] As can be seen from Figures 2 and 3. During the power-on process of the display driver circuit 10, the first power supply circuit 131 is first powered by an external power supply (3.3V). At this time, the first power supply circuit 131 provides the operating voltage (Vcore, abbreviated as: Vc, 0.9V) and the interface voltage (VIO, 1.8v) to the timing control circuit 14. The timing control circuit 14 may have a register 15, which stores the configuration data of the timing control circuit 14. The initialization process of the timing control circuit 14 may include the following two stages: the first stage is the process of the operating voltage (Vcore) and the interface voltage (IO) from the initial output to the stable output, and the process duration is about 100ms. The second stage is that after the voltage on the timing control circuit 14 stabilizes, the timing control circuit 14 downloads the configuration data stored in the register 15 from the register and performs initialization configuration according to the configuration data. The process duration is about 50ms. After the timing control circuit 14 completes the initialization of the above two stages, it can send the first driving timing signal to the voltage conversion circuit 111 in the first display driving circuit 11. That is, after receiving the two voltages output by the first voltage circuit, the timing control circuit 14 needs to be initialized for 150ms before it can normally output the first driving timing signal. However, during this process, the level of the first power signal provided by the power supply circuit 13 to the first display driving circuit 11 has jumped from the first level to the second level. The first power signal can be an analog power signal (AVDD), that is, the level of the analog power signal (AVDD) provided by the first power supply circuit 131 to the first display driving circuit 11 has jumped from a low level to a high level. The first power supply circuit 131 can now normally transmit the analog power signal (AVDD) to the first display driving circuit 11. The first display driving circuit 11 can be used to transmit data signals (Vdata) to multiple pixels p1 based on the analog power signal (AVDD). The second driving circuit is in an uncontrollable state. It is possible for the second driving circuit to send a low-level signal or a high-level signal to the multiple pixels p1. The high-level signal and the low-level signal can be one of a shutdown signal and an on signal, respectively. When the second driving circuit sends an on signal to the multiple pixels p1, the multiple pixels p1 may emit light under the action of the on signal and the data signal (Vdate), causing screen flickering on the display panel 20.

[0078] As shown in FIG. 4 , in the embodiment of the present application, the initialization process of the timing control circuit 14 may include two stages. In the first stage, the first power supply circuit 131 has not yet outputted the analog power supply signal (AVDD) to the first display driver circuit 11. At this time, the first display driver circuit 11 cannot send the data signal (Vdate) to the plurality of pixels p1 based on the analog power supply signal (AVDD). Therefore, in this stage, the timing signals (ESTV, ECB, ECK, GATEGOA, GCB, and GCK) outputted by the voltage conversion circuit 111 are in an uncontrollable state and do not affect the display image of the display panel. In the second stage, after the first power supply circuit 131 outputs the analog power supply signal (AVDD) to the first display driver circuit 11, the first display driver circuit 11 can control the second display driver circuit 12 based on the changes in the analog power supply signal (AVDD). That is, when the analog power supply signal (AVDD) jumps from a low level to a high level, since the voltage conversion circuit 111 in the first display driving circuit 11 has not yet received the first driving timing signal output by the timing control circuit 14, the voltage conversion circuit 111 is still in a non-operating state. Therefore, the first display driving circuit 11 can send a first control signal to the second display driving circuit 12. That is, the first display driving circuit 11 can uniformly pull up the output signal of the voltage conversion circuit 111 to control the output signal of the voltage conversion circuit 111 to be a high level, so that the gate control signal (GATEGOA) received in the second display driving circuit 12 can all be high levels. The second display driving circuit 12 can receive the high-level signal and send a shutdown signal to multiple pixels p1 according to the high-level signal to turn off multiple pixels p1.

[0079] Alternatively, the first control signal may include the gate control signal (GATEGOA) and the emission control signal (EMGOA) received in the second display driving circuit 12, that is, the first display driving circuit 11 may control the output signals of the voltage conversion circuit 111 to be high levels, so that the gate control signal (GATEGOA) and the emission control signal (EMGOA) received in the second display driving circuit 12 may be high levels, and the second display driving circuit 12 may receive the high-level signal and send a shutdown signal to multiple pixels p1 according to the high-level signal to shut down multiple pixels p1.

[0080] FIG5 is a schematic diagram of the structure of a pixel driving circuit provided in an embodiment of the present application. Referring to FIG5 , pixel p1 may optionally include a light-emitting device and a first transistor T1. A second display driving circuit 12 is electrically connected to the gate of the first transistor T1. A first electrode of the first transistor T1 is electrically connected to a terminal of the first display driving circuit 11. A second electrode of the first transistor T1 is electrically connected to a second power supply circuit 132. The first transistor T1 may include a P-type transistor. The first display driving circuit 11 may send a first control signal to the second display driving circuit 12. The second display driving circuit 12 may apply a high level to the gate of the first transistor T1 based on a gate control signal (GateGOA; abbreviated GGOA) to turn off the first transistor T1. This prevents the first electrode of the first transistor T1 from conducting a data signal (Vdata; abbreviated Vd) provided by the first display driving circuit 11, and the pixel p1 may be in an off state.

[0081] In an exemplary embodiment, pixel p1 may include a second transistor T2 and another transistor T3. The second display driver circuit 12 may be electrically connected to the gate of the second transistor T2, and the first electrode of the second transistor T2 is electrically connected to the second power supply circuit 132. The power supply circuit 13 is electrically connected, and the second electrode of the first transistor T1 is electrically connected to the other transistors T3. The second power supply circuit 132 is used to transmit a driving power signal (ELVDD) to the gate of the second transistor T2. The second display driver circuit 12 may apply a high level to the gate of the second transistor T2 based on the emission control signal (EMGOA) to turn off the second transistor T2. In this way, the two transistors connected to the second display driver circuit 12 can be turned off, further improving the stability of the pixel p1 when in the off state.

[0082] In an optional implementation, the first transistor T1 may include an N-type transistor, and the shutdown signal output from the second display driving circuit 12 to the first transistor T1 may be at a low level.

[0083] As shown in FIG4 , the first control signal can optionally have the same level as the analog power signal. Since other reference signals in the display driver circuit 10 have not yet been fully activated during this process, the voltage of the analog power signal that has been normally output can be used as the reference voltage for the first control signal.

[0084] FIG6 is a schematic diagram of the structure of a level conversion circuit provided in an embodiment of the present application, and FIG7 is a power-on timing diagram of a level conversion circuit provided in an embodiment of the present application. Referring to FIG6 and FIG7, the level conversion circuit may have multiple input signals, which may include a first input signal (GPIO Input), a communication flag signal (BCLD), an analog power signal (AVDD), a high-level output signal (VGH), and a low-level output signal (VGL), and may also have a first output signal (GPIO Output). As shown in FIG7, during the initial time period, that is, after the analog power signal (AVDD) sent by the power supply circuit 13 to the first display driver circuit 11 jumps from the first level (low level) to the second level (high level), and before the communication flag signal (BCLD) sent by the timing control circuit 14 to the first display driver circuit 11 jumps to the fourth level, the first display driver circuit 11 may control the level of the first output signal (GPIO Output) of the level conversion circuit to be high, that is, the level conversion circuit may uniformly pull up the output signal to turn off multiple pixels p1 through the second display driver circuit 12. Until the timing control circuit 14 sends a communication flag signal (BCLD) to the first display driving circuit 11 and jumps from the third level (low level) to the fourth level (high level), it indicates that the timing control circuit 14 is currently initialized. The timing control circuit 14 can send a normal timing control signal to the level conversion circuit in the first display driving circuit 11. The first display driving circuit 11 can control the first output signal (GPIO Output) of the level conversion circuit to be the second driving timing signal. At this time, the level conversion circuit starts to output normally.

[0085] That is, before the timing control circuit 14 is initialized, the first display driving circuit 11 can control the pixel p1 on the display panel 20 to remain off according to the power-on timing to avoid abnormal display on the display panel 20 .

[0086] FIG8 is a schematic structural diagram of a first display driver circuit 11 provided in an embodiment of the present application. Referring to FIG8 , the first display driver circuit 11 may optionally include a comparison circuit 112 and a source driver chip 113. The comparison circuit 112 is electrically connected to the power supply circuit 13 and the source driver chip 113, respectively. The comparison circuit 112 may be integrated on the source driver chip 113.

[0087] The comparison circuit 112 can be configured to generate a first indication signal when detecting that the level of the first power signal output by the power supply circuit 13 reaches a second level, and output the first indication signal to the source driver chip 113. The source driver chip 113 is configured to send a first control signal to the second display driver circuit 12 based on the first indication signal. The second level can be the level when the first power signal output by the power supply circuit 13 is in a normal operating state. For example, when the second level reaches 8V, the comparison circuit 112 can send the first indication signal to the source driver chip 113, so that the source driver chip 113 can respond promptly to changes in the first power signal output by the power supply circuit 13.

[0088] In an optional embodiment, the first display driver circuit 11 includes a comparison circuit 112 and a source driver chip 113, and the comparison circuit 112 is electrically connected to the timing control circuit 14 and the source driver chip 113, respectively. The comparison circuit 112 is used to generate a second indication signal when it detects that the level of the communication flag signal output by the timing control circuit 14 reaches a fourth level, and output the second indication signal to the source driver chip 113. The source driver chip 113 is used to send a second control signal to the second display driver circuit 12 based on the second indication signal. The fourth level can be a mark level when the communication between the timing control circuit 14 and the source driver chip 113 is in a normal working state. For example, when the fourth level reaches 1.8V, the comparison circuit 112 can send a second indication signal to the source driver chip 113, so that the source driver chip 113 can promptly receive the communication flag signal indicating that the initialization of the timing control circuit 14 is completed.

[0089] It should be noted that two comparison circuits 112 can be set in the first display driving circuit 11 and electrically connected to the power supply circuit 13 and the timing control circuit 14 respectively, or one comparison circuit 112 can be set and electrically connected to the power supply circuit 13 and the timing control circuit 14 respectively. This embodiment of the present application is not limited to this.

[0090] In an optional implementation, the second level may be greater than the first level, and the fourth level may be greater than the third level. The first level and the third level may both be 0V.

[0091] In summary, the embodiment of the present application provides a display driving circuit including a first display driving circuit, a second display driving circuit, a power supply circuit, and a timing control circuit. The first display driving circuit can turn off multiple pixels in the display panel through the second display driving circuit when the level of the first power supply signal reaches the second level; the first display driving circuit can also drive multiple pixels in the display panel through the second display driving circuit when the level of the communication flag signal reaches the fourth level. In this way, the first display driving circuit can turn off multiple pixels through the second display driving circuit when the timing control circuit is in the initialization state, thereby avoiding the screen flickering phenomenon of the display panel under the control of the uncertain signal output by the timing control circuit; and when the timing control circuit is in the initialization state and in the state after the initialization is completed, the second display driving circuit can drive multiple pixels so that the display panel displays normally, which can solve the problem of poor display effect of the display device in the related art and improve the display effect of the display device.

[0092] FIG9 is a flow chart of a method for driving a display panel according to an embodiment of the present application. The method can be applied to the first display driving circuit included in the display driving circuit shown in the above embodiment. As shown in FIG9 , the method includes:

[0093] Step 901: In response to a first power signal sent by a power supply circuit jumping from a first level to a second level, a first control signal is sent to a second display driving circuit.

[0094] Step 902: In response to the communication flag signal sent by the timing control circuit jumping from the third level to the fourth level, send a second control signal to the second display driving circuit.

[0095] The first control signal is used to instruct the second display driving circuit to control the plurality of pixels to be turned off, and the second control signal is used to instruct the second display driving circuit to drive the plurality of pixels.

[0096] In summary, an embodiment of the present application provides a method for driving a display panel, which is used for a first driving circuit in a display driving circuit, wherein the display driving circuit includes a first display driving circuit, a second display driving circuit, a power supply circuit, and a timing control circuit. The first display driving circuit can turn off multiple pixels in the display panel through the second display driving circuit when the level of the first power supply signal reaches the second level; the first display driving circuit can also drive multiple pixels in the display panel through the second display driving circuit when the level of the communication flag signal reaches the fourth level. In this way, the first display driving circuit can turn off multiple pixels through the second display driving circuit when the timing control circuit is in an initialization state, thereby avoiding the screen flickering phenomenon of the display panel under the control of the uncertain signal output by the timing control circuit; and when the timing control circuit is in the initialization state or in a state after the initialization is completed, the second display driving circuit can drive multiple pixels so that the display panel displays normally, which can solve the problem of poor display effect of the display device in the related art and improve the display effect of the display device.

[0097] FIG10 is a flow chart of another display panel driving method provided in an embodiment of the present application, which can be applied to the first display driving circuit included in the display driving circuit shown in the above embodiment. As shown in FIG10 , the method includes:

[0098] Step 1001: Monitor whether the transmission communication flag signal sent by the power supply circuit jumps from the first level to the second level.

[0099] The first display driver circuit may include a comparison circuit and a source driver chip, wherein the comparison circuit is electrically connected to the power supply circuit and the source driver chip, respectively. The comparison circuit may be integrated on the source driver chip. The comparison circuit may monitor whether the level of the first power signal output by the power supply circuit reaches the second level.

[0100] Step 1002: In response to the level of the first power signal sent by the power circuit reaching a second level, generate a first indication signal.

[0101] The second level may be the level when the first power signal output by the power supply circuit is in a normal working state. For example, when the second level reaches 8V, the comparison circuit may send a first indication signal to the source driver chip so that the source driver chip can respond to changes in the first power signal output by the power supply circuit in a timely manner.

[0102] Step 1003: Send a first control signal to the second display driving circuit based on the first indication signal.

[0103] The source driver chip may send a first control signal to the second display driver circuit based on the first indication signal, wherein the first control signal is used to instruct the second display driver circuit to control the plurality of pixels to be turned off.

[0104] Step 1004: monitor whether the transmission communication flag signal output by the timing control circuit jumps from the third level to the fourth level.

[0105] The first display driver circuit may include a comparison circuit and a source driver chip, wherein the comparison circuit is electrically connected to the power supply circuit and the source driver chip, respectively. The comparison circuit may be integrated on the source driver chip. The comparison circuit may monitor whether the transmission communication flag signal output by the timing control circuit reaches a fourth level.

[0106] Step 1005 : In response to the level of the communication sending flag signal output by the timing control circuit reaching a fourth level, generate a second indication signal.

[0107] The fourth level may be a flag level when the communication between the timing control circuit and the source driver chip is in a normal working state. For example, when the fourth level reaches 1.8 V, the comparison circuit may send a second indication signal to the source driver chip so that the source driver chip can promptly receive the communication flag signal indicating that the initialization of the timing control circuit is completed.

[0108] Step 1006: Send a second control signal to the second display driving circuit based on the second indication signal.

[0109] A second control signal may be sent to the second display driving circuit via the source driving chip based on the second indication signal, wherein the second control signal instructs the second display driving circuit to drive the plurality of pixels.

[0110] Optionally, step 1006 may include the following two steps:

[0111] (1) Based on the second indication signal, a first driving timing signal sent by the timing control circuit is received.

[0112] The first driving timing signal may include configuration information of the gate driving timing signal, where the configuration information includes at least one of a duty cycle, a rising edge slope, a high level amplitude, a frequency, and a signal duration.

[0113] (2) Sending a second driving timing signal to the second display driving circuit according to the first driving timing signal, wherein the high level amplitude of the second driving timing signal is greater than the high level amplitude of the first driving timing signal.

[0114] The first display driver circuit may include a voltage conversion (Level Shift; abbreviated as LS) circuit and a source driver chip. The voltage conversion circuit may be integrated into the source driver chip. The input end of the voltage conversion circuit may be electrically connected to the timing control circuit, and the output end of the voltage conversion circuit may be electrically connected to the second display driver circuit. The first display driver circuit may boost the voltage of the first drive timing signal through the voltage conversion circuit and send it to the display panel to normally drive the display panel.

[0115] In summary, an embodiment of the present application provides a method for driving a display panel, which is used for a first driving circuit in a display driving circuit, wherein the display driving circuit includes a first display driving circuit, a second display driving circuit, a power supply circuit, and a timing control circuit. The first display driving circuit can turn off multiple pixels in the display panel through the second display driving circuit when the level of the first power supply signal reaches the second level; the first display driving circuit can also drive multiple pixels in the display panel through the second display driving circuit when the level of the communication flag signal reaches the fourth level. In this way, the first display driving circuit can turn off multiple pixels through the second display driving circuit when the timing control circuit is in an initialization state, thereby avoiding the screen flickering phenomenon of the display panel under the control of the uncertain signal output by the timing control circuit; and when the timing control circuit is in the initialization state or in a state after the initialization is completed, the second display driving circuit can drive multiple pixels so that the display panel displays normally, which can solve the problem of poor display effect of the display device in the related art and improve the display effect of the display device.

[0116] FIG11 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. As shown in FIG11 , the display device includes a display panel and a display driver circuit, wherein the display driver circuit is electrically connected to the display panel. The display driver circuit can be the display driver circuit in any of the above embodiments.

[0117] Optionally, the display panel can be applied to any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. For example, an AMOLED display panel can be used. The display device can be an AMOLED display device, a mobile phone, tablet computer, television, monitor, or any other product or component with a display function.

[0118] According to another aspect of the present application, a computer program product or computer program is provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the above-described display panel driving method.

[0119] In this application, the terms "first", "second", "third" and "fourth" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more, unless otherwise expressly limited.

[0120] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0121] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0122] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0123] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display driving circuit, characterized in that: Used for a display panel, the display panel includes a plurality of pixels, the display driving circuit includes: a first display driving circuit, a second display driving circuit, a power supply circuit and a timing control circuit; The first display driving circuit is electrically connected to the power supply circuit and the timing control circuit respectively, the power supply circuit is used to send a first power supply signal to the first display driving circuit, and the timing control circuit is used to send a communication mark signal to the first display driving circuit; The first display driving circuit is electrically connected to the second display driving circuit, and the first display driving circuit is used to send a first control signal to the second display driving circuit when the level of the first power supply signal jumps from the first level to the second level, and send a second control signal to the second display driving circuit when the level of the communication flag signal is jumped from the third level to the fourth level; The second display driving circuit is electrically connected to the plurality of pixels, and is configured to turn off the plurality of pixels based on the first control signal and drive the plurality of pixels based on the second control signal.

2. The display driving circuit according to claim 1, characterized in that: The first display driving circuit comprises a comparison circuit and a source driving chip, wherein the comparison circuit is electrically connected to the power supply circuit and the source driving chip respectively; The comparison circuit is used for generating a first indication signal when it is detected that the level of the first power signal output by the power circuit reaches the second level, and outputting the first indication signal to the source driver chip; The source driver chip is used to send a first control signal to the second display driver circuit based on the first indication signal.

3. The display driving circuit according to claim 1, characterized in that: The first display driving circuit comprises a comparison circuit and a source driving chip, wherein the comparison circuit is electrically connected to the timing control circuit and the source driving chip respectively; The comparison circuit is used for generating a second indication signal when it is detected that the level of the communication flag signal output by the timing control circuit reaches a fourth level, and outputting the second indication signal to the source driver chip; The source driver chip is used to send a second control signal to the second display driver circuit based on the second indication signal.

4. The display driving circuit according to claim 1, characterized in that: The timing control circuit is further used to send a first driving timing signal to the first display driving circuit; The first display driving circuit is used to stop sending the first control signal to the second display driving circuit when the level of the communication flag signal to be sent jumps from the third level to the fourth level, and send a second driving timing signal to the second display driving circuit according to the first driving timing signal, the high level amplitude of the second driving timing signal is greater than the high level amplitude of the first driving timing signal, and the second driving timing signal is the second control signal.

5. The display driving circuit according to claim 1, characterized in that: The power supply circuit includes a first power supply circuit and a second power supply circuit; The first power supply circuit is coupled to the first display driving circuit, the first power supply circuit is used to send an analog power supply signal to the first display driving circuit, and the first display driving circuit is used to send data signals to the plurality of pixels based on the analog power supply signal; The second power supply circuit is electrically connected to the plurality of pixels, and the second power supply circuit is used to send a driving power supply signal to the plurality of pixels; The plurality of pixels are configured to emit light based on the data signal and the driving power signal.

6. The display driving circuit according to claim 5, characterized in that: The first control signal has the same level as the analog power signal.

7. The display driving circuit according to claim 5, characterized in that: The pixel comprises a light emitting device and a first transistor; The second display driving circuit is electrically connected to the gate of the first transistor, the first electrode of the first transistor is electrically connected to the first display driving circuit terminal, and the second electrode of the first transistor is electrically connected to the second power supply circuit.

8. The display driving circuit according to claim 1, characterized in that: The second level is greater than the first level, and the fourth level is greater than the third level.

9. A method for driving a display panel, characterized in that: Applied to a first display driving circuit included in the display driving circuit according to any one of claims 1 to 8, the method comprises: In response to the first power signal sent by the power circuit jumping from a first level to a second level, sending a first control signal to the second display driving circuit; In response to the communication flag signal sent by the timing control circuit jumping from the third level to the fourth level, sending a second control signal to the second display driving circuit; The first control signal is used to instruct the second display driving circuit to control the plurality of pixels to be turned off, and the second control signal instructs the second display driving circuit to drive the plurality of pixels.

10. The method according to claim 9, characterized in that The step of sending a first control signal to the second display driving circuit in response to the first power signal sent by the power circuit jumping from a first level to a second level comprises: Monitoring whether the transmission communication flag signal sent by the power supply circuit jumps from the first level to the second level; generating a first indication signal in response to the level of the first power signal sent by the power circuit reaching the second level; A first control signal is sent to the second display driving circuit based on the first indication signal.

11. The method according to claim 9, characterized in that The method of sending a second control signal to the second display driving circuit in response to the communication flag signal sent by the timing control circuit jumping from the third level to the fourth level comprises: monitoring whether the transmission communication flag signal output by the timing control circuit jumps from the third level to the fourth level; In response to the level of the transmission communication flag signal output by the timing control circuit reaching the fourth level, generating a second indication signal; A second control signal is sent to the second display driving circuit based on the second indication signal.

12. The method according to claim 9, characterized in that The sending a second control signal to the second display driving circuit based on the second indication signal comprises: Based on the second indication signal, receiving a first driving timing signal sent by the timing control circuit; A second driving timing signal is sent to the second display driving circuit according to the first driving timing signal, wherein a high level amplitude of the second driving timing signal is greater than a high level amplitude of the first driving timing signal.

13. A display device, characterized in that: It comprises a display panel and a display driving circuit, wherein the display driving circuit is electrically connected to the display panel, and the display driving circuit is the display driving circuit of the display panel according to any one of claims 1 to 8.

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