Shift register, gate drive circuit and display device

Abstract

A shift register comprises a display input reset circuit (1), an inverting circuit (2), at least one output circuit (5) and a first detection circuit (100), the display input reset circuit (1), the inverting circuit (2) and the output circuit (5) are connected to a pull-up node (PU), and the inverting circuit (2) and the output circuit (5) are connected to a pull-down node (PD); the first detection circuit (100) is connected with a signal acquisition point, acquisition control ends (CL1 and CL2) and a first signal detection line (SGD), and the first detection circuit (100) is configured to respond to control of signals provided by the acquisition control ends (CL1 and CL2), acquire voltage at the signal acquisition point and output detection voltage corresponding to the voltage at the signal acquisition point to the first signal detection line (SGD); the signal acquisition point is used for an external first chip (800) to adjust the effective level voltage provided by the third power supply end according to the detection voltage, and the signal acquisition point comprises at least one of a pull-down node (PD) and a signal output end (OUT).

Description

Shift register, gate drive circuit and display device Technical Field

[0001] The present invention relates to the field of display, and in particular to a shift register, a gate drive circuit and a display device. Background Art

[0002] Active matrix organic light-emitting diode (AMOLED) panels are becoming increasingly popular. The pixel display device of an AMOLED is an organic light-emitting diode (OLED). AMOLEDs emit light by driving a thin-film transistor (TFT) in a saturated state to generate a driving current, which then drives the light-emitting device to emit light.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present disclosure provides a shift register, comprising: a display input reset circuit, an inverting circuit, at least one output circuit, and a first detection circuit, wherein the display input reset circuit, the inverting circuit, and the output circuit are connected to a pull-up node, and the inverting circuit and the output circuit are connected to a pull-down node;

[0005] The display input reset circuit is connected to the display signal input terminal, the reset signal terminal, and the second power supply terminal, and is configured to write a valid level signal to the pull-up node in response to the control of the signal provided by the display signal input terminal, and write a voltage provided by the second power supply terminal to the pull-up node in response to the control of the signal provided by the reset signal terminal;

[0006] The inverting circuit is connected to the second power supply terminal and the third power supply terminal, and is configured to invert the voltage of the pull-up node in response to the voltage provided by the second power supply terminal and the effective level voltage provided by the third power supply terminal, and output the inverted voltage to the pull-down node;

[0007] The output circuit is connected to the pull-up node, the pull-down node, the corresponding signal output terminal, the corresponding output clock signal terminal, and the corresponding fourth power supply terminal, and is configured to write the signal provided by the output clock signal terminal to the corresponding signal output terminal in response to the control of the voltage at the pull-up node, and write the voltage provided by the corresponding fourth power supply terminal to the corresponding signal output terminal in response to the control of the voltage at the pull-up node;

[0008] The first detection circuit is connected to the signal acquisition point, the acquisition control terminal, and the first signal detection line, and is configured to acquire the voltage at the signal acquisition point in response to the control of the signal provided by the acquisition control terminal and output a detection voltage corresponding to the voltage at the signal acquisition point to the first signal detection line, so that the external first chip can adjust the effective level voltage provided by the third power supply terminal according to the detection voltage. The signal acquisition point includes at least one of the pull-down node and the signal output terminal.

[0009] In some embodiments, the first detection circuit includes: at least one of a first detection subcircuit and a second detection subcircuit, and the acquisition control terminal includes: a first acquisition control terminal or a second acquisition control terminal;

[0010] The first detection sub-circuit is connected to the pull-down node, the first acquisition control terminal, and a first signal detection line, and the first detection sub-circuit is configured to, in response to control of a signal provided by the first acquisition control terminal, acquire a voltage at the pull-down node and output a first detection voltage corresponding to the voltage at the pull-down node to the first signal detection line;

[0011] The second detection sub-circuit is connected to the signal output terminal, the second acquisition control terminal and the first signal detection line. The second detection sub-circuit is configured to collect the voltage at the pull-down node in response to the control of the signal provided by the second acquisition control terminal and output a second detection voltage corresponding to the voltage at the signal output terminal to the first signal detection line.

[0012] In some embodiments, the first detection sub-circuit includes: a fifty-first transistor;

[0013] The control electrode of the fifty-first transistor is connected to the first acquisition control terminal, the first electrode of the fifty-first transistor is connected to the pull-down node, and the second electrode of the fifty-first transistor is connected to the first signal detection line.

[0014] In some embodiments, the first detection sub-circuit includes: a fifty-first transistor, a fifty-second transistor, a fifty-third transistor, and a fifty-fourth transistor;

[0015] The control electrode of the fifty-first transistor is connected to the first acquisition control terminal, the first electrode of the fifty-first transistor is connected to the second electrode of the fifty-second transistor, and the second electrode of the fifty-first transistor is connected to the first signal detection line;

[0016] A control electrode of the fifty-second transistor is connected to the pull-down node, and a first electrode of the fifty-second transistor is connected to the second electrode of the fifty-third transistor and the first electrode of the fifty-fourth transistor;

[0017] The control electrode of the fifty-third transistor is connected to the first switch control terminal, and the first electrode of the fifty-third transistor is connected to the control electrode of the fifty-second transistor;

[0018] The control electrode of the fifty-fourth transistor is connected to the second switch control terminal, and the second electrode of the fifty-fourth transistor is connected to the seventh power supply terminal.

[0019] In some embodiments, the first detection sub-circuit further includes: a fifty-fifth transistor;

[0020] The second electrode of the fifty-second transistor is connected to the first electrode of the fifty-first transistor through the fifty-fifth transistor, the control electrode of the fifty-fifth transistor and the first electrode of the fifty-fifth transistor are both connected to the second electrode of the fifty-second transistor, and the second electrode of the fifty-fifth transistor is connected to the first electrode of the fifty-first transistor;

[0021] Alternatively, the second electrode of the fifty-first transistor is connected to the first signal detection line through the fifty-fifth transistor, the control electrode of the fifty-fifth transistor and the first electrode of the fifty-fifth transistor are both connected to the second electrode of the fifty-first transistor, and the second electrode of the fifty-fifth transistor is connected to the first signal detection line.

[0022] In some embodiments, the number of the output circuits is m, the number of the second detection sub-circuits is n, the number of the second acquisition control terminals is n, the second detection sub-circuits correspond one-to-one to the second acquisition control terminals, m and n are both positive integers, and m≥n;

[0023] Different second detection sub-circuits correspond to different output circuits, and the second detection sub-circuit is connected to the signal output end of the corresponding output circuit.

[0024] In some embodiments, the second detection sub-circuit includes: a fifty-sixth transistor;

[0025] The control electrode of the fifty-sixth transistor is connected to the corresponding second acquisition control terminal, the first electrode of the fifty-first transistor is connected to the pull-down node, and the second electrode of the fifty-first transistor is connected to the first signal detection line.

[0026] In some embodiments, the invention further includes: a step-down circuit;

[0027] The first detection circuit is connected to the first signal detection line through the step-down circuit. The step-down circuit is configured to step down the detection voltage output by the first detection circuit and output the stepped-down detection voltage to the first signal detection line.

[0028] In some embodiments, the step-down circuit includes: a first resistor and a second resistor;

[0029] The first end of the first resistor is connected to the first detection circuit, the second end of the first resistor is connected to the first signal detection line, the first end of the second resistor is connected to the second end of the first resistor, and the second end of the second resistor is connected to the ground end.

[0030] In some embodiments, the display input reset circuit includes:

[0031] A display input circuit is connected to a display signal input terminal and a pull-up node, and is configured to write a valid level signal to the pull-up node in response to control of a signal provided by the display signal input terminal;

[0032] A display reset circuit is connected to the display reset signal input terminal, the second power supply terminal and the pull-up node, and is configured to write the voltage provided by the second power supply terminal to the pull-up node in response to the control of the signal provided by the sensing reset signal input terminal;

[0033] The shift register further includes: a first voltage control circuit;

[0034] The first voltage control circuit is connected to the first power supply terminal, the pull-up node and the first voltage control node, and the first voltage control circuit is configured to write the voltage provided by the first power supply terminal to the first voltage control node in response to controlling the voltage at the pull-up node;

[0035] The shift register further includes: at least one of a second leakage prevention circuit and a display input leakage prevention circuit;

[0036] The display reset circuit is connected to the second power supply terminal via the second leakage protection circuit, the display reset circuit and the second leakage protection circuit are connected to a second leakage protection node, the second leakage protection node is connected to the first voltage control node, and the second leakage protection circuit is connected to the display reset signal input terminal. The second leakage protection circuit is configured to form a path between the second leakage protection node and the second power supply terminal in response to a valid level signal provided by the display reset signal input terminal, and to disconnect the second leakage protection node from the second power supply terminal in response to a non-valid level signal provided by the display reset signal input terminal.

[0037] The display input circuit is connected to the pull-up node through the display input leakage protection circuit, the display input circuit and the display input leakage protection circuit are connected to the display input leakage protection node, the display input leakage protection node is connected to the first voltage control node, and the display input leakage protection node is connected to the display signal input terminal. The display input leakage protection circuit is configured to form a path between the display input leakage protection node and the pull-up node in response to control of a valid level signal provided by the display signal input terminal, and to disconnect the circuit between the display input leakage protection node and the pull-up node in response to control of an invalid level signal provided by the display signal input terminal.

[0038] In some embodiments, the shift register further includes: at least one of a pull-up noise reduction circuit and a global reset circuit;

[0039] The pull-up noise reduction circuit is connected to the second power supply terminal, the pull-up node and the pull-down node, and is configured to write the voltage provided by the second power supply terminal to the pull-up node in response to the control of the valid level signal at the pull-down node;

[0040] The global reset circuit is connected to the global reset signal input terminal, the second power supply terminal, and the pull-up node, and is configured to write the voltage provided by the second power supply terminal to the pull-up node in response to the control of the signal provided by the global reset signal input terminal.

[0041] In some embodiments, the invention further includes: a first voltage control circuit;

[0042] The first voltage control circuit is connected to the first power supply terminal, the pull-up node and the first voltage control node, and the first voltage control circuit is configured to write the voltage provided by the first power supply terminal to the first voltage control node in response to controlling the voltage at the pull-up node;

[0043] The shift register circuit further includes: at least one of a first anti-leakage circuit and a third anti-leakage circuit;

[0044] The global reset circuit is connected to the second power supply terminal via the first leakage protection circuit. The global reset circuit and the first leakage protection circuit are connected to a first leakage protection node. The first leakage protection node is connected to the first voltage control node. The first leakage protection circuit is connected to the global reset signal input terminal. The first leakage protection circuit is configured to form a path between the first leakage protection node and the second power supply terminal in response to a valid level signal provided by the global reset signal input terminal, and to disconnect the path between the first leakage protection node and the second power supply terminal in response to a non-valid level signal provided by the global reset signal input terminal.

[0045] The pull-up noise reduction circuit is connected to the second power supply terminal via the third leakage protection circuit, the pull-up noise reduction circuit and the third leakage protection circuit are connected to a third leakage protection node, the third leakage protection node is connected to the first voltage control node, and the third leakage protection circuit is connected to the pull-down node, the third leakage protection circuit being configured to form a path between the third leakage protection node and the second power supply terminal in response to a valid level signal at the pull-down node, and to disconnect the path between the third leakage protection node and the second power supply terminal in response to a non-valid level signal at the pull-down node;

[0046] In some embodiments, further comprising:

[0047] The second detection circuit is connected to the first voltage control node, the third acquisition control terminal and the second signal detection line, and is configured to acquire the voltage at the first voltage control node in response to the control of the signal provided by the third acquisition control terminal and output a third detection voltage corresponding to the voltage at the first voltage control node to the second signal detection line, so that the external first chip can adjust the voltage provided by the first power supply terminal according to the third detection voltage.

[0048] In some embodiments, the second detection circuit includes: a fifty-seventh transistor;

[0049] The control electrode of the fifty-seventh transistor is connected to the third acquisition control terminal, the first electrode of the fifty-seventh transistor is connected to the first voltage control node, and the second electrode of the fifty-seventh transistor is connected to the second signal detection line.

[0050] In some embodiments, the first signal detection line is multiplexed as the second signal detection line.

[0051] In some embodiments, the inverter circuit includes: a thirty-seventh transistor, a thirty-eighth transistor, a thirty-ninth transistor, and a fortieth transistor;

[0052] The control electrode of the thirty-seventh transistor is connected to the third power supply terminal, the first electrode of the thirty-seventh transistor is connected to the control electrode of the thirty-seventh transistor, and the second electrode of the thirty-seventh transistor is connected to the control electrode of the thirty-eighth transistor;

[0053] The control electrode of the thirty-eighth transistor is connected to the first electrode of the fortieth transistor, the first electrode of the thirty-eighth transistor is connected to the third power supply terminal, and the second electrode of the thirty-eighth transistor is connected to the pull-down node.

[0054] A control electrode of the thirty-ninth transistor is connected to the pull-up node, a first electrode of the thirty-ninth transistor is connected to the pull-down node, and a second electrode of the thirty-ninth transistor is connected to the fifth power supply terminal or the pull-down node;

[0055] The control electrode of the fortieth transistor is connected to the pull-up node, and the second electrode of the fortieth transistor is connected to the second power supply terminal.

[0056] In some embodiments, the inverter circuit further includes: a forty-first transistor, wherein the second electrode of the thirty-seventh transistor is connected to the control electrode of the thirty-eighth transistor through the forty-first transistor;

[0057] The control electrode of the forty-first transistor is connected to the control electrode of the thirty-seventh transistor, the first electrode of the forty-first transistor is connected to the second electrode of the thirty-seventh transistor, and the second electrode of the forty-first transistor is connected to the control electrode of the thirty-eighth transistor.

[0058] In some embodiments, the inverter circuit includes: a twelfth transistor and a thirteenth transistor;

[0059] The control electrode of the twelfth transistor is connected to the third power supply terminal, the first electrode of the twelfth transistor is connected to the control electrode of the twelfth transistor, and the second electrode of the twelfth transistor is connected to the pull-down node;

[0060] The control electrode of the thirteenth transistor is connected to the pull-up node, the first electrode of the thirteenth transistor is connected to the pull-down node, and the second electrode of the thirteenth transistor is connected to the second power supply terminal.

[0061] In some embodiments, further comprising:

[0062] a sensing control circuit connected to the sensing control node, the sensing signal input terminal, and the random signal input terminal, the sensing control circuit being configured to write the signal provided by the sensing signal input terminal to the sensing control node in response to control by a signal provided by the random signal input terminal;

[0063] The sensing input circuit is connected to the sensing control node, the clock control signal input terminal, the sensing intermediate node and the pull-up node, and is configured to write a valid level signal to the sensing intermediate node in response to the control of the valid level signal at the sensing control node, and to form a path between the sensing intermediate node and the pull-up node in response to the control of the signal provided by the clock control signal input terminal.

[0064] In a second aspect, an embodiment of the present disclosure provides a gate drive circuit, which includes: a plurality of cascaded shift registers, wherein at least one of the shift registers adopts the shift register provided in the first aspect.

[0065] In some embodiments, the plurality of cascaded shift registers include: a plurality of effective shift registers providing driving signals to gate lines located in the display area and at least one dummy shift register other than the effective shift registers;

[0066] At least one of the virtual shift registers adopts the shift register provided in the first aspect.

[0067] In a third aspect, an embodiment of the present disclosure provides a display device, comprising: a display area and a non-display area surrounding the display area, wherein the gate driving circuit provided in the second aspect is arranged in the non-display area.

[0068] In some embodiments, the system further comprises: a plurality of pixel units arranged in an array and a plurality of signal reading lines, wherein the pixel units comprise: a pixel driving circuit having an external threshold compensation function, wherein the pixel driving circuit comprises: a driving transistor and a sensing switch circuit;

[0069] The sensing switch circuit is connected to the second electrode of the driving transistor and a signal read line, and the sensing switch circuit is configured to read the electrical signal at the second electrode of the driving transistor to the corresponding signal read line, so that an external second chip can perform external threshold compensation on the driving transistor according to the electrical signal at the second electrode of the driving transistor;

[0070] At least one of the signal readout lines is multiplexed as the first signal detection line.

[0071] In some embodiments, the second chip and the first chip are the same chip.

[0072] In some embodiments, the number of the shift register provided with the first detection circuit in the gate driving circuit is one;

[0073] One of the signal reading lines closest to the gate driving circuit in the display device is multiplexed as the first signal detection line.

[0074] In some embodiments, the first chip is further configured to control the voltage provided by the third power terminal to switch from a valid level voltage to a non-valid level voltage in response to the display device being switched to a shutdown state.

[0075] In some embodiments, the first chip includes: an analog-to-digital conversion module and a voltage adjustment module;

[0076] The analog-to-digital conversion module is connected to the first signal detection line and is configured to perform analog-to-digital conversion on the signal acquired from the first signal detection line to obtain a corresponding digital voltage;

[0077] The voltage adjustment module is connected to the analog-to-digital conversion module and is configured to obtain the voltage of the effective level voltage to be provided to the third power supply terminal according to a preset adjustment algorithm and the digital voltage provided by the analog-to-digital conversion module.

[0078] In some embodiments, the first chip further includes:

[0079] The power supply module is connected to the voltage adjustment module and is configured to output a corresponding effective level voltage to the third power supply terminal according to the voltage magnitude of the effective level voltage to be provided to the third power supply terminal determined by the voltage adjustment module.

[0080] In some embodiments, a switch circuit is provided between the first chip and the first signal detection line.

[0081] In some embodiments, the first signal detection line is further configured with an eleventh capacitor;

[0082] A first end of the eleventh capacitor is connected to the first detection line, and a second end of the eleventh capacitor is connected to the ground. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] FIG1 is a schematic diagram of the circuit structure of a pixel circuit in an organic light emitting diode display panel;

[0084] FIG2 is a working timing diagram of the pixel circuit shown in FIG1 ;

[0085] FIG3 is a schematic diagram of a circuit structure of a shift register involved in the related art;

[0086] FIG4A is a schematic diagram of a circuit structure of a shift register provided by an embodiment of the present disclosure;

[0087] FIG4B is a schematic diagram of another circuit structure of a shift register provided by an embodiment of the present disclosure;

[0088] FIG4C is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure;

[0089] FIG5 is a schematic diagram of another circuit structure of a shift register provided by an embodiment of the present disclosure;

[0090] FIG6 is a timing diagram of a voltage acquisition process performed by the first detection circuit in the shift register shown in FIG5 ;

[0091] FIG7 is a schematic diagram of another circuit structure of a shift register provided by an embodiment of the present disclosure;

[0092] FIG8 is a timing diagram of a voltage acquisition process performed by the first detection circuit in the shift register shown in FIG7 ;

[0093] 9A and 9B are schematic diagrams of two further circuit structures of a shift register provided by an embodiment of the present disclosure;

[0094] FIG10 is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure;

[0095] FIG11 is a timing diagram of a voltage acquisition process performed by the second detection circuit in the shift register shown in FIG10 ;

[0096] FIG12 is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure;

[0097] FIG13 is a schematic diagram of another circuit structure of a shift register provided by an embodiment of the present disclosure;

[0098] FIG14 is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure;

[0099] FIG15 is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure;

[0100] 16A and 16B are schematic diagrams of two further circuit structures of a shift register provided by an embodiment of the present disclosure;

[0101] FIG17 is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure;

[0102] FIG18 is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure;

[0103] FIG19 is a timing diagram of the operation of the shift register shown in FIG18 for display driving and sensing driving;

[0104] FIG20 is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure;

[0105] FIG21 is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure;

[0106] FIG22 is a schematic diagram of a circuit structure of a gate drive circuit in a disclosed embodiment;

[0107] FIG23 is a schematic structural diagram of a display device according to a disclosed embodiment;

[0108] FIG24 is a structural block diagram of the first chip in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0109] To enable those skilled in the art to better understand the technical solution of the present invention, a shift register, a gate driving circuit, and a display device provided by the present invention are described in detail below with reference to the accompanying drawings.

[0110] The terms "first", "second" and similar terms used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0111] The transistors used in the embodiments of the present disclosure can all be thin film transistors or field effect transistors or other devices with the same characteristics. In this embodiment, the coupling methods of the drain and source of each transistor can be interchangeable. Therefore, there is actually no difference between the drain and source of each transistor in the embodiments of the present disclosure. Here, only in order to distinguish the two poles of the transistor other than the control pole (i.e., the gate), one of the poles is called the drain and the other pole is called the source. The thin film transistors used in the embodiments of the present disclosure can be N-type transistors or P-type transistors. In the embodiments of the present disclosure, when an N-type thin film transistor is used, its first pole can be the source and the second pole can be the drain.

[0112] In this disclosure, "active voltage" refers to a voltage that, when input to the control electrode of a transistor, can turn the transistor on, and "inactive voltage" refers to a voltage that, when input to the control electrode of a transistor, can turn the transistor off. For N-type transistors, a high voltage is an active voltage, and a low voltage is an inactive voltage. For P-type transistors, a low voltage is an active voltage, and a high voltage is an inactive voltage.

[0113] In the following description, an N-type transistor is used as an example. In this case, the active voltage level refers to a high voltage level, and the inactive voltage level refers to a low voltage level. It is conceivable that when a P-type transistor is used, the timing of the control voltage change needs to be adjusted accordingly. The specific details are not detailed here, but are also within the scope of protection of this disclosure.

[0114] Figure 1 is a schematic diagram of the circuit structure of a pixel circuit within an organic light-emitting diode display panel. Figure 2 is an operational timing diagram of the pixel circuit shown in Figure 1. As shown in Figures 1 and 2, for an organic light-emitting diode display panel with external compensation, a frame can be divided into two phases: a display drive phase and a sensing phase. During the display drive phase, each row of pixel units in the display panel performs display drive; during the sensing phase, a row of pixel units in the display panel performs current extraction (i.e., sensing).

[0115] As shown in Figure 1, the pixel circuit includes a display switch transistor QTFT (with its control electrode connected to the first gate line G1), a drive transistor DTFT, a sense switch transistor STFT (with its control electrode connected to the second gate line G2), and a Cst. When external compensation is required for this pixel circuit, the pixel circuit operates in at least two phases: a display drive phase (including the data voltage writing process) and a sense drive phase (including the current reading process).

[0116] During the display drive phase, the data voltage Vdata in the data line Data needs to be written to the pixel unit; during the sensing drive phase, a test voltage Vsence needs to be written to the pixel unit via the data line Data, and the electrical signal at the drain of the driving transistor needs to be read to the signal read line RL via the sensing switch transistor STFT. During the current reading process, an effective level voltage needs to be written to the gate of the sensing switch transistor STFT via the corresponding second gate line G2. It should be noted that the pixel units in the OLED display panel are externally compensated. The specific compensation process and principles will not be repeated here.

[0117] For the first gate line G1 used to control the display switch transistor QTFT and the second gate line G2 used to control the sensing switch transistor STFT, corresponding gate drive circuits are respectively configured in the peripheral area of ​​the display panel. The gate drive circuit includes multiple cascaded shift register units, which can provide drive signals to the corresponding gate lines through the shift register units.

[0118] FIG3 is a schematic diagram of a circuit structure of a shift register involved in the related art. As shown in FIG3 , the shift register includes a display input reset circuit 1, an inverting circuit 2, and at least one output circuit 5 (only one output circuit 5 is shown in FIG1 ). The output circuit 5 includes an output transistor and a pull-down transistor. The control electrode of the output transistor is connected to the pull-up node PU, and the control electrode of the pull-down transistor is connected to the pull-down node PD. The inverting circuit 2 is connected to the second power supply terminal and the third power supply terminal. The inverting circuit 2 is configured to invert the voltage of the pull-up node PU in response to the non-valid level voltage provided by the second power supply terminal and the valid level voltage provided by the third power supply terminal, and output the inverted voltage to the pull-down node PD.

[0119] In actual applications, it is found that the time duration that the voltage at the pull-down node PD is in the high level state is much longer than the time duration that the voltage is in the high level state, that is, the voltage at the pull-down node PD is in the high level state for a long time, which will cause the threshold voltage of the pull-down transistor to drift positively (the threshold voltage gradually increases).

[0120] Furthermore, the high-level voltage at the pull-down node PD is provided by the inverter circuit 2. This high-level voltage is related to the high-level voltage (effective-level voltage) provided by the third power supply terminal to which the inverter circuit 2 is connected. The transistors within the inverter circuit 2 connected to the control electrode and the third power supply terminal will also experience a positive drift due to the control electrode being in a continuously high-level state. This will also cause the voltage written by the inverter circuit 2 to the pull-down node PD to gradually decrease.

[0121] It can be seen that in the related art, as the usage time increases, the high-level voltage output by the inverter circuit 2 to the pull-down node PD will gradually decrease, while the threshold voltage of the pull-down transistor in the output circuit 5 will gradually increase. There is a risk that the high-level voltage output by the inverter circuit 2 to the pull-down node PD cannot control the pull-down transistor to turn on, resulting in a decrease in the reliability of the shift register.

[0122] In order to effectively improve at least one of the technical problems existing in the related art, an embodiment of the present disclosure provides a shift register.

[0123] Figure 4A is a schematic diagram of a circuit structure of a shift register provided in an embodiment of the present disclosure. Figure 4B is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure. Figure 4C is a schematic diagram of yet another circuit structure of a shift register provided in an embodiment of the present disclosure. As shown in Figures 4A to 4C, the shift register includes: a display input reset circuit 1, an inverter circuit 2, at least one output circuit 5, and a first detection circuit 100. The display input reset circuit 1, inverter circuit 2, and output circuit 5 are connected to a pull-up node PU, and the inverter circuit 2 and output circuit 5 are connected to a pull-down node PD.

[0124] Among them, the display input reset circuit 1 is connected to the display signal input terminal INPUT1, the reset signal terminal RST, and the second power supply terminal. The display input reset circuit 1 is configured to write the valid level signal to the pull-up node PU in response to the control of the signal provided by the display signal input terminal INPUT1, and write the voltage provided by the second power supply terminal to the pull-up node PU in response to the control of the signal provided by the reset signal terminal RST.

[0125] The inverting circuit 2 is connected to the second power supply terminal and the third power supply terminal. The inverting circuit 2 is configured to invert the voltage of the pull-up node PU in response to the non-valid level voltage provided by the second power supply terminal and the valid level voltage provided by the third power supply terminal, and output the inverted voltage to the pull-down node PD.

[0126] The output circuit 5 is connected to the pull-up node PU, the pull-down node PD, the corresponding signal output terminal OUT, the corresponding output clock signal terminal CLKE, and the corresponding fourth power supply terminal. The output circuit 5 is configured to write the signal provided by the output clock signal terminal CLKE to the corresponding signal output terminal OUT in response to the control of the voltage at the pull-up node PU, and to write the voltage provided by the corresponding fourth power supply terminal to the corresponding signal output terminal OUT in response to the control of the voltage at the pull-up node PU.

[0127] The first detection circuit 100 is connected to the signal collection point, the collection control terminal, and the first signal detection line SGD. The first detection circuit 100 is configured to control the voltage at the signal collection point in response to the signal provided by the collection control terminal and output a detection voltage corresponding to the voltage at the signal collection point to the first signal detection line SGD, so that the external first chip can adjust the effective level voltage provided by the third power supply terminal according to the detection voltage. The signal collection point includes at least one of the pull-down node PD and the signal output terminal OUT.

[0128] In the embodiment of the present disclosure, the effective level voltage actually output by the inverter circuit 2 to the pull-down node PD can reflect the threshold voltage drift of the transistor whose control electrode is connected to the third power supply terminal in the inverter circuit 2, and when the voltage at the pull-up node PU is the effective level voltage and the fourth power supply terminal provides the effective level voltage, the voltage output by the signal output terminal OUT can reflect the overall threshold voltage drift of both the transistor whose control electrode is connected to the third power supply terminal in the inverter circuit 2 and the pull-down transistor in the output circuit 5.

[0129] Therefore, in the present disclosure, a first detection circuit 100 is provided to detect the effective level voltage at at least one of the pull-down node PD and the signal output terminal OUT, and output a corresponding detection voltage. The external first chip connected to the first signal detection line SGD can adjust (increase) the effective level voltage provided by the third power supply terminal according to the detection voltage, so that the effective level voltage output by the inverter circuit 2 to the pull-down node PD is always higher than the threshold voltage of the pull-down transistor, thereby ensuring that the pull-down transistor can always be in the on state when the inverter circuit 2 outputs the effective level voltage to the pull-down node PD, thereby improving the reliability of the shift register.

[0130] In some embodiments, the first detection circuit 100 includes: at least one of a first detection sub-circuit 100a and a second detection sub-circuit 100b, and the acquisition control terminal includes: a first acquisition control terminal CL1 or a second acquisition control terminal CL2.

[0131] The first detection sub-circuit 100a is connected to the pull-down node PD, the first acquisition control terminal CL1 and the first signal detection line SGD. The first detection sub-circuit 100a is configured to collect the voltage at the pull-down node PD in response to the control of the signal provided by the first acquisition control terminal CL1 and output a first detection voltage corresponding to the voltage at the pull-down node PD to the first signal detection line SGD.

[0132] The second detection sub-circuit 100b is connected to the signal output terminal OUT, the second collection control terminal CL2 and the first signal detection line SGD. The second detection sub-circuit 100b is configured to collect the voltage at the pull-down node PD in response to the control of the signal provided by the second collection control terminal CL2 and output a second detection voltage corresponding to the voltage at the signal output terminal OUT to the first signal detection line SGD.

[0133] 4A exemplarily shows a case where the first detection circuit 100 only includes the first detection sub-circuit 100a, FIG4B exemplarily shows a case where the first detection circuit 100 only includes the second detection sub-circuit 100b, and FIG4C exemplarily shows a case where the first detection circuit 100 includes both the first detection sub-circuit 100a and the second detection sub-circuit 100b.

[0134] In the present disclosure, the process of using the first detection sub-circuit 100a to detect the effective level voltage at the pull-down node PD is as follows: an effective level signal is provided to the reset signal terminal RST, so that the display input reset circuit 1 writes the non-effective level voltage provided by the second power supply terminal to the pull-up node PU. At this time, under the action of the inverting circuit 2, the inverting circuit 2 outputs an effective level voltage to the pull-down node PD based on the effective level voltage provided by the third power supply terminal. At the same time, an effective level signal is provided to the first acquisition control terminal CL1, so that the first detection sub-circuit 100a acquires the effective level voltage at the pull-down node PD and outputs a first detection voltage corresponding to the voltage at the pull-down node PD to the first signal detection line SGD. In the embodiment of the present disclosure, the first detection voltage output by the first detection sub-circuit 100a to the first signal detection line SGD can be equal to or unequal to the effective level voltage at the pull-down node PD (if they are unequal, it is sufficient that the two satisfy a certain preset relationship). This will be described in detail later.

[0135] In the present disclosure, the process of using the second detection sub-circuit 100b to detect the effective level voltage at the pull-down node PD is as follows: an effective level signal is provided to the reset signal terminal RST, so that the display input reset circuit 1 writes the non-effective level voltage provided by the second power supply terminal to the pull-up node PU. At this time, under the action of the inverting circuit 2, the inverting circuit 2 outputs an effective level voltage to the pull-down node PD based on the effective level voltage provided by the third power supply terminal. At the same time, an effective level signal is provided to the first acquisition control terminal CL1, and an effective level voltage is provided to the fourth power supply terminal corresponding to the output circuit 5 connected to the second detection sub-circuit 100b. This causes the second detection sub-circuit 100b to acquire the effective level voltage at the connected signal output terminal OUT and output a second detection voltage corresponding to the effective level voltage at the signal output terminal OUT to the first signal detection line SGD. In the embodiment of the present disclosure, the second detection voltage output by the second detection sub-circuit 100b to the first signal detection line SGD can be equal to or unequal to the effective level voltage at the signal output terminal OUT (if unequal, it is sufficient that the two satisfy a certain predetermined relationship). This will be described in detail later.

[0136] FIG5 is another circuit structure diagram of a shift register provided in an embodiment of the present disclosure. FIG6 is an operation timing diagram of the voltage acquisition process performed by the first detection circuit 100 in the shift register shown in FIG5 . As shown in FIG5 and FIG6 , the shift register is a specific optional implementation scheme based on the shift register shown in FIG4A . In some embodiments, the display input reset circuit 1 includes: a ninth transistor M9 and a tenth transistor M10, the inverting circuit 2 includes: a twelfth transistor M12 and a thirteenth transistor M13, and the output circuit 5 includes: a fifth transistor M5 and a seventeenth transistor M17, wherein part of the output circuit 5 may also include a first capacitor C1.

[0137] The control electrode of the ninth transistor M9 and the first electrode of the ninth transistor M9 are both connected to the display signal input terminal INPUT1 , and the second electrode of the ninth transistor M9 is connected to the pull-up node PU.

[0138] The control electrode of the tenth transistor M10 is connected to the display reset signal input terminal RST, the first electrode of the tenth transistor M10 is connected to the pull-up node PU, and the second electrode of the tenth transistor M10 is connected to the second power supply terminal.

[0139] The control electrode of the twelfth transistor M12 is connected to the third power supply terminal, the first electrode of the twelfth transistor M12 is connected to the control electrode of the twelfth transistor M12 , and the second electrode of the twelfth transistor M12 is connected to the pull-down node PD.

[0140] A control electrode of the thirteenth transistor M13 is connected to the pull-up node PU, a first electrode of the thirteenth transistor M13 is connected to the pull-down node PD, and a second electrode of the thirteenth transistor M13 is connected to the second power supply terminal.

[0141] A control electrode of the fifth transistor M5 is connected to the pull-up node PU, a first electrode of the fifth transistor M5 is connected to the corresponding output clock signal terminal CLKE, and a second electrode of the fifth transistor M5 is connected to the corresponding signal output terminal OUT.

[0142] A control electrode of the seventeenth transistor M17 is connected to the pull-down node PD, a first electrode of the seventeenth transistor M17 is connected to the corresponding signal output terminal OUT, and a second electrode of the seventeenth transistor M17 is connected to the corresponding fourth power supply terminal.

[0143] A first end of the first capacitor C1 is connected to the pull-up node PU, and a second end of the first capacitor C1 is connected to the corresponding signal output terminal OUT.

[0144] It should be noted that the specific circuit structure of the display input reset circuit 1, the inverting circuit 2 and the output circuit 5 exemplified above is only an optional implementation scheme in the present disclosure, which does not limit the technical solution of the present disclosure.

[0145] In some embodiments, the first detection sub-circuit 100a includes: a fifty-first transistor M51; the control electrode of the fifty-first transistor M51 is connected to the first acquisition control terminal CL1, the first electrode of the fifty-first transistor M51 is connected to the pull-down node PD, and the second electrode of the fifty-first transistor M51 is connected to the first signal detection line SGD.

[0146] The detection process of the first detection sub-circuit 100a and the principle of adjusting the effective level voltage output by the third power supply terminal based on the first detection voltage in the first signal detection line SGD will be described in detail below with reference to specific examples.

[0147] The second power supply terminal provides a low-level voltage V2, the third power supply terminal provides a high-level voltage V3, the fourth power supply terminal provides a high-level voltage V4, and the high-level voltage V4 ≥ the high-level voltage V3.

[0148] As shown in FIG6 , the first acquisition period (a period during which the gate drive circuit does not need to drive the display device, such as a blank period after the display device is powered on and before displaying the first frame, or between two adjacent frames) includes: a first sub-stage d1 and a second sub-stage d2.

[0149] In the first sub-phase d1, the display reset signal input terminal RST provides a high-level signal, and the first acquisition control terminal CL1 provides a low-level signal. The tenth transistor M10 is turned on, and the fifty-first transistor M51 is turned off. The low-level voltage provided by the second power supply terminal is written to the pull-up node PU, which is in a low-level state. Accordingly, the thirteenth transistor M13 is turned off, and the high-level voltage provided by the third power supply terminal is written to the pull-down node PD via the twelfth transistor M12. At this time, the voltage actually written to the pull-down node PD is V3-Vth_M12, where Vth_M12 is the threshold voltage of the twelfth transistor M12 during the first acquisition period. Accordingly, the seventeenth transistor M17 is turned on, and the fourth power supply terminal charges the signal output terminal OUT. When the voltage at the signal output terminal OUT is charged to V3-Vth_M12-Vth_M17, the gate-source voltage of the seventeenth transistor M17 equals the current threshold voltage Vth_M17 of the seventeenth transistor M17, and the seventeenth transistor M17 switches to the off state.

[0150] In the second sub-stage d2, the first acquisition control terminal CL1 provides a high-level signal, the fifty-first transistor M51 is turned on, and the voltage at the pull-down node PD is written to the first signal detection line SGD through the fifty-first transistor M51, that is, the first detection voltage Vdtc11 = V3 - Vth_M12 collected through the first signal detection line SGD.

[0151] After a period of time (which can be pre-set according to actual conditions), the second acquisition period begins (a period during which the gate drive circuit does not need to drive the display device, such as the blanking period between two adjacent frames after the display device completes power-on). The second acquisition period also includes two sub-stages: a first sub-stage d1 and a second sub-stage d2. The specific process is the same as that of the first acquisition period and will not be repeated here. In the second sub-stage d2 of the second acquisition period, the first detection voltage Vdtc12 collected on the first signal detection line SGD is V3-Vth_M12', and Vth_M12' is the threshold voltage of the twelfth transistor M12 in the second acquisition period. Generally, the threshold voltage of the twelfth transistor M12 will produce a positive drift under the action of the high-level voltage V3, that is, Vth_M12'>Vth_M12.

[0152] In the disclosed embodiment, the external first chip can determine the threshold voltage drift of the twelfth transistor M12 by comparing the first detection voltage Vdtc11 collected during the first acquisition period with the first detection voltage Vdtc12 collected during the second acquisition period. For example, the difference between the two first detection voltages is calculated as Vdtc11-Vdtc12 to determine the threshold voltage drift ΔVth_M12 of the twelfth transistor M12 from the first acquisition period to the second acquisition period, where ΔVth_M12 = Vth_M12'-Vth_M12 = Vdtc11-Vdtc12.

[0153] At this time, the effective level voltage provided by the third power supply terminal can be adjusted according to the threshold voltage drift of the twelfth transistor M12.

[0154] As an example, the effective level voltage V3' provided by the adjusted third power supply terminal is: V3'=V3+2*ΔVth_M12=V3+2*(Vdtc11-Vdtc12)

[0155] In actual applications, it is found that the threshold voltage drift of the seventeenth transistor M17 is substantially the same as the threshold voltage drift of the twelfth transistor M12, that is, the threshold voltage drift ΔVth_M12 of the twelfth transistor M12 from the first acquisition period to the second acquisition period is equal to or approximately equal to the threshold voltage drift ΔVth_M17 of the seventeenth transistor M17 from the first acquisition period to the second acquisition period. The threshold voltage of the seventeenth transistor M17 in the first acquisition period is denoted as Vth_M17, and the threshold voltage of the seventeenth transistor M17 in the second acquisition period is denoted as Vth_M17', where ΔVth_M17 = Vth_M17' - Vth_M17 ≈ ΔVth_M12.

[0156] During the first acquisition period, the difference between the control voltage of the seventeenth transistor M17 (the voltage at the pull-down node PD) and the threshold voltage of the seventeenth transistor M17 is V3 - Vth_M12 - Vth_M17. After the threshold voltage of the twelfth transistor M12 drifts to Vth_M12' and the threshold voltage of the seventeenth transistor M17 drifts to Vth_M17', to ensure that the seventeenth transistor M17 can still conduct normally, the effective level voltage provided by the third power terminal can be adjusted to V3', so that the difference between the control voltage of the seventeenth transistor M17 (i.e., V3' - Vth_M12') and the threshold voltage of the seventeenth transistor M17 (Vth_M17') remains at V3 - Vth_M12 - Vth_M17.

[0157] That is, V3'-Vth_M12'-Vth_M17'=V3-Vth_M12-Vth_M17

[0158] At this time, V3′=V3+(Vth_M12′-Vth_M12)+(Vth_M17′-Vth_M17)=V3+ΔVth_M12+ΔVth_M17;

[0159] Also, △Vth_M17≈△Vth_M12;

[0160] Therefore, V3'≈V3+2*△Vth_M12;

[0161] Also, ΔVth_M12=Vdtc11-Vdtc12;

[0162] Therefore, V3'≈V3+2*(Vdtc11-Vdtc12);

[0163] Therefore, in the embodiment of the present disclosure, when the effective level voltage provided by the third power supply terminal is adjusted based on the first detection voltage, the adjusted effective level voltage provided by the third power supply terminal can be adjusted to V3+2*(Vdtc11-Vdtc12).

[0164] Of course, the above adjustment method is merely one optional implementation in the present disclosure and does not limit the technical solution of the present disclosure. In actual applications, a corresponding adjustment algorithm can be set based on the first detection voltage as needed. Furthermore, the above example only illustrates the case where the first detection voltage is equal to the voltage at the pull-down node PD.

[0165] Figure 7 is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure. Figure 8 is an operational timing diagram of the voltage acquisition process performed by the first detection circuit within the shift register shown in Figure 7. As shown in Figures 7 and 8, unlike the first detection sub-circuit 100a shown in Figure 5 which only includes the fifty-first transistor M51, the first detection sub-circuit 100a shown in Figure 7 includes a fifty-first transistor M51, a fifty-second transistor M52, a fifty-third transistor M53, and a fifty-fourth transistor M54.

[0166] The control electrode of the fifty-first transistor M51 is connected to the first acquisition control terminal CL1 , the first electrode of the fifty-first transistor M51 is connected to the second electrode of the fifty-second transistor M52 , and the second electrode of the fifty-first transistor M51 is connected to the first signal detection line SGD.

[0167] A control electrode of the fifty-second transistor M52 is connected to the pull-down node PD, and a first electrode of the fifty-second transistor M52 is connected to the second electrode of the fifty-third transistor M53 and the first electrode of the fifty-fourth transistor M54.

[0168] The control electrode of the fifty-third transistor M53 is connected to the first switch control terminal J1, and the first electrode of the fifty-third transistor M53 is connected to the control electrode of the fifty-second transistor M52.

[0169] A control electrode of the fifty-fourth transistor M54 is connected to the second switch control terminal J2, and a second electrode of the fifty-fourth transistor M54 is connected to the seventh power supply terminal.

[0170] The voltage V7 provided by the seventh power supply terminal is a low-level voltage. As an example, the low-level voltage V7 may be equal to the low-level voltage V2 provided by the second power supply terminal.

[0171] 8 , between the first acquisition period and the second acquisition period is a non-acquisition period (the gate driving circuit can normally drive the display device). The first acquisition period and the second acquisition period both include: a first sub-stage d1 and a second sub-stage d2.

[0172] In the first sub-phase d1 of the first acquisition period, the display reset signal input terminal RST provides a high-level signal, the first acquisition control terminal CL1 provides a low-level signal, the first switch control terminal J1 provides a low-level signal, and the second switch control terminal J2 provides a high-level signal. At this time, the tenth transistor M10 is turned on, the fifty-first transistor M51 is turned off, the fifty-third transistor M53 is turned off, and the fifty-fourth transistor M54 is turned on. The low-level voltage provided by the second power supply terminal is written to the pull-up node PU, which is in a low-level state. Correspondingly, the thirteenth transistor M13 is turned off, and the high-level voltage provided by the third power supply terminal is written to the pull-down node PD via the twelfth transistor M12. At this time, the voltage actually written to the pull-down node PD is V3 - Vth_M12, where Vth_M12 is the threshold voltage of the twelfth transistor M12 during the first acquisition period.

[0173] In the second sub-phase d2 of the first acquisition period, the first acquisition control terminal CL1 provides a high-level signal, the first switch control terminal J1 provides a high-level signal, and the second switch control terminal J2 provides a low-level signal. At this time, the 51st transistor M51 and the 53rd transistor M53 are turned on, and the 54th transistor M54 is turned off.

[0174] Because the fifty-third transistor M53 is turned on, the voltage at the pull-up node PU is used to charge the first electrode of the fifty-first transistor M51 through the fifty-second transistor M52. When the voltage at the first electrode of the fifty-first transistor M51 is charged to V3 - Vth_M12 - Vth_M52, the gate-source voltage of the fifty-second transistor M52 is equal to the current threshold voltage Vth_M52 of the fifty-second transistor M52, and the fifty-second transistor M52 is switched to the off state. At this time, because the fifty-first transistor M51 is turned on, the first detection voltage Vdtc11 output to the first signal detection line SGD is equal to V3 - Vth_M12 - Vth_M52.

[0175] During the non-collection period, the first collection control terminal CL1 provides a low-level signal, the first switch control terminal J1 provides a low-level signal, and the second switch control terminal J2 provides a high-level signal. That is, the 51st transistor M51 and the 53rd transistor M53 are both turned off, and the 54th transistor M54 is turned on. This design ensures that, during the non-collection period, the stress experienced by the 52nd transistor M52 is the same as the stress experienced by the 17th transistor M17 in the output circuit 5. In other words, the threshold voltage shift of the 52nd transistor M52 is the same as the threshold voltage shift of the 17th transistor M17.

[0176] After the non-collection period ends, the second collection period begins. The specific operation process is the same as that of the first collection period and will not be repeated here. In the second collection period, the first detection sub-circuit 100a outputs a first detection voltage Vdtc12 = V3 - Vth_M12' - Vth_M52' to the first signal detection line SGD.

[0177] In the embodiment of the present disclosure, the external first chip can obtain the overall drift of the threshold voltage of the twelfth transistor M12 and the threshold voltage of the fifty-second transistor M52 by comparing the first detection voltage Vdtc11 collected during the first collection period with the first detection voltage Vdtc12 collected during the second collection period. For example, by subtracting the two first detection voltages Vdtc11-Vdtc12, the overall drift of the threshold voltage of the twelfth transistor M12 and the threshold voltage of the fifty-second transistor M52 from the first collection period to the second collection period (i.e., the corresponding non-collection period) can be obtained: ΔVth_M12+ΔVth_M52=(Vth_M12'-Vth_M12)+(Vth_M52'-Vth_M52)=Vdtc11-Vdtc12.

[0178] Furthermore, because the threshold voltage shift ΔVth_M52 of the fifty-second transistor M52 is the same as the threshold voltage shift ΔVth_M17 of the seventeenth transistor M17 , ΔVth_M12+ΔVth_M17=Vdtc11−Vdtc12.

[0179] During the first acquisition period, the difference between the control voltage of the seventeenth transistor M17 (the voltage at the pull-down node PD) and the threshold voltage of the seventeenth transistor M17 is V3 - Vth_M12 - Vth_M17. After the threshold voltage of the twelfth transistor M12 drifts to Vth_M12' and the threshold voltage of the seventeenth transistor M17 drifts to Vth_M17', to ensure that the seventeenth transistor M17 can still conduct normally, the effective level voltage provided by the third power terminal can be adjusted to V3', so that the difference between the control voltage of the seventeenth transistor M17 (i.e., V3' - Vth_M12') and the threshold voltage of the seventeenth transistor M17 (Vth_M17') remains at V3 - Vth_M12 - Vth_M17.

[0180] That is, V3'-Vth_M12'-Vth_M17'=V3-Vth_M12-Vth_M17;

[0181] At this time, V3′=V3+(Vth_M12′-Vth_M12)+(Vth_M17′-Vth_M17)=V3+ΔVth_M12+ΔVth_M17;

[0182] And because △Vth_M12+△Vth_M17=Vdtc11-Vdtc12;

[0183] Therefore, V3'=V3+(Vdtc11-Vdtc12).

[0184] Therefore, in the embodiment of the present disclosure, when the effective level voltage provided by the third power terminal is adjusted based on the first detection voltage, the adjusted effective level voltage provided by the third power terminal can be adjusted to V3+(Vdtc11-Vdtc12).

[0185] In the disclosed embodiment, the first detection voltage output by the first detection sub-circuit 100a to the first signal detection line SGD is different from the voltage at the pull-down node PD. Furthermore, the adjustment algorithm used to adjust the effective level voltage output by the third power supply terminal based on the first detection voltage in the disclosed embodiment is also different from that in the previous embodiment.

[0186] Figures 9A and 9B are schematic diagrams of two further circuit structures of the shift register provided in embodiments of the present disclosure. Figures 9A and 9B are further improvements based on the shift register shown in Figure 7 , wherein the first detection sub-circuit 100a includes not only the 51st to 54th transistors M51 to M54 shown in Figure 7 , but also a 55th transistor M55.

[0187] Referring to Figure 9A, as an example, the second electrode of the fifty-second transistor M52 is connected to the first electrode of the fifty-first transistor M51 through the fifty-fifth transistor M55, the control electrode of the fifty-fifth transistor M55 and the first electrode of the fifty-fifth transistor M55 are both connected to the second electrode of the fifty-second transistor M52, and the second electrode of the fifty-fifth transistor M55 is connected to the first electrode of the fifty-first transistor M51.

[0188] Referring to Figure 9B, as an example, the second electrode of the fifty-first transistor M51 is connected to the first signal detection line SGD through the fifty-fifth transistor M55, the control electrode of the fifty-fifth transistor M55 and the first electrode of the fifty-fifth transistor M55 are both connected to the second electrode of the fifty-first transistor M51, and the second electrode of the fifty-fifth transistor M55 is connected to the first signal detection line SGD.

[0189] The working sequence of the voltage acquisition process of the first detection circuit 100 in the shift register shown in Figures 9A and 9B can adopt the one shown in Figure 8 above. The specific working process description can refer to the corresponding content in the previous embodiment and will not be repeated here.

[0190] In Figures 9A and 9B , the diode-connected 55th transistor M55 effectively reduces the first detection voltage output by the first detection sub-circuit 100a to the first signal detection line SGD. Specifically, during the first acquisition period, the first detection voltage Vdtc11 output by the first detection circuit 100 is V3 - Vth_M12 - Vth_M52 - Vth_M55; during the second acquisition period, the first detection voltage Vdtc12 output by the first detection circuit 100 is V3 - Vth_M12' - Vth_M52' - Vth_M55. Vth_M55 is the threshold voltage of the 55th transistor M55.

[0191] In practical applications, the first chip connected to the first signal detection line SGD often has certain requirements for the voltage value of the input signal. For example, the input signal voltage must be less than or equal to 6V. However, the effective level voltage provided by the third power supply terminal is generally around 12V. In this case, there is a risk that the voltage output by the first detection sub-circuit 100a to the first signal detection line SGD will exceed 6V, thereby causing the first chip connected to the first signal detection line SGD to malfunction. However, by providing the fifty-fifth transistor M55 and pre-designing the threshold voltage of the fifty-fifth transistor M55, the first detection voltage output by the first detection sub-circuit 100a to the first signal detection line SGD can be controlled to always be less than 6V.

[0192] In addition, the configuration of the fifty-fifth transistor M55 can also effectively prevent the signal in the first signal detection line SGD from reversely charging the first detection sub-circuit 100a, which is beneficial to improving the service life of the transistor in the first detection sub-circuit 100a.

[0193] Figure 10 is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure. Figure 11 is an operational timing diagram of the voltage acquisition process performed by the second detection circuit within the shift register shown in Figure 10. In some embodiments, the second detection sub-circuit 100b includes: a fifty-sixth transistor M56; the control electrode of the fifty-sixth transistor M56 is connected to the corresponding second acquisition control terminal CL2; the first electrode of the fifty-first transistor M51 is connected to the pull-down node PD; and the second electrode of the fifty-first transistor M51 is connected to the first signal detection line SGD.

[0194] In this embodiment, the voltage V4 provided by the fourth power supply terminal connected to the output circuit 5 corresponding to the second detection circuit 200 is a high-level voltage, and the high-level voltage V4 ≥ the high-level voltage V3.

[0195] As shown in Figure 11, the first acquisition period includes a first sub-stage d1 and a second sub-stage d2. In the first sub-stage d1, the display reset signal input terminal RST provides a high-level signal, and the second acquisition control terminal CL2 provides a low-level signal. The tenth transistor M10 is turned on, and the fifty-first transistor M51 is turned off. The low-level voltage provided by the second power supply terminal is written to the pull-up node PU, which is in a low-level state. Correspondingly, the thirteenth transistor M13 is turned off, and the high-level voltage provided by the third power supply terminal is written to the pull-down node PD via the twelfth transistor M12. At this time, the voltage actually written to the pull-down node PD is V3 - Vth_M12, where Vth_M12 is the threshold voltage of the twelfth transistor M12 during the first acquisition period. Correspondingly, the seventeenth transistor M17 is turned on, and the fourth power supply terminal charges the signal output terminal OUT. When the voltage at the signal output terminal OUT is charged to V3-Vth_M12-Vth_M17, the gate-source voltage of the seventeenth transistor M17 is equal to the current threshold voltage Vth_M17 of the seventeenth transistor M17, and the seventeenth transistor M17 is switched to the cut-off state.

[0196] In the second sub-stage d2, the second acquisition control terminal CL2 provides a high-level signal, the fifty-sixth transistor M56 is turned on, and the voltage at the signal output terminal OUT is written to the first signal detection line SGD through the fifty-sixth transistor M56, that is, the second detection voltage Vdtc21 = V3 - Vth_M12 - Vth_M17 collected through the first signal detection line SGD.

[0197] After a period of time (which can be pre-set based on actual conditions), the second acquisition period begins. This period also consists of two sub-phases: the first sub-phase d1 and the second sub-phase d2. The specific process is identical to that of the first acquisition period and will not be repeated here. In the second sub-phase d2 of the second acquisition period, the first detection voltage Vdtc22 collected on the first signal detection line SGD is V3 - Vth_M12' - Vth_M17'.

[0198] In the disclosed embodiment, the external first chip can determine the overall drift of the threshold voltage of the twelfth transistor M12 and the threshold voltage of the seventeenth transistor M17 by comparing the second detection voltage Vdtc21 collected during the first collection period with the second detection voltage Vdtc22 collected during the second collection period. For example, by subtracting the two second detection voltages by Vdtc21-Vdtc22, the overall drift of the threshold voltage of the twelfth transistor M12 and the threshold voltage of the seventeenth transistor M17 from the first collection period to the second collection period (i.e., corresponding to the non-collection period) can be determined by ΔVth_M12+ΔVth_M17.

[0199] Similar to the voltage adjustment scheme corresponding to the shift register shown in FIG8 , in this embodiment, when the effective level voltage provided by the third power supply terminal is adjusted based on the second detection voltage, the adjusted effective level voltage V3′ provided by the third power supply terminal can be adjusted to V3+(Vdtc21-Vdtc22). The specific adjustment principle can be found in the corresponding content above and will not be repeated here.

[0200] In some embodiments, the number of output circuits 5 is m, the number of second detection sub-circuits 100b is n, and the number of second acquisition control terminals CL2 is n. Each second detection sub-circuit 100b corresponds to each second acquisition control terminal CL2 in a one-to-one correspondence, where m and n are both positive integers and m ≥ n. Different second detection sub-circuits 100b correspond to different output circuits 5, and each second detection sub-circuit 100b is connected to the signal output terminal OUT of the corresponding output circuit 5. This will be described in detail below with reference to examples.

[0201] Figure 12 is another circuit structure diagram of the shift register provided by the embodiment of the present disclosure. As shown in Figure 12, in some embodiments, the shift register includes a plurality of output circuits 5, which generally include a cascade output circuit 5 and at least one driving output circuit 5 (four driving output circuits 5 are exemplarily drawn in the accompanying drawings). Wherein, the signal output end of the cascade output circuit 5 is a cascade signal output end COUT, and the cascade signal output end COUT is connected to other shift registers but not to the gate line in the display area, and the signal output by the cascade signal output end COUT is used for the cascade between the shift registers; the signal output end of the driving output circuit 5 is a drive signal output end GOUT, and the drive signal output end GOUT is connected to the corresponding gate line in the display area but not to other shift registers, and the signal output by the drive signal output end GOUT is used to drive the corresponding gate line.

[0202] The output clock signal terminal of the cascade output circuit 5 is the cascade output clock signal terminal CLKD, and the output clock signal terminal of the driving output circuit 5 is the driving output clock signal terminals CLKE1 to CLKE4. The cascade output circuit 5 may include a first capacitor C1 or not.

[0203] FIG12 exemplarily shows a situation where a second detection sub-circuit 100 b is provided in the shift register, and the second detection sub-circuit 100 b is connected to the cascade signal output terminal COUT of the cascade output circuit 5 .

[0204] Of course, in some embodiments, the second detection sub-circuit 100 b may also be selectively connected to the driving signal output terminal OUT of a driving output circuit 5 .

[0205] FIG13 is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure. As shown in FIG13 , unlike FIG12 which only has one second detection sub-circuit 100 b, the embodiment shown in FIG13 illustrates multiple second detection sub-circuits 100 b corresponding one-to-one to the output circuit 5 .

[0206] The shift register shown in FIG13 includes a first sub-stage and a second sub-stage within one acquisition period. For the description of the first sub-stage, reference can be made to the description of the first sub-stage in FIG11 . Only the second sub-stage will be described in detail below.

[0207] Specifically, in the second sub-stage, a high-level signal is provided to each second acquisition control terminal CL2 in turn to control the fifty-sixth transistor M56 in each second detection sub-circuit 100b to be turned on in turn, thereby enabling each second detection sub-circuit 100b to write the corresponding second detection voltage to the first signal detection line SGD in turn.

[0208] In actual applications, the threshold voltage drift of the seventeenth transistor M17 in different output circuits 5 may vary. Therefore, multiple second detection sub-circuits 100b can be used to collect signals output from the signal output terminals OUT of different output circuits 5, thereby obtaining the overall drift of the threshold voltage of the seventeenth transistor M17 and the threshold voltage of the twelfth transistor M12 in different output circuits 5. Then, based on the second detection voltage output by each second detection sub-circuit 100b, an adjustment scheme for the effective level voltage provided by the third power supply terminal is determined.

[0209] As an example, an average value is calculated for the multiple second detection voltages collected by the multiple second detection sub-circuits 100b in the first collection period, and an average value is calculated for the multiple second detection voltages collected by the multiple second detection sub-circuits 100b in the second collection period, and then the effective level voltage provided by the third power supply terminal is adjusted based on the two average values.

[0210] Those skilled in the art should know that when the number of output circuits 5 is multiple, the number of second detection sub-circuits 100b set in the shift register can be one or more, and it is only necessary to ensure that the number of second detection sub-circuits 100b is less than or equal to the number of output circuits 5.

[0211] Figure 14 is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure. In the embodiment shown in Figure 14, the detection circuit includes not only a first detection sub-circuit 100a but also a second detection sub-circuit 100b, which can sequentially provide high-level signals to the first acquisition control terminal CL1 and each second acquisition control terminal CL2 to control the first detection sub-circuit 100a and each second detection sub-circuit 100b to sequentially provide a detection voltage to the first signal detection line SGD.

[0212] The first detection voltage output by the first detection sub-circuit 100a can reflect the threshold voltage drift of the transistor whose control electrode is connected to the third power supply terminal in the inverter circuit 2 (e.g., the twelfth transistor M12 in the figure). The second detection voltage output by the second detection sub-circuit 100b can reflect the overall threshold voltage drift of the transistor whose control electrode is connected to the third power supply terminal in the inverter circuit 2 and the pull-down transistor in the output circuit 5 (e.g., the seventeenth transistor M17 in the figure). Therefore, based on the difference between the second detection voltage and the first detection voltage, the threshold voltage drift of the corresponding pull-down transistor in the output circuit 5 can be reflected. That is, when both the first detection sub-circuit 100a and the second detection sub-circuit 100b are provided, the threshold voltage drift of the transistor whose control electrode is connected to the third power supply terminal in the inverter circuit 2 and the threshold voltage drift of the pull-down transistor in the output circuit 5 can be respectively obtained, thereby enabling precise control of the threshold voltage drift of the pull-down transistor, thereby facilitating subsequent precise regulation of the voltages provided to the respective electrodes of the pull-down transistor according to actual needs.

[0213] FIG15 is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure. As shown in FIG15 , the shift register shown in FIG15 includes not only a first detection circuit 100 but also a step-down circuit 6 disposed between the first detection circuit 100 and the step-down circuit 6. The step-down circuit 6 is configured to step down the detection voltage output by the first detection circuit 100 and output the stepped-down detection voltage to the first signal detection line SGD.

[0214] Similar to the step-down function of the fifty-fifth transistor M55 set in the previous embodiment, by setting the step-down voltage in the embodiment of the present disclosure, the voltage range of the first detection circuit 100 output to the first signal detection line SGD can be effectively controlled to avoid the situation where the external first chip cannot read due to the output voltage of the first detection circuit 100 being too large.

[0215] In practical applications, considering that the threshold voltage of the fifty-fifth transistor M55 (generally less than 3V) is generally not too large, the voltage reduction degree of the fifty-fifth transistor M55 is limited, so the above-mentioned voltage reduction circuit 6 can be additionally provided in the present disclosure.

[0216] In some embodiments, the step-down circuit 6 includes a first resistor R1 and a second resistor R2. A first end of the first resistor R1 is connected to the first detection circuit 100, a second end of the first resistor R1 is connected to the first signal detection line SGD, a first end of the second resistor R2 is connected to the second end of the first resistor R1, and a second end of the second resistor R2 is connected to ground. Voltage reduction can be achieved using the principle of resistor voltage division.

[0217] For the detailed description of the first detection circuit 100 in FIG15 , reference may be made to the contents in the previous embodiment, which will not be repeated here.

[0218] Figures 16A and 16B are schematic diagrams of two further circuit structures of the shift register provided in an embodiment of the present disclosure. As shown in Figures 16A and 16B, unlike the circuit structure in which the inverter circuit 2 includes the twelfth transistor M12 and the thirteenth transistor M13 in the previous embodiment, the inverter circuit 2 in the shift register shown in Figures 16A and 16B includes a thirty-seventh transistor M37, a thirty-eighth transistor M38, a thirty-ninth transistor M39, and a fortieth transistor M40.

[0219] The control electrode of the 37th transistor M37 is connected to the third power supply terminal, the first electrode of the 37th transistor M37 is connected to the control electrode of the 37th transistor M37, and the second electrode of the 37th transistor M37 is connected to the control electrode of the 38th transistor M38.

[0220] The control electrode of the 38th transistor M38 is connected to the first electrode of the 40th transistor M40 , the first electrode of the 38th transistor M38 is connected to the third power supply terminal, and the second electrode of the 38th transistor M38 is connected to the pull-down node PD.

[0221] The control electrode of the thirty-ninth transistor M39 is connected to the pull-up node PU, the first electrode of the thirty-ninth transistor M39 is connected to the pull-down node PD, and the second electrode of the thirty-ninth transistor M39 is connected to the fifth power supply terminal (shown in Figure 16A) or the pull-down node PD (shown in Figure 16B).

[0222] A control electrode of the 40th transistor M40 is connected to the pull-up node PU, and a second electrode of the 40th transistor M40 is connected to the second power supply terminal.

[0223] When the inverter circuit 2 adopts the configuration shown in FIG16 , the high-level voltage outputted by the inverter circuit 2 to the pull-up node PU is V3-Vth_M38, where Vth_M38 is the threshold voltage of the 38th transistor M38. The function of the 38th transistor M38 is similar to that of the 12th transistor M12 in the previous embodiment and will not be further described here.

[0224] In some embodiments, the inverter circuit 2 further includes: a forty-first transistor M41 , a second electrode of the thirty-seventh transistor M37 connected to a control electrode of the thirty-eighth transistor M38 via the forty-first transistor M41 ;

[0225] The control electrode of the forty-first transistor M41 is connected to the control electrode of the thirty-seventh transistor M37, the first electrode of the forty-first transistor M41 is connected to the second electrode of the thirty-seventh transistor M37, and the second electrode of the forty-first transistor M41 is connected to the control electrode of the thirty-eighth transistor M38.

[0226] In actual applications, it is found that when the 40th transistor M40 is in the cut-off state and the 37th transistor M37 is in the on state, a charging current with a short duration but a large current value will exist between the control electrode of the 38th transistor M38 and the effective level supply end (used to charge the control electrode of the 38th transistor M38). This charging current can easily cause damage to the 37th transistor M37, for example, causing the 37th transistor M37 to break down.

[0227] To improve the above problem, in the embodiment of the present disclosure, a forty-first transistor M41 is provided between the second electrode of the thirty-seventh transistor M37 and the control electrode of the thirty-eighth transistor M38. The provision of the forty-first transistor M41 can effectively reduce the charging current between the control electrode of the thirty-eighth transistor M38 and the effective level supply terminal, so as to prevent the charging current from breaking down the thirty-seventh transistor M37.

[0228] Fig. 17 is a schematic diagram of another circuit structure of a shift register provided by an embodiment of the present disclosure. As shown in Fig. 17, in some embodiments, the display input reset circuit 1 includes: a display input circuit 1a and a display reset circuit 1b.

[0229] The display input circuit 1a is connected to the display signal input terminal INPUT1 and the pull-up node PU. The display input circuit 1a is configured to write a valid level signal into the pull-up node PU in response to the control of the signal provided by the display signal input terminal INPUT1.

[0230] The display reset circuit 1b is connected to the display reset signal input terminal RST, the second power supply terminal and the pull-up node PU. The display reset circuit 1b is configured to write the voltage provided by the second power supply terminal to the pull-up node PU in response to the control of the signal provided by the display reset signal input terminal.

[0231] As an example, the display input circuit 1 a includes the aforementioned ninth transistor M9 , and the display reset circuit 1 b includes the aforementioned tenth transistor M10 .

[0232] In some embodiments, the shift register further includes at least one of a pull-up noise reduction circuit 7 and a global reset circuit 6 .

[0233] The pull-up noise reduction circuit 7 is connected to the second power supply terminal, the pull-up node PU and the pull-down node PD. The pull-up noise reduction circuit 7 is configured to write the voltage provided by the second power supply terminal to the pull-up node PU in response to the control of the valid level signal at the pull-down node PD.

[0234] The global reset circuit 6 is connected to the global reset signal input terminal T-RST, the second power supply terminal, and the pull-up node PU. The global reset circuit 6 is configured to write the voltage provided by the second power supply terminal to the pull-up node PU in response to the control of the signal provided by the global reset signal input terminal T-RST.

[0235] In some embodiments, the pull-up noise reduction circuit 7 includes a fourteenth transistor M14; the control electrode of the fourteenth transistor M14 is connected to the pull-down node PD, the first electrode of the fourteenth transistor M14 is connected to the pull-up node PU, and the second electrode of the fourteenth transistor M14 is connected to the second power supply terminal.

[0236] In some embodiments, the global reset circuit 6 includes a seventh transistor M7; the control electrode of the seventh transistor M7 is connected to the global reset signal input terminal T-RST, the first electrode of the seventh transistor M7 is connected to the pull-up node PU, and the second electrode of the seventh transistor M7 is connected to the second power supply terminal.

[0237] FIG18 is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure. FIG19 is a timing diagram of the shift register shown in FIG18 performing display driving and sensing driving. As shown in FIG18 and FIG19 , unlike the shift register shown in FIG17 , the shift register shown in FIG18 further includes a sensing control circuit 11 and a sensing input circuit 12.

[0238] Among them, the sensing control circuit 11 is connected to the sensing control node H, the sensing signal input terminal INPUT2 and the random signal input terminal OE. The sensing control circuit 11 is configured to write the signal provided by the sensing signal input terminal INPUT2 to the sensing control node H in response to the control of the effective level signal provided by the random signal input terminal OE.

[0239] The sensing input circuit 12 is connected to the sensing control node H, the clock control signal input terminal CLKA, the sensing intermediate node N and the pull-up node PU. The sensing input circuit 12 is configured to write a valid level signal to the sensing intermediate node N in response to the control of the valid level signal at the sensing control node H, and to form a path between the sensing intermediate node N and the pull-up node PU in response to the control of the valid level signal provided by the clock control signal input terminal CLKA.

[0240] In some embodiments, the sensing control circuit 11 includes a first transistor M1 .

[0241] A control electrode of the first transistor M1 is connected to the random signal input terminal OE, a first electrode of the first transistor M1 is connected to the sensing signal input terminal INPUT2 , and a second electrode of the first transistor M1 is connected to the sensing control node H.

[0242] In some embodiments, a hold capacitor C0 is configured at the sensing control node H. A first terminal of the hold capacitor C0 is connected to the sensing control node H, and a second terminal of the hold capacitor C0 is connected to a constant voltage supply terminal, such as ground or a power supply terminal. FIG18 illustrates an example where the second terminal of the hold capacitor is grounded.

[0243] In some embodiments, the sensing input circuit 12 includes a second transistor M2 and a third transistor M3 .

[0244] The control electrode of the second transistor M2 is connected to the sensing control node H, the first electrode of the second transistor M2 is connected to the clock control signal input terminal CLKA, and the second electrode of the second transistor M2 is connected to the sensing intermediate node N.

[0245] A control electrode of the third transistor M3 is connected to the clock control signal input terminal CLKA, a first electrode of the third transistor M3 is connected to the sensing middle node N, and a second electrode of the third transistor M3 is connected to the pull-up node PU.

[0246] As shown in Figure 19, the shift register includes the following steps during display driving and sensing driving: a display driving step, a sensing driving step, and a global reset step s1. The display driving step includes a display input phase t1, a display output phase t2, and a display reset phase t3; the sensing driving step includes a sensing preparation phase p1, a sensing input phase p2, a sensing output phase p3, and a sensing control reset phase p4.

[0247] The working state of each transistor in each stage of the shift register shown in FIG18 can be inferred by referring to the timing shown in FIG19 , and the specific contents are not described in detail here.

[0248] It should be noted that in the embodiments of the present disclosure, the present disclosure does not limit the order of the sensing control reset stage p4 and the global reset process s1. For example, the sensing control reset stage p4 can be located before the global reset process s1 (corresponding figure not provided), can be performed simultaneously with the global reset process s1 (as shown in FIG13 ), or can be located after the global reset process s1 (corresponding figure not provided). In the embodiments of the present disclosure, it is only necessary to ensure that the sensing control reset stage p4 is located after the sensing input stage p2 and the global reset process s1 is located after the sensing output stage p3.

[0249] FIG20 is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure. As shown in FIG20 , in some embodiments, the shift register further includes: a first voltage control circuit 14; the first voltage control circuit 14 is connected to the first power supply terminal, the pull-up node PU, and the first voltage control node OFF1, and the first voltage control circuit 14 is configured to write the voltage provided by the first power supply terminal to the first voltage control node OFF1 in response to controlling the voltage at the pull-up node PU.

[0250] The shift register further includes at least one of a first leakage protection circuit 15 , a second leakage protection circuit 16 , a third leakage protection circuit 17 , and a display input leakage protection circuit 1 a ′.

[0251] The global reset circuit 6 is connected to the second power supply terminal through the first leakage protection circuit 15. The global reset circuit 6 and the first leakage protection circuit 15 are connected to the first leakage protection node Q1. The first leakage protection node Q1 is connected to the first control voltage node OFF1. The first leakage protection circuit 15 is connected to the global reset signal input terminal T-RST. The first leakage protection circuit 15 is configured to form a path between the first leakage protection node Q1 and the second power supply terminal in response to the control of the valid level signal provided by the global reset signal input terminal T-RST, and to disconnect the first leakage protection node Q1 from the second power supply terminal in response to the control of the non-valid level signal provided by the global reset signal input terminal T-RST.

[0252] The display reset circuit 1b is connected to the second power supply terminal through the second anti-leakage circuit 16. The display reset circuit 1b and the second anti-leakage circuit 16 are connected to the second anti-leakage node Q2. The second anti-leakage node Q2 is connected to the first control voltage node OFF1. The second anti-leakage circuit 16 is connected to the display reset signal input terminal RST. The second anti-leakage circuit 16 is configured to form a path between the second anti-leakage node Q2 and the second power supply terminal in response to the control of the valid level signal provided by the display reset signal input terminal RST, and to open the circuit between the second anti-leakage node Q2 and the second power supply terminal in response to the control of the non-valid level signal provided by the display reset signal input terminal RST.

[0253] The pull-up noise reduction circuit 7 is connected to the second power supply terminal through the third anti-leakage circuit 17. The pull-up noise reduction circuit 7 and the third anti-leakage circuit 17 are connected to the third anti-leakage node Q3. The third anti-leakage node Q3 is connected to the first control voltage node OFF1. The third anti-leakage circuit 17 is connected to the pull-down node PD. The third anti-leakage circuit 17 is configured to form a path between the third anti-leakage node Q3 and the second power supply terminal in response to the control of the valid level signal at the pull-down node PD, and to disconnect the third anti-leakage node Q3 from the second power supply terminal in response to the control of the invalid level signal at the pull-down node PD.

[0254] The display input circuit 1a is connected to the pull-up node PU through the display input leakage protection circuit 1a'. The display input circuit 1a and the display input leakage protection circuit 1a' are connected to the display input leakage protection node XQ1. The display input leakage protection node XQ1 is connected to the first control voltage node OFF1. The display input leakage protection node XQ1 is connected to the display signal input terminal INPUT1. The display input leakage protection circuit 1a' is configured to form a path between the display input leakage protection node XQ1 and the pull-up node PU in response to the control of the valid level signal provided by the display signal input terminal INPUT1, and to disconnect the display input leakage protection node XQ1 and the pull-up node PU in response to the control of the non-valid level signal provided by the display signal input terminal INPUT1.

[0255] In the embodiment of the present disclosure, by setting the above-mentioned first anti-leakage circuit 15, it is possible to effectively prevent the voltage at the pull-up node PU from leaking through the global reset circuit 6; by setting the above-mentioned second anti-leakage circuit 16, it is possible to effectively prevent the voltage at the pull-up node PU from leaking through the display reset circuit 1b; by setting the above-mentioned third anti-leakage circuit 17, it is possible to effectively prevent the pull-up node PU from leaking through the pull-up noise reduction circuit 7; and by setting the above-mentioned display input anti-leakage circuit 1a', it is possible to effectively prevent the pull-up node PU from leaking through the display input circuit 1a.

[0256] The accompanying drawings exemplarily illustrate a case where the shift register includes the first leakage protection circuit 15 , the second leakage protection circuit 16 , the third leakage protection circuit 17 and the display input leakage protection circuit 1 a ′. This case is merely exemplary.

[0257] In some embodiments, the shift register further includes a sensing input leakage protection circuit 12'; the sensing input circuit 12 is connected to the pull-up node PU through the sensing input leakage protection circuit 12', the sensing input circuit 12 and the sensing input leakage protection circuit 12' are connected to the sensing input leakage protection node SQ1, the sensing input leakage protection node SQ1 is connected to the first control voltage node OFF1, the sensing input leakage protection node SQ1 is connected to the clock control signal input terminal CLKA, and the sensing input leakage protection circuit 12' is configured to form a path between the sensing input leakage protection node SQ1 and the pull-up node PU in response to the control of the valid level signal provided by the clock control signal input terminal CLKA, and to disconnect the sensing input leakage protection node SQ1 and the pull-up node PU in response to the control of the invalid level signal provided by the clock control signal input terminal CLKA.

[0258] Referring to Figure 20, in some embodiments, the first voltage control circuit 14 includes: a twentieth transistor M20, the first leakage protection circuit 15 includes: a twenty-first transistor M21, the second leakage protection circuit 16 includes: a twenty-second transistor M22, the third leakage protection circuit 17 includes: a twenty-third transistor M23, the display input leakage protection circuit 1a' includes a twenty-fourth transistor M24, and the sensing input leakage protection circuit 12' includes a twenty-fifth transistor M25.

[0259] A control electrode of the twentieth transistor M20 is connected to the pull-up node PU, a first electrode of the twentieth transistor M20 is connected to the first power supply terminal, and a second electrode of the twentieth transistor M20 is connected to the first control voltage node OFF1 .

[0260] A control electrode of the twenty-first transistor M21 is connected to the global reset signal input terminal T-RST, a first electrode of the twenty-first transistor M21 is connected to the first leakage protection node Q1, and a second electrode of the twenty-second transistor M22 is connected to the second power supply terminal.

[0261] A control electrode of the 22nd transistor M22 is connected to the display reset signal input terminal RST, a first electrode of the 22nd transistor M22 is connected to the second leakage protection node Q2, and a second electrode of the 22nd transistor M22 is connected to the second power supply terminal.

[0262] A control electrode of the twenty-third transistor M23 is connected to the pull-down node PD, a first electrode of the twenty-third transistor M23 is connected to the third leakage prevention node Q3, and a second electrode of the twenty-third transistor M23 is connected to the second power supply terminal.

[0263] A control electrode of the 24th transistor M24 is connected to the display signal input terminal INPUT1 , a first electrode of the 24th transistor M24 is connected to the display input leakage prevention node XQ1 , and a second electrode of the 24th transistor M24 is connected to the pull-up node PU.

[0264] The control electrode of the 25th transistor M25 is connected to the clock control signal input terminal CLKA, the first electrode of the 25th transistor M25 is connected to the sensing input anti-leakage node SQ1, and the second electrode of the 25th transistor M25 is connected to the pull-up node PU.

[0265] In addition, in the embodiment of the present disclosure, a sensing control leakage prevention circuit 11' may also be provided. The sensing control circuit 11 is connected to the sensing control node H via the sensing control leakage prevention circuit 11'. The sensing control leakage prevention circuit 11' and the sensing control circuit 11 are connected to the sensing control leakage prevention node GM. The sensing control leakage prevention circuit 11' is also connected to the eighth power supply terminal, the sensing control node H, and the random signal input terminal. The sensing control leakage prevention circuit 11' is configured to write the valid level signal provided by the eighth power supply terminal to the sensing control leakage prevention node GM in response to the control of the valid level signal at the sensing control node H. The sensing control leakage prevention circuit 11' is also configured to form a path between the sensing control leakage prevention node GM and the sensing control node H in response to the control of the valid level signal provided by the random signal input terminal OE, and to form a disconnection between the sensing control leakage prevention node GM and the sensing control node H in response to the control of the non-valid level signal provided by the random signal input terminal OE.

[0266] In some embodiments, the sensing control leakage prevention circuit 11 ′ includes a twenty-sixth transistor M26 and a twenty-seventh transistor M27 .

[0267] A control electrode of the twenty-sixth transistor M26 is connected to the sensing control node H, a first electrode of the twenty-sixth transistor M26 is connected to the first power supply terminal, and a second electrode of the twenty-sixth transistor M26 is connected to the sensing control anti-leakage node GM.

[0268] A control electrode of the twenty-seventh transistor M27 is connected to the random signal input terminal OE, a first electrode of the twenty-seventh transistor M27 is connected to the sensing control anti-leakage node GM, and a second electrode of the twenty-seventh transistor M27 is connected to the sensing control node H.

[0269] In some embodiments, the shift register unit further includes at least one of a first pull-down noise reduction circuit 18 and a second pull-down noise reduction circuit 19 .

[0270] Among them, the first pull-down noise reduction circuit 18 is connected to the pull-down node PD, the second power supply terminal, the sensing control node H and the clock control signal input terminal CLKA. The first pull-down noise reduction circuit 18 is configured to respond to the control of the valid level signal at the sensing control node H and the valid level signal provided by the clock control signal input terminal CLKA, and write the non-valid level signal provided by the second power supply terminal to the pull-down node PD to perform noise reduction processing on the output voltage of the pull-down node PD.

[0271] The second pull-down noise reduction circuit 19 is connected to the pull-down node PD, the second power supply terminal and the sensing signal input terminal INPUT2. The second pull-down noise reduction circuit 19 is configured to respond to the control of the valid level signal provided by the sensing signal input terminal INPUT2, and write the non-valid level signal provided by the second power supply terminal to the pull-down node PD to perform noise reduction processing on the output voltage of the pull-down node PD.

[0272] In some embodiments, the first pull-down noise reduction circuit 18 includes a twenty-ninth transistor M29 and a thirtieth transistor M30 , and the second pull-down noise reduction circuit 19 includes a thirty-first transistor M30 .

[0273] The control electrode of the 29th transistor M29 is connected to the clock control signal input terminal CLKA, the first electrode of the 29th transistor M29 is connected to the pull-down node PD, and the second electrode of the 29th transistor M29 is connected to the first electrode of the 30th transistor M30.

[0274] A control electrode of the 30th transistor M30 is connected to the sensing control node H, and a second electrode of the 30th transistor M30 is connected to the second power supply terminal.

[0275] A control electrode of the 31st transistor M30 is connected to the sensing signal input terminal INPUT2 , a first electrode of the 31st transistor M30 is connected to the pull-down node PD, and a second electrode of the 31st transistor M30 is connected to the second power supply terminal.

[0276] FIG21 is a schematic diagram of another circuit structure of a shift register provided in an embodiment of the present disclosure. As shown in FIG21 , in some embodiments, when a first voltage control circuit is provided within the shift register, the shift register may further include a second detection circuit 200 ; the second detection circuit 200 is connected to the first voltage control node OFF1, the third acquisition control terminal CL3, and the second signal detection line SGD′. The second detection circuit 200 is configured to acquire the voltage at the first voltage control node OFF1 in response to a signal provided by the third acquisition control terminal CL3 and output a third detection voltage corresponding to the voltage at the first voltage control node OFF1 to the second signal detection line SGD′, so that the external first chip can adjust the voltage provided by the first power supply terminal based on the third detection voltage.

[0277] When the voltage at the pull-up node PU is in a high-level state, the corresponding voltage is VPU_H. The eighth power supply terminal provides a voltage V8 ≥ VPU_H. At this time, the voltage at the first voltage-controlled node is VPU_H - Vth_M20, where Vth_M20 is the threshold voltage of the twentieth transistor M20 in the first voltage-controlled circuit. Therefore, by reading the voltage at the first voltage-controlled node, the threshold voltage drift of the twentieth transistor M20 can be obtained. Based on the threshold voltage drift of the twentieth transistor M20, the voltage provided by the first power supply terminal can be adjusted as needed. The specific adjustment method can be pre-designed according to actual needs and will not be detailed here.

[0278] In some embodiments, the second detection circuit 200 includes: a fifty-seventh transistor M57; the control electrode of the fifty-seventh transistor M57 is connected to the third acquisition control terminal CL3, the first electrode of the fifty-seventh transistor M57 is connected to the first control voltage node, and the second electrode of the fifty-seventh transistor M57 is connected to the second signal detection line SGD'.

[0279] To effectively reduce wiring, in some embodiments, the first signal detection line SGD is multiplexed as the second signal detection line SGD′. That is, the first signal detection line SGD can receive signals provided by the first detection circuit 100 and the second detection circuit 200 in a time-division multiplexing manner.

[0280] Of course, in some embodiments, the shift register may also include the second detection circuit 200 but not the first detection circuit 100 , and this situation should also fall within the protection scope of the present disclosure.

[0281] It should be noted that, in the above embodiments, different parts in different embodiments can be combined with each other, and the new technical solutions obtained by combining the embodiments should also fall within the scope of protection of this disclosure.

[0282] Based on the same inventive concept, an embodiment of the present disclosure also provides a gate drive circuit, which includes: multiple cascaded shift registers, wherein at least one shift register adopts the shift register provided in the previous embodiment. For specific description, please refer to the content of the previous embodiment, which will not be repeated here.

[0283] FIG22 is a schematic diagram of a circuit structure of a gate drive circuit in a disclosed embodiment. As shown in FIG22 , the multiple shift registers included in the gate drive circuit specifically include: multiple effective shift registers 300 b that provide drive signals to the gate lines Gate located in the display area, and at least one dummy shift register other than the effective shift registers 300 b; wherein, at least one dummy shift register 300 a uses the shift register provided in the previous embodiment; that is, at least one dummy shift register 300 a is provided with the above-mentioned first detection circuit 100.

[0284] In practical applications, the shift registers at the first two stages or the last two stages in a general gate driving circuit are virtual shift registers 300a, and the shift registers at the third stage to the third to last stage are effective shift registers 300b.

[0285] In the present disclosure, the first detection circuit 100 may be provided in any virtual shift register 300a, and of course, the first detection circuit 100 (configured with the first signal detection line SGD) may also be provided in any virtual shift register 300a. The present disclosure does not impose any limitation on this.

[0286] Based on the same inventive concept, the embodiments of the present disclosure also provide a display device. FIG23 is a schematic structural diagram of a display device in the disclosed embodiment. FIG24 is a block diagram of a structure of a first chip in the disclosed embodiment. As shown in FIG23 and FIG24 , the display device 500 includes: a display area 500a and a non-display area 500b surrounding the display area 500a. A gate drive circuit is provided in the non-display area 500b. The gate drive circuit adopts the gate drive circuit provided in the previous embodiment. For a detailed description, please refer to the content of the previous embodiment and will not be repeated here.

[0287] In some embodiments, the display device 500 further includes: a plurality of pixel units PIX arranged in an array and a plurality of signal readout lines. Referring again to FIG. 1 , in some embodiments, the pixel unit PIX includes: a pixel driving circuit with an external threshold compensation function, the pixel driving circuit including: a driving transistor DTFT and a sensing switch circuit STFT; the sensing switch circuit STFT is connected to the second electrode of the driving transistor DTFT and the signal readout line RL, and the sensing switch circuit STFT is configured to read an electrical signal at the second electrode of the driving transistor DTFT to the corresponding signal readout line RL, so that an external second chip (not shown) can perform external threshold compensation on the driving transistor DTFT based on the electrical signal at the second electrode of the driving transistor DTFT.

[0288] In some embodiments, at least one signal readout line RL is reused as the first signal detection line SGD. This design can effectively reduce the number of wirings in the display device and simplify the product structure.

[0289] In some embodiments, the second chip and the first chip 800 are the same chip.

[0290] In some embodiments, the number of shift registers provided with the first detection circuit 100 in the gate driving circuit is one; a signal reading line RL closest to the gate driving circuit in the display device is reused as the first signal detection line SGD.

[0291] In some embodiments, the first chip 800 is further configured to control the voltage provided by the third power supply terminal to switch from an active level voltage to an inactive level voltage in response to the display device being switched to a shutdown state. When the display device is switched to a shutdown state, the voltage provided by the third power supply terminal can be controlled to switch from an active level voltage to an inactive level voltage, thereby eliminating forward stress on the transistor in the inverter circuit 2 whose control electrode is connected to the third power supply terminal, thereby improving the forward drift problem of the transistor in the inverter circuit 2 whose control electrode is connected to the third power supply terminal.

[0292] In some embodiments, the first chip 800 includes: an analog-to-digital conversion module 801 and a voltage adjustment module 802; the analog-to-digital conversion module 801 is connected to the first signal detection line SGD, and the analog-to-digital conversion module 801 is configured to perform analog-to-digital conversion processing on the signal obtained from the first signal detection line SGD to obtain a corresponding digital voltage; the voltage adjustment module 802 is connected to the analog-to-digital conversion module 801, and the voltage adjustment module 802 is configured to obtain the voltage size of the effective level voltage to be provided to the third power supply terminal based on a preset adjustment algorithm and the digital voltage provided by the analog-to-digital conversion module 801.

[0293] In some embodiments, the first chip 800 also includes: a power supply module 803; the power supply module 803 is connected to the voltage adjustment module, and the power supply module 803 is configured to output a corresponding effective level voltage to the third power supply terminal based on the voltage size of the effective level voltage to be provided to the third power supply terminal determined by the voltage adjustment module 802.

[0294] In some embodiments, a switch circuit SW is provided between the first chip 800 and the first signal detection line SGD.

[0295] In some embodiments, the first signal detection line SGD is further configured with an eleventh capacitor C11 ; a first end of the eleventh capacitor C11 is connected to the first detection line SGD, and a second end of the eleventh capacitor C11 is connected to the ground.

[0296] It should be noted that the aforementioned multiplexing of the signal readout line RL closest to the gate drive circuit in a display device as the first signal detection line SGD is merely one optional implementation in the present disclosure and does not limit the disclosed technical solution. In the present disclosure, one or more randomly selected signal readout lines RL may be multiplexed as the first signal detection line SGD. Alternatively, a separate first signal detection line SGD may be provided in the display device. These implementations are all within the scope of protection of the present disclosure.

[0297] The display device provided in the embodiments of the present disclosure can be any product or component with a display function, such as an OLED display panel, a wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0298] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A shift register, wherein: include: A display input reset circuit, an inverting circuit, at least one output circuit and a first detection circuit, wherein the display input reset circuit, the inverting circuit and the output circuit are connected to a pull-up node, and the inverting circuit and the output circuit are connected to a pull-down node; The display input reset circuit is connected to the display signal input terminal, the reset signal terminal, and the second power supply terminal, and is configured to write a valid level signal to the pull-up node in response to the control of the signal provided by the display signal input terminal, and write a voltage provided by the second power supply terminal to the pull-up node in response to the control of the signal provided by the reset signal terminal; The inverting circuit is connected to the second power supply terminal and the third power supply terminal, and is configured to invert the voltage of the pull-up node in response to the voltage provided by the second power supply terminal and the effective level voltage provided by the third power supply terminal, and output the inverted voltage to the pull-down node; The output circuit is connected to the pull-up node, the pull-down node, the corresponding signal output terminal, the corresponding output clock signal terminal, and the corresponding fourth power supply terminal, and is configured to write the signal provided by the output clock signal terminal to the corresponding signal output terminal in response to the control of the voltage at the pull-up node, and write the voltage provided by the corresponding fourth power supply terminal to the corresponding signal output terminal in response to the control of the voltage at the pull-up node; The first detection circuit is connected to the signal collection point, the collection control terminal, and the first signal detection line, and is configured to collect the voltage at the signal collection point in response to the control of the signal provided by the collection control terminal and output a detection voltage corresponding to the voltage at the signal collection point to the first signal detection line, so that the external first chip can adjust the effective level voltage provided by the third power supply terminal according to the detection voltage. The signal collection point includes at least one of the pull-down node and the signal output terminal.

2. The shift register according to claim 1, wherein: The first detection circuit includes: at least one of a first detection subcircuit and a second detection subcircuit, and the acquisition control terminal includes: a first acquisition control terminal or a second acquisition control terminal; The first detection subcircuit is connected to the pull-down node, the first acquisition control terminal and the first signal detection line, and the first detection subcircuit is configured to collect the voltage at the pull-down node and output a first detection voltage corresponding to the voltage at the pull-down node to the first signal detection line in response to the control of the signal provided by the first acquisition control terminal; The second detection sub-circuit is connected to the signal output terminal, the second acquisition control terminal and the first signal detection line. The second detection sub-circuit is configured to collect the voltage at the pull-down node in response to the control of the signal provided by the second acquisition control terminal and output a second detection voltage corresponding to the voltage at the signal output terminal to the first signal detection line.

3. The shift register according to claim 2, wherein: The first detection subcircuit comprises: a fifty-first transistor; The control electrode of the fifty-first transistor is connected to the first acquisition control terminal, the first electrode of the fifty-first transistor is connected to the pull-down node, and the second electrode of the fifty-first transistor is connected to the first signal detection line.

4. The shift register according to claim 2, wherein: The first detection sub-circuit comprises: a fifty-first transistor, a fifty-second transistor, a fifty-third transistor and a fifty-fourth transistor; The control electrode of the fifty-first transistor is connected to the first acquisition control terminal, the first electrode of the fifty-first transistor is connected to the second electrode of the fifty-second transistor, and the second electrode of the fifty-first transistor is connected to the first signal detection line; The control electrode of the fifty-second transistor is connected to the pull-down node, and the first electrode of the fifty-second transistor is connected to the second electrode of the fifty-third transistor and the first electrode of the fifty-fourth transistor; The control electrode of the fifty-third transistor is connected to the first switch control terminal, and the first electrode of the fifty-third transistor is connected to the control electrode of the fifty-second transistor; The control electrode of the fifty-fourth transistor is connected to the second switch control terminal, and the second electrode of the fifty-fourth transistor is connected to the seventh power supply terminal.

5. The shift register according to claim 4, wherein: The first detection subcircuit further includes: a fifty-fifth transistor; The second electrode of the fifty-second transistor is connected to the first electrode of the fifty-first transistor through the fifty-fifth transistor, the control electrode of the fifty-fifth transistor and the first electrode of the fifty-fifth transistor are both connected to the second electrode of the fifty-second transistor, and the second electrode of the fifty-fifth transistor is connected to the first electrode of the fifty-first transistor; Alternatively, the second electrode of the fifty-first transistor is connected to the first signal detection line through the fifty-fifth transistor, the control electrode of the fifty-fifth transistor and the first electrode of the fifty-fifth transistor are both connected to the second electrode of the fifty-first transistor, and the second electrode of the fifty-fifth transistor is connected to the first signal detection line.

6. The shift register according to any one of claims 2 to 5, wherein: The number of the output circuits is m, the number of the second detection sub-circuits is n, the number of the second acquisition control terminals is n, the second detection sub-circuits correspond to the second acquisition control terminals one by one, m and n are both positive integers and m≥n; Different second detection sub-circuits correspond to different output circuits, and the second detection sub-circuit is connected to the signal output end of the corresponding output circuit.

7. The shift register according to any one of claims 2 to 6, wherein: The second detection subcircuit comprises: a fifty-sixth transistor; The control electrode of the fifty-sixth transistor is connected to the corresponding second acquisition control terminal, the first electrode of the fifty-first transistor is connected to the pull-down node, and the second electrode of the fifty-first transistor is connected to the first signal detection line.

8. The shift register according to any one of claims 1 to 7, wherein: Also includes: Step-down circuit; The first detection circuit is connected to the first signal detection line through the step-down circuit, and the step-down circuit is configured to step-down the detection voltage output by the first detection circuit and output the stepped-down detection voltage to the first signal detection line.

9. The shift register according to claim 8, wherein: The step-down circuit comprises: a first resistor and a second resistor; The first end of the first resistor is connected to the first detection circuit, the second end of the first resistor is connected to the first signal detection line, the first end of the second resistor is connected to the second end of the first resistor, and the second end of the second resistor is connected to the ground end.

10. The shift register according to any one of claims 1 to 9, wherein: The display input reset circuit comprises: A display input circuit connected to a display signal input terminal and a pull-up node, and configured to write a valid level signal to the pull-up node in response to control of a signal provided by the display signal input terminal; A display reset circuit is connected to the display reset signal input terminal, the second power supply terminal and the pull-up node, and is configured to write the voltage provided by the second power supply terminal to the pull-up node in response to the control of the signal provided by the display reset signal input terminal; The shift register further includes: a first voltage control circuit; The first voltage control circuit is connected to the first power supply terminal, the pull-up node and the first voltage control node, and the first voltage control circuit is configured to write the voltage provided by the first power supply terminal to the first voltage control node in response to the control of the voltage at the pull-up node; The shift register further includes: at least one of a second leakage protection circuit and a display input leakage protection circuit; The display reset circuit is connected to the second power supply terminal through the second leakage prevention circuit, the display reset circuit and the second leakage prevention circuit are connected to a second leakage prevention node, the second leakage prevention node is connected to the first voltage control node, the second leakage prevention circuit is connected to the display reset signal input terminal, and the second leakage prevention circuit is configured to form a path between the second leakage prevention node and the second power supply terminal in response to the control of the effective level signal provided by the display reset signal input terminal, and to disconnect the second leakage prevention node from the second power supply terminal in response to the control of the ineffective level signal provided by the display reset signal input terminal; The display input circuit is connected to the pull-up node through the display input leakage prevention circuit, the display input circuit and the display input leakage prevention circuit are connected to the display input leakage prevention node, and the display input leakage prevention node is connected to the first voltage control node. The display input leakage protection node is connected to the display signal input terminal, and the display input leakage protection circuit is configured to form a path between the display input leakage protection node and the pull-up node in response to the control of the valid level signal provided by the display signal input terminal, and to open the circuit between the display input leakage protection node and the pull-up node in response to the control of the non-valid level signal provided by the display signal input terminal.

11. The shift register according to any one of claims 1 to 10, wherein: The shift register further includes: at least one of a pull-up noise reduction circuit and a global reset circuit; The pull-up noise reduction circuit is connected to the second power supply terminal, the pull-up node and the pull-down node, and is configured to write the voltage provided by the second power supply terminal to the pull-up node in response to the control of the effective level signal at the pull-down node; The global reset circuit is connected to the global reset signal input terminal, the second power supply terminal, and the pull-up node, and is configured to write the voltage provided by the second power supply terminal to the pull-up node in response to the control of the signal provided by the global reset signal input terminal.

12. The shift register according to claim 11, wherein: Also includes: a first voltage control circuit; The first voltage control circuit is connected to the first power supply terminal, the pull-up node and the first voltage control node, and the first voltage control circuit is configured to write the voltage provided by the first power supply terminal to the first voltage control node in response to the control of the voltage at the pull-up node; The shift register circuit further includes: at least one of a first leakage protection circuit and a third leakage protection circuit; The global reset circuit is connected to the second power supply terminal through the first leakage prevention circuit, the global reset circuit and the first leakage prevention circuit are connected to a first leakage prevention node, the first leakage prevention node is connected to the first voltage control node, the first leakage prevention circuit is connected to the global reset signal input terminal, and the first leakage prevention circuit is configured to form a path between the first leakage prevention node and the second power supply terminal in response to the control of the effective level signal provided by the global reset signal input terminal, and to disconnect the first leakage prevention node from the second power supply terminal in response to the control of the ineffective level signal provided by the global reset signal input terminal; The pull-up noise reduction circuit is connected to the second power supply terminal through the third leakage prevention circuit, the pull-up noise reduction circuit and the third leakage prevention circuit are connected to a third leakage prevention node, the third leakage prevention node is connected to the first voltage control node, the third leakage prevention circuit is connected to the pull-down node, and the third leakage prevention circuit is configured to form a path between the third leakage prevention node and the second power supply terminal in response to the control of the effective level signal at the pull-down node, and to disconnect the third leakage prevention node from the second power supply terminal in response to the control of the ineffective level signal at the pull-down node; 13. The shift register according to claim 10 or 12, wherein: Also includes: The second detection circuit is connected to the first voltage control node, the third acquisition control terminal and the second signal detection line, and is configured to acquire the voltage at the first voltage control node in response to the control of the signal provided by the third acquisition control terminal and output a third detection voltage corresponding to the voltage at the first voltage control node to the second signal detection line, so that the external chip can adjust the voltage provided by the first power supply terminal according to the third detection voltage.

14. The shift register according to claim 13, wherein: The second detection circuit includes: a fifty-seventh transistor; The control electrode of the fifty-seventh transistor is connected to the third acquisition control terminal, the first electrode of the fifty-seventh transistor is connected to the first voltage control node, and the second electrode of the fifty-seventh transistor is connected to the second signal detection line.

15. The shift register according to claim 13 or 14, wherein: The first signal detection line is multiplexed as the second signal detection line.

16. The shift register according to any one of claims 1 to 15, wherein: The inverting circuit includes: a thirty-seventh transistor, a thirty-eighth transistor, a thirty-ninth transistor and a fortieth transistor; The control electrode of the thirty-seventh transistor is connected to the third power supply terminal, the first electrode of the thirty-seventh transistor is connected to the control electrode of the thirty-seventh transistor, and the second electrode of the thirty-seventh transistor is connected to the control electrode of the thirty-eighth transistor; The control electrode of the thirty-eighth transistor is connected to the first electrode of the fortieth transistor, the first electrode of the thirty-eighth transistor is connected to the third power supply terminal, and the second electrode of the thirty-eighth transistor is connected to the pull-down node. A control electrode of the thirty-ninth transistor is connected to the pull-up node, a first electrode of the thirty-ninth transistor is connected to the pull-down node, and a second electrode of the thirty-ninth transistor is connected to the fifth power supply terminal or the pull-down node; A control electrode of the 40th transistor is connected to the pull-up node, and a second electrode of the 40th transistor is connected to the second power supply terminal.

17. The shift register according to claim 16, wherein: The inverter circuit further includes: a 41st transistor, the second electrode of the 37th transistor is connected to the control electrode of the 38th transistor through the 41st transistor; The control electrode of the forty-first transistor is connected to the control electrode of the thirty-seventh transistor, the first electrode of the forty-first transistor is connected to the second electrode of the thirty-seventh transistor, and the second electrode of the forty-first transistor is connected to the control electrode of the thirty-eighth transistor.

18. The shift register according to any one of claims 1 to 15, wherein: The inverter circuit comprises: a twelfth transistor and a thirteenth transistor; The control electrode of the twelfth transistor is connected to the third power supply terminal, the first electrode of the twelfth transistor is connected to the control electrode of the twelfth transistor, and the second electrode of the twelfth transistor is connected to the pull-down node; The control electrode of the thirteenth transistor is connected to the pull-up node, the first electrode of the thirteenth transistor is connected to the pull-down node, and the second electrode of the thirteenth transistor is connected to the second power supply terminal.

19. The shift register according to any one of claims 1 to 18, wherein: Also includes: A sensing control circuit is connected to the sensing control node, the sensing signal input terminal and the random signal input terminal, and the sensing control circuit is configured to write the signal provided by the sensing signal input terminal to the sensing control node in response to the control of the signal provided by the random signal input terminal. input to the sensing control node; The sensing input circuit is connected to the sensing control node, the clock control signal input terminal, the sensing intermediate node and the pull-up node, and is configured to write a valid level signal to the sensing intermediate node in response to the control of a valid level signal at the sensing control node, and to form a path between the sensing intermediate node and the pull-up node in response to the control of a signal provided by the clock control signal input terminal.

20. A gate drive circuit, wherein: include: A plurality of cascaded shift registers, wherein at least one of the shift registers is a shift register as claimed in any one of claims 1 to 19.

21. The gate driving circuit according to claim 20, wherein: The plurality of cascaded shift registers include: a plurality of effective shift registers for providing driving signals to gate lines located in the display area and at least one virtual shift register other than the effective shift registers; At least one of the virtual shift registers adopts the shift register as claimed in any one of claims 1 to 15.

22. A display device, wherein: include: A display area and a non-display area surrounding the display area, wherein the gate driving circuit as claimed in claim 20 or 21 is arranged in the non-display area.

23. The display device according to claim 22, wherein: Also included are: a plurality of pixel units arranged in an array and a plurality of signal reading lines, wherein the pixel unit includes: a pixel driving circuit with an external threshold compensation function, wherein the pixel driving circuit includes: a driving transistor and a sensing switch circuit; The sensing switch circuit is connected to the second electrode of the driving transistor and the signal reading line, and the sensing switch circuit is configured to read the electrical signal at the second electrode of the driving transistor to the corresponding signal reading line, so that the external second chip can perform external threshold compensation on the driving transistor according to the electrical signal at the second electrode of the driving transistor; At least one of the signal readout lines is multiplexed as the first signal detection line.

24. The display device according to claim 22, wherein: The second chip is the same chip as the first chip.

25. The display device according to claim 23 or 24, wherein: The number of shift registers provided with the first detection circuit in the gate drive circuit is 1; One of the signal reading lines closest to the gate driving circuit in the display device is multiplexed as the first signal detection line.

26. The display device according to any one of claims 22 to 25, wherein: The first chip is further configured to control the voltage provided by the third power supply terminal to switch from a valid level voltage to a non-valid level voltage in response to the display device being switched to a shutdown state.

27. The display device according to any one of claims 22 to 26, wherein: The first chip includes: an analog-to-digital conversion module and a voltage adjustment module; The analog-to-digital conversion module is connected to the first signal detection line and is configured to perform analog-to-digital conversion processing on the signal obtained from the first signal detection line to obtain a corresponding digital voltage; The voltage adjustment module is connected to the analog-to-digital conversion module and is configured to obtain the voltage magnitude of the effective level voltage to be provided to the third power supply terminal according to a preset adjustment algorithm and the digital voltage provided by the analog-to-digital conversion module.

28. The display device according to claim 27, wherein: The first chip further includes: The power supply module is connected to the voltage adjustment module and is configured to output a corresponding effective level voltage to the third power supply terminal according to the voltage magnitude of the effective level voltage to be provided to the third power supply terminal determined by the voltage adjustment module.

29. The display device according to any one of claims 22 to 28, wherein: A switch circuit is provided between the first chip and the first signal detection line.

30. The display device according to any one of claims 22 to 29, wherein: The first signal detection line is further configured with an eleventh capacitor; A first end of the eleventh capacitor is connected to the first detection line, and a second end of the eleventh capacitor is connected to a ground end.

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