Adaptive gidl voltage for erasing non-volatile memory

Abstract

An apparatus is provided that includes a block of memory cells having a NAND string including a first select transistor and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on a block of memory cells by: determining a first count of the number of times the block of memory cells has been previously programmed and erased; determining a first drain-to-gate voltage of the first select transistor based on the first count, wherein the first drain-to-gate voltage is configured to cause the first select transistor to generate a first gate induced drain leakage current; and applying a first erase pulse to the first select transistor based on the determined first drain-to-gate voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of, and is hereby incorporated by reference in its entirety, U.S. non-provisional application Ser. No. 17 / 899,765, filed Aug. 31, 2022, and entitled “ADAPTIVE GIDL VOLTAGE FOR ERASING NON-VOLATILE MEMORY,” for all purposes. Background Art

[0003] Semiconductor memories are widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memories may include non-volatile memories or volatile memories. Non-volatile memories allow information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery). Examples of non-volatile memories include flash memory (e.g., NAND-type and NOR-type flash memory).

[0004] Memory systems can be used to store data provided by a host device (or other client). However, there are various challenges in operating such memory systems. In particular, as the size of memory cells decreases and the density of memory arrays increases, maintaining the integrity of the data being stored becomes more challenging. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Like numbered elements refer to common parts in different figures.

[0006] Figure 1 is a block diagram depicting one embodiment of a memory system.

[0007] Figure 2 is a block diagram of one embodiment of a memory die.

[0008] Figure 3 is a perspective view of a portion of one embodiment of a three-dimensional memory structure.

[0009] Figure 4A is a block diagram of a memory structure with two planes.

[0010] Figure 4B Depicted is a top view of a portion of a block of memory cells.

[0011] Figure 4C A cross-sectional view of a portion of a block of memory cells is depicted.

[0012] Figure 4DA view depicting the select gate layer and the word line layer.

[0013] Figure 4E is a cross-sectional view of a memory hole of a memory cell.

[0014] Figure 4F is a schematic diagram of multiple NAND strings.

[0015] Figure 5 The threshold voltage distribution is depicted.

[0016] Figure 6 is a table that describes one example of assigning data values ​​to data states.

[0017] 7A to 7E Various threshold voltage distributions are depicted and a process for programming nonvolatile memory is described.

[0018] Figure 8 is a flow chart describing an embodiment of a process for programming non-volatile memory.

[0019] Fig. 9 The word line voltages during program and verify operations are depicted.

[0020] Fig.10 A flow chart describing an embodiment of a process for erasing a population of memory cells is depicted.

[0021] Fig.11 Example erased threshold voltage distributions for a population of memory cells are depicted.

[0022] Fig.12A1 A flow chart describing an embodiment of a process for erasing a population of memory cells is depicted.

[0023] Fig.12A2 A table depicting program-erase cycle count values ​​and corresponding adaptive GIDL voltage values.

[0024] Fig. 12B A flow chart describing an embodiment of another process for erasing a population of memory cells is depicted.

[0025] Fig. 12C A flow chart describing an embodiment of yet another process for erasing a population of memory cells is depicted. DETAILED DESCRIPTION

[0026] 3D stacked non-volatile memory devices may be arranged in multiple blocks, where erase operations are typically performed one block at a time. The erase operation may include multiple erase verify iterations that are performed until the block meets the erase verify condition, at which point the erase operation ends.

[0027] In one approach, a memory device includes a NAND string having a drain-side select gate (SGD) at one end and a source-side select gate (SGS) at the other end. The select gates play an important role in the erase operation because they are used to generate a sufficient amount of gate-induced drain leakage (GIDL) current to boost the NAND string channel. The boosting of the channel creates a large channel-to-gate voltage that drives holes into the charge trapping layer, thereby lowering the threshold voltage of each memory cell. This technique is referred to herein as "GIDL erase".

[0028] In one approach, an erase pulse is applied to one or both of the SGD and SGS of a NAND string to provide a drain-to-gate voltage (referred to herein as the GIDL voltage) of sufficiently high magnitude to cause the select transistor to generate a GIDL current. However, the amount of GIDL current generated for a given GIDL voltage (referred to herein as the "GIDL current efficiency") decreases over the lifetime of a memory cell or group of memory cells. As the GIDL current efficiency decreases, the channel boosting decreases and the corresponding threshold voltage reduction decreases.

[0029] Techniques for providing an adaptive GIDL voltage for an erase operation on an erase block of nonvolatile memory cells are described. In an embodiment, the value of the adaptive GIDL voltage is determined based on the number of program-erase cycles for the erase block. In an embodiment, the adaptive GIDL voltage increases as the number of program-erase cycles for the erase block increases. In another embodiment, the value of the adaptive GIDL voltage is determined based on the number of erase-verify cycles used to erase the erase block. In an embodiment, the adaptive GIDL voltage increases as the number of erase-verify cycles increases.

[0030] Without wishing to be bound by any particular theory, we believe that increasing the adaptive GIDL voltage as the number of program-erase cycles or erase-verify cycle count increases can compensate for the decrease in GIDL current efficiency that occurs with increasing program-erase cycle counts.

[0031] Some non-volatile memory devices are used to store two ranges of charge, and therefore the memory cell can be programmed / erased between two data states: an erased state and a programmed state (corresponding to data "1" and data "0"). Such devices are called binary devices or single-level cells (SLC), and the data is binary data.

[0032] In contrast, multi-state flash memory cells (storing multi-state data) are implemented by identifying multiple different allowed threshold voltage ranges. Each different threshold voltage range corresponds to a predetermined value for the set of data bits. For example, some memory cells can store two or more bits. The specific relationship between the data programmed into the memory cell and the threshold voltage range of the memory cell depends on the data encoding scheme adopted by the memory cell.

[0033] In addition to the capacity increases caused by multi-state memory architectures, significant advances in memory technology have come from the steady shrinking of the physical size of memory cells. Smaller memory cells can be packed more densely on a given die area, resulting in more memory capacity for the same price as older memory technologies.

[0034] Figure 1 1 is a block diagram of an embodiment of a memory system 100 that implements the technology. In an embodiment, the memory system 100 is a solid state drive ("SSD"). The memory system 100 may also be a memory card, a USB drive, or other types of memory systems. The technology of the present invention is not limited to any one type of memory system. The memory system 100 is connected to a host 102, which may be a computer, a server, an electronic device (e.g., a smart phone, a tablet computer, or other mobile device), an appliance, or another device that uses memory and has data processing capabilities. In some embodiments, the host 102 is separated from the memory system 100 but connected to the memory system. In other embodiments, the memory system 100 is embedded in the host 102.

[0035] Figure 1 The components of the memory system 100 depicted in FIG. 1 are electrical circuits. The memory system 100 includes a controller 104 connected to one or more memory dies 106 and a local high-speed volatile memory 108 (e.g., DRAM). The one or more memory dies 106 each include a plurality of non-volatile memory cells. More information about the structure of each memory die 106 is provided below. The controller 104 uses the local high-speed volatile memory 108 to perform certain functions. For example, the local high-speed volatile memory 108 stores logic in a physical address translation table ("L2P table").

[0036] Controller 104 includes a host interface 110 that is connected to and communicates with host 102. In one embodiment, host interface 110 provides a PCIe interface. Other interfaces such as SCSI, SATA, etc. may also be used. Host interface 110 is also connected to a network on chip (NOC) 112, which is a communication subsystem on an integrated circuit. In other embodiments, NOC 112 may be replaced by a bus.

[0037] NOC can span synchronous and asynchronous clock domains, or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication, and brings significant improvements compared to conventional bus and cross switch interconnection. Compared with other designs, NOC improves the scalability of system on chip (SoC) and the power efficiency of complex SoC. In an embodiment, the wires and links of NOC are shared by many signals. Since all links in NOC can run simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems continues to increase, NOC provides enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges).

[0038] Connected to and in communication with the NOC 112 are a processor 114, an ECC engine 116, a memory interface 118, and a DRAM controller 120. The DRAM controller 120 is used to operate and communicate with a local high-speed volatile memory 108 (e.g., DRAM). In other embodiments, the local high-speed volatile memory 108 may be SRAM or another type of volatile memory.

[0039] The ECC engine 116 performs error correction services. For example, the ECC engine 116 performs data encoding and decoding according to the implemented ECC technology. In one embodiment, the ECC engine 116 is an electrical circuit programmed by software. For example, the ECC engine 116 can be a programmable processor. In other embodiments, the ECC engine 116 is a customized dedicated hardware circuit without any software. In another embodiment, the functions of the ECC engine 116 are implemented by the processor 114.

[0040] Processor 114 performs various controller memory operations, such as programming, erasing, reading, and memory management processes. In an embodiment, processor 114 is programmed by firmware. In other embodiments, processor 114 is a customized dedicated hardware circuit without any software. In an embodiment, processor 114 also implements the conversion module as a software / firmware process or as a dedicated hardware circuit.

[0041] In many systems, non-volatile memory is addressed internally to the storage system using physical addresses associated with one or more memory dies. However, the host system will use logical addresses to address various memory locations. This enables the host to assign data to consecutive logical addresses while the storage system is free to store data between locations on one or more memory dies as desired. To implement such a system, a controller (e.g., a translation module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory dies.

[0042] One example implementation is to maintain a table (e.g., the L2P table described above) that identifies the conversion between logical addresses and physical addresses. An entry in the L2P table may include an identification of a logical address and a corresponding physical address. Although logical address to physical address tables (or L2P tables) include the word "table," they need not be tables in the literal sense. Rather, logical address to physical address tables (or L2P tables) may be any type of data structure.

[0043] In some examples, the memory space of the storage system is so large that all L2P tables cannot be saved in the local memory 108. In this case, the entire set of L2P tables is stored in the memory die 106, and a subset of the L2P tables is cached (L2P cache) in the local high-speed volatile memory 108.

[0044] In an embodiment, memory interface 118 communicates with one or more memory dies 106. In an embodiment, memory interface 118 provides a switch mode interface. Other interfaces may also be used. In some exemplary implementations, memory interface 118 (or another portion of controller 104) implements a scheduler and buffer for transmitting data to one or more memory dies and receiving data from one or more memory dies.

[0045] Figure 2 is a functional block diagram of one embodiment of memory die 200 . Figure 1 Each of the one or more memory dies 106 may be implemented as Figure 2 The memory die 200 is provided. Figure 2 The components depicted in are electrical circuits. In an embodiment, each memory die 200 includes a memory structure 202, a control circuit 204, and a read / write circuit 206. The memory structure 202 can be addressed by word lines via a row decoder 208 and by bit lines via a column decoder 210.

[0046] In an embodiment, the read / write circuit 206 includes a plurality of sense blocks 212, which include SB1, SB2, ..., SBp (sense circuit) and allow parallel reading or programming (writing) of a page (multiple pages) of data in a plurality of memory cells. In an embodiment, each sense block 212 includes a sense amplifier and a group of latches connected to the bit line. The latch stores the data to be written and / or the data that has been read. In an embodiment, each sense amplifier 212 includes a bit line driver. In an embodiment, commands and data are transmitted between the controller 104 and the memory die 200 via lines 214. In an embodiment, the memory die 200 includes a group of input and / or output (I / O) pins connected to the lines 214.

[0047] In an embodiment, control circuit 204 cooperates with read / write circuit 206 to perform memory operations (e.g., write, read, erase, etc.) on memory structure 202. In an embodiment, control circuit 204 includes state machine 216, on-chip address decoder 218, and power control circuit 220. In an embodiment, state machine 216 provides die-level control of memory operations. In an embodiment, state machine 216 can be programmed by software. In other embodiments, state machine 216 does not use software and is fully implemented in hardware (e.g., electrical circuit). In some embodiments, state machine 216 can be replaced by a microcontroller or a microprocessor. In an embodiment, control circuit 204 includes buffers, such as registers, ROM fuses, and other storage devices for storing default values ​​(such as base voltage and other parameters).

[0048] On-chip address decoder 218 provides an address interface between addresses used by controller 104 and hardware addresses used by row decoder 208 and column decoder 210. Power control module 220 controls the power and voltage provided to word lines and bit lines during memory operations. Power control module 220 may include a charge pump for generating voltages.

[0049] For the purposes of this document, control circuitry 204, read / write circuitry 206, row decoder 208, and column decoder 210 comprise control circuitry for memory structure 202. In other embodiments, other circuitry that supports and operates on memory structure 202 may be referred to as control circuitry. For example, in some embodiments, controller 104 may operate as or may be part of a control circuitry. The control circuitry may also be implemented as a microprocessor or other type of processor that is hardwired or programmed to perform the functions described herein.

[0050] For purposes of this document, control circuitry 204, read / write circuitry 206, row decoder 208, and column decoder 210 comprise peripheral circuitry for memory structure 202 because they are not part of memory structure 202, but are instead on the same die as memory structure 202 and are used to operate memory structure 202.

[0051] In an embodiment, memory structure 202 is a three-dimensional memory array of non-volatile memory cells. In an embodiment, memory structure 202 is a monolithic three-dimensional memory array in which multiple memory levels are formed over a single substrate such as a wafer. The memory structure can be any type of non-volatile memory formed in one or more physical layers of an array of memory cells having an active area disposed over a silicon (or other type) substrate. In one example, the non-volatile memory cells of memory structure 202 include vertical NAND strings having a charge trapping material such as described. The NAND string includes memory cells connected by a channel.

[0052] In another embodiment, the memory structure 202 includes a two-dimensional memory array of non-volatile memory cells. In an example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (eg, NOR type flash memory) may also be used.

[0053] The exact type of memory array architecture or memory cells included in memory structure 202 is not limited to the above examples. Many different types of memory array architectures or memory cell technologies may be used to form memory structure 202. For the purposes of the new techniques described herein, no specific non-volatile memory technology is required.

[0054] Other examples of suitable technologies for the memory cells of the memory structure 202 include ReRAM memory, magnetoresistive memory (MRAM), phase change memory (PCM), etc. Examples of suitable technologies for the architecture of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0055] One example of a cross-point memory includes a reversible resistance-switching element arranged in a cross-point array accessed by an X-line and a Y-line (e.g., a word line and a bit line). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization cell.

[0056] Conductive bridge memory elements can be used as state change elements based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element can include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes.

[0057] MRAM uses magnetic storage elements to store data. The magnetic storage element is formed by two ferromagnetic plates, each of which can remain magnetized, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match the magnetization of the external magnetic field to store memory. The memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines that are arranged at right angles to each other, parallel to the cell, one above the cell and one below the cell. When current passes through them, an induced magnetic field is generated.

[0058] Phase change memory (PCM) exploits the unique properties of chalcogenide glasses. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve a non-thermal phase change by simply changing the coordination state of the germanium atoms with a laser pulse (or a light pulse from another source). Therefore, the programming dose is the laser pulse. The programming of a memory cell can be inhibited by preventing the memory cell from receiving light.

[0059] Those of ordinary skill in the art will recognize that the techniques described herein are not limited to a single particular memory structure, but encompass many related memory structures that are within the scope of the techniques described herein and as understood by those of ordinary skill in the art.

[0060] Figure 3 is a perspective view of a portion of an embodiment of a three-dimensional memory array including a memory structure 202. In an embodiment, the memory structure 202 includes a plurality of non-volatile memory cells. For example, Figure 3 A portion of a block of memory cells is shown. The depicted structure includes a set of bit lines BL located above a stack of alternating dielectric and conductive layers. For purposes of illustration, one of the dielectric layers is labeled D and one of the conductive layers (also called word line layers) is labeled W.

[0061] The number of alternating dielectric layers and conductive layers can vary based on specific implementation requirements. One set of embodiments includes 108 to 300 alternating dielectric layers and conductive layers. An exemplary embodiment includes 96 data word line layers, 8 selection layers, 6 dummy word line layers, and 110 dielectric layers. More or less than 108 to 300 layers may also be used. In an embodiment, the alternating dielectric layers and conductive layers are divided into four regions by local interconnects LI. Figure 3 Two regions and two local interconnects LI are shown.

[0062] The source line layer SL is below the alternating dielectric layer and word line layer. A memory hole is formed in the stack of alternating dielectric layers and conductive layers. For example, the memory hole is marked as MH. Note that Figure 3 In FIG. 1 , the dielectric layers are depicted as a perspective view so that the reader can see the memory holes positioned in the stack of alternating dielectric and conductive layers.

[0063] In an embodiment, a NAND string is formed by filling the memory holes with a material including a charge trapping material to form a vertical column of memory cells. In an embodiment, each memory cell can store one or more data bits. In an embodiment, each memory hole MH is associated with and coupled to a corresponding one of the bit lines BL. In an embodiment, each bit line BL is coupled to one or more memory holes MH. More details of a three-dimensional memory array including memory structure 202 are described below.

[0064] Figure 4A 2 is a block diagram illustrating an exemplary organization of a memory structure 202 that is divided into two planes 400a and 400b. Both planes are on the same memory die 200 ( Figure 2 ) on a plane. Each plane is then divided into M blocks. In one example, each plane has about 2000 blocks. However, a different number of blocks and planes may also be used. The portion 402 of block 2 of the memory plane 400a is in Figure 4A Shown by dotted lines.

[0065] In an embodiment, a block of memory cells is the unit of erase. That is, all memory cells of a block are erased together. In other embodiments, memory cells may be grouped into blocks for other reasons, such as to organize memory structure 202 to enable signaling and selection circuits. In some embodiments, a block represents a group of connected memory cells because the memory cells of a block share a common set of word lines. Although Figure 4A Two planes on the same die are shown, but in other embodiments, more than two planes may be implemented.For example, memory structure 202 may include 2 to 8 (or more) planes.

[0066] FIG. 4B to FIG. 4F Depicts the corresponding Figure 3 An exemplary three-dimensional (“3D”) NAND structure of a structure. Figure 4B is a portion 402 depicting the memory structure 202 ( Figure 4A ) is a top view of the block diagram. Figure 4B It can be seen that portion 402 extends in direction 404 and direction 406. In an embodiment, the memory array has many layers, however, Figure 4B Only the top layer is shown.

[0067] Figure 4B A plurality of circles representing memory holes (which are also referred to as memory columns) are depicted. For example, Figure 4BMemory holes 408, 410, 412, and 414 are depicted. Each of the memory holes includes a plurality of select transistors (also referred to as select gates) and a plurality of memory cells. In an embodiment, each memory hole implements a NAND string. Because portion 402 extends in directions 404 and 406, the block includes more than Figure 4B The memory holes depicted in FIG.

[0068] Figure 4B Also depicted is a set of bit lines 424, including bit lines 426, 428, 430, 432, ..., 434. In an embodiment, each memory well is associated with and coupled to a corresponding one of the bit lines. In an embodiment, each bit line is coupled to one or more memory wells. Figure 4B Twenty-four bit lines are shown because only a portion of the block is depicted. It is contemplated that more than twenty-four bit lines are connected to the memory holes of the block. Each of the circles representing memory holes has an "x" to indicate that it is connected to a bit line. For example, bit line 432 is connected to memory holes 408, 410, 412, and 414.

[0069] Figure 4B The portion 402 depicted in FIG. 4 includes a set of local interconnects 436, 438, 440, 442, and 444 that connect the various layers to the source line below the memory hole. The local interconnects 436, 438, 440, 442, and 444 are also used to divide each layer of the block into four regions. For example, Figure 4B The top layer depicted in is divided into four regions designated as String0, String1, Sting2, and String3. In a layer implementing a block of memory cells, String0, String1, Sting2, and String3 may be referred to as word line fingers separated by local interconnects.

[0070] In an embodiment, the word line fingers on a common level of a block are connected together to form a single word line. In another embodiment, the word line fingers on the same level are not connected together. In an exemplary implementation, the bit line is connected to a single memory hole in each of String0, String1, String2, and String3. In this implementation, each block has sixteen rows of active columns, and each bit line is connected to four rows in each block.

[0071] In an embodiment, all four rows connected to a common bit line are connected to the same word line (via different word line fingers on the same level connected together). Therefore, the system uses source side select lines and drain side select lines to select one (or another subset) of the four for the memory operation (program, verify, read, and / or erase) to be performed.

[0072] although Figure 4B Four regions String0, String1, String2, and String3 are shown, each with four rows of memory holes, and sixteen rows of memory holes in a block, but these exact numbers are exemplary implementations. Other embodiments may include more or fewer regions per block, more or fewer rows of memory holes per region, and more or fewer rows of memory holes per block. Figure 4B It is also shown that the memory holes are staggered. In other embodiments, different staggering patterns can be used. In some embodiments, the memory holes are not staggered.

[0073] Figure 4C A portion of one embodiment of a three-dimensional memory structure 202 is depicted, showing Figure 4B The cross-sectional view cuts through the memory holes 410 and 454 of String1 (see Figure 4B ). Figure 4C The structure includes four drain side selection layers SGD0, SGD1, SGD2 and SGD3; four source side selection layers SGS0, SGS1, SGS2 and SGS3; six dummy word line layers DD0, DD1, DS0, DS1, WLDL, WLDU; and one hundred and twelve data word line layers WLL0 to WLL111 for connecting to memory cells. Other embodiments may implement more or less than four drain side selection layers, more or less than four source side selection layers, more or less than six dummy word line layers, and more or less than one hundred and twelve word lines.

[0074] Memory holes 410 and 454 are depicted as protruding through the drain side selection layer, the source side selection layer, the dummy word line layer, and the word line layer. In one embodiment, each memory hole includes a vertical NAND string. Below the memory hole and the layers listed below is a substrate 456, an insulating film 458 on the substrate, and a source line SL. The NAND string of memory hole 410 has a source terminal at the bottom of the stack and a drain terminal at the top of the stack. Figure 4B Consistent, Figure 4C Memory via 410 is shown connected to bit line 432 via connector 460. Local interconnects 438 and 440 are also depicted.

[0075] For ease of reference, the following items are collectively referred to as conductive layers: drain side selection layers SGD0, SGD1, SGD2, and SGD3; source side selection layers SGS0, SGS1, SGS2, and SGS3; dummy word line layers DD0, DD1, DS0, DS1, WLDL, and WLDU; and word line layers WLL0 to WLL111. In an embodiment, the conductive layers are made of a combination of TiN and tungsten. In other embodiments, other materials may be used to form the conductive layers, such as doped polysilicon, metals (such as tungsten), or metal silicides. In some embodiments, different conductive layers may be formed of different materials.

[0076] Between the conductive layers are dielectric layers DL0 to DL127. For example, dielectric layer DL120 is above word line layer WLL110 and below word line layer WLL111. In an embodiment, the dielectric layer is made of SiO2. In other embodiments, other dielectric materials may be used to form the dielectric layer.

[0077] The non-volatile memory cells are formed along memory holes that extend through alternating conductive layers and dielectric layers in the stack. In an embodiment, the memory cells are arranged in NAND strings. Word line layers WLL0 to WLL111 are connected to memory cells (also referred to as data memory cells). Dummy word line layers DD0, DD1, DS0, DS1, WLDL, and WLDU are connected to dummy memory cells. Dummy memory cells do not store host data and are not eligible to store host data (data provided from the host, such as data from a host user), while data memory cells are eligible to store host data.

[0078] In some embodiments, the data memory cells and the dummy memory cells may have the same structure. The dummy word lines are connected to the dummy memory cells. The drain side selection layers SGD0, SGD1, SGD2, and SGD3 are used to electrically connect and disconnect the NAND string to the bit line. The source side selection layers SGS0, SGS1, SGS2, and SGS3 are used to electrically connect and disconnect the NAND string to the source line SL.

[0079] Figure 4C Also shown is a "joining region". In an embodiment, etching one hundred and twelve word line layers intermixed with dielectric layers is expensive and / or challenging. To alleviate this burden, one embodiment includes laying down a first stack of fifty-six word line layers alternating with dielectric layers, laying down a joining region, and laying down a second stack of fifty-six word line layers alternating with dielectric layers. The joining region is positioned between the first stack and the second stack. The joining region is used to connect the first stack to the second stack.

[0080] exist Figure 4CIn the embodiment, the first stack is labeled as the "lower group of word lines" and the second stack is labeled as the "upper group of word lines". In an embodiment, the bonding region is made of the same material as the word line layer. In one set of exemplary implementations, the plurality of word lines (control lines) include a first stack of alternating word line layers and dielectric layers, a second stack of alternating word line layers and dielectric layers, and a bonding region between the first stack and the second stack, such as Figure 4C Depicted.

[0081] Figure 4D Depicted Figure 4C 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 , 33 , 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 , 47 , 48 , 49 , 50 , 51 , 52 , 53 Figure 4B As described, in an embodiment, local interconnects 436, 438, 440, 442, and 444 divide the conductive layer into four regions / fingers.

[0082] For example, the word line layer WLL110 is divided into regions String0 W110 、String1 W110 、String2 W110 and String3 W110 In one embodiment, four word line fingers on the same level are connected together. In another embodiment, each word line finger operates as a separate word line.

[0083] Likewise, the drain side select gate layer SGD0 (top layer) is divided into regions Strin0 SGD0 、String1 SGD0 、String2 SGD0 and String3 SGD0 , also referred to as fingers or select line fingers. In one embodiment, four select line fingers on the same level are connected together. In another embodiment, each select line finger operates as a separate word line.

[0084] Figure 4E Depicted Figure 4CA cross-sectional view of String1 including a portion of a memory hole 410. In an embodiment, the memory hole (e.g., memory hole 410) is shaped as a cylinder. However, in other embodiments, the memory hole may have other shapes. In an embodiment, the memory hole 410 includes a core layer 480, a channel 482 surrounding the core layer 480, a tunneling dielectric 484 surrounding the channel 482, and a charge trapping layer 486 surrounding the tunneling dielectric 484. In an embodiment, the core layer 480 is a dielectric material (e.g., SiO2), the channel 482 is polysilicon, the tunneling dielectric 484 has an ONO structure, and the charge trapping layer 486 is silicon nitride. Other memory materials and structures may also be used. The technology described herein is not limited to any particular material or structure.

[0085] Figure 4E Dielectric layers DLL121, DLL120, DLL119, DLL118, and DLL117 are depicted, as well as word line layers WLL107, WLL108, WLL109, WLL110, and WLL111. In an embodiment, each of the word line layers includes a word line region 488 surrounded by an aluminum oxide layer 490, which is surrounded by a blocking oxide (SiO2) layer 492. The physical interaction of the word line layers with the memory holes forms a memory cell. Therefore, in an embodiment, the memory cell includes a channel 482, a tunneling dielectric 484, a charge trapping layer 486, a blocking oxide layer 492, an aluminum oxide layer 490, and a word line region 488.

[0086] For example, word line layer WLL111 and a portion of memory hole 410 constitute memory cell MC1. Word line layer WLL110 and a portion of memory hole 410 constitute memory cell MC2. Word line layer WLL109 and a portion of memory hole 410 constitute memory cell MC3. Word line layer WLL108 and a portion of memory hole 410 constitute memory cell MC4. Word line layer WLL107 and a portion of memory hole 410 constitute memory cell MC5. In other architectures, the memory cells may have different structures; however, the memory cells will still be storage cells.

[0087] In an embodiment, when a memory cell is programmed, electrons are stored in a portion of the charge trapping layer 486 associated with the memory cell. In response to an appropriate voltage on the word line region 488, these electrons are attracted from the channel 482 into the charge trapping layer 486 through the tunneling dielectric 484. The threshold voltage of the memory cell increases in proportion to the amount of charge stored.

[0088] In an embodiment, programming the memory cell is achieved by Fowler-Nordheim tunneling of electrons into the charge trapping layer 486. During an erase operation, electrons return to the channel 482 or holes are injected into the charge trapping layer 486 to recombine with the electrons. In an embodiment, erasing is achieved using hole injection into the charge trapping layer 486 via a physical mechanism such as gate induced drain leakage, as described in more detail below.

[0089] Figure 4F is corresponding to FIG. 4A to FIG. 4E Schematic diagram of portion 402 in block 2 of FIG. 4, including bit lines 426, 428, 430, 432, ..., 434 and word lines WLL0 to WLL111. Within the block, each bit line is connected to four NAND strings. Drain side selection lines SGD0, SGD1, SGD2, and SGD3 are used to determine which of the four NAND strings is connected to the associated bit line. Source side selection lines SGS0, SGS1, SGS2, and SGS3 are used to determine which of the four NAND strings is connected to a common source line.

[0090] As described above, portion 402 may be divided into four regions designated as String0, String1, Sting2, and String3. String0 corresponds to those vertical NAND strings controlled by select transistors SGD0 and SGS0, String1 corresponds to those vertical NAND strings controlled by select transistors SGD1 and SGS1, String2 corresponds to those vertical NAND strings controlled by select transistors SGD2 and SGS2, and String3 corresponds to those vertical NAND strings controlled by select transistors SGD3 and SGS3.

[0091] During any given memory operation, a subset of memory cells will be identified as being subject to one or more portions of the memory operation. Those memory cells identified as being subject to the memory operation are referred to as selected memory cells. Those memory cells not identified as being subject to the memory operation are referred to as unselected memory cells. Depending on the memory architecture, memory type, and memory operation, unselected memory cells may be actively or passively excluded from being subject to the memory operation.

[0092] During memory operation, some word lines are referred to as selected word lines because these word lines are connected to selected memory cells. Unselected word lines are not connected to selected memory cells. Similarly, selected word lines are connected to selected memory cells, and unselected bit lines are not connected to selected memory cells.

[0093] Although Figure 3 and 4A to 4FAn exemplary memory system of is a three-dimensional memory structure including vertical NAND strings with charge trapping material, but other (2D and 3D) memory structures may also be used with the techniques described herein.

[0094] The memory system discussed above can be erased, programmed, and read. At the end of a successful programming process (with verification), the threshold voltage of the memory cell should be within one or more distributions of threshold voltages for programmed memory cells or within the distribution of threshold voltages for erased memory cells, as appropriate. Figure 5 Example threshold voltage distributions for a memory array are illustrated when each memory cell stores three bits of data. However, other embodiments may use other data capacities per memory cell (e.g., such as one bit, two bits, four bits, or five bits of data per memory cell).

[0095] Figure 5 Eight threshold voltage distributions corresponding to eight data states are shown. The first threshold voltage distribution (data state) S0 represents an erased memory cell. The other seven threshold voltage distributions (data states) S1 to S7 represent programmed memory cells and are therefore also referred to as programmed states.

[0096] Each threshold voltage distribution (data state) corresponds to a predetermined value for a set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the memory cell depends on the data encoding scheme employed by the cell. In an embodiment, data values ​​are assigned to threshold voltage ranges using a Gray code assignment so that if the threshold voltage of a memory cell is erroneously shifted to its adjacent physical state, only one bit will be affected.

[0097] Figure 5 Seven read reference voltages Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7 are shown for reading data from memory cells. By testing (e.g., performing a sensing operation) whether the threshold voltage of a given memory cell is above or below the seven read reference voltages, the system can determine the data state (S0, S1, S2, S3, ..., S7) that the memory cell is in.

[0098] Figure 5 Also shown are seven verification reference voltages Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7. When programming memory cells to data states S1, S2, S3, S4, S5, S6, and S7, the system will test whether these memory cells have threshold voltages greater than or equal to Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7, respectively.

[0099] In an embodiment referred to as full sequence programming, memory cells can be programmed directly from erased data state S0 to any of programmed states S1 to S7. For example, a population of memory cells to be programmed can be first erased so that all memory cells in the population are in erased data state S0. Then, a programming process is used to program the memory cells directly into data states S1, S2, S3, S4, S5, S6, and / or S7. For example, while some memory cells are being programmed from data state S0 to data state S1, other memory cells are being programmed from data state S0 to data state S2 and / or from data state S0 to data state S3, and so on. Figure 5 The arrows indicate full sequence programming.

[0100] In addition to full sequence programming, the techniques described herein may also be used with other types of programming, including but not limited to multi-level programming / multi-phase programming. In some embodiments, programming states S1 to S7 may overlap, wherein the controller 104 ( Figure 1 ) relies on error correction to identify the correct data being stored.

[0101] Figure 6 is a table that describes an example of assigning data values ​​to data states. Figure 6 In the table, S0=111, S1=110, S2=100, S3=000, S4=010, S5=011, S6=001, and S7=101. Other encodings of data may also be used. The techniques disclosed herein do not require a specific data encoding. In an embodiment, when a block is subjected to an erase operation, all memory cells are moved to data state S0, i.e., the erased state. Figure 6 In some embodiments, when a memory cell is erased (eg, in data state S0), all bits stored in the memory cell are "1".

[0102] 7A to 7E A multi-stage programming method is illustrated. In this embodiment, the programming process includes three stages. Before programming, the memory cells are erased so that all memory cells connected to the common word line are in the erased threshold voltage distribution E, such as Fig. 7A Described in.

[0103] During the first programming phase, those memory cells that are targeted (due to the data to be stored in those memory cells) to data states S4, S5, S6, or S7 are programmed to the intermediate threshold voltage distribution IM. Those memory cells targeted to data states S0, S1, S2, or S3 remain in the erased threshold voltage distribution E. The first phase is Figure 7B Memory cells programmed to the intermediate threshold voltage distribution IM are programmed to the target threshold voltage VvIM.

[0104] During the second programming phase, those memory cells in the erased threshold voltage distribution E are programmed to their target data states. For example, those memory cells to be programmed to data state S3 are programmed to data state S3 from the erased threshold voltage distribution E, those memory cells to be programmed to data state S2 are programmed to data state S2 from the erased threshold voltage distribution E, those memory cells to be programmed to data state S1 are programmed to data state S1 from the erased threshold voltage distribution E, and those memory cells to be in data state S0 are not programmed during the second phase of the programming process. Therefore, the erased threshold voltage distribution E becomes data state S0.

[0105] Moreover, during the second programming phase, those memory cells in the intermediate state threshold voltage distribution IM are programmed to their target data states. For example, those memory cells to be programmed to data state S7 are programmed from the intermediate threshold voltage distribution IM to data state S7, those memory cells to be programmed to data state S6 are programmed from the intermediate threshold voltage distribution IM to data state S6, those memory cells to be programmed to data state S5 are programmed from the intermediate threshold voltage distribution IM to data state S5, and those memory cells to be in data state S4 are programmed from the intermediate threshold voltage distribution IM to data state S4. The second programming phase is Figure 7C Example in.

[0106] like Figure 7C As can be seen in FIG. 1 , at the end of the second programming phase, data states S1 to S7 overlap with adjacent data states. For example, data state S1 overlaps with data state S2, data state S2 overlaps with data states S1 and S3, data state S3 overlaps with data states S2 and S4, data state S4 overlaps with data states S3 and S5, data state S5 overlaps with data states S4 and S6, and data state S6 overlaps with data states S5 and S7. In some embodiments, all or some of the data states do not overlap.

[0107] In the third programming phase, each of the data states S1 to S7 is tightened so that they no longer overlap with adjacent states. Fig.7D The final result of the three-stage programming process is depicted in step 7E, which shows data states S0 to S7. In some embodiments, data state S0 is wider than data states S1 to S7. In an embodiment, data states S0 can be stored in the memory according to the programming state. Figure 6 Encoding table 7A to 7E The data status.

[0108] In some embodiments, those memory cells to be programmed to data state S4 are not programmed during the second phase and therefore remain in the intermediate threshold voltage distribution IM. During the third programming phase, the memory cells are programmed from the intermediate threshold voltage distribution IM to S4. In other embodiments, memory cells designated for other states may also remain in the intermediate threshold voltage distribution IM or the erase threshold voltage distribution E during the second phase.

[0109] A programming operation of a group of memory cells typically involves applying a series of programming voltage pulses to the memory cells after providing the memory cells in an erased state. For example, the programming voltage pulses may be applied to a word line that is connected to the control gates of the memory cells.

[0110] In one approach, incremental step pulse programming (ISPP) is performed where the programming voltage pulse amplitude increases sequentially in step size. A verification operation may be performed after each programming voltage pulse to determine whether the memory cell has been programmed. When programming of a memory cell is complete, the memory cell may be locked out from further programming while programming of other memory cells continues.

[0111] Figure 8 8 is a flow chart describing an embodiment of a process 800 for programming a memory cell. In an exemplary embodiment, the control circuit discussed above is used to program the memory cell in the memory die 106 ( Figure 1 ) is executed on the state machine 216. For example, the process 800 can be performed on the state machine 216 ( Figure 2 ) direction. Process 800 can also be used to implement the full sequence programming discussed above. In addition, process 800 can be used to implement each stage in a multi-stage programming process.

[0112] In step 802 of process 800, the programming voltage (V P ) is initialized to the starting programming voltage V Pinit (eg, between about 12V to about 16V, or some other value), and a program counter PC maintained by state machine 216 is initialized to 1.

[0113] In step 804, the value V P A programming pulse is applied to a selected word line (a word line selected for programming). In an embodiment, a group of memory cells that are programmed simultaneously are all connected to the same word line (a selected word line). If a memory cell is to be programmed, the corresponding bit line coupled to the memory cell is grounded.

[0114] If the memory cell should remain at its current threshold voltage, the corresponding bit line coupled to the memory cell is connected to Vdd to inhibit programming. In an embodiment, the unselected word lines receive one or more boosted voltages (e.g., between about 7V to about 11V, or some other value) to perform a boosting scheme known in the art.

[0115] In step 804, programming pulses are applied to all memory cells connected to the selected word line so that all connected memory cells are programmed simultaneously. That is, they are programmed at the same time or during overlapping times (both are considered simultaneous). In this way, all memory cells connected to the selected word line will have their threshold voltage changed simultaneously unless they have been locked out from being programmed.

[0116] In step 806, the memory cells are verified using a set of appropriate verify reference voltages to perform one or more verify operations. In an embodiment, the verify process is performed by testing whether the threshold voltage of the memory cells selected for programming has reached the appropriate verify reference voltages.

[0117] In step 808, the memory system counts the number of memory cells that have not reached their corresponding target threshold voltage distribution. That is, the system counts the number of memory cells that have failed the verification process so far. This count can be generated by the state machine 216 ( Figure 2 )、Controller 104( Figure 1 ) or other logical components to complete. In the remaining discussion, the term "controller device" may be Figure 1 The controller 104, Figure 2 The control circuit 204, Figure 2 One or more of the state machine 216 or other similar controller devices.

[0118] In an embodiment, the sensing block 212 ( Figure 2 ) will store the state (pass / fail) of its corresponding memory cell. In an embodiment, one total count reflects the total number of memory cells currently being programmed that have failed the last verification step. In another embodiment, a separate count is kept for each data state.

[0119] In step 810, it is determined whether the count from step 808 is less than or equal to a predetermined limit. In an embodiment, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during a read process of a page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, the programming process can stop and report a "pass" status in step 812. In this case, enough memory cells are programmed correctly so that the remaining few memory cells that have not been fully programmed can be corrected using ECC during the read process.

[0120] In some embodiments, the predetermined limit used in step 810 is lower than the number of bits that can be corrected by an error correction code (ECC) during the read process to allow for future / additional errors. When programming less than all of the memory cells of a page, or comparing counts of only one data state (or less than all of the states), the predetermined limit can be a fraction (proportional or not) of the number of bits that can be corrected by the ECC during the read process of the page of memory cells. In some embodiments, the limit is not predetermined. Instead, the limit changes based on the number of errors that have been counted for the page, the number of program-erase cycles performed, or other criteria.

[0121] If the number of failed memory cells is not less than the predetermined limit, the programming process continues at step 814 and checks the program counter PC against a program limit value (PLV). Examples of program limit values ​​include 6, 12, 16, 20, and 30, although other values ​​may be used. If the program counter PC is greater than or equal to the program limit value PLV, the programming process is considered to have failed and a "failed" status is reported in step 816.

[0122] If the program counter PC is not greater than or equal to the program limit value PLV, the process continues at step 820, during which the program counter PC is incremented by 1 and the program voltage V P is stepped to the next magnitude. For example, the next programming pulse will have a programming step size ΔV greater than the previous pulse. P The program pulse is then applied to the selected word line in order to perform another iteration of the programming process 800 (steps 804 to 818). Each pass through steps 804 to 818 is referred to herein as a "programming loop."

[0123] Generally, during verify operations and read operations, a selected word line is connected to a voltage (an example of a reference signal) whose level is determined for each read operation (eg, Figure 5of read comparison levels Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7) or a verification operation (e.g., Figure 5 The verification target levels Vv1, Vv2, Vv3, Vv4, Vv5, Vv6 and Vv7 of the memory cells are specified in order to determine whether the threshold voltage of the selected memory cells has reached this level.

[0124] In an embodiment, after applying an appropriate read or verify voltage to a selected word line, the conduction current of the memory cell is measured to determine whether the memory cell is turned on (conducting current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the threshold voltage of the memory cell.

[0125] If the conduction current is measured to be no greater than a certain value, the memory cell is not turned on, and the voltage applied to the word line is no greater than the threshold voltage of the memory cell. During a read or verify process, unselected memory cells are provided with one or more read pass voltages (also referred to as bypass voltages) at their control gates so that these memory cells will operate as pass gates (e.g., conduct current regardless of whether these memory cells are being programmed or erased).

[0126] There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured at the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or does not allow) the NAND string including the memory cell to discharge the corresponding bit line. The voltage on the bit line is measured after a period of time to see if the bit line has been discharged. It should be noted that the techniques described herein can be used with different methods known in the art for verification / reading. Other reading and verification techniques known in the art can also be used.

[0127] As described above, at step 804, a programming pulse is applied to the selected word line, and at step 806, a set of appropriate verification reference voltages are used to verify the memory cells coupled to the selected word line to perform one or more verification operations. Steps 804 and 806 are part of an iterative loop in which the programming pulses are applied as a series of programming pulses of increasing magnitude, with verification reference pulses inserted between consecutive programming pulses. Such an iterative loop is referred to herein as a "program-verify iteration".

[0128] Fig. 9 An example of such a program-verify pulse applied to a selected word line is shown. In particular, Fig. 9 Depicted in Figure 8Programming pulses 900, 902, and 904 are applied to the selected word line during three consecutive iterations of step 804. Between programming pulses 900, 902, and 904, Figure 8 During three consecutive program-verify iterations of steps 804 to 806, a verify pulse is applied to the selected word line to determine whether the threshold voltage of the memory cell is greater than a corresponding verify reference voltage.

[0129] As described above, in an embodiment, a population of memory cells to be programmed is first erased so that all memory cells in the population are in an erased data state (e.g., Figure 5 In state S0 or Fig. 7A When a programmed memory cell is subsequently selected for reprogramming, the memory cell is erased again before programming.

[0130] Each programming and erasing iteration of a memory cell or group of memory cells is referred to herein as a "program-erase cycle," and the number of program-erase cycles performed on a memory cell or group of memory cells is referred to herein as a "program-erase cycle count," or "PEC." In an embodiment, a controller device maintains a memory structure (e.g., Figure 2 A record of program-erase cycle counts for each memory cell or group of memory cells of the memory structure 202 of A.

[0131] An erase operation of memory cells in a block typically involves one or more "erase-verify iterations," also referred to as "erase-verify cycles," where each iteration involves channel boosting followed by an erase verify test until the erase operation is complete.

[0132] In an embodiment of an erase-verify cycle, the voltage of the channel is boosted while the voltage of the word line is maintained at a low level (e.g., at or close to 0V). In an embodiment, the channel is boosted by applying one or more erase pulses to the block. In one technique, one or more erase pulses are applied to the select transistor to generate a GIDL current, thereby boosting the NAND string channel. This technique is referred to herein as "GIDL erase".

[0133] In an embodiment, an erase pulse is applied to a select transistor of a NAND string to provide a drain-to-gate voltage (referred to herein as a GIDL voltage or GV) of sufficiently high magnitude such that the select transistor generates a GIDL current. The GIDL current is a result of carrier generation (e.g., electron-hole pair generation) due to band-to-band tunneling and / or trap-assisted generation.

[0134] The GIDL current may be generated at either end of the NAND string. The drain-side GIDL current may be generated by applying one or more erase pulses to provide a drain-side GIDL voltage GV between the drain terminal and the gate terminal of the drain-side select transistor connected to the bit line. D The source-side GIDL current may be generated by applying one or more erase pulses to provide a source-side GIDL voltage GV between the drain terminal and the gate terminal of the source-side select transistor connected to the source line. S .

[0135] GIDL erase based on GIDL current generated at only one end (eg, drain side or source side) of a NAND string is called single-sided GIDL erase. GIDL erase based on GIDL current generated at both ends of a NAND string is called double-sided GIDL erase.

[0136] In an embodiment, the GIDL current can cause one type of carrier (eg, holes) to move primarily into the NAND channel and thereby increase the potential of the channel (boosting). At the same time, another type of carrier (eg, electrons) is extracted from the channel by the electric field.

[0137] For example, electrons can be extracted in the direction of the bit line or in the direction of the source line. Boosting of the channel creates a large channel-to-gate voltage that drives holes into the charge-trapping layer, thereby lowering the threshold voltage of each memory cell.

[0138] Therefore, in an embodiment, one or more erase pulses are applied to provide a drain side GIDL voltage GV to the drain side select transistor. D and / or applying one or more erase pulses to provide a source side GIDL voltage GV to the source side select transistor S .

[0139] In an embodiment, each erase pulse includes a first erase pulse and a corresponding second erase pulse. In an embodiment, a GIDL erase operation includes applying a first erase pulse (referred to herein as a "drain erase pulse") to the drain terminal of a select transistor while applying a corresponding second erase pulse (referred to herein as a "gate erase pulse") to the gate terminal of the select transistor. In an embodiment, the drain erase pulse and the corresponding gate erase pulse provide a GIDL voltage GV to the select transistor.

[0140] In an embodiment, one or more first drain erase pulses (each having a magnitude of Verase) are applied to the drain terminal of the drain side select transistor, while one or more corresponding first gate erase pulses (each having a magnitude of Vsgd) are applied to the gate terminal of the drain side select transistor. In an embodiment, each first drain erase pulse and the corresponding first gate erase pulse provide a drain side GIDL voltage GV to the drain side select transistor. D In this embodiment, the drain side GIDL voltage is:

[0141] GV D =(Verase-Vsgd) (1)

[0142] Additionally or alternatively, one or more second drain erase pulses (each second drain erase pulse having a magnitude Verase) are applied to the drain terminal of the source side select transistor, while one or more corresponding second gate erase pulses (each second gate erase pulse having a magnitude Vsgs) are applied to the gate terminal of the source side select transistor. In an embodiment, each second drain erase pulse and the corresponding second gate erase pulse provide a source side GIDL voltage GV to the source side select transistor. S In this embodiment, the source side GIDL voltage is:

[0143] GV S =(Verase-Vsgs) (2)

[0144] In an embodiment, Verase may have a value of about 15V to about 25V, Vsgd may have a value of about 5V to about 15V, Vsgs may have a value of about 5V to about 15V, and the drain side GIDL voltage GV D may have a value of about 0V to about 20V, and the source side GIDL voltage GV S It may have a value of about 0 V to about 20 V, although other values ​​may be used.

[0145] From equations (1) and (2) above, it can be seen that if Verase has a fixed value, the drain side GIDL voltage GV D and source side GIDL voltage GV S This can be increased or decreased by respectively decreasing or increasing the gate erase pulse magnitudes Vsgd and Vsgs.

[0146] Conventionally, Verase, Vsgd, and Vsgs have fixed values ​​(and thus the drain-side GIDL voltage GV D and source side GIDL voltage GV Shas a fixed value), which may be determined based on simulation data or based on empirical data obtained from sampling of actual memory dies, or based on a combination of these two techniques.

[0147] An erase verification test as a sensing operation may be performed after applying each erase pulse to determine whether the threshold voltage of each memory cell has been reduced to below the erase verification voltage. If the threshold voltage of the memory cell is below the erase verification voltage, the memory cell passes the erase verification test. If the threshold voltage of the memory cell is not below the erase verification voltage, the memory cell fails the erase verification test.

[0148] In an embodiment, when less than a threshold number of memory cells in a block fail the erase verify test, the erase operation for the block is complete. As used herein, the threshold number is also referred to as the "fail bit threshold number". The fail bit threshold number is sometimes referred to as a "bit scan pass / fail" or "BSPF" value.

[0149] In an embodiment, the fail bit threshold number BSPF is the number of bits that can be corrected by an error correction code (ECC) during a read process of a page of memory cells. In other embodiments, other criteria may be used to specify the fail bit threshold number BSPF. In an embodiment, the fail bit threshold number BSPF has a fixed value. For example, the fail bit threshold number BSPF=25 or some other value.

[0150] In an embodiment, the erase operation for a block must be within the maximum number of erase-verify cycles (EV M ) within 10 seconds. For example, the maximum number of erase-verify cycles EV M Can be 6 or some other value. If the maximum number of erase-verify cycles EV M If more than the fail bit threshold number BSPF of memory cells in a block fail the erase verify test, a block erase failure occurs. For example, if the fail bit threshold number BSPF = 25 and the maximum number of erase-verify cycles EV M =6, then within 6 erase-verify cycles, if more than 25 memory cells in a block fail the erase-verify test, a block erase failure may occur.

[0151] Fig.10 1 is a flow chart describing an embodiment of a process 1000 for erasing a population of memory cells (eg, an erase block of memory cells). In an exemplary embodiment, the control circuit discussed above is used to perform a Figure 1 ) is executed on the state machine 216. For example, the process 1000 may be executed on the state machine 216 ( Figure 2 ) direction.

[0152] In an embodiment, state machine 216 maintains an erase-verify cycle counter EVL as a block for memory cells in process 1000. In step 1002 of process 1000, an erase-verify cycle counter EVL is initialized to one.

[0153] At step 1004, erase pulses are applied to the memory cells of the erase block. In an embodiment, each erase pulse may include providing a drain-side GIDL voltage GV to the drain-side select transistors of each NAND string in the erase block. D The first drain erase pulse and the corresponding first gate erase pulse may include providing a source side GIDL voltage GV to the source side select transistor of each NAND string in the erase block. S A second drain erase pulse and a corresponding second gate erase pulse are provided.

[0154] At step 1006, an erase verify test is performed on the memory cells of the erase block, such as described above.

[0155] At step 1008, the memory system counts the number of memory cells in the erase block that have not passed the erase verification test. That is, the system counts the number of memory cells in the erase block that have a threshold voltage that is not less than the erase verification voltage. This count can be performed by the state machine 216 ( Figure 2 )、Controller 104( Figure 1 ) or other logical components to complete.

[0156] At step 1010, it is determined whether the count from step 1008 is less than or equal to the fail bit threshold number BSPF. If it is determined at step 1010 that the count at step 1008 is less than or equal to the fail bit threshold number BSPF, then at step 1012 the erase process 1000 is deemed to have passed.

[0157] In contrast, if it is determined at step 1010 that the count at step 1008 is not less than or equal to the fail bit threshold number BSPF, then at step 1014 the erase-verify cycle counter EVL is incremented by one.

[0158] At step 1016, it is determined whether the erase-verify cycle counter EVL is greater than the maximum number of erase-verify cycles EV M If the erase-verify cycle counter EVL is greater than the maximum number of erase-verify cycles EV M , then at step 1018, the erase process 1000 is deemed to have failed. In other words, the maximum number of erase-verify cycles EV M If more than a threshold number of failed bits BSPF of memory cells in an erase block fail the erase verify test, the erase is deemed to have failed.

[0159] On the contrary, if it is determined that the erase-verify cycle counter EVL is less than or equal to the maximum number of erase-verify cycles EV M , then process 1000 loops back to step 1004 and another erase pulse is applied to the memory cells of the erase block.

[0160] Therefore, each pass through step 1004 to step 1010 is an example of an erase-verify cycle. The loop of step 1004 to step 1016 is repeated until the number of memory cells in the erase block that have not passed the erase verify test is less than or equal to the fail bit threshold number BSPF (whereby the erase operation passes), or the erase-verify cycle counter EVL is greater than the maximum number EV of erase-verify cycles. M (Thus the erase operation failed).

[0161] In process 1000 , if at step 1010 it is determined that the count at step 1008 is less than or equal to the fail bit threshold number BSPF, then the value of the erase-verify cycle counter EVL is the number of erase-verify cycles required for the erase block to pass the erase verify test at step 1006 .

[0162] An indication of the time required to complete an erase operation of a memory cell is referred to herein as an erase speed, and is described in terms of the number of erase-verify cycles required for a memory cell to pass an erase verify test. For example, a first memory cell may pass an erase verify test in 2 erase-verify cycles, and a second memory cell may pass an erase verify test in 6 erase-verify cycles. In this case, the second memory cell may be considered to have a slower erase speed than the first memory cell because the second memory cell requires more erase-verify cycles to pass the erase verify test.

[0163] The erase speed tends to slow down with increasing program-erase cycle counts. In other words, as the memory cell is subjected to increasing program-erase cycle counts, the memory cell requires more erase-verify cycles to pass the erase verify test.

[0164] Without wishing to be bound by any particular theory, we believe that this erase slowdown is due to the formation of physical traps in the oxide layer of the memory cell, and that this trap formation increases with increasing program-erase cycle counts.

[0165] Additionally, without wishing to be bound by any particular theory, we believe that this erase slowdown is also a result of decreasing GIDL current efficiency with increasing program-erase cycle counts. In particular, without wishing to be bound by any particular theory, we believe that for a fixed GIDL voltage GV, as the program-erase cycle count increases, the GIDL current decreases, the channel boosting decreases, and the corresponding threshold voltage reduction decreases.

[0166] However, as a result of process variations, memory cells within the same erase block experience different degrees of erase slowdown. Therefore, as the program-erase cycle count increases, the erase speed can vary from memory cell to memory cell within the erase block. For illustration, Fig.11 Depicted is an example erased threshold voltage distribution for a population of memory cells that have been erased using N erase-verify cycles.For example, if N=2, then each memory cell receives N=2 erase pulses.

[0167] Curve 1100 depicts an example erased threshold voltage distribution for a population of "fresh" (ie, before any program-erase cycle count) memory cells. Curve 1100 has a single bell-shaped curve portion centered at the first erased threshold voltage Vde1 and encompassing substantially all memory cells.

[0168] In contrast, curve 1102 depicts an example erased threshold voltage distribution for a population of the same memory cells after M program-erase cycle counts (e.g., M=100k program-erase cycle counts). Curve 1102 includes a first bell-shaped curve portion 1102a centered at a second erased threshold voltage Vde2 and a second bell-shaped curve portion 1102b centered at a third erased threshold voltage Vde3. The first bell-shaped curve portion 1102a and the second bell-shaped curve portion 1102b together cover substantially all memory cells.

[0169] Fig.11 Two separate phenomena are illustrated. First, after M=100k program-erase cycle counts, substantially all memory cells erase more slowly than when fresh. In particular, after the same number of erase-verify cycles (e.g., N=2), the threshold voltages of the memory cells after M=100k program-erase cycle counts are all higher than the threshold voltages of the memory cells when fresh. Thus, all memory cells have experienced an erase slowdown compared to their behavior when fresh.

[0170] Second, the memory cells experience different degrees of erase slowdown. In particular, the first bell-shaped curve portion 1102a corresponds to a first subgroup of memory cells, and the second bell-shaped curve portion 1102b corresponds to a second subgroup of memory cells. The second subgroup of memory cells has experienced a greater amount of erase slowdown than the first subgroup of memory cells, as evidenced by the threshold voltage distribution of the second subgroup of memory cells being higher than the threshold voltage distribution of the first subgroup of memory cells.

[0171] As a result of the slowed erase, additional (e.g., >N) erase-verify cycles will be required to lower the threshold voltage of the memory cells to near the first erase threshold voltage Vde1. However, simply applying additional erase pulses may introduce other problems. In particular, lowering the threshold voltage of the second subgroup of memory cells to near the first erase threshold voltage Vde1 may require so many additional erase pulses that the first subgroup of memory cells becomes over-erased.

[0172] That is, the threshold voltage of the first subgroup of memory cells will be shifted much lower than the first erase threshold voltage Vde1. This over-erasure can then affect subsequent programming, thereby increasing the number of programming pulses required to program the over-erased memory cells. Over-erasure can also reduce data retention and increase neighboring word line interference for the first subgroup of memory cells.

[0173] exist Fig.10 In the example process 1000, an erase pulse is applied at step 1004 to reduce the drain side GIDL voltage GV D Provided to the drain-side select transistor of each NAND string in the erase block and / or the source-side GIDL voltage GV S A source side select transistor is provided to each NAND string in an erase block.

[0174] As described above, conventionally, Verase, Vsgd, and Vsgs have fixed values ​​(and thus the drain-side GIDL voltage GV D and source side GIDL voltage GV S has a fixed value), which may be determined based on simulation data or based on empirical data obtained from sampling of actual memory dies, or based on a combination of these two techniques.

[0175] For a fresh memory cell, the drain side GIDL voltage GV D and source side GIDL voltage GV S Using a fixed value is not a problem because most memory cells erase at a uniform rate and the threshold is usually satisfied in one or two erase-verify cycles. However, the drain-side GIDL voltage GV D and source side GIDL voltage GV S Using a fixed value may become problematic due to the slowing down of erase speed that occurs with increasing program-erase cycle counts.

[0176] In particular, as described above, as the program-erase cycle count increases, the GIDL current efficiency decreases for a fixed GIDL voltage, which in turn reduces the amount of threshold voltage reduction per erase pulse. Therefore, without wishing to be bound by any particular theory, we believe that as the program-erase cycle count increases, the drain-side GIDL voltage GVD and source side GIDL voltage GV S Using a fixed value results in a smaller threshold voltage drop per erase pulse, thus requiring more erase pulses at higher program-erase cycle counts.

[0177] In particular, as described above, the threshold voltage of the memory cell being erased decreases at a slower rate with increasing program-erase cycle counts. Therefore, for a given number of erase-verify cycles in process 1000, a higher number of memory cells will fail the erase-verify test at step 1006. This in turn will result in the need for additional erase-verify cycles to reduce the threshold voltage of the memory cells. As described above, subjecting all memory cells in an erase block to additional erase-verify cycles results in over-erasure of some memory cells in the erase block.

[0178] Techniques are described for adaptively increasing the GIDL voltage to compensate for the decrease in GIDL current efficiency that occurs with increasing program-erase cycle counts.

[0179] To simplify the remaining discussion, the term “adaptive GIDL voltage GV a ” will be used to describe the adaptive drain side GIDL voltage GV D and / or adaptive source side GIDL voltage GV S One of ordinary skill in the art will appreciate that the techniques described below can be applied to both single-sided and double-sided GIDL erase techniques.

[0180] Fig.12A1 1 is a flow chart describing an embodiment of a process 1200a for erasing a group of memory cells (e.g., an erase block of memory cells). In an exemplary embodiment, the control circuit discussed above is used to perform a Figure 1 ) is executed on the state machine 216. For example, the process 1200a can be executed on the state machine 216 ( Figure 2 ) direction.

[0181] In step 1202 of process 1200a, an erase-verify cycle counter EVL maintained by state machine 216 is initialized to 1.

[0182] At step 1204, the program-erase cycle count of the erase block is determined. For example, as described above in an embodiment, the controller device maintains a program-erase cycle count for the memory structure (e.g., Figure 2 A memory structure 202 of A) contains a record of program-erase cycle counts for each memory cell or group of memory cells. In an embodiment, at step 1204, the program-erase cycle counts for the erase block can be determined from this record.

[0183] At step 1206, the adaptive GIDL voltage GV a Determined based on the program-erase cycle count determined at step 1204. For example, Fig.12A2 Depicts the program-erase cycle count value and the corresponding adaptive GIDL voltage GV a As described below, the adaptive GIDL voltage GV a The value is adaptively increased based on the program-erase cycle count value.

[0184] In the illustrated example, the adaptive GIDL voltage GV a The value of GV is adaptively increased in a step-wise manner based on the program-erase cycle count value. In particular, for a program-erase cycle count in a first value range between 1 and 9999, the corresponding adaptive GIDL voltage GV a is equal to the initial GIDL voltage GV0 (eg, 7.6 V). The initial GIDL voltage GV0 may be determined based on simulation data or based on empirical data obtained from sampling of actual memory dies or based on a combination of both techniques.

[0185] For a program-erase cycle count in a second value range greater than the first value range between 10000 and 19999, the corresponding adaptive GIDL voltage GV a =GV0+Δ, where Δ is an offset value (eg, Δ=0.2V or some other value). For program-erase cycle counts in a third value range greater than the second value range between 20,000 and 29,999, the corresponding adaptive GIDL voltage GV a = equal to the initial GIDL voltage GV0 + 2xΔ. For a program-erase cycle count in a fourth value range greater than the third value range between 30000 and 39999, the corresponding adaptive GIDL voltage GV a Equal to the initial GIDL voltage GV0+3xΔ, and so on.

[0186] At this point, as the program-erase cycle count increases, the corresponding adaptive GIDL voltage GV a Without wishing to be bound by any particular theory, we believe that as the program-erase cycle count increases, the adaptive GIDL voltage GV increases. a The decrease in GIDL current efficiency that occurs with increasing program-erase cycle counts can be compensated. Without wishing to be bound by any particular theory, we believe that increasing the adaptive GIDL voltage GV with increasing program-erase cycle counts a A more uniform threshold voltage reduction per erase pulse may be provided independent of program-erase cycle count.

[0187] Therefore, a lower GIDL voltage GV can be used to reduce the program-erase cycle count, and as the program-erase cycle count increases, a higher GIDL voltage GV can be used. Without wishing to be bound by any particular theory, we believe that using an adaptive GIDL voltage GV that varies based on the program-erase cycle count a The number of erase failures can be reduced and over-erasure of memory cells can be reduced.

[0188] As mentioned above, if Verase has a fixed value, the drain side GIDL voltage GV D and source side GIDL voltage GV S This can be increased or decreased by respectively decreasing or increasing the gate erase pulse magnitudes Vsgd and Vsgs.

[0189] Those skilled in the art will appreciate that the program-erase cycle count step breakpoint value may be different from Fig.12A2 , and more or fewer stepwise breakpoint values ​​may be used. In addition, a person skilled in the art will understand that the offset value Δ may be a fixed value or a variable value. In addition, a person skilled in the art will understand that the adaptive GIDL voltage GV a It can be determined in other ways based on the program-erase cycle count. For example, the adaptive GIDL voltage GV a It may be determined from a linear or non-linear equation based on program-erase cycle count, or by some other technique.

[0190] Reference again Fig.12A1 At step 1208, the adaptive GIDL voltage GV determined at step 1206 is used. a The erase pulses are applied to the memory cells of the erase block. In an embodiment, each erase pulse may include providing a drain-side GIDL voltage GV to the drain-side select transistor of each NAND string in the erase block. D The first drain erase pulse and the corresponding first gate erase pulse may include providing a source side GIDL voltage GV to the source side select transistor of each NAND string in the erase block. S A second drain erase pulse and a corresponding second gate erase pulse are provided.

[0191] At step 1210, an erase verify test is performed on the memory cells of the erase block, such as described above. At step 1212, the memory system counts the number of memory cells in the erase block that have not passed the erase verify test. That is, the system counts the number of memory cells in the erase block that have a threshold voltage that is not less than the erase verify voltage. This count may be performed by the state machine 216 ( Figure 2 )、Controller 104( Figure 1) or other logical components to complete.

[0192] At step 1214, it is determined whether the count from step 1212 is less than or equal to the fail bit threshold number BSPF. If it is determined at step 1214 that the count at step 1212 is less than or equal to the fail bit threshold number BSPF, then at step 1216 the erase process 1200a is deemed to have passed.

[0193] In contrast, if it is determined at step 1214 that the count at step 1212 is not less than or equal to the fail bit threshold number BSPF, then at step 1218 , the erase-verify cycle counter EVL is incremented by one.

[0194] At step 1220, it is determined whether the erase-verify cycle counter EVL is greater than the maximum number of erase-verify cycles EV M If the erase-verify cycle counter EVL is greater than the maximum number of erase-verify cycles EV M , then at step 1222, the erase process 1200a is deemed to have failed. In other words, the maximum number of erase-verify cycles EV M If more than a threshold number of failed bits BSPF of memory cells in an erase block fail the erase verify test, the erase is deemed to have failed.

[0195] On the contrary, if it is determined at step 1220 that the erase-verify cycle counter EVL is not greater than the maximum number EV of erase-verify cycles, M , the process 1200a loops back to step 1208 and based on the adaptive GIDL voltage GV determined at step 1206 a Another erase pulse is applied to the memory cells of the erase block.

[0196] The loop of step 1208 to step 1220 is repeated until the number of memory cells in the erase block that have not passed the erase verification test is less than or equal to the fail bit threshold number BSPF (whereby the erase operation passes), or the erase-verify cycle counter EVL is greater than the maximum number EV of erase-verify cycles. M (Thus the erase operation failed).

[0197] Without wishing to be bound by any particular theory, we believe that using an adaptive GIDL voltage GV that varies based on the program-erase cycle count a (such as described above and FIG. 12A1 to FIG. 12A2 ) will occur fewer block erase failures and memory system performance will improve.

[0198] exist Fig.12A1 In the example process 1200a, the adaptive GIDL voltage GV aThe value of is determined directly based on the program-erase cycle count. Alternatively, the adaptive GIDL voltage GV a The value of can be determined by other criteria that are indirectly related to the program-erase cycle count.

[0199] For example, substantially all memory cells in an erase block may pass the erase verification test in K erase-verify cycles (e.g., K=2). However, as described above, additional erase-verify cycles (i.e., >K) are typically required to lower the threshold voltage of the memory cells as the program-erase cycle count increases. Therefore, in another embodiment, when the number of erase-verify cycles required to lower the threshold voltage of the memory cells in the erase block is greater than K, the adaptive GIDL voltage GV a The value of can be adjusted. Two example processes for implementing this embodiment are described below. In the following examples, the variable K is also referred to as the "erase cycle upper limit K".

[0200] Fig. 12B 1 is a flow chart describing an embodiment of a process 1200b for erasing a group of memory cells (e.g., an erase block of memory cells). In an exemplary embodiment, the control circuit discussed above is used to perform a Figure 1 ) is executed on the state machine 216. For example, the process 1200b can be executed on the state machine 216 ( Figure 2 ) direction.

[0201] In an embodiment, process 1200b is implemented each time an erase block is erased. As described in more detail below, each time an erase block is successfully erased, two values ​​are saved (e.g., in state machine 216): the current value of the erase cycle upper limit K and the adaptive GIDL voltage GV a For example, the current value of the erase cycle upper limit K can be saved as the “previous erase cycle upper limit Kp”, and the adaptive GIDL voltage GV a The current value of the adaptive GIDL voltage GV p ”.

[0202] In an embodiment, before the process 1200b is implemented on the erase block for the first time, the value of the previous erase cycle upper limit Kp is initialized to a predetermined value (e.g., Kp=2). A person of ordinary skill in the art will understand that the value of the previous erase cycle upper limit Kp can be initialized to a value greater than or less than 2. In an embodiment, before the process 1200b is implemented on the erase block for the first time, the previous adaptive GIDL voltage GV p The value of is set to the initial GIDL voltage GV0. For example, GV0 = 7.6V or some other value.

[0203] In step 1224b of process 1200b, the erase-verify cycle counter EVL maintained by state machine 216 is initialized to 1. In addition, the erase cycle upper limit K is initialized to the value of the previous erase cycle upper limit Kp. Therefore, in the above example, the erase cycle upper limit K is initialized to K=2.

[0204] At step 1226, the adaptive GIDL voltage GV a Initialized to the previous adaptive GIDL voltage GV p When the process 1200b is first implemented on an erase block, the adaptive GIDL voltage GV a is initialized to the initial GIDL voltage GV0. For example, GV a =GV0=7.6V.

[0205] At step 1208, the adaptive GIDL voltage GV specified at step 1226 is used. a The erase pulses are applied to the memory cells of the erase block. In an embodiment, each erase pulse may include providing a drain-side GIDL voltage GV to the drain-side select transistor of each NAND string in the erase block. D The first drain erase pulse and the corresponding first gate erase pulse may include providing a source side GIDL voltage GV to the source side select transistor of each NAND string in the erase block. S A second drain erase pulse and a corresponding second gate erase pulse are provided.

[0206] At step 1210, an erase verify test is performed on the memory cells of the erase block, such as described above. At step 1212, the memory system counts the number of memory cells in the erase block that have not passed the erase verify test. That is, the system counts the number of memory cells in the erase block that have a threshold voltage that is not less than the erase verify voltage. This count may be performed by the state machine 216 ( Figure 2 )、Controller 104( Figure 1 ) or other logical components to complete.

[0207] At step 1214, it is determined whether the count from step 1212 is less than or equal to the fail bit threshold number BSPF. If it is determined at step 1214 that the count at step 1212 is less than or equal to the fail bit threshold number BSPF, then at step 1228b, the current value of the erase cycle upper limit K is saved as the value of the previous erase cycle upper limit Kp, and the adaptive GIDL voltage GV is set to 0. a The current value of the adaptive GIDL voltage GV is saved as the previous p At step 1216, the erase process 1200b is deemed to have passed.

[0208] In contrast, if it is determined at step 1214 that the count at step 1212 is not less than or equal to the fail bit threshold number BSPF, then at step 1218 the erase-verify cycle counter EVL is incremented by one.

[0209] At step 1230, it is determined whether the erase-verify cycle counter EVL is greater than the erase cycle upper limit K. If the erase-verify cycle counter EVL is not greater than the erase cycle upper limit K, then at step 1220, it is determined whether the erase-verify cycle counter EVL is greater than the maximum number of erase-verify cycles EVL. M If the erase-verify cycle counter EVL is greater than the maximum number of erase-verify cycles EV M , then at step 1222, the erase process 1200b is deemed to have failed. In other words, the maximum number of erase-verify cycles EV M If more than a threshold number of failed bits BSPF of memory cells in an erase block fail the erase verify test, the erase is deemed to have failed.

[0210] On the contrary, if it is determined at step 1220 that the erase-verify cycle counter EVL is not greater than the maximum number EV of erase-verify cycles, M , the process 1200a loops back to step 1208 and another erase pulse is applied to the memory cells of the erase block.

[0211] The loop of step 1208 to step 1220 is repeated until the number of memory cells in the erase block that have not passed the erase verification test is less than or equal to the fail bit threshold number BSPF (whereby the erase operation passes), or the erase-verify cycle counter EVL is greater than the maximum number EV of erase-verify cycles. M (Thus the erase operation failed).

[0212] If it is determined at step 1230 that the erase-verify cycle counter EVL is greater than the erase cycle upper limit K, then the adaptive GIDL voltage GV a is set equal to the adaptive GIDL voltage GV a =The current value of +Δ, where Δ is an offset value (eg, Δ=0.2V or some other value). In this regard, when the erase-verify cycle counter EVL is greater than the erase cycle upper limit K, the corresponding adaptive GIDL voltage GV a Increase.

[0213] Without wishing to be bound by any particular theory, we believe that increasing the adaptive GIDL voltage GV as the erase-verify cycle count increases aThe decrease in GIDL current efficiency that occurs with increasing program-erase cycle counts can be compensated. Without wishing to be bound by any particular theory, we believe that increasing the adaptive GIDL voltage GV with increasing erase-verify cycle counts a A more uniform threshold voltage reduction per erase pulse may be provided independent of program-erase cycle count.

[0214] Therefore, a lower GIDL voltage GV can be used to reduce the erase-verify cycle count, and as the program-erase cycle count increases, a higher GIDL voltage GV can be used. Without wishing to be bound by any particular theory, we believe that using an adaptive GIDL voltage GV that varies based on the erase-verify cycle count a (As mentioned above and in Fig. 12B ) can reduce the number of erase failures and reduce over-erasure of memory cells.

[0215] At step 1234 , the erase cycle upper limit K is incremented by a constant, such as 1. One of ordinary skill in the art will appreciate that at step 1234 , the erase cycle upper limit K may be incremented by a constant greater than 1.

[0216] Therefore, instead of increasing the adaptive GIDL voltage GV based only on the program-erase cycle count, a , when the number of erase-verify cycles begins to increase, process 1200b increases the adaptive GIDL voltage GV a In this regard, process 1200b can account for die-to-die variations in the amount of erase speed slowdown that occurs with increasing program-erase cycle counts.

[0217] For example, the first memory die may first exceed the erase cycle cap K=2 starting from 10,000 program-erase cycles, while the second memory die may first exceed the erase cycle cap K=2 starting from 50,000 program-erase cycles. The process 1200b thus allows the adaptive GIDL voltage GV to be increased based on the actual behavior of the memory die rather than just based on the number of program-erase cycles. a .

[0218] Without wishing to be bound by any particular theory, we believe that using an adaptive GIDL voltage GV that varies based on an erase-verify cycle counter EVL exceeding an erase cycle upper limit K a The number of erase failures can be reduced and over-erasure of memory cells can be reduced.

[0219] The process 1200b then continues to step 1220 and determines whether the erase-verify cycle counter EVL is greater than the maximum number of erase-verify cycles EVL. MThe loop of step 1208 to step 1220 is repeated until the number of memory cells in the erase block that have not passed the erase verification test is less than or equal to the fail bit threshold number BSPF (whereby the erase operation passes), or the erase-verify cycle counter EVL is greater than the maximum number of erase-verify cycles EV M (Thus the erase operation failed).

[0220] When the process 1200b is implemented next time in the same erase block, the erase cycle upper limit K and the adaptive GIDL voltage GV a The variables Kp and GV are initialized at steps 1224b and 1226, respectively, to the values ​​of the variables from the previous instance of process 1200b implemented on the same erase block and saved at step 1228b as the previous values ​​of the erase cycle cap Kp and the adaptive GIDL voltage GV p The previous value of .

[0221] In process 1200b, each time the erase-verify cycle counter EVL exceeds the value of the erase cycle upper limit K, the value of the erase cycle upper limit K is incremented by 1 at step 1234. Without wishing to be bound by any particular theory, we believe that this will allow the value of the erase cycle upper limit K to gradually increase as the erase speed of the erase block begins to decrease.

[0222] Alternatively, instead of allowing the value of the erase cycle upper limit K to gradually increase as the erase speed of the erase block begins to decrease, the value of the erase cycle upper limit K may be fixed to a desired value (eg, K=2). Fig. 12C Such embodiments are described.

[0223] Specifically, Fig. 12C 12 is a flow chart of a process 1200c for erasing a group of memory cells (eg, an erase block of memory cells). In an exemplary embodiment, the control circuit discussed above is used to perform a Figure 1 ) is executed on the state machine 216. For example, the process 1200c can be executed on the state machine 216 ( Figure 2 ) direction.

[0224] In an embodiment, process 1200c is implemented each time an erase block is erased. As described in more detail below, each time an erase block is successfully erased, the adaptive GIDL voltage GV a The current value of the adaptive GIDL voltage GV is saved (eg, in the state machine 216). a can be saved as the "previous adaptive GIDL voltage GV p ”.

[0225] In an embodiment, before the first implementation of process 1200c on an erase block, the previously adapted GIDL voltage GV p The value of is set to the initial GIDL voltage GV0. For example, GV0 = 7.6V or some other value.

[0226] In step 1224c of process 1200b, the erase-verify cycle counter EVL maintained by state machine 216 is initialized to 1, and the erase cycle upper limit K is initialized to a predetermined value, for example, K = 2. Other values ​​may be used for the erase cycle upper limit K.

[0227] At step 1226, the adaptive GIDL voltage GV a The value is initialized to the previous adaptive GIDL voltage GV p When the process 1200b is first implemented on an erase block, the adaptive GIDL voltage GV a The value of is initialized to the value of the initial GIDL voltage GV0. For example, GV a =GV0=7.6V.

[0228] At step 1208, erase pulses are applied to the memory cells of the erase block. In an embodiment, each erase pulse may include providing a drain-side GIDL voltage GV to the drain-side select transistors of each NAND string in the erase block. D The first drain erase pulse and the corresponding first gate erase pulse may include providing a source side GIDL voltage GV to the source side select transistor of each NAND string in the erase block. S A second drain erase pulse and a corresponding second gate erase pulse are provided.

[0229] At step 1210, an erase verify test is performed on the memory cells of the erase block, such as described above.

[0230] At step 1212, the memory system counts the number of memory cells in the erase block that have not passed the erase verify test. That is, the system counts the number of memory cells in the erase block that have a threshold voltage that is not less than the erase verify voltage. This count can be performed by the state machine 216 ( Figure 2 )、Controller 104( Figure 1 ) or other logical components to complete.

[0231] At step 1214, it is determined whether the count from step 1212 is less than or equal to the fail bit threshold number BSPF. If it is determined at step 1214 that the count at step 1212 is less than or equal to the fail bit threshold number BSPF, then the adaptive GIDL voltage GV at step 1228c is a is saved as the previous adaptive GIDL voltage GVp At step 1216, the erase process 1200c is deemed to have passed.

[0232] In contrast, if it is determined at step 1214 that the count at step 1212 is not less than or equal to the fail bit threshold number BSPF, then at step 1218 the erase-verify cycle counter EVL is incremented by one.

[0233] At step 1230, it is determined whether the erase-verify cycle counter EVL is greater than the erase cycle upper limit K. If the erase-verify cycle counter EVL is not greater than the erase cycle upper limit K, then at step 1220, it is determined whether the erase-verify cycle counter EVL is greater than the maximum number of erase-verify cycles EVL. M If the erase-verify cycle counter EVL is greater than the maximum number of erase-verify cycles EV M , then at step 1222, the erase process 1200b is deemed to have failed. In other words, the maximum number of erase-verify cycles EV M If more than a threshold number of failed bits BSPF of memory cells in an erase block fail the erase verify test, the erase is deemed to have failed.

[0234] On the contrary, if it is determined at step 1220 that the erase-verify cycle counter EVL is not greater than the maximum number EV of erase-verify cycles, M , the process 1200a loops back to step 1208 and another erase pulse is applied to the memory cells of the erase block.

[0235] The loop of step 1208 to step 1220 is repeated until the number of memory cells in the erase block that have not passed the erase verification test is less than or equal to the fail bit threshold number BSPF (whereby the erase operation passes), or the erase-verify cycle counter EVL is greater than the maximum number EV of erase-verify cycles. M (Thus the erase operation failed).

[0236] If it is determined at step 1230 that the erase-verify cycle counter EVL is greater than the erase cycle upper limit K, then the adaptive GIDL voltage GV a is set equal to the adaptive GIDL voltage GV a =The current value of +Δ, where Δ is an offset value (eg, Δ=0.2V or some other value). In this regard, when the erase-verify cycle counter EVL is greater than the erase cycle upper limit K, the corresponding adaptive GIDL voltage GV a Increase.

[0237] Without wishing to be bound by any particular theory, we believe that increasing the adaptive GIDL voltage GV as the erase-verify cycle count increasesa The decrease in GIDL current efficiency that occurs with increasing program-erase cycle counts can be compensated. Without wishing to be bound by any particular theory, we believe that increasing the adaptive GIDL voltage GV with increasing erase-verify cycle counts a A more uniform threshold voltage reduction per erase pulse may be provided independent of program-erase cycle count.

[0238] Therefore, a lower GIDL voltage GV can be used to reduce the erase-verify cycle count, and as the program-erase cycle count increases, a higher GIDL voltage GV can be used. Without wishing to be bound by any particular theory, we believe that using an adaptive GIDL voltage GV that varies based on the erase-verify cycle count a (As mentioned above and in Fig. 12C ) can reduce the number of erase failures and reduce over-erasure of memory cells.

[0239] Therefore, process 1200c does not increase the adaptive GIDL voltage GV based solely on the program-erase cycle count. a , but increases the adaptive GIDL voltage GV when the number of erase-verify cycles starts to increase a In this regard, process 1200c can account for die-to-die variations in the amount of erase speed slowdown that occurs with increasing program-erase cycle counts.

[0240] For example, the first memory die may first exceed the erase cycle cap K=2 starting from 10,000 program-erase cycles, while the second memory die may first exceed the erase cycle cap K=2 starting from 50,000 program-erase cycles. The process 1200c thus allows the adaptive GIDL voltage GV to be increased based on the actual behavior of the memory die rather than just based on the number of program-erase cycles. a .

[0241] At step 1220, it is determined whether the erase-verify cycle counter EVL is greater than the maximum number of erase-verify cycles EV M The loop of step 1208 to step 1220 is repeated until the number of memory cells in the erase block that have not passed the erase verification test is less than or equal to the fail bit threshold number BSPF (whereby the erase operation passes), or the erase-verify cycle counter EVL is greater than the maximum number of erase-verify cycles EV M (Thus the erase operation failed).

[0242] Additionally, if process 1200c results in successful erasure of memory cells in the erase block, then at step 1228c the GIDL voltage GV a The current value of the adaptive GIDL voltage GV is saved as the previousp At this point, when the process 1200c is implemented next time in the same erase block, the adaptive GIDL voltage GV a The value of will be initialized at step 1226 to the value of this variable from a previous instance of implementing process 1200c on the same erase block.

[0243] One embodiment includes an apparatus comprising: a block of memory cells having a NAND string including a first select transistor; and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by: determining a first count of the number of times the block of memory cells has been previously programmed and erased; determining a first drain-to-gate voltage of the first select transistor based on the first count, wherein the first drain-to-gate voltage is configured to cause the first select transistor to generate a first gate-induced drain leakage current; and applying a first erase pulse to the first select transistor based on the determined first drain-to-gate voltage.

[0244] One embodiment includes an apparatus comprising: a block of memory cells having a NAND string including a select transistor; and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells in a plurality of erase-verify cycles, determine a drain-to-gate voltage of the select transistor based on the number of erase-verify cycles performed on the erase block, wherein the drain-to-gate voltage is configured to cause the select transistor to generate a gate-induced drain leakage current, and apply a first erase pulse to the select transistor based on the determined drain-to-gate voltage.

[0245] One embodiment includes a method that includes performing a first erase operation on a block of memory cells having a NAND string including a select transistor in a plurality of erase-verify cycles. Each erase-verify cycle includes applying an erase pulse to the select transistor, wherein the erase pulse includes providing a drain-to-gate voltage of the select transistor, wherein the drain-to-gate voltage is configured to cause the select transistor to generate a gate-induced drain leakage current; performing a first erase verify test on the block of memory cells; counting the number of memory cells in the block that failed the erase verify test; determining that the count is greater than a threshold number; incrementing the number of erase-verify cycles performed on the erased block; determining that the number of erase-verify cycles exceeds an erase cycle cap; and incrementing the drain-to-gate voltage by an offset.

[0246] For the purposes of this document, references in the specification to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0247] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element, or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" if they are directly connected or indirectly connected, such that they are able to communicate electronic signals between them.

[0248] For the purposes of this document, the term "based on" may be understood as "based, at least in part, on."

[0249] For the purposes of this document, the use of numerical terms such as a "first" object, a "second" object, and a "third" object without additional context may not imply an ordering of the objects, but may be used for identification purposes to identify different objects.

[0250] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0251] The above detailed description has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the precise form disclosed by the invention. Many modifications and variations are possible in light of the above teachings. The described embodiments are selected to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and in various modifications suitable for the specific use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A device, comprising: a block of memory cells comprising a NAND string, the NAND string including a first select transistor; and A control circuit coupled to the block of memory cells, the control circuit being configured to perform an erase operation on the block of memory cells by: determining a first count of the number of times the block of memory cells has been previously programmed and erased; determining a first drain-to-gate voltage for the first select transistor based on the first count, wherein the first drain-to-gate voltage is configured to cause the first select transistor to generate a first gate-induced drain leakage current; as well as A first erase pulse is applied to the first selection transistor based on the determined first drain-to-gate voltage. 2 . The device of claim 1 , wherein the first drain-to-gate voltage is adaptively increased based on the first count.

3. The apparatus of claim 1, wherein the first drain-to-gate voltage increases adaptively as the number of times the block of memory cells has been previously programmed and erased increases. 4 . The apparatus of claim 1 , wherein the first drain-to-gate voltage adaptively increases in a stepwise manner based on the first count.

5. The apparatus of claim 1 , wherein the first drain-to-gate voltage comprises: an initial first drain-to-gate voltage when the first count is within a first value range; and The initial first drain-to-gate voltage is added with an offset when the first count is within a second range of values ​​greater than the first range of values. The apparatus of claim 5 , wherein the offset is a fixed value. 7 . The apparatus of claim 1 , wherein the first drain-to-gate voltage is determined from a linear equation or a nonlinear equation based on a program-erase cycle count.

8. The device according to claim 1, wherein: The NAND string also includes a second select transistor; and The control circuit is further configured to perform the erase operation on the block of memory cells by: determining a second drain-to-gate voltage of the second select transistor based on the first count, wherein the second drain-to-gate voltage is configured to cause the second select transistor to generate a second gate-induced drain leakage current; as well as A second erase pulse is applied to the second select transistor based on the determined second drain-to-gate voltage.

9. The device of claim 8, wherein the second drain-to-gate voltage is adaptively increased based on the first count.

10. The apparatus of claim 8, wherein the second drain-to-gate voltage increases adaptively as the number of times the block of memory cells has been previously programmed and erased increases.

11. The apparatus of claim 1 , wherein the control circuit is further configured to: performing an erase verify test on the block of memory cells; counting the number of memory cells in the block that fail the erase verify test; determining that the count is less than or equal to a threshold number; and It is determined that the erase operation has passed.

12. The apparatus of claim 1, wherein the control circuit is further configured to: performing an erase verify test on the block of memory cells; counting the number of memory cells in the block that fail the erase verify test; determining that the count is greater than a threshold number; and It is determined that the erase operation has failed.

13. A device, comprising: a block of memory cells comprising NAND strings, the NAND strings including select transistors; and a control circuit coupled to the block of memory cells, the control circuit being configured to: performing an erase operation on the block of memory cells in a plurality of erase-verify cycles; determining a drain-to-gate voltage of the select transistor based on a number of erase-verify cycles performed on an erase block, wherein the drain-to-gate voltage is configured to cause the select transistor to generate a gate-induced drain leakage current; as well as A first erase pulse is applied to the select transistor based on the determined drain-to-gate voltage.

14. The apparatus of claim 13, wherein the control circuit is further configured to: determining that the number of erase-verify cycles exceeds an erase cycle upper limit; and Increments the drain-to-gate voltage by an offset. The apparatus of claim 14 , wherein the offset is a fixed value.

16. The apparatus of claim 13, wherein the erase-verify cycle comprises: applying the first erase pulse to the select transistor; performing an erase verify test on the block of memory cells; counting the number of memory cells in the block that fail the erase verify test; determining that the count is greater than a threshold number; incrementing a number of erase-verify cycles performed on the erase block; determining that the number of the erase-verify cycles exceeds an erase cycle upper limit; as well as Increments the drain-to-gate voltage by an offset.

17. The apparatus of claim 13, wherein the erase-verify cycle comprises: applying the first erase pulse to the select transistor; performing an erase verify test on the block of memory cells; counting the number of memory cells in the block that fail the erase verify test; determining that the count is greater than the threshold number; incrementing a number of erase-verify cycles performed on the erase block; determining that the number of the erase-verify cycles exceeds an erase cycle upper limit; Incrementing the drain-to-gate voltage by an offset; as well as Increment the erase cycle limit.

18. The apparatus of claim 17, wherein the control circuit is further configured to: determining that the number of erase-verify cycles is less than or equal to a maximum number of erase-verify cycles; and A second erase pulse is applied to the select transistor based on the incremented drain-to-gate voltage.

19. A method comprising: A first erase operation is performed on a block of memory cells including NAND strings including select transistors in a plurality of erase-verify cycles, each erase-verify cycle comprising: applying an erase pulse to the select transistor, wherein the erase pulse comprises providing a drain-to-gate voltage of the select transistor, wherein the drain-to-gate voltage is configured to cause the select transistor to generate a gate induced drain leakage current; performing a first erase verify test on the block of memory cells; counting the number of memory cells in the block that fail the erase verify test; determining that the count is greater than a threshold number; incrementing a number of erase-verify cycles performed on the erase block; determining that the number of erase-verify cycles exceeds an erase cycle upper limit; and Increments the drain-to-gate voltage by an offset. 20 . The method of claim 19 , further comprising applying a second erase pulse to the select transistor based on the incremented drain-to-gate voltage.

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