Power supply system and electronic device

Abstract

The invention provides a power supply system and electronic equipment, a power supply control module in the system generates a target control signal, and the target control signal is a first control signal or a second control signal; the voltage source module outputs bias current, first bias voltage, second bias voltage, first reference voltage and second reference voltage; the reference voltage buffer module outputs a voltage reference signal based on a first bias voltage and a first reference voltage. The first voltage stabilization module generates an analog circuit working voltage based on a target control signal, a bias current, a second bias voltage, a second reference voltage and a voltage reference signal; the analog circuit working voltage output by the first voltage stabilizing module when the target control signal is the first control signal is larger than the analog circuit working voltage output when the target control signal is the second control signal. The power supply system provided by the invention can be in different working modes such as the first mode and the second mode, and can meet different requirements of electronic equipment on power supply efficiency, power consumption and the like.

Description

Technical Field

[0001] The present application relates to the field of power supply technology, and in particular to a power supply system and electronic equipment. Background Art

[0002] The power supply system is a core component in electronic devices, responsible for converting raw electricity into a form suitable for use in specific devices. Although the power supply system plays a vital role in electronic devices, there is a common problem in the existing technology, that is, the power supply system has a single working mode, which makes the power supply system unable to adapt to the changing application environment and thus cannot meet the needs of electronic equipment. Summary of the invention

[0003] The technical problem to be solved by the present application is to provide a power supply system that can avoid having a single working mode.

[0004] To solve the above problems, the following solutions are proposed:

[0005] A power supply system, comprising:

[0006] A power control module, a voltage source module, a reference voltage buffer module and a first voltage stabilization module;

[0007] The power control module is used to generate a target control signal, wherein the target control signal is a first control signal when the power system is in a first mode, or a second control signal when the power system is in a second mode; the power consumption of the power system in the first mode is greater than the power consumption of the power system in the second mode;

[0008] The voltage source module is used to output a bias current, a bias voltage and a reference voltage; the reference voltage includes at least a first reference voltage and a second reference voltage;

[0009] The reference voltage buffer module is used to output a voltage reference signal based on the bias voltage and the first reference voltage;

[0010] The first voltage stabilizing module is used to generate an analog circuit operating voltage based on the target control signal, the bias current, the second reference voltage and the voltage reference signal; wherein the analog circuit operating voltage output by the first voltage stabilizing module when the target control signal is the first control signal is greater than the analog circuit operating voltage output when the target control signal is the second control signal.

[0011] The above system may optionally further include: a second voltage stabilizing module;

[0012] The second voltage stabilizing module is used to output a digital circuit operating voltage when the power supply system is in the first mode; and stop working when the power supply system is in the second mode.

[0013] In the above system, optionally, the voltage source module comprises:

[0014] Bias circuit and bandgap reference source;

[0015] The bias circuit is used to output a bias current;

[0016] The bandgap reference source is used to output a bias voltage and a reference voltage based on the bias current.

[0017] In the above system, optionally, the bias circuit comprises:

[0018] A first MOS tube, a second MOS tube, a third MOS tube, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a first resistor and a second resistor;

[0019] The gate of the first MOS tube is connected to the drain of the second MOS tube, and the drain of the first MOS tube is connected to the drain of the third MOS tube; the source of the first MOS tube is connected to the collector of the fourth switch tube;

[0020] The source of the second MOS tube is connected to the base of the first switch tube, the emitter of the first switch tube is connected to the power supply; the base of the first switch tube is connected to the base of the second switch tube;

[0021] The emitter of the second switch tube is connected to the power supply, the base of the second switch tube is connected to the source of the third MOS tube; the gate of the third MOS tube is connected to the gate of the second MOS tube;

[0022] One end of the first resistor is connected to the power supply, and the other end is connected to the collector of the third switch tube; the base of the third switch tube is connected to the base of the fourth switch tube; the emitter of the third switch tube is connected to the collector of the fifth switch tube and the base of the sixth switch tube respectively;

[0023] The emitter of the fourth switch tube is connected to the base of the fifth switch tube and the collector of the sixth switch tube respectively; the emitter of the fifth switch tube is grounded, and the emitter of the sixth switch tube is grounded through the second resistor.

[0024] In the above system, optionally, the bandgap reference source comprises:

[0025] a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a third MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh switch tube, an eighth switch tube, a ninth switch tube, a tenth switch tube, an eleventh switch tube and a twelfth switch tube; wherein the fourth MOS tube is an intrinsic tube;

[0026] The gate of the fourth MOS tube is connected to the gate of the third MOS tube; the source of the fourth MOS tube is connected to the collector of the eleventh switch tube; the drain of the fourth MOS tube is connected to the source of the twelfth MOS tube;

[0027] The base of the eleventh switch tube is connected to the base of the second switch tube and the base of the second switch tube respectively; the emitter of the eleventh switch tube is connected to the power supply;

[0028] The gate of the twelfth MOS tube is respectively connected to the drain of the twelfth MOS tube and the gate of the thirteenth MOS tube; the drain of the twelfth MOS tube is connected to the collector of the seventh switch tube; the source of the twelfth MOS tube is respectively connected to the source of the thirteenth MOS tube, the source of the fourteenth MOS tube, the gate of the sixth MOS tube, the gate of the seventh MOS tube, the gate of the eighth MOS tube, and the source of the fifteenth MOS tube;

[0029] The emitter of the seventh switch tube is connected to one end of the third resistor, and the other end of the third resistor is respectively connected to one end of the fourth resistor and the emitter of the eighth switch tube; the base of the fourth switch tube is connected to the base of the eighth switch tube; the other end of the fourth resistor is grounded;

[0030] The base of the eighth switch tube is connected to the first reference voltage output terminal, the collector of the eighth switch tube is connected to the drain of the thirteenth MOS tube, and the gate of the thirteenth MOS tube is connected to the gate of the ninth MOS tube;

[0031] The gate of the fifth MOS tube is connected to the gate of the fourth switch tube, the drain of the fifth MOS tube is connected to the third bias current output terminal, the source of the fifth MOS tube is connected to the collector of the twelfth switch tube, the emitter of the twelfth switch tube is connected to the power supply; the base of the twelfth switch tube is connected to the base of the eleventh switch tube;

[0032] The gate of the fourteenth MOS tube is respectively connected to the drain of the ninth MOS tube, the seventh resistor, and the drain of the sixteenth MOS tube; the drain of the fourteenth MOS tube is respectively connected to the drain of the thirteenth MOS tube and the gate of the fifteenth MOS tube; the drain of the fifteenth MOS tube is respectively connected to the base and collector of the ninth switch tube;

[0033] The emitter of the ninth switch tube is connected to the base and collector of the tenth switch tube respectively; the emitter of the tenth switch tube is grounded;

[0034] The source of the sixth MOS tube is grounded through the fifth resistor and the sixth resistor in sequence; the source of the sixth MOS tube is connected to the second reference voltage output terminal;

[0035] The drain of the seventh MOS tube is connected to the power supply, and the source of the seventh MOS tube is connected to the drain of the eighth MOS tube; the source of the eighth MOS tube is respectively connected to the second reference voltage output terminal, the drain of the tenth MOS tube, the drain of the eleventh MOS tube, the drain of the eighteenth MOS tube, and the source of the ninth MOS tube;

[0036] The gate of the tenth MOS tube is connected to the gate of the eleventh MOS tube and the gate of the eighteenth MOS tube respectively; the source of the tenth MOS tube is connected to the drain of the seventh MOS tube; the source of the eleventh MOS tube is connected to the output terminal of IBIAS1; the source of the eighteenth MOS tube is connected to the second bias current output terminal;

[0037] One end of the seventh resistor is connected to the gate of the fourteenth MOS tube and the drain of the ninth MOS tube respectively, and the other end is connected to the drain of the sixteenth MOS tube;

[0038] The gate of the sixteenth MOS tube is connected to the gate of the seventeenth MOS tube, the source of the sixteenth MOS tube and the source of the seventeenth MOS tube are grounded; the drain of the seventeenth MOS tube is connected to the source of the tenth MOS tube.

[0039] In the above system, optionally, the power supply system in the first mode includes:

[0040] The voltage source module is turned on, the reference voltage buffer module is turned on, the first voltage stabilizing module is turned on in a low power consumption state, the second voltage stabilizing module is turned off, and the power control module is turned on.

[0041] In the above system, optionally, the power supply system in the second mode includes:

[0042] The voltage source module is turned on, the reference voltage buffer module is turned on, the first voltage stabilizing module is turned on in a normal power consumption state, the second voltage stabilizing module is turned on, and the power control module is turned on.

[0043] In the above system, optionally, the reference voltage buffer module includes:

[0044] A nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, a twenty-second MOS tube, a twenty-third MOS tube, a twenty-fourth MOS tube, a twenty-fifth MOS tube, a twenty-sixth MOS tube, a first capacitor, and a second capacitor;

[0045] The drain of the nineteenth MOS tube is connected to the power supply, and the gate of the nineteenth MOS tube is connected to the output end of the first bias voltage; the source of the nineteenth MOS tube is respectively connected to the source of the twentieth MOS tube, the source of the twenty-first MOS tube, and the source of the twenty-sixth MOS tube;

[0046] The gate of the 20th MOS tube is connected to the drain of the 20th MOS tube and the gate of the 21st MOS tube respectively; the drain of the 20th MOS tube is connected to the drain of the 22nd MOS tube;

[0047] The gate of the twenty-second MOS tube is connected to the output end of the second reference voltage, and the source of the twenty-second MOS tube is connected to the drain of the twenty-fourth MOS tube and the source of the twenty-third MOS tube respectively;

[0048] The gate of the twenty-fourth MOS transistor is connected to the output end of the second bias voltage, and the source of the twenty-fourth MOS transistor is grounded;

[0049] The drain of the twenty-first MOS tube is respectively connected to the gate of the twenty-sixth MOS tube, one end of the first capacitor and the drain of the twenty-third MOS tube; the other end of the first capacitor is respectively connected to the drain of the twenty-sixth MOS tube, the voltage reference signal output end, the gate of the twenty-third MOS tube, the first end of the second capacitor and the drain of the twenty-fifth MOS tube; the other end of the second capacitor and the source of the twenty-fifth MOS tube are grounded, and the gate of the twenty-fifth MOS tube is connected to the gate of the 20th MOS tube.

[0050] In the above system, optionally, the first voltage stabilizing module includes:

[0051] a twenty-seventh MOS tube, a twenty-eighth MOS tube, a twenty-ninth MOS tube, a thirtieth MOS tube, a thirty-first MOS tube, a thirty-second MOS tube, a thirty-third MOS tube, a thirty-fourth MOS tube, a thirty-fifth MOS tube, a thirty-sixth MOS tube, a thirty-seventh MOS tube, a thirty-eighth MOS tube, an eighth resistor, a ninth resistor, a tenth resistor and an eleventh resistor; wherein the nineteenth MOS tube is an intrinsic tube;

[0052] The source of the twenty-seventh MOS tube is connected to the first bias current output terminal, the gate of the twenty-seventh MOS tube is connected to the feedback voltage output terminal, the drain of the twenty-seventh MOS tube is respectively connected to the drain and gate of the twenty-ninth MOS tube, and the source of the twenty-ninth MOS tube is grounded;

[0053] The gate of the 28th MOS tube is connected to the VREF output terminal, the drain of the 28th MOS tube is respectively connected to the gate of the 31st MOS tube, the gate of the 30th MOS tube, and the drain of the 30th MOS tube, and the source of the 30th MOS tube is grounded;

[0054] The drain of the thirty-first MOS tube is connected to the second bias current output terminal, and the source of the thirty-first MOS tube is grounded;

[0055] The gate of the thirty-second MOS tube is connected to the second bias current output terminal, and the drain of the thirty-second MOS tube is connected to the third bias current IBIAS3 output terminal and the gate of the thirty-third MOS tube respectively;

[0056] The source of the thirty-third MOS tube is connected to the drain of the thirty-fourth MOS tube, the gate of the thirty-fourth MOS tube and the gate of the thirty-fifth MOS tube, and the drain of the thirty-third MOS tube is grounded through the eighth resistor;

[0057] The source of the thirty-fourth MOS tube and the source of the thirty-fifth MOS tube are connected to a power source;

[0058] One end of the ninth resistor is respectively connected to the drain of the thirty-fifth MOS tube and the analog circuit working voltage output terminal, and the other end of the ninth resistor is respectively connected to the feedback voltage output terminal and one end of the tenth resistor; the other end of the tenth resistor is respectively connected to one end of the eleventh resistor and the source of the thirty-sixth MOS tube, and the other end of the eleventh resistor and the drain of the thirty-sixth MOS tube are grounded;

[0059] The gate of the thirty-sixth MOS tube is respectively connected to the drain of the thirty-seventh MOS tube and the drain of the thirty-eighth MOS tube, the source of the thirty-seventh MOS tube is connected to the voltage reference signal output end, the gate of the thirty-seventh MOS tube and the gate of the thirty-eighth MOS tube are connected to the control signal output end of the power control module; the source of the thirty-eighth MOS tube is grounded.

[0060] An electronic device comprises the above power supply system.

[0061] To achieve the above objectives, the present application provides the following technical solutions:

[0062] Compared with the prior art, this application has the following advantages:

[0063] The present application provides a power supply system and an electronic device, the system comprising: a power supply control module, a voltage source module, a reference voltage buffer module and a first voltage stabilizing module; the power supply control module is used to generate a target control signal, the target control signal is a first control signal when the power supply system is in a first mode, or a second control signal when the power supply system is in a second mode; the power consumption of the power supply system in the first mode is greater than the power consumption of the power supply system in the second mode; the voltage source module is used to output a bias current, a bias voltage and a reference voltage; the reference voltage includes at least a first reference voltage and a second reference voltage; the reference voltage buffer module is used to output a voltage reference signal based on the bias voltage and the first reference voltage; the first voltage stabilizing module is used to generate an analog circuit operating voltage based on the target control signal, the bias current, the second reference voltage and the voltage reference signal; wherein the analog circuit operating voltage output by the first voltage stabilizing module when the target control signal is the first control signal is greater than the analog circuit operating voltage output when the target control signal is the second control signal. The power supply system provided by the present application can be in different operating modes such as the first mode and the second mode, and can meet different requirements of electronic equipment for power efficiency, power consumption, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0065] Figure 1 A schematic diagram of the structure of a power supply system provided for this application;

[0066] Figure 2A schematic diagram of the structure of another power supply system provided in this application;

[0067] Figure 3 A schematic diagram of the structure of a voltage source module provided in this application;

[0068] Figure 4 A schematic diagram of the structure of a reference voltage buffer module provided in this application;

[0069] Figure 5 A schematic diagram of the structure of a first voltage stabilizing module provided in this application;

[0070] Figure 6 A schematic diagram of the structure of an electronic device provided in this application. DETAILED DESCRIPTION

[0071] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0072] The specific implementation of the present application is described below with reference to the schematic diagram of the power supply system structure.

[0073] See also Figure 1 , shows a schematic diagram of the structure of a power supply system provided in an embodiment of the present application, including:

[0074] A power control module 101, a voltage source module 102, a reference voltage buffer module 103 and a first voltage stabilizing module 104;

[0075] The power control module 101 is used to generate a target control signal, where the target control signal is a first control signal when the power system is in the first mode, or a second control signal when the power system is in the second mode; the power consumption of the power system in the first mode is greater than the power consumption of the power system in the second mode;

[0076] Optionally, the power supply system being in the first mode includes: the voltage source module is turned on, the reference voltage buffer module is turned on, the first voltage stabilizing module is turned on in a low power consumption state, the second voltage stabilizing module is turned off, and the power control module is turned on.

[0077] Optionally, the power supply system being in the second mode includes: the voltage source module being turned on, the reference voltage buffer module being turned on, the first voltage stabilizing module being turned on in a normal power consumption state, the second voltage stabilizing module being turned on, and the power control module being turned on.

[0078] In this embodiment, the target control signal may be used to indicate an output analog circuit operating voltage.

[0079] The voltage source module 102 is used to output a bias current, a bias voltage and a reference voltage; the reference voltage includes at least a first reference voltage and a second reference voltage;

[0080] In this embodiment, the voltage source module can provide a reference voltage for the reference voltage buffer module and the first voltage stabilization module.

[0081] Optionally, the voltage source module can output a variety of low-voltage voltage sources to serve as power supplies for POR circuits, over-temperature, over-voltage, and under-voltage protection circuits. It can also generate low-power low-dropout linear regulators LDO based on the reference voltage. These LDOs do not have high requirements for settling time or load capacity, so they can achieve low power consumption.

[0082] A reference voltage buffer module 103, configured to output a voltage reference signal based on a bias voltage and a first reference voltage;

[0083] In this embodiment, the voltage reference signal can be used as the power supply of the power module.

[0084] The first voltage stabilization module 104 is used to generate an analog circuit operating voltage based on a target control signal, a bias current, a second reference voltage and a voltage reference signal; wherein the analog circuit operating voltage output by the first voltage stabilization module when the target control signal is a first control signal is greater than the analog circuit operating voltage output when the target control signal is a second control signal.

[0085] In an embodiment provided in the present application, based on the above solution, optionally, Figure 2 As shown, the power supply system further includes a second voltage stabilizing module 105;

[0086] The second voltage stabilizing module 105 is used to output the digital circuit working voltage when the power supply system is in the first mode; and stop working when the power supply system is in the second mode.

[0087] In this embodiment, the voltage source module can provide a reference voltage for the second voltage stabilization module.

[0088] The power supply system provided in the present application can be in different working modes such as the first mode and the second mode, and can meet different requirements of electronic devices for power efficiency, power consumption, etc.

[0089] In an embodiment provided in the present application, based on the above solution, optionally, the voltage source module includes:

[0090] Bias circuit and bandgap reference source;

[0091] A bias circuit, used for outputting a bias current;

[0092] A bandgap reference source is used to output a bias voltage and a reference voltage based on a bias current.

[0093] In this embodiment, the bias circuit can be used to provide bias current to each module in the power supply system.

[0094] See also Figure 3 , is a schematic diagram of the structure of a voltage source module provided in an embodiment of the present application, wherein the bias circuit in the voltage source module comprises: a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a fifth switch tube Q5, a sixth switch tube Q6, a first resistor R1, and a second resistor R2;

[0095] The gate of the first MOS tube M1 is connected to the drain of the second MOS tube M2, and the drain of the first MOS tube M1 is connected to the drain of the third MOS tube M3; the source of the first MOS tube M1 is connected to the collector of the fourth switch tube Q4;

[0096] The source of the second MOS tube M2 is connected to the base of the first switch tube Q1, and the emitter of the first switch tube Q1 is connected to the power supply; the base of the first switch tube Q1 is connected to the base of the second switch tube Q2;

[0097] The emitter of the second switch tube Q2 is connected to the power supply, the base of the second switch tube Q2 is connected to the source of the third MOS tube M3; the gate of the third MOS tube M3 is connected to the gate of the second MOS tube M2;

[0098] One end of the first resistor R1 is connected to the power supply, and the other end is connected to the collector of the third switch tube Q3; the base of the third switch tube Q3 is connected to the base of the fourth switch tube Q4; the emitter of the third switch tube Q3 is connected to the collector of the fifth switch tube Q5 and the base of the sixth switch tube Q6 respectively;

[0099] The emitter of the fourth switch tube Q4 is connected to the base of the fifth switch tube Q5 and the collector of the sixth switch tube Q6 respectively; the emitter of the fifth switch tube Q5 is grounded, and the emitter of the sixth switch tube Q6 is grounded through the second resistor R2.

[0100] In this embodiment, the switch tubes Q1 to Q6 may be bipolar junction transistors; and the MOS tubes M1 to M3 may be high-voltage resistant MOS tubes.

[0101] In an embodiment provided in the present application, based on the above solution, optionally, see Figure 3, a bandgap reference source, including: a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a ninth MOS tube M9, a tenth MOS tube M10, an eleventh MOS tube M11, a twelfth MOS tube M12, a third MOS tube M3, a fourteenth MOS tube M14, a fifteenth MOS tube M15, a sixteenth MOS tube M16, a seventeenth MOS tube M17, an eighteenth MOS tube M18, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh switch tube Q7, an eighth switch tube Q8, a ninth switch tube Q9, a tenth switch tube Q10, an eleventh switch tube Q11 and a twelfth switch tube Q12; wherein the fourth MOS tube M4 is an intrinsic tube;

[0102] The gate of the fourth MOS tube M4 is connected to the gate of the third MOS tube M3; the source of the fourth MOS tube M4 is connected to the collector of the eleventh switch tube Q11; the drain of the fourth MOS tube M4 is connected to the source of the twelfth MOS tube M12;

[0103] The base of the eleventh switch tube Q11 is connected to the base of the second switch tube Q2 and the base of the second switch tube Q2 respectively; the emitter of the eleventh switch tube Q11 is connected to the power supply;

[0104] The gate of the twelfth MOS tube M12 is respectively connected to the drain of the twelfth MOS tube M12 and the gate of the thirteenth MOS tube M13; the drain of the twelfth MOS tube M12 is connected to the collector of the seventh switch tube Q7; the source of the twelfth MOS tube M12 is respectively connected to the source of the thirteenth MOS tube M13, the source of the fourteenth MOS tube M14, the gate of the sixth MOS tube M6, the gate of the seventh MOS tube M7, the gate of the eighth MOS tube M8, and the source of the fifteenth MOS tube M15;

[0105] The emitter of the seventh switch tube Q7 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is respectively connected to one end of the fourth resistor R4 and the emitter of the eighth switch tube Q8; the base of the fourth switch tube Q4 is connected to the base of the eighth switch tube Q8; the other end of the fourth resistor R4 is grounded;

[0106] The base of the eighth switch tube Q8 is connected to the output end of the first reference voltage VREF, the collector of the eighth switch tube Q8 is connected to the drain of the thirteenth MOS tube M13, and the gate of the thirteenth MOS tube M13 is connected to the gate of the ninth MOS tube M9;

[0107] The gate of the fifth MOS tube M5 is connected to the gate of the fourth switch tube Q4, the drain of the fifth MOS tube M5 is connected to the output end of the third bias current IBIAS3, the source of the fifth MOS tube M5 is connected to the collector of the twelfth switch tube Q12, the emitter of the twelfth switch tube Q12 is connected to the power supply; the base of the twelfth switch tube Q12 is connected to the base of the eleventh switch tube Q11;

[0108] The gate of the fourteenth MOS tube M14 is respectively connected to the drain of the ninth MOS tube M9, the seventh resistor R7, and the drain of the sixteenth MOS tube M16; the drain of the fourteenth MOS tube M14 is respectively connected to the drain of the thirteenth MOS tube M13 and the gate of the fifteenth MOS tube M15; the drain of the fifteenth MOS tube M15 is respectively connected to the base and collector of the ninth switch tube Q9;

[0109] The emitter of the ninth switch tube Q9 is connected to the base and collector of the tenth switch tube Q10 respectively; the emitter of the tenth switch tube Q10 is grounded;

[0110] The source of the sixth MOS tube M6 is grounded through the fifth resistor R5 and the sixth resistor R6 in sequence; the source of the sixth MOS tube M6 is connected to the output terminal of the second reference voltage VHREF;

[0111] The drain of the seventh MOS tube M7 is connected to the power supply, and the source of the seventh MOS tube M7 is connected to the drain of the eighth MOS tube M8; the source of the eighth MOS tube M8 is respectively connected to the output end of the second reference voltage VHREF, the drain of the tenth MOS tube M10, the drain of the eleventh MOS tube M11, the drain of the eighteenth MOS tube M18, and the source of the ninth MOS tube M9;

[0112] The gate of the tenth MOS tube M10 is connected to the gate of the eleventh MOS tube M11 and the gate of the eighteenth MOS tube M18 respectively; the source of the tenth MOS tube M10 is connected to the drain of the seventh MOS tube M7; the source of the eleventh MOS tube M11 is connected to the output end of IBIAS1; the source of the eighteenth MOS tube M18 is connected to the output end of the second bias current IBIAS2;

[0113] One end of the seventh resistor R7 is respectively connected to the gate of the fourteenth MOS transistor M14 and the drain of the ninth MOS transistor M9, and the other end is connected to the drain of the sixteenth MOS transistor M16;

[0114] The gate of the sixteenth MOS tube M16 is connected to the gate of the seventeenth MOS tube M17, the source of the sixteenth MOS tube M16 and the source of the seventeenth MOS tube M17 are grounded; the drain of the seventeenth MOS tube M17 is connected to the source of the tenth MOS tube M10.

[0115] In this embodiment, the MOS transistors M4 to M6 may be high-voltage resistant MOS transistors, M7 may be a high-voltage resistant intrinsic transistor, and the switch transistors Q7 to Q12 may be bipolar junction transistors.

[0116] In an embodiment provided in the present application, based on the above solution, optionally, the structural diagram of the reference voltage buffer module is as follows: Figure 4 As shown, the reference voltage buffer module specifically includes:

[0117] A nineteenth MOS tube M19, a twentieth MOS tube M20, a twenty-first MOS tube M21, a twenty-second MOS tube M22, a twenty-third MOS tube M23, a twenty-fourth MOS tube M24, a twenty-fifth MOS tube M25, a twenty-sixth MOS tube M26, a first capacitor C1 and a second capacitor C2;

[0118] The drain of the nineteenth MOS tube M19 is connected to the power supply, and the gate of the nineteenth MOS tube M19 is connected to the output end of the first bias voltage VHREF1; the source of the nineteenth MOS tube M19 is respectively connected to the source of the twentieth MOS tube M20, the source of the twenty-first MOS tube M21, and the source of the twenty-sixth MOS tube M26;

[0119] The gate of the 20th MOS tube M20 is connected to the drain of the 20th MOS tube M20 and the gate of the 21st MOS tube M21 respectively; the drain of the 20th MOS tube M20 is connected to the drain of the 22nd MOS tube M22;

[0120] The gate of the twenty-second MOS tube M22 is connected to the output end of the second reference voltage VHREF, and the source of the twenty-second MOS tube M22 is connected to the drain of the twenty-fourth MOS tube M24 and the source of the twenty-third MOS tube M23 respectively;

[0121] The gate of the twenty-fourth MOS tube M24 is connected to the output end of the second bias voltage VBIAS, and the source of the twenty-fourth MOS tube M24 is grounded;

[0122] The drain of the twenty-first MOS tube M21 is respectively connected to the gate of the twenty-sixth MOS tube M26, one end of the first capacitor C1 and the drain of the twenty-third MOS tube M23; the other end of the first capacitor C1 is respectively connected to the drain of the twenty-sixth MOS tube M26, the output end of the voltage reference signal VANA_ON, the gate of the twenty-third MOS tube M23, the first end of the second capacitor C2 and the drain of the twenty-fifth MOS tube M25; the other end of the second capacitor C2 and the source of the twenty-fifth MOS tube M25 are grounded, and the gate of the twenty-fifth MOS tube M25 is connected to the gate of the twentieth MOS tube M20.

[0123] In this embodiment, the voltages VHREF1 , VHREF, and VBIAS required by the reference voltage buffer module are provided by the voltage source module.

[0124] Optionally, VHREF can be used as the input reference voltage of the amplifier, and VHREF1 and VBIAS can be used as bias voltages. The high-voltage-resistant native MOS tubes M24, M25, and M26 are used to withstand high voltages so that other tubes can work under low voltage conditions. Since the power supply only needs to be started once after power-on, the load capacity requirement is very low, and the bias current of the circuit can be designed to be relatively small, so the circuit only consumes low working power consumption when working. Therefore, this circuit can work under hundreds of volts of working voltage and has low power consumption.

[0125] In this embodiment, the output voltage of the reference voltage buffer module is: VANAON=VHREF.

[0126] In an embodiment provided in the present application, based on the above solution, optionally, the structural diagram of the first voltage stabilizing module is as follows: Figure 5 , the first voltage stabilizing module includes:

[0127] a twenty-seventh MOS tube M27, a twenty-eighth MOS tube M28, a twenty-ninth MOS tube M29, a thirtieth MOS tube M30, a thirty-first MOS tube M31, a thirty-second MOS tube M32, a thirty-third MOS tube M33, a thirty-fourth MOS tube M34, a thirty-fifth MOS tube M35, a thirty-sixth MOS tube M36, a thirty-seventh MOS tube M37, a thirty-eighth MOS tube M38, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10 and an eleventh resistor R11; wherein the nineteenth MOS tube M19 is an intrinsic tube;

[0128] The source of the twenty-seventh MOS tube M27 is connected to the output end of the first bias current IBIAS1, the gate of the twenty-seventh MOS tube M27 is connected to the output end of the feedback voltage VFB, the drain of the twenty-seventh MOS tube M27 is respectively connected to the drain and gate of the twenty-ninth MOS tube M29, and the source of the twenty-ninth MOS tube M29 is grounded;

[0129] The gate of the twenty-eighth MOS tube M28 is connected to the VREF output terminal, the drain of the twenty-eighth MOS tube M28 is respectively connected to the gate of the thirty-first MOS tube M31, the gate of the thirtieth MOS tube M30, and the drain of the thirtieth MOS tube M30, and the source of the thirtieth MOS tube M30 is grounded;

[0130] The drain of the thirty-first MOS tube M31 is connected to the output terminal of the second bias current IBIAS2, and the source of the thirty-first MOS tube M31 is grounded;

[0131] The gate of the thirty-second MOS tube M32 is connected to the output end of the second bias current IBIAS2, and the drain of the thirty-second MOS tube M32 is connected to the output end of the third bias current IBIAS3 and the gate of the thirty-third MOS tube M33 respectively;

[0132] The source of the thirty-third MOS tube M33 is connected to the drain of the thirty-fourth MOS tube M34, the gate of the thirty-fourth MOS tube M34 and the gate of the thirty-fifth MOS tube M35, and the drain of the thirty-third MOS tube M33 is grounded through the eighth resistor R8;

[0133] The source of the thirty-fourth MOS tube M34 and the source of the thirty-fifth MOS tube M35 are connected to the power supply;

[0134] One end of the ninth resistor R9 is respectively connected to the drain of the thirty-fifth MOS tube M35 and the analog circuit working voltage output end, and the other end of the ninth resistor R9 is respectively connected to the feedback voltage VFB output end and one end of the tenth resistor R10; the other end of the tenth resistor R10 is respectively connected to one end of the eleventh resistor R11 and the source of the thirty-sixth MOS tube M36, and the other end of the eleventh resistor R11 and the drain of the thirty-sixth MOS tube M36 are grounded;

[0135] The gate of the thirty-sixth MOS tube M36 is respectively connected to the drain of the thirty-seventh MOS tube M37 and the drain of the thirty-eighth MOS tube M38, the source of the thirty-seventh MOS tube M37 is connected to the output end of the voltage reference signal NANA_ON, the gate of the thirty-seventh MOS tube M37 and the gate of the thirty-eighth MOS tube M38 are connected to the target control signal LP_EN output end of the power control module; the source of the thirty-eighth MOS tube M38 is grounded.

[0136] In this embodiment, M27 can be a high-voltage resistant intrinsic tube, which can withstand high voltage so that other tubes can work under low voltage conditions. BIAS1, IBIAS2, and IBIAS are provided by the voltage source module, VREF is used as the input reference voltage of the amplifier, IBIAS1, IBIAS2, and IBIAS are used as bias currents, and the high-voltage resistant native mos tube M27 is used to withstand high voltage so that other tubes can work under low voltage conditions. Since the power supply only needs to be started once after power-on, the requirements for the establishment time and accuracy are very low, and the bias current of the circuit can be designed to be relatively small, so the working power consumption of the circuit is relatively low. In addition, in the low-power mode, the output voltage of VCOM is lower than the output voltage in the normal mode. Therefore, this circuit can work under a working voltage of hundreds of volts and has low power consumption.

[0137] In this embodiment, the size ratio of the bipolar junction transistors Q7 and Q8 is K, K is 8, the mirror ratio of the MOS tubes P12 and P13 is 1, and the size ratio of the bipolar junction transistors Q3, Q4, Q5, and Q6 is K1:1:1:K2, which is set to 2:1:1:4, and we can get:

[0138]

[0139] Wherein, I is the current flowing through R2, VBE8 is the voltage difference between the base of Q7 and the first end of R4, and the first end of R4 is connected to the emitter of Q7 through R3.

[0140] Optionally, the target control signal may be a high level signal or a low level signal.

[0141] In this embodiment, EN_LP is at a high level, and the output voltage in the second mode (low power consumption mode) is:

[0142]

[0143] In this embodiment, EN_LP is at a low level, and the output voltage in the first mode (normal mode) is:

[0144]

[0145] The power supply system provided in the embodiment of the present application can handle high voltage and low power consumption problems at the same time, and can provide a stable power supply voltage and achieve low power consumption, thus meeting the dual requirements of electronic equipment for power efficiency and power consumption.

[0146] The present application also provides an electronic device, the structural diagram of the electronic device is as follows Figure 6 As shown, it includes the power supply system mentioned above.

[0147] In this application, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0148] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. A person of ordinary skill in the art may understand and implement it without creative work.

[0149] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0150] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power supply system, characterized in that: include: A power control module, a voltage source module, a reference voltage buffer module and a first voltage stabilization module; The power control module is used to generate a target control signal, wherein the target control signal is a first control signal when the power system is in the first mode, or a second control signal when the power system is in the second mode; The power consumption of the power supply system in the first mode is greater than the power consumption of the power supply system in the second mode; The voltage source module is used to output a bias current, a bias voltage and a reference voltage; The reference voltage includes at least a first reference voltage and a second reference voltage; The reference voltage buffer module is used to output a voltage reference signal based on the bias voltage and the first reference voltage; The first voltage stabilizing module is used to generate an analog circuit operating voltage based on the target control signal, the bias current, the second reference voltage and the voltage reference signal; wherein the analog circuit operating voltage output by the first voltage stabilizing module when the target control signal is the first control signal is greater than the analog circuit operating voltage output when the target control signal is the second control signal.

2. The system according to claim 1, characterized in that Also includes: The second voltage stabilizing module; The second voltage stabilizing module is used for outputting a digital circuit operating voltage when the power supply system is in the first mode; When the power supply system is in the second mode, the power supply system stops working.

3. The system according to claim 1, characterized in that The voltage source module comprises: Bias circuit and bandgap reference source; The bias circuit is used to output a bias current; The bandgap reference source is used to output a bias voltage and a reference voltage based on the bias current.

4. The system according to claim 3, characterized in that The bias circuit comprises: A first MOS tube, a second MOS tube, a third MOS tube, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a first resistor and a second resistor; The gate of the first MOS tube is connected to the drain of the second MOS tube, and the drain of the first MOS tube is connected to the drain of the third MOS tube; the source of the first MOS tube is connected to the collector of the fourth switch tube; The source of the second MOS tube is connected to the base of the first switch tube, the emitter of the first switch tube is connected to the power supply; the base of the first switch tube is connected to the base of the second switch tube; The emitter of the second switch tube is connected to the power supply, the base of the second switch tube is connected to the source of the third MOS tube; the gate of the third MOS tube is connected to the gate of the second MOS tube; One end of the first resistor is connected to the power supply, and the other end is connected to the collector of the third switch tube; the base of the third switch tube is connected to the base of the fourth switch tube; the emitter of the third switch tube is connected to the collector of the fifth switch tube and the base of the sixth switch tube respectively; The emitter of the fourth switch tube is connected to the base of the fifth switch tube and the collector of the sixth switch tube respectively; the emitter of the fifth switch tube is grounded, and the emitter of the sixth switch tube is grounded through the second resistor.

5. The system according to claim 4, characterized in that The bandgap reference source comprises: a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a third MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh switch tube, an eighth switch tube, a ninth switch tube, a tenth switch tube, an eleventh switch tube and a twelfth switch tube; wherein the fourth MOS tube is an intrinsic tube; The gate of the fourth MOS tube is connected to the gate of the third MOS tube; the source of the fourth MOS tube is connected to the collector of the eleventh switch tube; the drain of the fourth MOS tube is connected to the source of the twelfth MOS tube; The base of the eleventh switch tube is connected to the base of the second switch tube and the base of the second switch tube respectively; the emitter of the eleventh switch tube is connected to the power supply; The gate of the twelfth MOS tube is respectively connected to the drain of the twelfth MOS tube and the gate of the thirteenth MOS tube; the drain of the twelfth MOS tube is connected to the collector of the seventh switch tube; the source of the twelfth MOS tube is respectively connected to the source of the thirteenth MOS tube, the source of the fourteenth MOS tube, the gate of the sixth MOS tube, the gate of the seventh MOS tube, the gate of the eighth MOS tube, and the source of the fifteenth MOS tube; The emitter of the seventh switch tube is connected to one end of the third resistor, and the other end of the third resistor is respectively connected to one end of the fourth resistor and the emitter of the eighth switch tube; the base of the fourth switch tube is connected to the base of the eighth switch tube; the other end of the fourth resistor is grounded; The base of the eighth switch tube is connected to the first reference voltage output terminal, the collector of the eighth switch tube is connected to the drain of the thirteenth MOS tube, and the gate of the thirteenth MOS tube is connected to the gate of the ninth MOS tube; The gate of the fifth MOS tube is connected to the gate of the fourth switch tube, the drain of the fifth MOS tube is connected to the third bias current output terminal, the source of the fifth MOS tube is connected to the collector of the twelfth switch tube, the emitter of the twelfth switch tube is connected to the power supply; the base of the twelfth switch tube is connected to the base of the eleventh switch tube; The gate of the fourteenth MOS tube is respectively connected to the drain of the ninth MOS tube, the seventh resistor, and the drain of the sixteenth MOS tube; the drain of the fourteenth MOS tube is respectively connected to the drain of the thirteenth MOS tube and the gate of the fifteenth MOS tube; the drain of the fifteenth MOS tube is respectively connected to the base and collector of the ninth switch tube; The emitter of the ninth switch tube is connected to the base and collector of the tenth switch tube respectively; the emitter of the tenth switch tube is grounded; The source of the sixth MOS tube is grounded through the fifth resistor and the sixth resistor in sequence; the source of the sixth MOS tube is connected to the second reference voltage output terminal; The drain of the seventh MOS tube is connected to the power supply, and the source of the seventh MOS tube is connected to the drain of the eighth MOS tube; the source of the eighth MOS tube is respectively connected to the second reference voltage output terminal, the drain of the tenth MOS tube, the drain of the eleventh MOS tube, the drain of the eighteenth MOS tube, and the source of the ninth MOS tube; The gate of the tenth MOS tube is connected to the gate of the eleventh MOS tube and the gate of the eighteenth MOS tube respectively; the source of the tenth MOS tube is connected to the drain of the seventh MOS tube; the source of the eleventh MOS tube is connected to the output terminal of IBIAS1; the source of the eighteenth MOS tube is connected to the second bias current output terminal; One end of the seventh resistor is connected to the gate of the fourteenth MOS tube and the drain of the ninth MOS tube respectively, and the other end is connected to the drain of the sixteenth MOS tube; The gate of the sixteenth MOS tube is connected to the gate of the seventeenth MOS tube, the source of the sixteenth MOS tube and the source of the seventeenth MOS tube are grounded; the drain of the seventeenth MOS tube is connected to the source of the tenth MOS tube.

6. The system according to claim 3, characterized in that The power supply system in the first mode includes: The voltage source module is turned on, the reference voltage buffer module is turned on, the first voltage stabilizing module is turned on in a low power consumption state, the second voltage stabilizing module is turned off, and the power control module is turned on.

7. The system according to claim 3, characterized in that The power supply system being in the second mode includes: The voltage source module is turned on, the reference voltage buffer module is turned on, the first voltage stabilizing module is turned on in a normal power consumption state, the second voltage stabilizing module is turned on, and the power control module is turned on.

8. The system according to claim 1, characterized in that The reference voltage buffer module comprises: A nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube, a twenty-second MOS tube, a twenty-third MOS tube, a twenty-fourth MOS tube, a twenty-fifth MOS tube, a twenty-sixth MOS tube, a first capacitor, and a second capacitor; The drain of the nineteenth MOS tube is connected to the power supply, and the gate of the nineteenth MOS tube is connected to the first bias voltage output terminal; the source of the nineteenth MOS tube is respectively connected to the source of the twentieth MOS tube, the source of the twenty-first MOS tube, and the source of the twenty-sixth MOS tube; The gate of the 20th MOS tube is connected to the drain of the 20th MOS tube and the gate of the 21st MOS tube respectively; the drain of the 20th MOS tube is connected to the drain of the 22nd MOS tube; The gate of the twenty-second MOS tube is connected to the second reference voltage output terminal, and the source of the twenty-second MOS tube is connected to the drain of the twenty-fourth MOS tube and the source of the twenty-third MOS tube respectively; The gate of the twenty-fourth MOS transistor is connected to the second bias voltage output terminal, and the source of the twenty-fourth MOS transistor is grounded; The drain of the twenty-first MOS tube is respectively connected to the gate of the twenty-sixth MOS tube, one end of the first capacitor and the drain of the twenty-third MOS tube; the other end of the first capacitor is respectively connected to the drain of the twenty-sixth MOS tube, the voltage reference signal output end, the gate of the twenty-third MOS tube, the first end of the second capacitor and the drain of the twenty-fifth MOS tube; the other end of the second capacitor and the source of the twenty-fifth MOS tube are grounded, and the gate of the twenty-fifth MOS tube is connected to the gate of the 20th MOS tube.

9. The system according to claim 1, characterized in that The first voltage stabilizing module comprises: a twenty-seventh MOS tube, a twenty-eighth MOS tube, a twenty-ninth MOS tube, a thirtieth MOS tube, a thirty-first MOS tube, a thirty-second MOS tube, a thirty-third MOS tube, a thirty-fourth MOS tube, a thirty-fifth MOS tube, a thirty-sixth MOS tube, a thirty-seventh MOS tube, a thirty-eighth MOS tube, an eighth resistor, a ninth resistor, a tenth resistor and an eleventh resistor; wherein the nineteenth MOS tube is an intrinsic tube; The source of the twenty-seventh MOS tube is connected to the first bias current output terminal, the gate of the twenty-seventh MOS tube is connected to the feedback voltage output terminal, the drain of the twenty-seventh MOS tube is respectively connected to the drain and gate of the twenty-ninth MOS tube, and the source of the twenty-ninth MOS tube is grounded; The gate of the 28th MOS tube is connected to the VREF output terminal, the drain of the 28th MOS tube is respectively connected to the gate of the 31st MOS tube, the gate of the 30th MOS tube, and the drain of the 30th MOS tube, and the source of the 30th MOS tube is grounded; The drain of the thirty-first MOS tube is connected to the second bias current output terminal, and the source of the thirty-first MOS tube is grounded; The gate of the thirty-second MOS tube is connected to the second bias current output terminal, and the drain of the thirty-second MOS tube is connected to the third bias current output terminal and the gate of the thirty-third MOS tube respectively; The source of the thirty-third MOS tube is connected to the drain of the thirty-fourth MOS tube, the gate of the thirty-fourth MOS tube and the gate of the thirty-fifth MOS tube, and the drain of the thirty-third MOS tube is grounded through the eighth resistor; The source of the thirty-fourth MOS tube and the source of the thirty-fifth MOS tube are connected to a power source; One end of the ninth resistor is respectively connected to the drain of the thirty-fifth MOS tube and the analog circuit working voltage output terminal, and the other end of the ninth resistor is respectively connected to the feedback voltage output terminal and one end of the tenth resistor; the other end of the tenth resistor is respectively connected to one end of the eleventh resistor and the source of the thirty-sixth MOS tube, and the other end of the eleventh resistor and the drain of the thirty-sixth MOS tube are grounded; The gate of the thirty-sixth MOS tube is respectively connected to the drain of the thirty-seventh MOS tube and the drain of the thirty-eighth MOS tube, the source of the thirty-seventh MOS tube is connected to the voltage reference signal output end, the gate of the thirty-seventh MOS tube and the gate of the thirty-eighth MOS tube are connected to the control signal output end of the power control module; the source of the thirty-eighth MOS tube is grounded.

10. An electronic device, characterized in that: Comprising a power supply system as claimed in any one of claims 1 to 9.

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