A quantized transaction processor based on risc-v instruction extensions

Abstract

The application discloses a quantification transaction processor based on RISC-V instruction extension, which comprises a quantification transaction strategy special instruction set for realizing quantification transaction strategies and technical indexes, and a quantification transaction processor micro-architecture for realizing the special instruction set and realizing quantification transaction. The technical scheme of the application can improve the efficiency of calculating various transaction strategies and technical indexes.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, and in particular relates to a quantitative trading processor based on RISC-V instruction extension. Background Technology

[0002] With the development of the financial sector, a technological investment decision-making method, quantitative trading, has emerged. Quantitative trading refers to replacing subjective human judgment with advanced mathematical models. It utilizes computer technology to sift through massive amounts of historical data to identify multiple "high-probability" events that can generate excess returns, thereby formulating strategies. This significantly reduces the impact of investor sentiment fluctuations and avoids irrational investment decisions made during periods of extreme market euphoria or pessimism. Driven by computer systems, software technology, and algorithm theory, quantitative trading and its strategies have developed rapidly. However, timeliness is a significant constraint in the financial sector. As strategy complexity and computational efficiency requirements increase, the efficiency gains from algorithm optimization are no longer sufficient; dedicated processors are needed to further enhance efficiency. Summary of the Invention

[0003] The technical problem to be solved by this invention is to provide a quantitative trading processor based on RISC-V instruction extensions, which can improve the efficiency of calculating various trading strategies and technical indicators.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] A quantitative trading processor based on RISC-V instruction extensions, comprising:

[0006] A dedicated instruction set for quantitative trading strategies, used to implement quantitative trading strategies and technical indicators;

[0007] The quantitative trading processor microarchitecture is used to implement the aforementioned dedicated instruction set to enable quantitative trading.

[0008] As a preferred option, the dedicated instruction set for quantitative trading strategies includes: control instructions, computation instructions, and memory access instructions; among which...

[0009] The control commands include: synchronization commands and loop commands;

[0010] The operation instructions include: indicator operation instructions and vector operation instructions. The indicator operation instructions include: moving average instruction MA, average true range instruction ATR, relative strength index instruction RSI, trend indicator instruction CCI, standard deviation index instruction STD, channel range indicator instruction Range, and Turtle technical indicator instruction Turtle. The vector operation instructions include: vector addition and subtraction instructions and vector logical operation instructions.

[0011] Memory access instructions include: vector access and transfer instructions.

[0012] As a preferred embodiment, the microarchitecture of a quantitative trading processor includes: an instruction fetch unit, an execution unit, and a strategy computation unit; wherein...

[0013] The instruction fetching unit is used to prefetch, sort, distribute, and schedule different types of instructions;

[0014] The execution unit is used to distribute instructions to the corresponding arithmetic units for execution according to different instruction types, and is also used to maintain the data correlation of instructions;

[0015] The strategy calculation unit is used to receive strategy instructions, configure internal operators, and calculate various strategies and technical indicators.

[0016] Preferably, the policy computation unit includes: a policy unit decoder, a vector loading and import module and a vector register, a policy unit write-back module and an operator module; wherein...

[0017] The strategy unit decoder is used to fully decode custom instructions, obtain all instruction information, including policy calculation configuration information, data processing address, operation type and read / write operation information, and pass it to the operator module;

[0018] The vector loading and import module and vector register are used to store vector data and implement vector loading and import instructions;

[0019] The strategy unit write-back module is used to save the calculation results of each instruction and write the results back to the correct location through configuration information;

[0020] The operator module is used to calculate trading strategies, technical indicators, and vector operations, including the MA moving average operator, ATR volatility range operator, RSI relative strength operator, CCI trend indicator operator, STD standard deviation operator, Range channel range indicator operator, and Turtle technical indicator operator.

[0021] Preferably, the address generator in the instruction fetching unit is connected to the pre-branch prediction module and the bus control module to generate the instruction address. The bus control module is connected to the bus interface unit and the instruction memory, and is connected to the pre-decoding module and the value distribution module in the execution unit through a selector. The value distribution module is connected to the control instruction judgment module and the arithmetic operation unit, long instruction unit, load memory unit, and policy decoder in the policy calculation execution unit, respectively, for executing different types of instructions. The policy decoder is connected to the data interface and the operator module, and is used to allocate the policy instruction to different modules according to the type of policy instruction. The data interface module is connected to the vector register through the vector loading import module, and is also connected to the policy unit write-back module. The execution unit is connected to the write-back register module together with the delivery module through the write-back arbitration selector.

[0022] As a preferred approach, the instruction execution flow is as follows: Instructions are pre-stored in the instruction memory. The address generator generates the instruction address PC and sends it to the bus control module. The bus control module retrieves the instruction corresponding to the PC and sends it to the pre-decoding module and the value distribution module. If the instruction is a jump instruction, the jump address is directly generated after pre-branch prediction. If it is not a jump instruction, the value distribution module distributes it to the arithmetic unit, long instruction unit, load memory unit, and strategy calculation and execution unit according to different instruction types. If it is a trading strategy instruction, the instruction information is fully decoded by the strategy unit decoder. The data information input data interface module is used to obtain the data required by the instruction through the external data memory. The calculation information is input to the operator module, which schedules and configures the internal operators according to the calculation information. The operator module also receives the calculation data input from the vector register, which is input to the write-back arbitration selector through the strategy write-back module. After the delivery module adjudicates, the data is written back to the correct register position.

[0023] This invention addresses the acceleration of quantitative trading strategies by using a dedicated processor, which improves the computational efficiency of the strategy compared to general-purpose processors and software acceleration. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0025] Figure 1 This is a diagram illustrating the overall microarchitecture of a quantitative trading processor based on RISC-V instruction extensions, as described in an embodiment of the present invention.

[0026] Figure 2This is a hardware structure diagram of the control instructions in a quantitative trading processor based on RISC-V instruction extensions according to an embodiment of the present invention;

[0027] Figure 3 This is a hardware structure diagram of the MA operator in a quantitative trading processor based on RISC-V instruction extensions according to an embodiment of the present invention;

[0028] Figure 4 This is a hardware structure diagram of the ATR operator in a quantitative trading processor based on RISC-V instruction extensions according to an embodiment of the present invention;

[0029] Figure 5 This is a hardware structure diagram of the RSI operator in the quantitative trading processor based on RISC-V instruction extension according to an embodiment of the present invention;

[0030] Figure 6 This is a hardware structure diagram of the CCI operator in a quantitative trading processor based on RISC-V instruction extensions according to an embodiment of the present invention;

[0031] Figure 7 This is a hardware structure diagram of the STD operator in the quantitative trading processor based on RISC-V instruction extension according to an embodiment of the present invention;

[0032] Figure 8 This is a hardware structure diagram of the Range operator in the quantitative trading processor based on RISC-V instruction extension according to an embodiment of the present invention;

[0033] Figure 9 This is a hardware structure diagram of the Turtle operator in the quantitative trading processor based on RISC-V instruction extensions according to an embodiment of the present invention;

[0034] Figure 10 This is a hardware structure diagram of memory access instructions in a quantitative trading processor based on RISC-V instruction extensions according to an embodiment of the present invention.

[0035] Figure 11 This is a diagram illustrating the instruction dependency problem. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] Example 1:

[0039] like Figure 1 As shown, this embodiment of the invention also provides a quantitative trading processor based on RISC-V instruction extensions, comprising:

[0040] A dedicated instruction set for quantitative trading strategies, used to implement quantitative trading strategies and technical indicators at the instruction level;

[0041] A quantitative trading processor microarchitecture designed to enable quantitative trading based on a dedicated instruction set.

[0042] As one embodiment of the present invention, the dedicated instruction set for quantitative trading strategies is shown in Table 1. Based on the type of instruction, it is divided into three types: control instructions, operation instructions, and memory access instructions. The control instructions mainly include synchronization instructions and loop instructions; the operation instructions mainly include indicator operation instructions and vector operation instructions. Indicator operation instructions include Moving Average (MA), Average True Range (ATR), Relative Strength Index (RSI), Common Index (CCI), Standard Deviation (STD), Range, and Turtle technical indicators. Vector operation instructions mainly consist of basic vector operation instructions, i.e., vector addition and subtraction instructions, and also include logical vector operation instructions, i.e., vector AND, OR, and NOT instructions; the memory access instructions mainly consist of vector storage, retrieval, and transfer instructions.

[0043] Table 1

[0044]

[0045] Furthermore, control instructions are divided into synchronous instructions and loop instructions. Synchronous instructions are used to address instruction dependencies between different instruction queues, while loop instructions are used to improve the efficiency of repeatedly executing a portion of instructions. The control instruction structure is shown in Table 2. The opcode, funct3, and funct7 fields correspond to the opcode (0001011) and function code of the control instruction, respectively. The rs1 field is the PC address of the source instruction, the rs2 field is the control enable signal, and the rd field is the PC address of the destination instruction. The hardware implementation of the control instructions is as follows... Figure 2 As shown, it consists of several AND gates. The input is the instruction machine code, and the output is the control instruction type. After decoding, if the instruction is a loop instruction, the PC of the instruction to be looped is returned to the instruction fetch module. If the instruction is a synchronization instruction, a synchronization instruction is inserted between the PCs of the two target instructions.

[0046] Table 2

[0047]

[0048] Furthermore, the arithmetic instructions are the key part of the instruction set, and are divided into index arithmetic instructions and vector arithmetic instructions.

[0049] Furthermore, the indicator calculation instructions are shown in items 1-7 of Table 3. The opcode and funct3 fields represent the operation code (0101011) and function code of the indicator calculation instructions, respectively. The rs1 and rs2 fields are the addresses of the closing price and highest price data required by the indicator, respectively. The imm field is the time span or lowest price, and the rd field is the address where the indicator calculation result is stored. The hardware structure of the moving average indicator (MA) operator consists of an adder, a divider, an accumulator, and a selector, with the connections as follows: Figure 3 As shown; the hardware structure of the Mean True Range (ATR) operator consists of three subtractors, one adder, two absolute value operators, one accumulator, one divider, and two selectors, connected as follows: Figure 4 As shown; the hardware structure of the Relative Strength Index (RSI) operator consists of one adder, three subtractors, two accumulators, four dividers, and one selector, with the connections as follows: Figure 5 As shown; the hardware structure of the CCI operator consists of three adders, two subtractors, one multiplier, four dividers, two accumulators, one absolute value finder, and one selector, with the connections as follows: Figure 6 As shown; the hardware structure of the standard deviation index (STD) operator consists of two adders, one subtractor, one multiplier, two dividers, two accumulators, a square root operator, and a selector, with the connections as follows: Figure 7 As shown; the hardware structure of the Range operator for the channel range index consists of two subtractors, two maximum value finders, two minimum value finders, and two selectors, connected as follows: Figure 8 As shown; the hardware structure of the Turtle operator in the Turtle technical indicator consists of a maximum value finder, a minimum value finder, and two selectors, connected as follows: Figure 9 As shown.

[0050] Table 3

[0051]

[0052] Furthermore, vector operation instructions include basic vector operation instructions and vector logical operation instructions. Basic vector operation instructions include vector addition and subtraction instructions. The instruction structure is shown in items 8-9 of Table 3. The opcode and funct3 fields correspond to the opcode (1011011) and function code of the basic vector operation instructions, respectively. The rs1 and rs2 fields are the addresses of the input vectors, the imm field is the vector size, and the rd field is the address where the calculated output vector is stored. Vector logical operation instructions are shown in items 10-11 of Table 3. The opcode and funct3 fields correspond to the opcode (1011011) and function code of the scalar arithmetic operation instructions, respectively. The rs1 and rs2 fields are the addresses of the input vectors, the imm field is the vector size, and the rd field is the address where the vector calculation result is stored.

[0053] Furthermore, memory access instructions include vector access instructions. The instruction structure for memory access instructions is shown in Table 4. The opcode and funct3 fields correspond to the opcode (1111011) and function code of the memory access instruction, respectively. The rs1 and offset fields are the base address and offset address of the vector, respectively. The imm field is the vector size, and the rd field is the address of the destination register. The hardware implementation of memory access instructions is as follows: Figure 10 As shown, this is used to implement data transfer between memory and registers.

[0054] Table 4

[0055]

[0056] As one embodiment of the present invention, the quantitative trading processor microarchitecture includes: an instruction fetching unit, an execution unit, and a strategy calculation unit.

[0057] Furthermore, the instruction fetch unit implements the instruction queue design, where instructions are fed into their corresponding instruction queues via a pre-decoder. In the microarchitecture, instruction queues are divided into three types: control instruction queues, arithmetic instruction queues, and memory access instruction queues. Instructions from different queues are issued out of order, while those from the same queue are executed sequentially. However, there are situations where instructions from different queues have dependencies. For example... Figure 11 As shown, the execution of instruction C requires instruction A to complete before it can proceed, and the execution of instruction E requires instruction D to complete before it can proceed. In this case, a synchronization instruction is needed to solve this problem. By introducing a synchronization instruction S between the two dependent instructions, the synchronization instruction will initiate the execution of instructions C and E only after instructions A and D have completed. Although this leads to a decrease in instruction parallelism, it reduces unnecessary data conflicts caused by instruction dependencies, greatly reducing the possibility of processor anomalies.

[0058] Furthermore, the execution unit receives instructions from the instruction fetch unit, first determining the instruction type, and then distributing it to different processing units according to the instruction queue, including the arithmetic unit, long instruction unit, and load-memory unit. It also includes write-back arbitration, which writes the result back to the corresponding memory or register based on the different instructions. The execution unit is used to implement the processor's basic instruction set.

[0059] Furthermore, the policy computation unit includes a policy unit decoding module, a data interface, a vector register, a policy unit write-back module, and several execution operators. The policy unit decoding module receives instructions of the operation type and first decodes them, including parsing the instruction format, identifying the operation type, and extracting parameters. After decoding, the policy unit decoding module configures the operator's functionality according to the instruction content. The operators here include the arithmetic logic unit (ALU) and the hardware implementation modules for each instruction mentioned in S1. The policy unit decoding module configures the operators to perform specific tasks, including setting the operator's operation mode, precision requirements, and resource allocation. After configuration, the policy unit decoding module starts the operator and puts it into an enabled state, i.e., ready to execute the computation task. Simultaneously, the policy unit decoding module also drives the data interface, which is the channel for system interaction with external storage or memory. The data interface is responsible for reading necessary input data from memory or other data sources, providing source data for the operator's operation. After the operation is completed, the operator writes the generated result to the corresponding memory location in the system through the data interface. The policy execution unit also includes a data storage section, including DMA, cache, NRAM neural network memory, WRAM weight memory, and DRAM data memory. When the storage module receives a memory access instruction, it reads neuron data from DRAM into NRAM and weight data into WRAM. Upon receiving a read data enable from the computation module, it reads neuron data from NRAM, preprocesses the neuron data, and then sends it to the MFU (Matrix Function Unit). The MFU, upon receiving the instruction, receives the preprocessed neuron data from the VFU (Variable Function Unit) and reads the weight data from WRAM. After computation, it writes the result back to NRAM. If an index calculation instruction is received, it retrieves the required data from DRAM and sends it to the SFU (Structured Function Unit) to calculate the technical index, then writes the result back to DRAM.

[0060] This invention's processor calculates technical indicators and trading strategies by designing seven quantitative trading technical indicator instructions and expanding the strategy operator execution unit. Leveraging the repetitive mathematical operations between different trading strategies, the processor analyzes and decomposes trading strategies, designs instructions for these repetitive operations, and utilizes the scalability of the RISC-V architecture to integrate technical indicator operators, effectively improving the computational efficiency of trading strategies and technical indicators.

[0061] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A quantized transaction processor based on RISC-V instruction extension, characterized in that, The application relates to a quantification transaction processor micro-architecture and a quantification transaction strategy special instruction set. The quantification transaction processor micro-architecture is used for implementing the special instruction set and realizing quantification transaction. The quantification transaction strategy special instruction set comprises control instructions, operation instructions and memory access instructions. The control instructions comprise synchronization instructions and loop instructions. The operation instructions comprise index operation instructions and vector operation instructions, the index operation instructions comprise a moving average line instruction MA, an average true fluctuation range instruction ATR, a relative strength index instruction RSI, a trend index instruction CCI, a standard deviation index instruction STD, a channel range index instruction Range and a turtle technical index instruction Turtle, and the vector operation instructions comprise vector addition and subtraction instructions and vector logical operation instructions. The memory access instructions comprise vector access and transfer instructions. The quantification transaction processor micro-architecture comprises a fetch unit, an execution unit and a strategy calculation unit. The fetch unit is used for pre-fetching, sequencing, distributing and scheduling different types of instructions. The execution unit is used for distributing different instructions to corresponding operation units for execution and maintaining data correlation of the instructions. The strategy calculation unit is used for receiving strategy instructions, configuring internal operators and calculating each strategy and technical index. The strategy calculation unit comprises a strategy unit decoder, a vector loading import module and a vector register, a strategy unit write-back module and an operator module. The strategy unit decoder is used for fully decoding self-defined instructions, obtaining all instruction information, including configuration information of strategy calculation, processing data addresses, operation types and read-write operation information, and delivering the information to the operator module. The vector loading import module and the vector register are used for storing vector data and implementing vector loading import instructions. The strategy unit write-back module is used for saving calculation results of each instruction and writing the results back to correct positions through configuration information. The operator module is used for implementing calculation of transaction strategies, technical indexes and vector operations, including an MA average line operator, an ATR fluctuation range operator, an RSI relative strength operator, a CCI trend index operator, an STD standard deviation operator, a Range channel range index operator and a Turtle turtle technical index operator. An address generator in an instruction acquisition unit is connected with a pre-branch prediction module and a bus control module to generate instruction addresses, the bus control module is connected with a bus interface unit and an instruction memory, and is connected to a pre-decoding module and a fetch distribution module in an execution unit through a selector, the fetch distribution module is connected with a control instruction judgment module and an arithmetic operation unit, a long instruction unit, a loading and storing unit and a strategy decoder in a strategy calculation execution unit, and is respectively used for executing different types of instructions; the strategy decoder is connected with a data interface and an operator module, is used for distributing different modules according to types of strategy instructions, the data interface module is connected with a vector register through a vector loading import module, and is also connected with a strategy unit write-back module; the execution unit is connected with a delivery module to a write-back register module through a write-back arbitration selector.

2. The quantized transaction processor based on RISC-V instruction extension according to claim 1, wherein, ​ 3. The quantized transaction processor based on RISC-V instruction extension according to claim 2, characterized in that, The instruction execution flow is as follows: instructions are stored in advance in an instruction memory, an address generator generates an instruction address PC to a bus control module, the bus control module takes out the instruction corresponding to the PC to a pre-decoding module and a fetch distribution module; if the instruction is a jump instruction, a jump address is directly generated through pre-branch prediction; if it is not a jump instruction, the fetch distribution module distributes it to an arithmetic operation unit, a long instruction unit, a load storage unit and a strategy calculation execution unit according to different instruction types; if it is a transaction strategy instruction, the instruction is fully decoded by a strategy unit decoder, data information is input into a data interface module to obtain data required by the instruction through an external data memory, calculation information is input into an operator module to schedule and configure internal operators, the operator module also receives calculation data input from a vector register, and the calculation data is input into a write-back arbitration selector through a strategy write-back module and is arbitrated by a delivery module to be written back to a correct register position.

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