A method and system for debugging and running brain-like computing chips

Abstract

The present invention discloses a method and system for debugging and running a brain-like computing chip. Compared with the prior art, the system includes a host computer and a slave computer. The host computer and the slave computer are connected through a transmission control protocol to improve the reliability of communication transmission. A command buffer module is introduced into the host computer. The host computer packages communication data and a command header into the command buffer module to achieve a one-time connection between the host computer and the slave computer, thereby reducing the overhead of multiple connections and improving communication efficiency. In the slave computer, a sending module and a receiving module of a field programmable gate array based on a first-in-first-out queue and a handshake mechanism play a role in buffering communication data, thereby achieving congestion control of communication data and reducing communication complexity.

Description

Technical Field

[0001] The present invention relates to the field of brain-like artificial intelligence technology, and in particular to a method and system for debugging and running brain-like computing chips. Background Art

[0002] In order to solve the problems of low computing efficiency and high energy consumption of the central processing unit (CPU) when processing large amounts of data, there are currently two development routes: one is to continue using the traditional von Neumann architecture, which is mainly represented by three types of chips, including graphics processing units (GPU), field programmable gate arrays (FPGA) and application-specific integrated circuits (ASIC); the other is to use the human brain neuron structure to design chips to enhance computing power, with the goal of complete anthropomorphism, and the pursuit of continuously approaching the human brain in chip architecture. These chips are called brain-like computing chips.

[0003] Brain-like computing chips are one of the architectures of artificial intelligence chips. They are designed to simulate the human brain and have greater advantages in power consumption and learning ability than traditional chips. Traditional computer chips are designed in accordance with the von Neumann architecture. The storage and calculation of data are separated in space. Every time the computer performs a calculation, it needs to call back and forth between the CPU and memory. Frequent data exchange leads to low efficiency in processing massive amounts of information. In addition, when the chip is working, most of the electrical energy will be converted into heat energy, resulting in increased power consumption. Brain-like computing chips are different from the traditional von Neumann storage and calculation separation characteristics. Brain-like computing chips realize efficient information processing based on bionic pulse neurons. They have the technical advantages of low power consumption and low latency. They are one of the potential technologies to break the "memory wall". They have broad application value and potential in the field of edge computing that is sensitive to power consumption and latency. At present, countries and organizations such as the European Union, the United States, and Switzerland have successively carried out relevant research and released a number of brain-like computing chips, such as TrueNorth released by IBM in 2015; Intel released Loihi in 2017 to support online self-learning; Tsinghua University's "Tianji Chip" appeared on the cover of Nature in 2019. In 2020, the Darwin II generation of brain-like computers jointly developed by Zhejiang University and Zhijiang Laboratory was released.

[0004] The application of brain-like computing chips involves a complete data communication process from the host computer to the lower-level brain-like computing chip. These communications include the configuration information of the host computer initiating the operation and reset of the brain-like computing chip, the data that needs to be written to the corresponding neurons, the input pulse data, etc. There are two parts of data communication involved, one is the communication from the host computer to the lower-level brain-like computing chip, and the other is the communication during the calculation inside the brain-like computing chip. The data communication inside the brain-like computing chip has been determined when the brain-like computing chip is designed.

[0005] For data communication from the host computer to the lower computer brain-like computing chip, the invention application with the publication number CN117973467A discloses a network structure and communication method for ultra-large-scale brain-like chips. The configuration and data are sent separately, and the data transmission direction is controlled by bus control signals. The host computer and the lower computer are connected through the User Datagram Protocol (UDP), and the lower computer and the brain-like computing chip communicate through the Universal Asynchronous Receiver / Transmitter (UART). In this method, the host computer and the lower computer are transmitted through UDP, which is unreliable, and a data selector is used to solve the problem that serial communication cannot be established normally when the brain-like computing chip enters the normal working state from the hardware configuration state. However, the introduction of the data selector will increase the complexity of communication and increase the system delay. In addition, the scalability of this method is poor and cannot meet the communication needs of the increasingly diverse brain-like computing chips. Summary of the invention

[0006] The purpose of the present invention is to provide a method and system for debugging and operating brain-like computing chips, which is used to solve the problems of communication signal delay, complex communication system and unreliable communication in the debugging and operation process of existing brain-like computing chips.

[0007] To achieve the above-mentioned purpose of the invention, an embodiment provides a system for debugging and operating a brain-like computing chip, which is applied in the debugging and operating of communication data of a brain-like computing chip. The system includes a host computer and a slave computer, and the host computer and the slave computer are connected via a transmission control protocol, wherein the host computer includes a command buffer module, and the slave computer includes a command parsing module, a sending module, and a receiving module;

[0008] The command buffer module is used to store the communication data and multiple command headers output by the upper computer, and send all commands and communication data to the lower computer through the transmission control protocol;

[0009] The command parsing module is used to parse the communication data obtained from the host computer in turn, determine the type of command according to the command output by the host computer, perform different operations based on the type of command, and output the parsed data;

[0010] The sending module is used to receive the parsed data, convert the parsed data to adapt to the brain-like computing chip, and then send the data converted by the sending module to the brain-like computing chip;

[0011] The receiving module is used to receive communication data from the brain-like computing chip, convert the data calculated by the brain-like computing chip to adapt to the command parsing module, and then send the data converted by the receiving module to the command parsing module.

[0012] In one embodiment, the command header includes a read command, a write command, a pulse input command, a run command and a reset command;

[0013] The read command is used by the host computer to read communication data from the target address of the brain-like computing chip;

[0014] The write command is used by the host computer to write communication data to the target address of the brain-like computing chip;

[0015] The pulse input command is used to input pulse information into the target core of the brain-like computing chip;

[0016] The operation command is used to initiate an operation signal to the brain-like computing chip;

[0017] The reset command is used to initiate a reset signal to the brain-like computing chip.

[0018] In one embodiment, the command header is formed by encoding based on the command, and the encoding length of a command header is 32 bits, represented as [31:0]. The encoding length is divided, and each bit width after the division performs a corresponding function. The bit width includes: [1:0], [4:2], [5], [15:6] and [31:16];

[0019] The bit width [1:0] indicates the direction, which is used to select the direction from which the communication data is input to the brain-like computing chip;

[0020] The bit width [4:2] indicates the command type;

[0021] The bit width [5] represents the stop bit, which is used to determine whether to stop the connection between the upper computer and the lower computer;

[0022] The bit width [15:6] represents a reserved bit, which is used to reserve a command;

[0023] The bit width [31:16] represents the microchip count, which is used to calculate the amount of communication data transmitted based on the write command, the read command and the pulse transmission command.

[0024] In one embodiment, the sending of all commands and communication data to the lower computer via the transmission control protocol includes: based on the transmission control protocol, the upper computer inputs all commands and communication data into the command buffer module and then establishes a connection with the lower computer; after the upper computer and the lower computer are connected, the upper computer transmits all commands and communication data to the lower computer.

[0025] In one embodiment, the type of command is determined according to the command output by the upper computer, and different operations are performed based on the type of command, including: when the lower computer receives a command from the upper computer, if it is a run command or a reset command, the lower computer directly initiates a run or reset request to the brain-like computing chip; if it is a read command, a write command or a pulse input command, the length of the communication data transmission is parsed based on the command parsing module, and the communication data is sent to the sending module for processing.

[0026] In one embodiment, the conversion of the parsed communication data to adapt to the brain-like computing chip module includes: temporarily storing the parsed communication data in a first-in-first-out queue, processing the parsed communication data according to the command type based on a field programmable gate array, and the sending module converting the processed communication data into communication data that can be recognized by the brain-like computing chip interface.

[0027] In one embodiment, the conversion of the communication data calculated by the brain-like computing chip to adapt to the command parsing module includes: temporarily storing the communication data calculated by the brain-like computing chip in a first-in-first-out queue, processing the communication data output by the brain-like computing chip according to the command type based on a field programmable gate array, and the receiving module converting the processed communication data into communication data that can be recognized by the command parsing module interface.

[0028] The present invention also provides a method for debugging and running a brain-like computing chip, comprising the following steps:

[0029] Based on the host computer, the communication data and command header required by the brain-like computing chip are placed in the command buffer module, and a connection is established with the lower computer through the transmission control protocol;

[0030] The communication data and commands output by the host computer are transmitted to the command parsing module, which parses the received communication data based on the type of command and outputs the parsed data;

[0031] The parsed communication data is transmitted to the sending module, and after conversion by the sending module, it is transmitted to the brain-like computing chip for calculation;

[0032] After the communication data calculated by the brain-like computing chip is returned to the command parsing module through the receiving module, it is returned to the host computer based on the connection between the host computer and the slave computer.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] Compared with the prior art, the method and system for debugging and running brain-like computing chips provided by the present invention include a host computer and a slave computer. The host computer and the slave computer are connected through a transmission control protocol to improve the reliability of communication transmission. A command buffer module is introduced into the host computer. The host computer packages communication data and command headers into the command buffer module to achieve a one-time connection between the host computer and the slave computer, reducing the overhead of multiple connections and improving communication efficiency. In the slave computer, the sending module and the receiving module of the field programmable gate array based on a first-in-first-out queue and a handshake mechanism play the role of communication data buffering, realizing congestion control of communication data and reducing communication complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0036] Figure 1 A schematic diagram of the system structure for debugging and running brain-like computing chips;

[0037] Figure 2 It is the communication mode between the upper computer and the lower computer based on the command buffer module;

[0038] Figure 3 This is the workflow diagram of the host computer;

[0039] Figure 4 This is the workflow diagram of the lower computer;

[0040] Figure 5 It is the communication method between the command parsing module and the brain-like computing chip. DETAILED DESCRIPTION

[0041] To make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific implementation methods described herein are only used to explain the present invention and do not limit the scope of protection of the present invention.

[0042] The brain-like computing chip is a computing hardware inspired by the human brain nervous system, which has dendrite storage areas, axon storage areas, etc., as well as some external interfaces, which requires that the data input into the brain-like computing chip must follow the specified interface protocol. The application requires the host computer to configure the dendrite table and axon table of the brain-like computing chip in the slave computer, and the host computer initiates the debugging, operation, reset and other functions of the brain-like computing chip. Most brain-like computing chips are driven by time steps (TimeStep). The brain-like computing chip in this embodiment is initiated by the operation signal (tick signal), and the reset operation of the brain-like computing chip is initiated by the reset signal (rst signal).

[0043] like Figure 1 As shown, the system for debugging and running brain-like computing chips provided by the embodiment is used in the debugging and operation of communication data of brain-like computing chips, and mainly includes two parts. The first part is composed of a command buffer module of the upper computer and a command parsing module of the lower computer. The upper computer will input multiple commands and communication data of this application into the command buffer module. This part can transmit all commands and communication data to the lower computer for command parsing and processing after establishing a connection between the upper computer and the lower computer.

[0044] The second part is mainly composed of a sending module (TX module) and a receiving module (RX module). The parsed communication data is input into the brain-like computing chip through the TX module. Since there is still a certain gap between the communication data parsed by the command parsing module and the communication data required by the brain-like computing chip, and there is a mismatch between the communication speed between the host computer and the slave computer and the communication speed of the brain-like computing chip, the TX module here mainly plays the role of communication data conversion and communication data buffering. Similarly, the communication data calculated by the brain-like computing chip is returned to the host computer through the RX module.

[0045] like Figure 2 The figure shows the communication method between the upper computer and the lower computer based on the command buffer module. The upper computer's calling operations on the brain-like computing chip include chip configuration, neuron state reading, pulse input, etc., which can be summarized into five basic command operations, which can be summarized as read command, write command, pulse input command, run command and reset command, as shown in Table 1.

[0046] Table 1 Command header types and functions

[0047]

[0048] The function of the write command is to write some communication data to the target address in the storage area of ​​the brain-like computing chip, which needs to be implemented by transmitting a write packet to the chip; the function of the read command is to read the content stored in the target address in the storage area of ​​the brain-like computing chip, which needs to be implemented by transmitting a read packet to the chip; the pulse input command requires the pulse information to be input into a core of the brain-like computing chip, which needs to be implemented by transmitting a pulse packet to the chip; a run of the brain-like computing chip is initiated by a tick signal from the Field Programmable Gate Array (FPGA), and the function of the run command is to initiate a tick signal to the brain-like computing chip to perform neuron status update calculations. The function of the reset command is to restore the entire chip to the default configuration state, which is implemented by sending an RST signal from the FPGA to the brain-like computing chip.

[0049] The initiation of the command comes from the call of the upper computer software platform to the brain-like computing chip, and only when it is passed to the brain-like computing chip through the software and hardware communication interface can the command play a role. The communication between the upper computer and the lower computer is realized at the physical level using an Ethernet cable connection, and the command needs to be encoded to complete the transmission in the Ethernet link. In the embodiment, the above five command types are encoded into the form of a command header, as shown in Table 2.

[0050] Table 2 Command header encoding format

[0051]

[0052] The length of a command header code is 32, expressed as [31:0], which is the same as the length of the microchip. Among them, [1:0] indicates the direction from which the subsequent data packet is transmitted to the brain-like computing chip; [4:2] indicates the command type; the next 1 bit indicates whether to stop the connection between the upper computer and the lower computer; [15:6] indicates the reserved bit, which is used to reserve the command; [31:16] indicates the number of microchips transmitted by the command, which is mainly used for the data packet transmission of write commands, read commands and pulse transmission commands.

[0053] The data communication between the host computer and the slave computer is connected by Ethernet cable at the physical level, and the Transmission Control Protocol (TCP) is used at the network transmission layer to achieve reliable data transmission. TCP is a connected protocol. If a connection is established every time a command is transmitted, it will obviously reduce efficiency. Therefore, a command buffer module (Command Buffer) is designed in the host computer to handle the transmission of multiple commands. By recording multiple commands into a command buffer module, all commands in the command buffer module are transmitted in a subsequent transmission. When the connection needs to be disconnected after the transmission is completed, the stop connection flag in the command header can be set to 1 to disconnect the connection. When the host computer needs to initiate a call to the brain-like computing chip, it can write configuration, pulse input and other communication data to the command buffer module, and then initiate a command transmission to send all commands in the command buffer module to the slave computer.

[0054] In the embodiment, Figure 3 and Figure 4 The figure shows the operation flow chart of the brain-like computing chip. Figure 3 For the workflow of the host computer, Figure 4 This is the workflow of the lower computer.

[0055] like Figure 3 As shown in the figure, when starting an application, the user packs the communication data and corresponding command headers required by the application into the command buffer module, and then establishes a reliable TCP connection with the lower computer. If the TCP connection is successfully established, the command header and corresponding communication data will be taken out in turn and sent to the lower computer through this TCP connection. If these commands contain read commands, the connection will remain connected until the corresponding return ends.

[0056] like Figure 4 As shown in the figure, after the lower computer is initialized, it will listen for TCP connections. When the lower computer establishes a TCP connection with the upper computer, the command parsing module will obtain and parse the command header. If it is a run command, it will immediately send a tick signal to the brain-like computing chip; if it is a reset command, it will immediately send an rst signal to the brain-like computing chip; if it is a read-write command or a pulse input command, it will send the following communication data to the TX module according to the information in the command header; in particular, if it is a read command, it will wait for the communication data calculated by the brain-like computing chip to return, and hand over the communication data to the RX module, and then return it to the upper computer through the command parsing module.

[0057] In the embodiment, it is considered that there may be a mismatch between the communication speed between the upper computer and the lower computer and the communication speed of the brain-like computing chip. Therefore, a first-in first-out queue (FIFO) is designed for both the TX module and the RX module to implement congestion control and solve the complexity problem of the communication system. Figure 5 As shown, one side of the TX module is connected to the command parsing module, and the data after command parsing is temporarily stored in the FIFO, and then input to the TX module for data processing. If it is a run command, the FPGA will call the run command of the brain-like computing chip at this time. If it is a reset command, the FPGA will call the reset command of the brain-like computing chip. For read commands, write commands and pulse input commands, the command parsing module will parse out the communication data and length information actually to be input to the brain-like computing chip according to the input command type, and input the information parsed by the command parsing module to the TX module; the other side of the TX module is connected to the external interface of the brain-like computing chip. After receiving the parsed information, the TX module will organize the information into data that can be recognized by the brain-like computing chip interface, and input it to the brain-like computing chip through the corresponding interface.

[0058] The RX module is similar to the TX module. For data from the brain-like computing chip, the RX module will store the received data in the FIFO. When the brain-like computing chip does not return communication data within a period of time, it is considered that the communication data transmission returned by the chip has ended. After passing through the command parsing module, it establishes a connection with the host computer and returns the communication data to the host computer.

[0059] The specific implementation methods described above provide a detailed description of the technical solutions and beneficial effects of the present invention. It should be understood that the above is only the most preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, supplements and equivalent substitutions made within the scope of the principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A system for debugging and running brain-like computing chips, characterized in that: It is used in the debugging and operation of communication data of brain-like computing chips. The system includes a host computer and a slave computer, and the host computer and the slave computer are connected through a transmission control protocol. The host computer includes a command buffer module, and the slave computer includes a command parsing module, a sending module and a receiving module. The command buffer module is used to store the communication data and multiple command headers output by the host computer, and send all commands and communication data to the slave computer through the transmission control protocol, wherein the command header includes a read command, a write command, a pulse input command, a run command and a reset command; The read command is used by the host computer to read communication data from the target address of the brain-like computing chip; The write command is used by the host computer to write communication data to the target address of the brain-like computing chip; The pulse input command is used to input pulse information into the target core of the brain-like computing chip; The operation command is used to initiate an operation signal to the brain-like computing chip; The reset command is used to initiate a reset signal to the brain-like computing chip; The command header is formed by encoding based on the command. The encoding length of a command header is 32 bits, which is represented by [31:0]. The encoding length is divided, and each bit width after the division performs a corresponding function. The bit width includes: [1:0], [4:2], [5], [15:6] and [31:16]; the bit width [1:0] indicates the direction, which is used to select the direction from which the communication data is input to the brain-like computing chip; the bit width [4:2] indicates the command type; the bit width [5] indicates the stop bit, which is used to determine whether to stop the connection between the upper computer and the lower computer; the bit width [15:6] indicates the reserved bit, which is used to reserve the command; the bit width [31:16] indicates the microchip count, which is used to calculate the amount of communication data transmitted based on the write command, the read command and the pulse transmission command; The command parsing module is used to parse the communication data obtained from the host computer in turn, determine the type of command according to the command output by the host computer, perform different operations based on the type of command, and output the parsed communication data; The sending module is used to receive the parsed communication data, convert the parsed communication data to adapt to the brain-like computing chip, and then send the communication data converted by the sending module to the brain-like computing chip; The receiving module is used to receive the communication data calculated by the brain-like computing chip, convert the communication data calculated by the brain-like computing chip to adapt to the command parsing module, and then send the communication data converted by the receiving module to the command parsing module.

2. The system for debugging and running brain-like computing chips according to claim 1, characterized in that: The method of sending all commands and communication data to the lower computer through the transmission control protocol includes: based on the transmission control protocol, the upper computer inputs all commands and communication data into the command buffer module and then establishes a connection with the lower computer. After the upper computer and the lower computer are connected, the upper computer transmits all commands and communication data to the lower computer.

3. The system for debugging and running brain-like computing chips according to claim 1, characterized in that: The method of judging the type of command according to the command output by the upper computer and performing different operations based on the type of command includes: when the lower computer receives the command from the upper computer, if it is a run command or a reset command, the lower computer directly initiates a run or reset request to the brain-like computing chip; if it is a read command, a write command or a pulse input command, the length of the communication data transmission is parsed based on the command parsing module, and the communication data is sent to the sending module for processing.

4. The system for debugging and running brain-like computing chips according to claim 1, characterized in that: The conversion of the parsed communication data to adapt to the brain-like computing chip module includes: temporarily storing the parsed communication data in a first-in-first-out queue, processing the parsed communication data according to the command type based on a field programmable gate array, and the sending module converting the processed communication data into communication data that can be recognized by the brain-like computing chip interface.

5. The system for debugging and running brain-like computing chips according to claim 1, characterized in that: The method of converting the communication data calculated by the brain-like computing chip to adapt to the command parsing module includes: temporarily storing the communication data calculated by the brain-like computing chip in a first-in-first-out queue, processing the communication data output by the brain-like computing chip according to the command type based on the field programmable gate array, and the receiving module converting the processed communication data into communication data that can be recognized by the command parsing module interface.

6. A method for debugging and running a brain-like computing chip, characterized in that: The method uses the system for debugging and running a brain-like computing chip according to any one of claims 1 to 5, comprising the following steps: Based on the host computer, the communication data and command header required by the brain-like computing chip are placed in the command buffer module, and a connection is established with the lower computer through the transmission control protocol; The communication data and commands output by the host computer are transmitted to the command parsing module, which parses the received communication data based on the type of command and outputs the parsed data; The parsed communication data is transmitted to the sending module, and after conversion by the sending module, it is transmitted to the brain-like computing chip for calculation; After the communication data calculated by the brain-like computing chip is returned to the command parsing module through the receiving module, it is returned to the host computer based on the connection between the host computer and the slave computer.

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