Circuits and methods for radar, light or camera systems

Abstract

The invention relates to a circuit system, a method, a computer program product and a non-volatile computer-readable storage medium, which can be used, for example, for a radar system, a light system or a camera system. The invention relates to a circuit system comprising at least two individual logic modules (10) which are connected to each other by means of a connection device (20) in such a way that data processing (40) can be performed by the at least two individual logic modules (10) by means of a combination of a respective memory (11) and a computing unit (12).

Description

Technical Field

[0001] The invention relates to a circuit system having the features of independent claim 1, a method having the features of independent claim 12, a computer program product having the features of independent claim 14 and a non-volatile computer-readable storage medium having the features of independent claim 15. Background Art

[0002] Known radar systems and components used therefor are becoming increasingly powerful. This can be attributed primarily to the fact that radar systems usually have a plurality of transmitting devices, receiving devices and / or transceivers, in particular data is generated during reception. In addition, so-called corner radar systems are known, which have good results when imaging with a relatively small number of transmitting and / or receiving devices, in particular antennas, as well as memory and / or computing power. However, at the same time, the cost pressures in production, installation and / or maintenance are becoming increasingly greater. In particular, the weight and / or installation space should not be too large.

[0003] In order to meet the ever-increasing demands for more performance, especially for range and / or angle measurement capabilities, the number of antennas can (or must) be significantly increased. This can concern the antennas on the one hand, but also the subsequent data processing in the RF chain (HF-Kette). This can be achieved with the help of existing RF modules, such as MMICs (monolithic microwave integrated circuits) and / or µC / DSPs (microcontrollers / digital signal controllers) or FPGAs (field programmable gate arrays). In addition, there are cost-optimized monolithic integrated circuits (ICs) (or single logic modules) on the market and in development, in which the µC / DSP and the RF part are integrated in one module.

[0004] However, the storage and / or computing capacity of such a monolithic integrated circuit or a single logic module is usually insufficient for storing and / or computing all necessary data, especially for real-time computing for the above requirements, especially in high-performance fields such as automobiles.

[0005] In this case, for example, computers or computing units have hitherto been provided in particular separately or externally in order to cope with the high storage and / or computing requirements and preferably to enable (complete) computing and / or essentially real-time computing. Summary of the invention

[0006] The object of the present invention is therefore to at least partially overcome at least one of the above disadvantages. In particular, the object of the present invention is to use any single logic modules in such a way that simpler, improved, less expensive, modular, expandable and / or replaceable production, installation and / or maintenance can be achieved.

[0007] The above-mentioned object is achieved by a circuit system having the features of independent claim 1, by a method having the features of independent claim 12, by a computer program product having the features of independent claim 14 and by a non-volatile computer-readable storage medium having the features of independent claim 15. Further features and details of the invention are derived from the dependent claims, the description and the drawings. The features and details described here in conjunction with the circuit system according to the invention naturally also apply in conjunction with the method according to the invention and / or in conjunction with the computer program product according to the invention and / or in conjunction with the non-volatile computer-readable storage medium according to the invention, and vice versa, so that the disclosures concerning the various aspects of the invention always refer to each other or can refer to each other. In particular, the advantages described within the scope of the first, second, third, fourth and / or fifth aspects also apply to the first, second, third, fourth and / or fifth aspects, respectively.

[0008] The above-mentioned task is solved according to a first aspect of the present invention by a circuit system for a radar system, a lidar system or a camera system, the circuit system comprising at least two single logic modules, each of which comprises a memory and / or a computing unit, and the at least two single logic modules are interconnected via a connection device (Schaltvorrichtung or line device) so that data processing can be performed by the at least two single logic modules (only) through a combination of corresponding memories and computing units.

[0009] Preferably, the at least two single logic modules described here are interconnected so that they become a virtual large chip, and the sum of the memory and computing performance is (again) sufficient to realize advanced computing and / or storage intensive systems, such as systems with multiple channels for sending and / or receiving. In particular, the possibility of building cost-optimized and / or expandable modules based on monolithic integrated circuit modules (or single logic modules) can be realized here, and the modules can advantageously realize simpler, improved, lower-cost and / or replaceable manufacturing, installation and / or maintenance. The at least two single logic modules described here can have single logic modules with the same structure, which advantageously simplifies design and / or maintenance and can mean cost advantages. In addition, multiple single logic modules can be set, for example, not only 2, but 3, 4, 5, 6, 8, 10, 16, 24, 48, 96, 128, 256, 512 single logic modules, so as to advantageously provide expandable solutions for multi-channel systems in particular. A larger number can realize more complex and / or more advanced circuits with more number of sending, receiving and / or transceiver channels.

[0010] At least one, preferably each of the at least two single logic modules has a memory and / or a computing unit, which can be used in particular for data processing. Here, the one or more single logic modules can be basically configured as a transmitting and / or receiving unit for radar waves, which in particular has a (relatively small) computing unit for signal evaluation. The single logic module can have at least one MMIC (monolithic microwave integrated circuit) here. In this way, a particularly efficient distribution of memory and / or computing operations can be achieved. This can include, for example, receiving, converting (for example within the scope of analog-to-digital conversion and / or digital-to-analog conversion) and / or calculating steps in a radar system, such as row- and / or column-based Fourier transforms, which can in particular be performed in part by part, and can therefore be particularly suitable in order to distribute the calculation to multiple memories and / or computing units. It can be provided here that all or only a portion of the data is sent to a single logic module, and in particular data can also be forwarded here, especially data that is not necessary for partial calculations.

[0011] The memory can include or be a non-volatile transient storage medium. The memory can be an internal memory of a single logic module, which is in particular provided for storing data or data parts, such as the first data part and / or the second data part. The memories of different logic modules can preferably be designed identically in order to advantageously enable simple replacement.

[0012] The computing unit can have a CPU, FPGA, microcontroller and / or ASIC. The computing unit can be an internal computing unit of a single logic module, which is especially configured for data processing, computing operations (multiple operations and / or partial operations or operation parts), especially for separate calculations preferably separated from other single logic modules. The computing unit can calculate separate results based on (first or second, etc.) partial operations within the scope of separate calculations, so as to advantageously achieve an optimized distribution of the operations, especially so as to be able to distribute computationally intensive operations (the operations cannot be achieved by only one computing unit) to at least two computing units. This can save costs, weight and / or installation space for larger, especially external computing units.

[0013] In the scope of the present invention, the switching device, in particular configured as a switch, can have a hardware-based interconnection between the at least two single logic modules. In this case, the distribution of data and / or tasks can also be realized in software, for example by dedicated control of the single logic modules. Thus, on the one hand, a combined virtual chip can be formed. In addition, a switchable and / or expandable module system can be formed, in which components can be removed, added and / or changed, which has the effect of cost-effectiveness, environmental friendliness and / or performance improvement.

[0014] The access device can connect the memories and / or the computing units of the at least two individual logic modules in order to preferably realize a data connection which allows an exchange of data.

[0015] In this case, the circuit system, the at least two individual logic modules and / or the switching device can be provided in particular for radar systems, for example for the 24 GHz ISM band in the frequency range 24.0 GHz-24.25 GHz. However, applications in other frequency ranges (e.g. around 77 GHz) and / or methods such as in cameras and / or lidars are also conceivable.

[0016] It can be advantageous within the scope of the present invention that the connection device has a housing and is arranged on a circuit board arranged in the housing, in particular the at least two single logic modules are connected to each other via the connection device or the circuit board so that data processing can be performed only and / or only by a combination of corresponding memories and / or computing units, in particular each of the at least two single logic modules is constructed so that its memory and / or computing unit cannot perform data processing alone. It can be provided here that data processing and / or real-time data processing can be (completely) realized, in particular only by connecting the at least two single logic modules to each other. The circuit board can realize the electrical interconnection of the single logic modules, for example. In particular, it is conceivable that the circuit board has an interface to which the single logic modules can be flexibly connected and / or connected, in order to control these single logic modules and / or to realize data exchange, for example. This can realize advantageous installation and / or maintenance.

[0017] It is conceivable within the scope of the present invention that each of the at least two single logic modules has data transmission, in particular data transmission via a connection device, which includes data exchange with a memory and / or a computing unit of at least one other single logic module (preferably all other single logic modules), and the data exchange especially includes the exchange of at least one memory address, a read command and / or a write command. Preferably, the data transmission can include data exchange between a memory and / or a computing unit of the first single logic module and at least one other single logic module, in particular at least one memory and / or a computing unit of all other single logic modules. This can preferably be done via a connection device so that at least part of the central control can be advantageously achieved. Thus, for example, the improved method can be implemented centrally, while the single logic modules can preferably remain unchanged. It can be provided that a connection device is used in the case of three or more single logic modules in order to advantageously improve the data transmission.

[0018] In the context of the invention, it can be provided that the access device has a PCIe interface and / or an InfiniBand bus arrangement, to which the at least two single logic modules are connected for data transmission. As a result, one or each single logic module can access a memory and / or a computing unit of at least one other single logic module, in particular via data communication. A PCIe (Peripheral Component Interconnect Express) connection can be particularly preferred, in particular in order to enable a particularly fast, robust and / or cost-effective connection.

[0019] It is also conceivable that the connection device has a daisy chain connection, and the at least two single logic modules are directly connected to each other, especially data exchange without a switch can be realized. A particularly simple interconnection can be realized here, wherein a switch (no switch) is not particularly required for connection, which advantageously saves cost, weight and / or material. In addition, it is conceivable that a combination between a daisy chain connection, a PCIe interface and / or an Infini bandwidth bus device is set, and data exchange and / or redundancy can be advantageously optimized here. The daisy chain connection can preferably optimize, especially reduce the data rate for a single logic module and / or for each single logic module, for example because it is shared. In the case of a daisy chain connection, it is conceivable that basically only adjacent single logic modules have a (direct) connection. Therefore, low complexity and / or susceptibility to interference can be maintained. Alternatively or additionally, it is also conceivable that there is a connection with each other single logic module, so that data exchange can be optimized, so that redundancy can be advantageously prevented and faster calculation can be achieved.

[0020] It is also conceivable that the data transmission has an Ethernet connection, in particular, each of the at least two single logic modules can be connected to a switch for data transmission, in particular, the switch is provided on a switch circuit board separated from the circuit board of the connection device, and the switch circuit board can be preferably provided outside the housing of the connection device. By providing it externally, a particularly modular, replaceable, improved configuration and / or a simpler installation and / or maintenance can be achieved. In addition, a smaller susceptibility to interference or mutual influence can be achieved thereby. Being arranged on the same circuit board can mean a smaller weight and / or space requirement here. In addition, data transmission can be optimized by radio frequency technology, in particular for specific application situations. The Ethernet connection can have a particularly good compatibility with other components and / or be particularly user-friendly. It is also conceivable that the design of the connection device is flexible, in particular, for example, using an Ethernet connection, a PCIe interface and / or an Infini bandwidth bus device according to availability. Thus, particularly high flexibility and / or robustness can be achieved within the scope of maintenance. In addition, the product can therefore be particularly well connected to an existing system, such as a bus system in the automotive industry. This can advantageously save costs. Alternatively, it is conceivable that the contact-connecting device is mounted on a circuit board in the housing, in particular together with the at least two individual logic modules. This allows for more compact and / or more cost-effective production.

[0021] Within the scope of the present invention, a protocol including remote direct memory access (RDMA) can optionally be used for data exchange by data transmission, in particular to relieve the burden on the memory and / or computing unit of at least one of the at least two single logic modules. It is preferred that the burden on the memory and / or computing unit of all single logic modules can be relieved. It is preferred that the network interface controller (NIC) in the single logic module can read and / or write data independently, and the computing unit does not have to intervene for this purpose. In addition, it is also conceivable to integrate this mechanism into the NIC of the single logic module. Alternatively or additionally, the RDMA mechanism can be simulated by the computing unit, in particular for each single logic module. In particular, within the scope of Ethernet connections, the use of this protocol can ensure particularly high compatibility, efficiency and / or user-friendliness. For example, it can be provided that the access device has a MultiGMAC connection, which uses an Ethernet connection and / or an RDMA protocol, in particular, in which reading and / or writing are advantageously implemented in parallel and common calculations are advantageously implemented.

[0022] Furthermore, it can be provided within the scope of the present invention that the at least two single logic modules have LO reference clock sharing and / or digital synchronization, which can be implemented in particular via a connection device by data transmission and / or by a separate synchronization circuit between the at least two single logic modules. It can be provided here that additional (or redundant) synchronization can be implemented by the connection device or by a separate connection device. Therefore, errors or deviations in synchronization can be better and / or more reliably identified. More robust and / or redundant synchronization can also be achieved thereby. In general, the error susceptibility of the system can be reduced thereby. It can be provided here that the synchronization of the single logic modules is achieved at least partially by coordinated transmission and / or reception. This can mean or support particularly robust synchronization.

[0023] In connection with the present invention, it is conceivable that the data processing comprises at least a calculation based on the data recorded or detected by the radar system, the lidar system or the camera system, the calculation comprising a plurality of calculation operations, which in particular cannot be performed individually and / or in real time by a single single logic module, the plurality of calculation operations can be divided into preferably substantially uniform calculation operation parts, which can preferably be evenly divided between the at least two single logic modules for individual calculations, whereby the calculation can be performed and / or can be performed in real time. In particular, the calculation or the plurality of calculation operations can be performed and / or performed in real time (only) by dividing the calculation operations into the at least two single logic modules, otherwise the calculation cannot be performed, cannot be performed substantially in real time and / or can only be performed by an undesirable external, in particular heavier, bulky and / or more expensive calculation unit. By dividing, costs, installation space, complexity, weight and / or manufacturing costs, installation costs or maintenance costs can be advantageously saved. It is also conceivable that an external and / or separate memory and / or a calculation unit (for example, included by the access device) must be constructed with less storage and / or computing power. The division can advantageously save costs, installation space, complexity, weight and / or manufacturing, installation or maintenance costs. In addition, the system can be customized more flexibly to the application. A uniform division can mean that the number of computing operations is substantially halved if two single logic modules are present. This can also mean that, in the case of n single logic modules, the respective single logic module essentially performs, in particular, exactly 1 / n of the computing operations.

[0024] In addition, it is conceivable that the calculation includes a Fourier transform, especially a fast Fourier transform (FFT), and the separate calculation includes the calculation of a sub-area of ​​the Fourier transform. It can be provided here that a fast Fourier transform is performed in multiple dimensions. For example, a single logic module can calculate a one-dimensional FFT here and the other dimensions of the FFT are performed by means of other single logic modules. Particularly efficient parallelization and / or acceleration can be achieved thereby. For example, a fast chirp sequence (Fast-Chirp-Sequence) can be sent within the scope of a radar system (for example, in an FMCW radar system). The repetition rate during transmission, especially the chirp repetition rate, can be between 15 and 40 μs here, for example. The data can include ADC data here, which can especially include received data digitized by an analog-to-digital converter (ADC). For example, it can be analyzed for a chirp, preferably each chirp, especially in the time domain and preferably corrected for these data (for example, within the scope of a post-processing step). In this, a Fourier transform, especially an FFT, such as an FFT in one dimension, can be performed within 15 to 40 μs. In this case, each "Bin" (also called Range-Rbins or Rbins (range intervals)) of the FFT can correspond to a range grid (or range interval) in particular, depending on the selected chirp bandwidth. In this case, it can be provided that in particular individual columns and / or rows of a (especially discrete) two-dimensional matrix are processed individually. It can be provided that intervention is carried out precisely at this position, in particular by common or individual calculations (for example individual calculations). For example, in a circuit system with four single logic modules (for example chips 0, 1, 2, 3), approximately three quarters of the FFT data, in particular the Range-FFT data, of each single logic module can be sent to other chips, for example via an Ethernet connection. In this case, it can be provided that, for example, the following mode is used:

[0025] Chip 0:

[0026] - reserves Rbins 0 to 63 and stores them in its memory,

[0027] - Send 64 to 127 to chip 1, 128 to 191 to chip 2 and 192 to 255 to chip 3;

[0028] Chip 1:

[0029] - reserves Rbins 64 to 127 and stores them in its memory,

[0030] - Send 0 to 63 to chip 0, 128 to 191 to chip 2 and 192 to 255 to chip 3;

[0031] Chip 2:

[0032] - retains Rbins128 to 191 and stores them in its memory,

[0033] - Send 0 to 63 to chip 0, 64 to 127 to chip 1 and 192 to 255 to chip 3;

[0034] Chip 3:

[0035] - retain Rbins192 to 255 and store them in memory,

[0036] - Send 0 to 63 to chip 0, 64 to 127 to chip 1 and 128 to 191 to chip 2.

[0037] It can be provided that one of the chips or single logic modules cannot process all the data alone, especially cannot process all the data at the required speed, for example, in real time. In this case, it can be sent as described above, for example, by connecting the device or data transmission. At the end of a sequence, especially at the end of a chirp sequence (which can last for example 15 to 20ms), a quarter of the complete data (especially of the sequence) can be (basically) present in each single logic module, preferably in its memory. It can be provided that one of the at least two single logic modules, preferably all single logic modules, especially independently undertake further processing and / or post-processing steps, for example, within the scope of separate calculations. This can especially include Fourier transform, especially FFT or v-FFT on RangeBins stored in its memory. Alternatively or additionally, this can also include coherent integration of the collected (Tx / Rx) data or ADC data. Alternatively or additionally, this can also include peak detection. It is also possible to set a certain overlap in the edge region, for example, in order to optimize post-processing steps, such as pattern recognition, which will deteriorate or not work in the edge region. In the above example, at the edges (or edge regions) between the Rbins (63 / 64, 127 / 128 and 191 / 192) data can still be exchanged, e.g. to ensure no edge detection. For example a comparison can be made if a (local) maximum at the edge location is or should be verified during the calculation.

[0038] It can be advantageous within the scope of the present invention that each of the at least two single logic modules is also configured to perform at least one post-processing step based on the individual results of the individual calculations of the single logic module after the individual calculations in order to obtain a post-processing result. The post-processing can in particular include the steps described in the above example. Thus, this can include coherent integration of the collected (Tx / Rx) data or ADC data. Alternatively or additionally, this can also include peak detection, which can advantageously enable more precise detection, for example by equalization. It is also conceivable to use at least one signal filter, for example for smoothing, noise reduction and / or signal-to-noise ratio optimization, in order to advantageously improve the overall result.

[0039] According to a second aspect of the present invention, the above object is solved by a method for data processing by means of a circuit system according to the first aspect of the present invention, the method comprising at least the following steps for each of the at least two single logic modules:

[0040] The data for data processing is received by a single logic module,

[0041] storing the first data portion in a memory of the single logic module,

[0042] sending at least one second data portion to the memory of at least one further single logic module, preferably the first data portion and the at least second data portion overlapping redundantly only in edge regions,

[0043] The calculation unit of the single logic module performs individual calculations of the first arithmetic operation part based on the first data part to obtain individual results.

[0044] Receiving can include receiving data sent by another single logic module (for example, as in the above example), and in particular, a plurality of computing operations or data used therefor can be preferably divided substantially evenly among the memories and / or computing units of all single logic modules. It can also be provided that the single logic module basically processes or only processes the data forwarded to it by the sending, receiving and / or transceiving element connected to the single logic module, and the latter especially forwards the data only to one single logic module (favorable for optimization and / or simple connection) or all single logic modules (favorable for achieving optimized distribution of data, for example, favorable for improving calculation speed). The number of the at least two single logic modules can be used as a reciprocal to determine the size of the data portion (as in particular in the above example). For example, it is conceivable that in the case of two single logic modules, the first single logic module basically stores half of the data, for example, as the first data portion, in its memory, and preferably sends the other half of the data, for example, as the second data portion, to the second single logic module, and the second single logic module especially stores the second data portion in its memory. As mentioned above, a 5% data overlap can be performed in the edge area of ​​the data, and in particular, the first data portion and the second data portion share 5% of the data, that is, this part of the data is contained in the same manner in the two data sets. In the case of multiple single logic modules, the second data portion can have multiple data portions or components (as in particular in the above example), which are sent to different single logic modules, preferably in order to achieve uniform division. It can also be provided that all data not stored by a single logic module are sent to all other single logic modules respectively, and preferably each single logic module only stores the relevant data in its memory. The amount of data in the memory of the corresponding single logic module can thus be minimized. After storage and transmission, it is preferably possible to perform calculations based on the data in the memory of the corresponding single logic module. It can be provided that the first single logic module (only) performs a separate calculation based on (its) first data portion. Correspondingly, it can be provided that the second, third, etc. single logic modules (only) perform separate calculations based on the first, second, third, etc. data portions. The (necessary) memory and / or computing power can thus be divided, so that faster calculations and / or especially substantially real-time calculations can be achieved.

[0045] In the scope of the method, it can be provided that before receiving data for data processing by a single logic module, at least the following steps are performed: sending data to the single logic module by the access device, especially after the single logic module performs a separate calculation of the first operation part based on the first data part by the computing unit of the single logic module, at least one of the following steps is performed: based on the separate results, the single logic module performs a post-processing step to obtain a post-processing result, and the access device and / or the computing unit combine the separate results or the post-processing results to obtain the total result. In the scope of radar imaging, the total result can be, for example, a range profile, a range slow-time data matrix and / or a range Doppler map. The total result can then be provided to other systems of the motor vehicle, for example, in order to make a decision for autonomous driving in an advantageous manner. It can be provided here that as a post-processing step, compensation for the distance offset is performed, which is especially performed by a computing unit in a single logic module, all computing units of each single logic module together (especially distributed) and / or by a computing unit in the access device.

[0046] It is conceivable within the scope of the present invention that each single logic module has a (own) computing unit and / or a (own) memory. It is conceivable that, for example, another computing unit and / or another memory is provided in the switch-on device in addition (or alternatively). This can be advantageous for storing specific data and / or instructions in the switch-on device and / or for executing them by the switch-on device, so that the memory and / or computing operations can be saved elsewhere, especially in the single logic module, which can advantageously achieve a more cost-effective manufacturing and / or a higher flexibility. The switch-on device can also be used as a master in the generated circuit system, which can achieve a particularly efficient distribution of storage and / or computing, thereby preferably preventing and / or minimizing redundancy. It can therefore be ensured that data is not sent back and forth unnecessarily before the necessary computing operations are performed.

[0047] According to the third aspect of the invention, the above-mentioned task is solved by a computer program product according to the invention, which includes instructions that can be executed by a computing unit, in particular a single logic module, and when the computer program product is executed by the computing unit, the instructions enable the computing unit to implement the method according to the invention, in particular according to the second aspect of the invention.

[0048] According to a fourth aspect of the present invention, the above mentioned task is solved by a non-volatile computer readable storage medium according to the present invention, which comprises a computer program product according to the third aspect of the present invention.

[0049] It is also conceivable that, according to a fifth aspect, the above object is solved by a vehicle comprising a circuit system according to the first aspect of the invention and / or a non-volatile computer-readable storage medium according to the fourth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Further advantages, features and details of the invention are apparent from the following description, in which a number of embodiments of the invention are described in detail with reference to the accompanying drawings. The features mentioned in the claims and the description may be important for the invention individually or in any combination. The invention is described in detail below with reference to the accompanying drawings. The drawings are as follows:

[0051] Figure 1 Shows a single logic module and a switch-on device of a circuit system according to the present invention;

[0052] Figure 2 A circuit system having a switch-on device is shown;

[0053] Figure 3 A circuit system having a daisy chain connection is shown;

[0054] Figure 4 The method according to the present invention is shown;

[0055] Figure 5 The method according to the invention is shown, in particular a separate calculation;

[0056] Figure 6 The method according to the invention, in particular the post-processing, is shown. DETAILED DESCRIPTION

[0057] Figure 1 A single logic module 10 according to the invention is shown, which comprises a memory 11 and a computing unit 12. The memory 11 can have a non-volatile computer-readable storage medium 90 according to the fourth aspect of the invention, which can in particular include a computer program product 80 according to the third aspect. Furthermore, a connection device 20 according to the invention is shown, which can in particular additionally or alternatively have a non-volatile computer-readable storage medium 90 according to the fourth aspect of the invention, which can in particular include a computer program product 80 according to the third aspect. Furthermore, the connection device 20 can be arranged in a housing 21, which preferably completely surrounds the connection device 20 in order to protect the connection device from forces.

[0058] Figure 2The circuit system 1 according to the invention is shown, which comprises (at least) two individual logic modules 10, each of which in turn has a memory 11 and a computing unit 12. Data processing 40 can be performed in the memory 11 and / or in the computing unit 12. In particular, a first data portion 51 can be performed in the individual logic module 10 (here on the left). In particular, a second data portion 52 can be performed in the individual logic module 10 (here on the right). It can be provided that the first data portion 51 and the second data portion 52 together essentially correspond to (received or recorded) measurement data or data 50. The individual logic modules 10 can be connected via a connection device 20. In particular, a data transmission 30 can be realized via the connection device 20 to carry out a data exchange 31. The connection device 20 can have a housing 21. A printed circuit board 22 can be arranged in the housing 21, which circuit board can, for example, realize an electrical interconnection of the individual logic modules 10.

[0059] Figure 3 The circuit system 1 according to the invention is shown, which comprises (at least) two single logic modules 10, each of which has a memory 11 and a computing unit 12. A daisy chain connection 32 can be provided between the corresponding memory 11 and / or computing unit 12. As a result, the single logic modules 10 can be connected directly, so that advantageously no connection via a connection device 20 is required. This can reduce complexity and costs. Alternatively, it is conceivable to additionally provide a connection device 20 in order to advantageously achieve an even better distribution and / or optimization of storage steps and / or computing steps. Data transmission 30 or data exchange 31 can be carried out via the daisy chain connection 32. It can be provided that data 50 or data parts, such as a first data part 51 and / or a second data part 52, are received and stored 11 by the single logic module 10.

[0060] Figure 4 A method according to the invention is shown, for example, for data processing 40 by means of a circuit system 1 according to the first aspect of the invention, which method comprises at least the following steps for each of the at least two single logic modules 10:

[0061] - data 50 are sent 105 by the switched-on device 20,

[0062] - receiving 110 data 50 for data processing 40 by a single logic module 10,

[0063] - storing 120 the first data portion 51 in the memory 11 of the single logic module 10,

[0064] - sending 130 at least one second data portion 52 to the memory 11 of at least one further single logic module 10, preferably the first data portion 51 and the at least second data portion 52 overlapping redundantly only in edge regions,

[0065] - performing calculation 140 of a plurality of calculation operations 141 based on the data 50,

[0066] - Obtained total result 160.

[0067] Figure 5 A method 100 is shown, wherein in particular the steps of a calculation 140 of a plurality of calculation operations 141 are shown in more detail. The plurality of calculation operations 141 can be divided into individual calculation operation 142 parts, preferably into substantially uniform parts, which are then performed in individual calculations 143 by the first individual logic module 10, for example (only) based on the first data part 51. As a result, an individual result 144 can be determined (individually) preferably by a calculation unit 12 of one or each individual logic module 10.

[0068] Figure 6 A method 100 is shown in which a post-processing step 150 is performed based on the individual results 144 or the individual results 144 of the individual logic modules 10. The post-processing step is preferably performed individually by the respective computing unit 12 of the individual logic modules 10 in order to advantageously enable a fast and / or distributed calculation 140. In this case, a post-processing result 151 can be determined in each case. The post-processing results can then be combined to form an overall result 160. It is also conceivable that the post-processing step 150 is not performed and the overall result 160 is thus obtained directly. The overall result 160 can be combined, for example, by the connection device 20, preferably by combining the individual results 144 of all the individual logic modules 10.

[0069] Reference numerals list

[0070] 1 Circuit system

[0071] 10 single logic modules

[0072] 11 Memory

[0073] 12 computing units

[0074] 20. Connect the device

[0075] 21 Shell

[0076] 22 Circuit Board

[0077] 23Switch

[0078] 24 switch circuit board

[0079] 30Data transmission

[0080] 31Data Exchange

[0081] 32 daisy chain connection

[0082] 40 Data Processing

[0083] 50 data

[0084] 51 First data part

[0085] 52 Second data part

[0086] 80 Computer program products

[0087] 90 Storage Media

[0088] 100 Methods

[0089] 105 Data sent by connected device

[0090] 110 Data received by a single logic module

[0091] 120 Storing the first data portion

[0092] 130 Send the second data part

[0093] 140 Calculation

[0094] 141 multiple operations

[0095] 142 Operation part

[0096] 143 calculated separately

[0097] 144 individual results

[0098] 150 Post-processing steps

[0099] 151 Post-processing results

[0100] 160 total results

Claims

1. A circuit system (1) for a radar system, a lidar system or a camera system, the circuit system comprising at least two single logic modules (10), the single logic modules each comprising a memory (11) and a computing unit (12), wherein: The at least two single logic modules (10) are connected to each other via a connection device (20) so that data processing (40) can be performed by the at least two single logic modules (10) through a combination of a corresponding memory (11) and a computing unit (12).

2. The circuit system (1) according to claim 1, characterized in that The connection device (20) has a housing (21) and is arranged on a circuit board (22) arranged in the housing (21), in particular, the at least two single logic modules (10) are connected to each other via the connection device (20) so that data processing (40) can be performed only and / or only through a combination of corresponding memories (11) and / or computing units (12), in particular, each of the at least two single logic modules (10) is constructed so that its memory (11) and / or computing unit (12) cannot perform data processing (40) alone.

3. The circuit system (1) according to claim 1 or 2, characterized in that: Each of the at least two single logic modules (10) has a data transmission (30) via a connection device (20), wherein the data transmission (30) includes a data exchange (31) with a memory (11) and / or a computing unit (12) of at least one other single logic module (10), wherein the data exchange (31) in particular includes an exchange of at least one memory address, a read command and / or a write command.

4. The circuit system (1) according to any one of the preceding claims, characterized in that The connection device (20) has a PCIe interface and / or an Infini bandwidth bus device, and the at least two single logic modules (10) are connected to the PCIe interface and / or the Infini bandwidth bus device to perform data transmission (30).

5. The circuit system (1) according to any one of the preceding claims, characterized in that The connection device (20) has a daisy chain connection (32), and the at least two single logic modules (10) are directly connected to each other, in particular enabling switchless data exchange (31).

6. The circuit system (1) according to any one of the preceding claims, characterized in that The data transmission (30) has an Ethernet connection, in particular, each of the at least two single logic modules (10) can be connected to a switch (23) for data transmission (30), the connection device (20) has a switch (23) and / or the switch (23) is arranged on a switch circuit board (24) separated from the circuit board (22) of the connection device (20), preferably, the switch circuit board (24) can be arranged outside the housing (21) of the connection device (20).

7. The circuit system (1) according to any one of the preceding claims, characterized in that Protocols including remote direct memory access (RDMA) can be used for data exchange (31) via data transmission (30), in particular in order to relieve the memory (11) and / or the computing unit (12) of at least one of the at least two single logic modules (10).

8. The circuit system (1) according to any one of the preceding claims, characterized in that The at least two single logic modules (10) have LO reference clock sharing and / or digital synchronization, which can be achieved in particular by data transmission (30) via a switching device (20) and / or by a separate synchronization circuit between the at least two single logic modules (10).

9. The circuit system (1) according to any one of the preceding claims, characterized in that The data processing (40) comprises at least a calculation (140) based on data (50) recorded by a radar system, a lidar system or a camera system, wherein the calculation (140) comprises a plurality of computing operations (141), which in particular cannot be performed individually and / or in real time by a single single logic module (10), wherein the plurality of computing operations (141) can be divided into preferably substantially uniform computing operation parts (142), which can preferably be evenly divided between the at least two single logic modules (10) for separate calculations (143), thereby enabling the calculation (140) to be performed and / or can be performed in real time.

10. The circuit system (1) according to claim 9, characterized in that The calculation (140) comprises a Fourier transformation, in particular a fast Fourier transformation, and the individual calculation (143) comprises the calculation of a sub-region of the Fourier transformation.

11. The circuit system (1) according to claim 9 or 10, characterized in that Each of the at least two single logic modules (10) is further configured to perform at least one post-processing step (150) based on a single result (144) of the single logic module's single calculation (143) after the single calculation (143) so as to obtain a post-processing result (151).

12. A method (100) for data processing (40) by means of a circuit system (1) according to any one of the preceding claims, the method comprising, for each of the at least two single logic modules (10), at least the following steps: receiving (110) data (50) for data processing (40) by a single logic module (10), storing (120) the first data portion (51) in a memory (11) of a single logic module (10), sending (130) at least one second data portion (52) to a memory (11) of at least one further single logic module (10), preferably the first data portion (51) and at least the second data portion (52) overlapping redundantly only in edge regions, A single calculation (143) of the first arithmetic operation part (142) is performed by a calculation unit (12) of the single logic module (10) based on the first data part (51) to obtain a single result (144).

13. The method (100) according to claim 12, wherein: At least the following steps are performed before the single logic module (10) receives (110) data (50) for data processing (40): By connecting the device (20) to send (105) data (50) to the single logic module (10), In particular, after the calculation unit (12) of the single logic module (10) performs a separate calculation (143) of the first arithmetic operation part (142) based on the first data part (51), at least one of the following steps is performed: performing a post-processing step (150) by the single logic module (10) based on the individual results (144) so ​​as to obtain a post-processing result (151), The individual results (144) or the post-processing results (151) are combined by the switching device (20) and / or the computing unit (12) in order to obtain an overall result (160).

14. A computer program product (80) comprising instructions executable by a computing unit (12), in particular a single logic module (10), which instructions, when the computer program product (80) is executed by the computing unit (12), cause the computing unit (12) to carry out the method (100) according to claim 12 or 13.

15. A non-volatile computer-readable storage medium (90) comprising a computer program product (80) according to the preceding claim.

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