A display panel driving method and display device

Abstract

Embodiments of the present application provide a display panel driving method and a display device. The driving method comprises: generating a first timing signal comprising a plurality of first type pulses; wherein the timing of the first type pulse is located at the tail of the refresh frame timing, and the pulse width of the first type pulse is NH, and the value range of N is 8≤N≤12; scanning the start signal end of the first gate drive circuit of the display panel by using the first timing signal; wherein the output end of the first gate drive circuit is used to provide a control signal to the compensation transistor of the pixel circuit. By shortening the pulse width of the first type pulse in the refresh frame, the high level charging time of the start signal end of the first gate drive circuit is shortened, the positive charge in the parasitic capacitor and the capacitor CQ is reduced, so that the node Q can be converted from high level to low level in time, so as to improve the display defect phenomenon of the upper and lower split screens.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel driving method and display device. BACKGROUND

[0002] At present, the display screen is prone to have the problem of parasitic capacitance due to corrosion in the reliability running test (high temperature and high humidity), and the existence of the parasitic capacitance can cause display defects. For example, for the first gate driving circuit (SC1) providing a control signal to the compensation TFT (Thin Film Transistor) of the pixel circuit, the circuit structure is as shown in Figure 1 (parasitic capacitance can be connected in parallel across the capacitor CQ), and the signal timing can refer to Figure 2 (in the refresh frame, the second pulse width of the starting signal end SC1_STV of SC1 is 16H), when SC1_STV (the starting signal end of SC1) is at high level and SC1_CK (the clock signal end of SC1) is at low level, the capacitor CQ and the parasitic capacitance are charged with positive charges, and the transistor T1 is in the off state. When SC1_STV is converted to low level, the positive charges in the capacitor CQ and the parasitic capacitance are neutralized first, and then the capacitor CQ is charged with negative charges, so that the node Q is converted to low level, and the transistor T1 is turned on. However, if there are too many positive charges in the parasitic capacitance and the capacitor CQ, the voltage of the node Q may not be able to turn on the transistor T1, causing display defects of the upper and lower split screens, as shown in Figure 3 . SUMMARY

[0003] The purpose of the embodiments of the present application is to provide a display panel driving method and display device to improve the display defects of the upper and lower split screens. The specific technical solutions are as follows:

[0004] In a first aspect, the embodiments of the present application provide a display panel driving method, which comprises:

[0005] generating a first timing signal comprising a plurality of first type pulses; wherein the timing of the first type pulses is located at the tail of the refresh frame timing, and the pulse width of the first type pulses is NH, and the value range of N is 8≤N≤12;

[0006] scanning the starting signal end of the first gate driving circuit of the display panel by using the first timing signal; wherein the output end of the first gate driving circuit is used to provide a control signal to the compensation transistor of the pixel circuit.

[0007] In a possible implementation, the first timing signal further comprises a plurality of second type pulses;

[0008] The timing of the second type of pulse is located at the head of the refresh frame timing, and the pulse width of the second type of pulse is MH, and the value range of M is N≤M≤12;

[0009] The pulse interval width between the first type of pulse and the second type of pulse is LH, and the value range of L is 16≤L≤24.

[0010] In one possible implementation, the method further includes:

[0011] generating a third timing signal including a plurality of third-type pulses; wherein the timing length of the third-type pulses is not less than the timing length of the holding frame, and in terms of time sequence, the start time of the holding frame is not earlier than the start time of the third-type pulses, and the end time of the holding frame is not later than the end time of the third-type pulses;

[0012] The clock signal terminal of the second gate driving circuit of the display panel is scanned by using the third timing signal; wherein the output terminal of the second gate driving circuit is used to provide a control signal to the first reset transistor of the pixel circuit.

[0013] In a possible implementation manner, the first type of pulse, the second type of pulse, and the third type of pulse are all invalid level signals.

[0014] In one possible implementation, the method further includes:

[0015] generating a fourth timing signal including a plurality of fourth-type pulses; wherein the timing of the fourth-type pulses is located at the end of the refresh frame timing, and the fourth-type pulses and the first-type pulses have an overlapping portion in time sequence;

[0016] The fourth timing signal is used to scan the start signal terminal of the second gate driving circuit.

[0017] In a possible implementation manner, the fourth type of pulse is an invalid level signal.

[0018] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel and a display driver chip;

[0019] The display panel includes a plurality of pixel rows, a first gate driving circuit connected to each pixel row, and a second gate driving circuit connected to each pixel row; each pixel row includes a plurality of pixel circuits; each pixel circuit includes a compensation transistor and a first reset transistor;

[0020] The display driving chip is configured to generate a first timing signal comprising a plurality of first type pulses; a time sequence of the first type pulses is located at a tail of a refresh frame time sequence, and a pulse width of the first type pulses is NH, and N is in a range of 8 ≤ N ≤ 12; and the first timing signal is used to scan a start signal end of a first gate driving circuit of the display panel; and an output end of the first gate driving circuit is configured to provide a control signal to a compensation transistor of a pixel circuit.

[0021] In a possible implementation,

[0022] The first timing signal further comprises a plurality of second type pulses; a time sequence of the second type pulses is located at a head of the refresh frame time sequence, and a pulse width of the second type pulses is MH, and M is in a range of N ≤ M ≤ 12; and a pulse interval width between the first type pulses and the second type pulses is LH, and L is in a range of 16 ≤ L ≤ 24.

[0023] In a possible implementation,

[0024] The display driving chip is further configured to generate a third timing signal comprising a plurality of third type pulses; a time sequence length of the third type pulses is not less than a time sequence length of a holding frame, and in a time sequence, a start time of the holding frame is not earlier than a start time of the third type pulses, and an end time of the holding frame is not later than an end time of the third type pulses; and the third timing signal is used to scan a clock signal end of a second gate driving circuit of the display panel; and an output end of the second gate driving circuit is configured to provide a control signal to a first reset transistor of a pixel circuit.

[0025] In a possible implementation,

[0026] The display driving chip is further configured to generate a fourth timing signal comprising a plurality of fourth type pulses; a time sequence of the fourth type pulses is located at the tail of the refresh frame time sequence, and the fourth type pulses and the first type pulses have an overlapping part in the time sequence; and the fourth timing signal is used to scan a start signal end of the second gate driving circuit.

[0027] The embodiments of the present application have the following beneficial effects:

[0028] The display panel driving method and the display device provided by the embodiment of the present application, the driving method comprises: generating a first timing signal comprising a plurality of first type pulses; wherein the timing of the first type pulse is located at the tail of the refresh frame timing, and the pulse width of the first type pulse is NH, and the value range of N is 8≤N≤12; using the first timing signal to scan the start signal end of the first gate drive circuit of the display panel; wherein the output end of the first gate drive circuit is used to provide a control signal to the compensation transistor of the pixel circuit. By shortening the pulse width of the first type pulse in the refresh frame (compared with the second pulse width of the start signal end SC1_STV of the first gate drive circuit SC1 in the related art, which is 16H, the embodiment of the present application is shortened to 8H-12H), the high level charging time of the start signal end of the first gate drive circuit is shortened, the positive charge in the parasitic capacitor and the capacitor CQ is reduced, so that the node Q can be converted from high level to low level in time, so as to improve the display defect phenomenon of the upper and lower split screens.

[0029] Of course, implementing any product or method of the present application does not necessarily require achieving all the advantages described above at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other embodiments can also be obtained by those skilled in the art based on these drawings.

[0031] Figure 1 A structural schematic diagram of the first gate drive circuit in the related art;

[0032] Figure 2 A timing schematic diagram of various signals in the related art;

[0033] Figure 3 A schematic diagram of the display defect phenomenon of the upper and lower split screens in the related art;

[0034] Figure 4 A structural schematic diagram of the second gate drive circuit in the related art;

[0035] Figure 5 A schematic diagram of the display defect phenomenon of the horizontal bright line in the related art;

[0036] Figure 6 A first flow schematic diagram of the display panel driving method provided by the embodiment of the present application;

[0037] Figure 7 A structural schematic diagram of the pixel circuit in the related art;

[0038] Figure 8 Timing diagram of improved signals in the present application;

[0039] Figure 9 Second flow diagram of the display panel driving method provided by the embodiment of the present application;

[0040] Figure 10 Third flow diagram of the display panel driving method provided by the embodiment of the present application;

[0041] Figure 11 One structural diagram of the display device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art based on the present application shall fall within the scope of protection of the present application.

[0043] At present, the display screen is prone to have the problem of parasitic capacitance due to corrosion in the reliability running test (high temperature and high humidity), and the existence of the parasitic capacitance can cause display defects. For example, for the first gate drive circuit (SC1) providing a control signal to the compensation transistor T10 of the pixel circuit, the circuit structure is as shown in Figure 1 The gate drive circuit SC1 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C_ON, a second capacitor CQ, and a third capacitor CB (each transistor is a P-type transistor), and the connection relationship of each device is as follows:

[0044] The gate of the first transistor T1 is connected with the second end of the seventh transistor T7 and the first end of the second capacitor CQ, respectively, the first end of the first transistor T1 is connected with a low-level signal end VGL, and the second end of the first transistor T1 is connected with an output end SC1_OUT and the second end of the second capacitor CQ, respectively;

[0045] The gate of the seventh transistor T7 is connected with the low-level signal end VGL, and the first end of the seventh transistor T7 is connected with the second end of the third transistor T3 and the gate of the sixth transistor T6, respectively;

[0046] The gate of the third transistor T3 is connected with a clock signal end SC1_CK, and the first end of the third transistor T3 is connected with a start signal end SC1_STV and the gate of the fourth transistor T4, respectively;

[0047] The first end of the fourth transistor T4 is connected with the high level signal end VGH, and the second end of the fourth transistor T4 is connected with the gate of the fifth transistor T5 and the second end of the first capacitor C_ON respectively;

[0048] The first end of the fifth transistor T5 is connected with the clock signal end SC1_CK and the first end of the first capacitor C_ON respectively, and the second end of the fifth transistor T5 is connected with the second end of the sixth transistor T6, the gate of the second transistor T2 and the first end of the third capacitor CB respectively;

[0049] The first end of the second transistor T2 is connected with the output end SC1_OUT, and the second end of the second transistor T2 is connected with the second end of the third capacitor CB and the high level signal end VGH respectively;

[0050] The first end of the sixth transistor T6 is connected with the high level signal end VGH.

[0051] The signal timing of the gate drive circuit SC1 can refer to Figure 2 In the refresh frame, the first pulse (high level) width of the start signal end SC1_STV of SC1 is 12H, the second pulse (high level) width of the start signal end SC1_STV of SC1 is 16H, and the pulse interval (low level) width between the two pulses is 12H, 1H is a horizontal scanning period, and 1H is equal to 2.9us (microsecond). When SC1_STV is at high level and SC1_CK is at low level, the third transistor T3 is in an open state, and the seventh transistor is in an open state due to the low level signal of VGL, which will charge the second capacitor CQ and the parasitic capacitor with positive charge, and the first transistor T1 is in a closed state. When SC1_STV is converted to low level, the positive charge in the second capacitor CQ and the parasitic capacitor is neutralized first, and then the second capacitor CQ is charged with negative charge, so that the node Q is converted to low level, and the first transistor T1 is opened. However, if the high level of SC1_STV lasts for a long time, the positive charge in the parasitic capacitor and the second capacitor CQ is large, which may cause the voltage of the node Q to be unable to open the transistor T1, and SC1_OUT outputs high level, causing the display of the upper and lower split screens to be poor, as shown in Figure 3 .

[0052] On the other hand, the display screen is easy to cause the transistor TFT characteristic shift during the reliability running test. Once the transistor TFT characteristic shifts, the transistor TFT that should be turned off is actually not turned off. For example, for the second gate drive circuit (SC4) providing a control signal to the first reset transistor T11 of the pixel circuit, the circuit structure is as shown in Figure 4As shown, the gate drive circuit SC4 includes a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a twentieth transistor T20, a twenty-first transistor T21, a fourth capacitor C_ON', a fifth capacitor CQ', a sixth capacitor CB' (each transistor is a P-type transistor), and the connection relationship of each device is as follows:

[0053] The gate of the fifteenth transistor T15 is connected with the second end of the twenty-first transistor T21 and the first end of the fifth capacitor CQ' respectively, the first end of the fifteenth transistor T15 is connected with a low-level signal end VGL, and the second end of the fifteenth transistor T15 is connected with an output end SC4_OUT and the second end of the fifth capacitor CQ' respectively;

[0054] The gate of the twenty-first transistor T21 is connected with the low-level signal end VGL, and the first end of the twenty-first transistor T21 is connected with the second end of the seventeenth transistor T17 and the gate of the twentieth transistor T20 respectively;

[0055] The gate of the seventeenth transistor T17 is connected with a clock signal end SC4_CK, and the first end of the seventeenth transistor T17 is connected with a start signal end SC4_STV and the gate of the eighteenth transistor T18 respectively;

[0056] The first end of the eighteenth transistor T18 is connected with a high-level signal end VGH, and the second end of the eighteenth transistor T18 is connected with the gate of the nineteenth transistor T19 and the second end of the fourth capacitor C_ON' respectively;

[0057] The first end of the nineteenth transistor T19 is connected with the clock signal end SC4_CK and the first end of the fourth capacitor C_ON' respectively, and the second end of the nineteenth transistor T19 is connected with the second end of the twentieth transistor T20, the gate of the sixteenth transistor T16 and the first end of the sixth capacitor CB' respectively;

[0058] The first end of the sixteenth transistor T16 is connected with the output end SC4_OUT, and the second end of the sixteenth transistor T16 is connected with the second end of the sixth capacitor CB' and the high-level signal end VGH respectively;

[0059] The first end of the twentieth transistor T20 is connected with the high-level signal end VGH.

[0060] The signal timing of the gate drive circuit SC4 can be referred to Figure 2In the refresh frame, the pulse (high level) width of the start signal end SC4_STV of the SC4 is 16H, the SC4_STV maintains low level in the holding frame, the eighteenth transistor T18 is turned on, the VGH high level signal is written to the node Q1, the voltage of the node Q1 maintains high level, but the clock signal end SC4_CK of the SC4 still maintains the pulse signal consistent with the refresh frame, the characteristics of the transistor TFT are offset in the reliability high temperature and high humidity process, the nineteenth transistor T19 cannot be completely turned off, the pulse signal of the clock signal end SC4_CK leaks to the sixth capacitor CB', the low level is accumulated over time, and the characteristics of the sixteenth transistor T16 are offset, so that the T16 cannot be completely turned off, the VGH high level signal leaks to the output end SC4_OUT of the SC4 through the T16, the low level signal output by the SC4_OUT slowly rises, and the sixteenth transistor T16 is turned on at a certain time node. The above situation causes the low level signal output by the SC4_OUT to be converted to high level in advance, and the high level time is longer, causing the display of the horizontal bright line to be poor, as shown in Figure 5 .

[0061] In order to improve at least one of the above problems, the embodiments of the present application provide a display panel driving method and a display device.

[0062] The display panel driving method provided by the embodiments of the present application is described in detail below. Referring to Figure 6 , a first flowchart of the display panel driving method provided by the embodiments of the present application includes the following steps:

[0063] Step S601, a first timing signal including a plurality of first pulses is generated; wherein the timing of the first pulse is located at the tail of the refresh frame timing, and the pulse width of the first pulse is NH, and the value range of N is 8≤N≤12.

[0064] It can be understood that, since each transistor in the first gate drive circuit SC1 is a P-type transistor, the first pulse (high level) is an invalid level signal, and the pulse interval (low level) is an effective level signal.

[0065] It can be understood that the first pulse is the second pulse of the start signal end SC1_STV of the first gate drive circuit SC1 in each refresh frame.

[0066] In the refresh frame, a new data signal Data is charged and applied to the gate of the driving transistor T9 of the pixel circuit; in the holding frame, the data signal Data of the previous frame is maintained and used.

[0067] The circuit structure of the pixel circuit can be seen from Figure 7 , Figure 7The 7T1C pixel circuit is taken as an example, and the 7T1C means that the pixel circuit includes 7 transistors (a data writing transistor T8, a driving transistor T9, a compensation transistor T10, a first reset transistor T11, a first light-emitting control transistor T12, a second light-emitting control transistor T13, and a second reset transistor T14, each of which is an N-type transistor), and 1 storage capacitor (Cst), wherein VDD is a positive power supply signal terminal, and VSS is a negative power supply signal terminal.

[0068] In step S602, the first timing signal is used to scan a start signal terminal SC1_STV of a first gate drive circuit SC1 of the display panel; wherein an output terminal SC1_OUT of the first gate drive circuit SC1 is configured to provide a control signal to a compensation transistor T10 of a pixel circuit.

[0069] The output terminal SC1_OUT of the first gate drive circuit SC1 is connected to the gate of the compensation transistor T10.

[0070] In the embodiment of the present application, by shortening the pulse width of the first type of pulse in the refresh frame (compared to the second pulse width of the start signal terminal SC1_STV of SC1 in the related art, which is 16H, the present embodiment shortens it to 8H-12H, the shorter the better, but at the same time, it needs to be considered that it does not conflict with other signals, and the effect of 8H is the best effect), the high-level charging time of the start signal terminal of the first gate drive circuit is shortened, the positive charge in the parasitic capacitor and the capacitor CQ is reduced, the node Q can be converted from high level to low level in time, the problem that the transistor T1 cannot be turned on due to too much positive charge in the parasitic capacitor and the capacitor CQ is improved, the stability of the transistor is increased, the reliability risk is reduced, and the display defect phenomenon of the upper and lower split screens is improved. And the scheme adopted in the present embodiment only needs to program new timing on the existing process, without introducing new process and increasing process flow, reducing the introduction of reliability problems and the increase of cost. Compared with improving from the perspective of backplane manufacturing process, the timing improvement period is faster and the cost is lower.

[0071] In a possible implementation, the first timing signal further includes a plurality of second type of pulses;

[0072] The timing of the second type of pulse is located at the head of the refresh frame timing, and the pulse width of the second type of pulse is MH, and the value range of M is N≤M≤12.

[0073] The pulse interval width between the first type of pulse and the second type of pulse is LH, and the value range of L is 16≤L≤24.

[0074] It can be understood that, as described above, the second type of pulse (high level) is an invalid level signal.

[0075] It can be understood that the second type of pulse is the first pulse of the start signal end SC1_STV of the first gate drive circuit SC1 in each refresh frame.

[0076] The pulse width of the second type of pulse can also be shortened. The improvement effect brought by shortening the pulse width of the first type of pulse is better than that brought by shortening the pulse width of the second type of pulse.

[0077] In summary, the improved signal timing of the first gate drive circuit SC1 can be seen from Figure 8 It can be understood that, Figure 8 In the middle, the first type of pulse is shortened to 8H, the pulse interval width between the first type of pulse and the second type of pulse is 20H, and the second type of pulse width is 12H.

[0078] In a possible implementation, referring to Figure 9 , based on Figure 6 The method further includes the following steps:

[0079] Step S901, generating a third timing signal including a plurality of third type of pulses; wherein the timing length of the third type of pulse is not less than the timing length of the holding frame, and in time sequence, the starting time of the holding frame is not earlier than the starting time of the third type of pulse, and the ending time of the holding frame is not later than the ending time of the third type of pulse.

[0080] It can be understood that, since each transistor in the second gate drive circuit SC4 is a P-type transistor, the third type of pulse (high level) is an invalid level signal, and the pulse interval (low level) is an effective level signal.

[0081] Step S902, scanning the clock signal end SC4_CK of the second gate drive circuit SC4 of the display panel by using the third timing signal; wherein the output end of the second gate drive circuit SC4 is used to provide a control signal to the first reset transistor T11 of the pixel circuit.

[0082] The output end SC4_OUT of the second gate drive circuit SC4 is connected to the gate of the first reset transistor T11.

[0083] In the embodiment of the present application, by optimizing all the timing signals of the clock signal end SC4_CK of the second gate drive circuit SC4 in the holding frame to high level, the gate of the sixteenth transistor T16 is always kept at high level in the holding frame (T16 is always in the off state), which increases the stability of the transistor, reduces the reliability risk, and improves the display defect of the horizontal bright line caused by the failure of T16 to completely turn off. Moreover, the scheme adopted in the embodiment of the present application only needs to program new timing on the existing process, does not introduce new process, and does not increase the process flow, thereby reducing the introduction of reliability problems and the increase of cost. Compared with the improvement from the perspective of backplane manufacturing process, the timing improvement period is faster and the cost is lower.

[0084] In a possible implementation, the first type of pulse, the second type of pulse and the third type of pulse are all invalid level signals.

[0085] The specific analysis is the same as described above, which will not be repeated here.

[0086] In a possible implementation, referring to Figure 10 , based on Figure 9 The method further includes the following steps:

[0087] Step S1001, generating a fourth timing signal including a plurality of fourth type of pulses; wherein the timing of the fourth type of pulse is located at the tail of the refresh frame timing, and the fourth type of pulse has an overlapping part in time sequence with the first type of pulse.

[0088] Step S1002, scanning the start signal end SC4_STV of the second gate drive circuit SC4 by using the fourth timing signal.

[0089] It can be understood that, since each transistor in the second gate drive circuit SC4 is a P-type transistor, the fourth type of pulse (high level) is an invalid level signal.

[0090] It can be understood that the fourth type of pulse is the pulse of the start signal end SC4_STV of the second gate drive circuit SC4 in each refresh frame.

[0091] In summary, the improved signal timing of the second gate drive circuit SC4 can be referred to Figure 8 .

[0092] In the embodiment of the present application, in order to ensure the pulse overlapping part of SC1_STV and SC4_STV, the pulse width of SC4_STV in the refresh frame can be expanded from the existing 16H (16H can be referred to Figure 2 ) to 20H, so as to improve the low gray scale and afterimage and other defects.

[0093] In a possible implementation, the fourth type of pulse is a non-effective level signal.

[0094] The specific analysis is the same as described above, and will not be repeated here.

[0095] In a possible implementation, the method further includes the following steps: generating a fifth timing signal; and scanning a clock signal end SC1_CK of the first gate drive circuit SC1 by using the fifth timing signal.

[0096] The timing waveform of the fifth timing signal (see SC1_CK in FIG. 6) is the same as the timing waveform of the clock signal end SC1_CK of the first gate drive circuit SC1 in the related art (see SC1_CK in FIG. 2). Figure 8 Figure 2 The timing waveform of the fifth timing signal (see SC1_CK in FIG. 6) is the same as the timing waveform of the clock signal end SC1_CK of the first gate drive circuit SC1 in the related art (see SC1_CK in FIG. 2).

[0097] Embodiments of the present application also provide a display device 1, which is shown in FIG. 11. Figure 11 The display device 1 includes a display panel 11 and a display drive chip 12.

[0098] The display panel 11 includes a plurality of pixel rows 111, a first gate drive circuit SC1 connected to each of the pixel rows 111, and a second gate drive circuit SC4 connected to each of the pixel rows 111. Each of the pixel rows 111 includes a plurality of pixel circuits. Each of the pixel circuits includes a compensation transistor T10 and a first reset transistor T11.

[0099] The display drive chip 12 is configured to generate a first timing signal including a plurality of first type of pulses. The timing of the first type of pulse is located at the tail of a refresh frame timing, and the pulse width of the first type of pulse is NH, where the value of N is in the range of 8≤N≤12. The display drive chip 12 is further configured to scan a start signal end SC1_STV of a first gate drive circuit SC1 of the display panel by using the first timing signal. The output end SC1_OUT of the first gate drive circuit SC1 is configured to provide a control signal to the compensation transistor T10 of the pixel circuit.

[0100] One first gate drive circuit SC1 can be connected to one / multiple pixel rows 111, and one second gate drive circuit SC4 can be connected to one / multiple pixel rows 111. One pixel row 111 can be connected to multiple first gate drive circuits SC1, and one pixel row 111 can be connected to multiple second gate drive circuits SC4. The present application does not make specific limitations in this regard. Figure 11 In the present application, one first gate drive circuit SC1 is connected to one pixel row 111, and one second gate drive circuit SC4 is connected to one pixel row 111.

[0101] The remaining analysis is the same as described above, and will not be repeated here.​

[0102] In a possible implementation,

[0103] The first timing signal further comprises a plurality of second type pulses; the timing of the second type pulses is located at the head of the refresh frame timing, and the pulse width of the second type pulses is MH, and M is in the range of N≤M≤12; the pulse interval width between the first type pulses and the second type pulses is LH, and L is in the range of 16≤L≤24.

[0104] The specific analysis is the same as described above, and will not be repeated here.

[0105] In a possible implementation, referring to Figure 11 ,

[0106] The display driving chip 12 is further configured to generate a third timing signal comprising a plurality of third type pulses; the timing length of the third type pulses is not less than the timing length of the holding frame, and in the time sequence, the starting time of the holding frame is not earlier than the starting time of the third type pulses, and the ending time of the holding frame is not later than the ending time of the third type pulses; and scan the clock signal end SC4_CK of the second gate driving circuit SC4 of the display panel by using the third timing signal; the output end SC4_OUT of the second gate driving circuit SC4 is configured to provide a control signal to the first reset transistor T11 of the pixel circuit.

[0107] The specific analysis is the same as described above, and will not be repeated here.

[0108] In a possible implementation, referring to Figure 11 ,

[0109] The display driving chip 12 is further configured to generate a fourth timing signal comprising a plurality of fourth type pulses; the timing of the fourth type pulses is located at the tail of the refresh frame timing, and the fourth type pulses and the first type pulses have an overlapping part in the time sequence; and scan the starting signal end SC4_STV of the second gate driving circuit SC4 by using the fourth timing signal.

[0110] The specific analysis is the same as described above, and will not be repeated here.

[0111] In a possible implementation, referring to Figure 11 ,

[0112] The display driving chip 12 is further configured to generate a fifth timing signal; and scan the clock signal end SC1_CK of the first gate driving circuit SC1 by using the fifth timing signal.

[0113] It is to be noted that, as used in this document, the terminology "first", "second", etc. is merely used to differentiate one entity or action from another, and does not necessarily imply any actual physical or logical relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0114] Each of the embodiments described in the specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other. Each of the embodiments focuses on the difference from other embodiments. In particular, for the system embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the description of the method embodiments.

[0115] The above only describes the preferred embodiments of the present application, and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel driving method, characterized in that: The method comprises: Generate a first timing signal including a plurality of first-type pulses; wherein the timing of the first-type pulses is located at the end of the refresh frame timing, and the pulse width of the first-type pulses is NH, and the value range of N is 8≤N≤12; Scanning a start signal terminal of a first gate driving circuit of the display panel using the first timing signal; wherein the output terminal of the first gate driving circuit is used to provide a control signal to a compensation transistor of a pixel circuit; The first timing signal further includes a plurality of second-type pulses; The timing of the second type of pulse is located at the head of the refresh frame timing, and the pulse width of the second type of pulse is MH, and the value range of M is N≤M≤12; The pulse interval width between the first type of pulse and the second type of pulse is LH, and the value range of L is 16≤L≤24; The first type of pulses and the second type of pulses are both invalid level signals.

2. The method according to claim 1, characterized in that The method further comprises: generating a third timing signal including a plurality of third-type pulses; wherein the timing length of the third-type pulses is not less than the timing length of the holding frame, and in terms of time sequence, the start time of the holding frame is not earlier than the start time of the third-type pulses, and the end time of the holding frame is not later than the end time of the third-type pulses; The clock signal terminal of the second gate driving circuit of the display panel is scanned by using the third timing signal; wherein the output terminal of the second gate driving circuit is used to provide a control signal to the first reset transistor of the pixel circuit.

3. The method according to claim 2, characterized in that The third type of pulse is an invalid level signal.

4. The method according to claim 2, characterized in that The method further comprises: generating a fourth timing signal including a plurality of fourth-type pulses; wherein the timing of the fourth-type pulses is located at the end of the refresh frame timing, and the fourth-type pulses and the first-type pulses have an overlapping portion in time sequence; The fourth timing signal is used to scan the start signal terminal of the second gate driving circuit.

5. The method according to claim 4, characterized in that The fourth type of pulse is an invalid level signal.

6. A display device, characterized in that: The display device includes a display panel and a display driver chip; The display panel includes a plurality of pixel rows, a first gate driving circuit connected to each pixel row, and a second gate driving circuit connected to each pixel row; each pixel row includes a plurality of pixel circuits; each pixel circuit includes a compensation transistor and a first reset transistor; The display driver chip is used to: generate a first timing signal including a plurality of first-type pulses; wherein the timing of the first-type pulses is located at the end of the refresh frame timing, and the pulse width of the first-type pulses is NH, and the value range of N is 8≤N≤12; use the first timing signal to scan the start signal end of the first gate driver circuit of the display panel; wherein the output end of the first gate driver circuit is used to provide a control signal to the compensation transistor of the pixel circuit; The first timing signal further includes a plurality of second-type pulses; the timing of the second-type pulses is located at the head of the refresh frame timing, and the pulse width of the second-type pulses is MH, where the value range of M is N≤M≤12; the pulse interval width between the first-type pulses and the second-type pulses is LH, where the value range of L is 16≤L≤24; The first type of pulses and the second type of pulses are both invalid level signals.

7. The display device according to claim 6, wherein: The display driver chip is also used to: generate a third timing signal including multiple third-type pulses; wherein the timing length of the third-type pulse is not less than the timing length of the holding frame, and in time sequence, the start time of the holding frame is not earlier than the start time of the third-type pulse, and the end time of the holding frame is not later than the end time of the third-type pulse; and use the third timing signal to scan the clock signal end of the second gate drive circuit of the display panel; wherein the output end of the second gate drive circuit is used to provide a control signal to the first reset transistor of the pixel circuit.

8. The display device according to claim 7, wherein: The display driver chip is further used to: generate a fourth timing signal including multiple fourth-type pulses; wherein the timing of the fourth-type pulses is located at the end of the refresh frame timing, and the fourth-type pulses and the first-type pulses have an overlapping part in time sequence; and use the fourth timing signal to scan the start signal end of the second gate drive circuit.

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