Semiconductor structure and manufacturing method thereof
By forming air gaps in the semiconductor structure and utilizing the low dielectric constant of air to reduce the parasitic capacitance between metal layers, the problem of performance degradation caused by reduced line width is solved, thereby achieving performance improvement.
Patent Information
- Application Number
- CN202510950639.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-09
- Publication Date
- 2025-10-17
AI Technical Summary
As the line width of semiconductor chips decreases, the parasitic capacitance between metal layers increases, resulting in a decrease in chip performance.
By forming a groove in the semiconductor structure, covering it with a sacrificial layer and removing the sacrificial layer at the bottom of the groove, filling the first isolation layer and controlling its height, removing the sacrificial layer to form an air gap, and finally forming a second isolation layer on the remaining isolation layer, the air gap is used to reduce the parasitic capacitance between the metal layers.
The parasitic capacitance between metal layers is effectively reduced, and the performance of the chip is improved.
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Figure CN120809680A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor, in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND
[0002] With the development of semiconductor related technology, the line width of chip is also decreasing to meet the demand of small size of integrated circuit. However, the line width of chip is gradually decreasing, which means that the distance between adjacent metal lines is getting closer and closer, and the parasitic capacitance between metal layers is getting larger and larger, resulting in the performance of chip being reduced.
[0003] Therefore, there is a need to reduce the parasitic capacitance between metal layers. SUMMARY
[0004] Therefore, the purpose of the present application is to provide a semiconductor structure and a manufacturing method thereof, which can reduce the parasitic capacitance between metal layers to improve the performance of chip.
[0005] The present application provides a manufacturing method of a semiconductor structure, the semiconductor structure comprising a metal layer, the metal layer comprising a plurality of grooves; the method comprising:
[0006] forming a sacrificial layer covering the sidewall of the groove and the bottom of the groove; removing the sacrificial layer at the bottom of the groove;
[0007] forming a first isolation layer, the first isolation layer filling the groove;
[0008] removing part of the first isolation layer to a remaining first isolation layer reaching a preset height;
[0009] removing the sacrificial layer;
[0010] forming a second isolation layer on the remaining first isolation layer, the space between the second isolation layer, the first isolation layer and the metal layer forming an air gap, the height of the air gap being the preset height.
[0011] Optionally, the forming of the second isolation layer on the remaining first isolation layer comprises:
[0012] forming an isolation material on the remaining first isolation layer, the isolation material covering the surface of the metal layer;
[0013] removing part of the thickness of the isolation material to the surface of the isolation material and the metal layer being flush, forming a second isolation layer.
[0014] Optionally, the material of the first isolation layer and the material of the second isolation layer are the same, and the material of the first isolation layer is oxide.
[0015] Optionally, the thickness of the sacrificial layer on the sidewall of the groove remains constant in the direction from the top of the groove towards the bottom of the groove.
[0016] Optionally, the thickness of the sacrificial layer on the sidewall of the groove is the same as the width of the air gap.
[0017] Optionally, the material of the sacrificial layer is carbon or silicon nitride.
[0018] The present application provides a semiconductor structure, which comprises a metal layer, the metal layer comprising a plurality of grooves.
[0019] The first isolation layer and the second isolation layer are arranged in the groove, the second isolation layer being above the first isolation layer, the space between the second isolation layer, the first isolation layer and the metal layer forming an air gap, the height of the air gap being the height of the first isolation layer.
[0020] Optionally, the material of the first isolation layer is the same as the material of the second isolation layer.
[0021] Optionally, the second isolation layer is flush with the side surface of the metal layer away from the bottom of the groove.
[0022] Optionally, the space between the second isolation layer, the first isolation layer and the metal layer forms two air gaps.
[0023] The present application provides a method for manufacturing a semiconductor structure, the semiconductor structure comprising a metal layer, the metal layer comprising a plurality of grooves. The method comprises: forming a sacrificial layer, the sacrificial layer covering the sidewall of the groove and the bottom of the groove, removing the sacrificial layer at the bottom of the groove, wherein the position of the sacrificial layer can be used for subsequent formation of an air gap; forming a first isolation layer, the first isolation layer filling the groove, removing part of the first isolation layer to a remaining first isolation layer reaching a preset height, wherein the preset height is the height of the air gap to be formed subsequently; removing the sacrificial layer to form an air gap at the position of the sacrificial layer; and forming a second isolation layer on the remaining first isolation layer, the space between the second isolation layer, the first isolation layer and the metal layer forming an air gap. That is, by forming an air gap using the sacrificial layer, since the air gap is arranged between the metal layers, the air gap is air, the dielectric constant of air is low, which can reduce the parasitic capacitance between the metal layers, i.e. air is used as the intermetal dielectric layer to reduce the parasitic capacitance between the metal layers. BRIEF DESCRIPTION OF DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0025] Figure 1 A flowchart of a method for manufacturing a semiconductor structure is shown.
[0026] Figures 2-9 A structure diagram of a semiconductor structure manufactured by the method for manufacturing a semiconductor structure according to the embodiments of the present application is shown. DETAILED DESCRIPTION
[0027] In order to make the personnel in the technical field better understand the present application, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.
[0028] In the following description, many specific details are set forth in order to fully understand the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the connotation of the present application, therefore the present application is not limited by the specific embodiments disclosed below.
[0029] The present application is described in detail in conjunction with the schematic diagram, and when the embodiments of the present application are described, in order to facilitate the description, the sectional view showing the structure will be partially enlarged without the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the present application herein. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in actual manufacture.
[0030] With the development of semiconductor related technology, the line width of the chip is also decreasing accordingly to meet the demand of small size of integrated circuit. However, the gradual decrease of the line width of the chip means that the distance between adjacent metal lines is getting closer and closer, and the parasitic capacitance between metal layers is getting larger and larger, resulting in the decline of the performance of the chip.
[0031] Therefore, there is a need to reduce the parasitic capacitance between metal layers at present, and low dielectric constant material can be used as the metal layer medium to reduce the parasitic capacitance between metal layers.
[0032] Based on this, the application provides a manufacturing method of a semiconductor structure, the semiconductor structure comprising a metal layer, the metal layer comprising a plurality of grooves. The method comprises: forming a sacrificial layer, the sacrificial layer covering the sidewall of the groove and the bottom of the groove, and removing the sacrificial layer located at the bottom of the groove. The position of the sacrificial layer can be used for subsequent formation of an air gap. A first isolation layer is formed, the first isolation layer filling the groove, and part of the first isolation layer is removed to a remaining first isolation layer reaching a preset height, wherein the preset height is the height of the air gap formed subsequently. The sacrificial layer is removed, so that the air gap is formed at the position of the sacrificial layer. A second isolation layer is formed on the remaining first isolation layer, and the space between the second isolation layer, the first isolation layer and the metal layer forms the air gap. That is, the air gap is formed by using the sacrificial layer. Since the air gap is provided between the metal layers, the air gap is air, the dielectric constant of air is low, and the parasitic capacitance between the metal layers can be reduced, that is, air is used as the intermetal dielectric layer to reduce the parasitic capacitance between the metal layers.
[0033] In order to better understand the technical solutions and technical effects of the application, specific embodiments will be described in detail below with reference to the drawings.
[0034] Referring to Figure 1 , the figure is a flowchart of a manufacturing method of a semiconductor structure provided by an embodiment of the application.
[0035] The semiconductor structure provided by the embodiment of the application comprises a metal layer 110. Referring to Figure 2 , the metal layer 110 comprises a plurality of grooves 120, and the interlayer dielectric can be formed in the grooves 120 subsequently. The material of the metal layer 110 can be a material with good electrical conductivity, such as gold or copper.
[0036] The manufacturing method of the semiconductor structure provided by the embodiment of the application comprises the following steps:
[0037] S101, a sacrificial layer is formed, the sacrificial layer covering the sidewall of the groove and the bottom of the groove, and the sacrificial layer located at the bottom of the groove is removed.
[0038] In the embodiment of the application, considering that the grooves 120 are used to form the interlayer dielectric in the metal layer 110 subsequently to reduce the parasitic capacitance between the metal layers, the lower the dielectric constant of the interlayer dielectric, the better the effect of reducing the parasitic capacitance between the metal layers. The dielectric constant of air is about 1, which is lower than that of other materials, so the air gap can be formed in the grooves 120 to reduce the parasitic capacitance between the metal layers to a greater extent.
[0039] In order to form the air gap in the grooves 120, the sacrificial layer 130 can be formed in the grooves 120 first. Referring to Figure 3As shown, the sacrificial layer 130 covers the sidewall of the recess 120 and the bottom of the recess 120. The sacrificial layer 130 can be formed by a deposition process, and at this time, the sacrificial layer 130 also covers the side surface of the metal layer 110 away from the bottom of the recess 120.
[0040] Specifically, considering that the sacrificial layer 130 needs to be used to form an air gap later, the material of the sacrificial layer 130 can be selected as a material that is easy to form an air gap. For example, the material of the sacrificial layer 130 can be carbon or silicon nitride. When the material of the sacrificial layer 130 is carbon, the process of removing the sacrificial layer 130 is relatively simple.
[0041] After the sacrificial layer 130 is formed on the sidewall of the recess 120 and the bottom of the recess 120, the sacrificial layer 130 located at the bottom of the recess 120 can be removed, as shown in Figure 4 Specifically, the sacrificial layer 130 located at the bottom of the recess 120 can be removed by bombarding the sacrificial layer 130 located at the bottom of the recess 120 with high-energy particles.
[0042] In the embodiments of the present application, considering that the shape or thickness of the sacrificial layer 130 will affect the shape and width of the air gap, when the sacrificial layer 130 is formed, the shape or thickness of the sacrificial layer 130 can be designed to adjust the spatial state of the air gap.
[0043] Specifically, along the direction from the top of the recess 120 to the bottom of the recess 120, the thickness of the sacrificial layer 130 located on the sidewall of the recess 120 remains the same, that is, the thickness of the sacrificial layer 130 located on the sidewall of the recess 120 is uniform, so that when the air gap is formed later, the shape of the air gap is also uniform along the direction from the top of the recess 120 to the bottom of the recess 120.
[0044] Considering that the air gap is formed by removing the material of the sacrificial layer 130, the thickness of the sacrificial layer 130 located on the sidewall of the recess 120 is the same as the width of the air gap. That is, by adjusting the thickness of the sacrificial layer 130 located on the sidewall of the recess 120, the width of the formed air gap can be adjusted, and then the volume of the air gap is adjusted, so that the degree of reducing the parasitic capacitance between the metal layers by using the air gap is controlled.
[0045] S102, a first isolation layer is formed, and the first isolation layer fills the recess.
[0046] In the embodiments of the present application, after the sacrificial layer 130 located at the bottom of the recess 120 is removed, the first isolation layer 140 can be formed, and the first isolation layer 140 fills the recess 120, that is, the first isolation layer 140 fills the remaining space of the recess 120 which is not filled by the sacrificial layer 130.
[0047] Referring to Figure 5As shown, the first isolation layer 140 also covers the side surface of the sacrificial layer 130 away from the bottom of the groove 120, so as to fill the remaining space of the groove 120.
[0048] Specifically, the first isolation layer 140 will not be removed subsequently and will be arranged in the groove 120, so the first isolation layer 140 also serves as an intermetal dielectric layer, and the material of the first isolation layer 140 can also be a material with low dielectric constant. For example, the material of the first isolation layer 140 can be an oxide.
[0049] S103, removing part of the first isolation layer until the remaining first isolation layer reaches a preset height.
[0050] In the embodiment of the present application, after the groove 120 is filled with the first isolation layer 140, part of the first isolation layer 140 in the groove 120 can be removed until the remaining first isolation layer 140 reaches a preset height, wherein the preset height is calculated based on the bottom of the groove 120.
[0051] The first isolation layer 140 covering the surface of the sacrificial layer 130 and part of the first isolation layer 140 in the groove 120 can be removed by etching process, as shown in Figure 6 .
[0052] The remaining first isolation layer 140 reaches the preset height, and the subsequently formed air gap also has the preset height, so the thickness of the removed first isolation layer 140 can be controlled to adjust the height of the formed air gap, and then adjust the volume of the air gap, so as to control the degree of reducing the parasitic capacitance between the metal layers by using the air gap.
[0053] S104, removing the sacrificial layer.
[0054] In the embodiment of the present application, after the first isolation layer 140 with the preset height is formed, the sacrificial layer 130 can be removed, as shown in Figure 7 , so as to subsequently form an air gap.
[0055] Specifically, the sacrificial layer 130 on the side surface of the metal layer 110 away from the bottom of the groove 120 and the sacrificial layer 130 on the side wall of the groove 120 can be removed at the same time.
[0056] S105, forming a second isolation layer on the remaining first isolation layer, the space between the second isolation layer, the first isolation layer and the metal layer forms an air gap, and the height of the air gap is the preset height.
[0057] In the embodiments of the present application, after the removal of the sacrificial layer 130, the second isolation layer 150 can be formed on the remaining first isolation layer 140, that is, the second isolation layer 150 is continuously formed on the first isolation layer 140 with the preset height.
[0058] Since the distance between the first isolation layer 140 and the sidewall of the groove 120 is small, when the second isolation layer 150 is formed, the second isolation layer 150 will not fill the inside of the groove 120, but will form a film layer based on the surface of the first isolation layer 140 away from the bottom of the groove 120. In this way, the space between the second isolation layer 150, the first isolation layer 140 and the metal layer 110 forms an air gap, and since the second isolation layer 150 does not fill the space after the removal of the sacrificial layer 120, the height of the air gap formed is the preset height of the first isolation layer 140.
[0059] When the second isolation layer 150 is formed on the first isolation layer 140, the isolation material 151 can be first formed on the remaining first isolation layer 140, covering the side surface of the metal layer 110 away from the bottom of the groove 120, as shown in FIG. 4B, and then the isolation material 151 is removed to a certain thickness so that the surface of the isolation material 151 is flush with the surface of the metal layer 110, forming the second isolation layer 150, as shown in FIG. 4C. Figure 8 Figure 9
[0060] Specifically, the material of the second isolation layer 150 can be the same as that of the first isolation layer 140. That is, if the material of the first isolation layer 140 is oxide, the material of the second isolation layer 150 is also oxide.
[0061] Therefore, by forming an air gap using a sacrificial layer, since the air gap is provided between the metal layers, the air gap is air, and the dielectric constant of air is low, which can reduce the parasitic capacitance between the metal layers, that is, air is used as the intermetal dielectric layer to reduce the parasitic capacitance between the metal layers. The present application can also control the height of the air gap by controlling the preset height of the first isolation layer, so that the air gap can be effectively formed even in the case of small line width, that is, small spacing between the metal layers.
[0062] That is, the method for manufacturing a semiconductor structure provided by the present application, the semiconductor structure comprising a metal layer, the metal layer comprising a plurality of recesses. The method comprises: forming a sacrificial layer, the sacrificial layer covering the sidewall of the recess and the bottom of the recess; removing the sacrificial layer at the bottom of the recess, wherein the position of the sacrificial layer can be used for subsequent formation of an air gap; forming a first isolation layer, the first isolation layer filling the recess; removing part of the first isolation layer to a remaining first isolation layer reaching a preset height, wherein the preset height is the height of the air gap to be formed subsequently; and removing the sacrificial layer to form an air gap at the position of the sacrificial layer. A second isolation layer is formed on the remaining first isolation layer, and the space between the second isolation layer, the first isolation layer and the metal layer forms an air gap. That is, by forming the air gap by using the sacrificial layer, since the air gap is provided between the metal layers, the air gap is air, the dielectric constant of air is low, which can reduce the parasitic capacitance between the metal layers, that is, air is used as the intermetal dielectric layer to reduce the parasitic capacitance between the metal layers.
[0063] Based on the method for manufacturing a semiconductor structure provided by the above embodiments, the present application further provides a semiconductor structure, which will be described below with reference to Figure 9 FIG. 1, which is a schematic diagram of the cross-sectional structure of a semiconductor structure provided by an embodiment of the present application. The semiconductor structure provided by the present application comprises a metal layer 110, wherein the metal layer 110 comprises a plurality of recesses 120.
[0064] The recess 120 is provided with a first isolation layer 140 and a second isolation layer 150, and the second isolation layer 150 is located above the first isolation layer 140, which is defined in the direction from the bottom of the recess 120 to the top of the recess 120.
[0065] The space between the second isolation layer 150, the first isolation layer 140 and the metal layer 110 forms an air gap, and the height of the air gap is the height of the first isolation layer 140.
[0066] Specifically, the material of the second isolation layer 150 can be the same as that of the first isolation layer 140. That is, if the material of the first isolation layer 140 is oxide, the material of the second isolation layer 150 is also oxide.
[0067] In the embodiments of the present application, the second isolation layer 150 does not fill the inside of the recess 120, but forms a film layer based on the surface of the first isolation layer 140 away from the bottom of the recess 120. In this way, the space between the second isolation layer 150, the first isolation layer 140 and the metal layer 110 forms an air gap, and since the second isolation layer 150 does not fill the inside of the recess 120, the height of the air gap formed is the preset height of the first isolation layer 140.
[0068] In actual application, to keep the flat surface, the second isolation layer 150 is flush with the side surface of the bottom of the groove 120 and the side surface of the metal layer 110 away from the bottom of the groove 120.
[0069] In the embodiments of the present application, the space between the second isolation layer 150, the first isolation layer 140 and the metal layer 110 forms two air gaps, i.e. two symmetrical air gaps are formed on the two sides of the first isolation layer 140, and the parasitic capacitance between the metal layers is reduced by using the two air gaps.
[0070] Each of the embodiments in the present specification is described in a progressive manner, and the same and similar parts between the embodiments can be referred to each other. Each embodiment mainly explains the difference from other embodiments. In particular, for the structural embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the related parts can be referred to the part of the method embodiments.
[0071] The above only describes the preferred embodiments of the present application. Although the present application has been disclosed as above with the preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solutions of the present application, or modify equivalent embodiments with the disclosed methods and technical contents without departing from the scope of the technical solutions of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the content of the technical solutions of the present application, still belongs to the scope of protection of the technical solutions of the present application.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: The semiconductor structure includes a metal layer, wherein the metal layer includes a plurality of grooves; and the method includes: forming a sacrificial layer, the sacrificial layer covering the sidewalls and the bottom of the groove; and removing the sacrificial layer located at the bottom of the groove; forming a first isolation layer, wherein the first isolation layer fills the groove; removing a portion of the first isolation layer until the remaining first isolation layer reaches a preset height; removing the sacrificial layer; A second isolation layer is formed on the remaining first isolation layer, and an air gap is formed in the space between the second isolation layer, the first isolation layer, and the metal layer. The height of the air gap is the preset height.
2. The method according to claim 1, characterized in that The forming of the second isolation layer on the remaining first isolation layer comprises: forming an isolation material on the remaining first isolation layer, wherein the isolation material covers a surface of the metal layer; A portion of the thickness of the isolation material is removed until the isolation material is flush with the surface of the metal layer to form a second isolation layer.
3. The method according to claim 2, characterized in that The material of the first isolation layer is the same as that of the second isolation layer, and the material of the first isolation layer is oxide.
4. The method according to claim 1, wherein The thickness of the sacrificial layer on the sidewall of the groove remains consistent along the direction from the top of the groove to the bottom of the groove.
5. The method according to claim 4, characterized in that The thickness of the sacrificial layer located on the sidewall of the groove is the same as the width of the air gap.
6. The method according to claim 1, characterized in that The material of the sacrificial layer is carbon or silicon nitride.
7. A semiconductor structure, characterized in that The semiconductor structure includes a metal layer, and the metal layer includes a plurality of grooves; A first isolation layer and a second isolation layer are provided in the groove, the second isolation layer is located above the first isolation layer, and the space between the second isolation layer, the first isolation layer and the metal layer forms an air gap, the height of the air gap being the height of the first isolation layer.
8. The semiconductor structure according to claim 7, wherein: The material of the first isolation layer is the same as that of the second isolation layer.
9. The semiconductor structure according to claim 7, wherein: A surface of the second isolation layer that is away from the bottom of the groove is flush with a surface of the metal layer that is away from the bottom of the groove.
10. The semiconductor structure according to any one of claims 7 to 9, characterized in that: Two air gaps are formed between the second isolation layer, the first isolation layer and the metal layer.