In-situ storage NVSRAM cell based on charge trap programming method

Abstract

The present application relates to the field of memory, and provides an in-situ storage NVSRAM unit based on a charge capture programming method. The SRAM storage unit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; the gate of the first PMOS transistor is connected to the source of the first NMOS transistor; the gate of the second PMOS transistor is connected to the source of the second NMOS transistor; the drain of the first NMOS transistor is connected to the first bit line through the third NMOS transistor; the drain of the second NMOS transistor is connected to the second bit line through the fourth NMOS transistor; the drain of the first PMOS transistor is connected to the source of the first non-volatile transistor; the drain of the second PMOS transistor is connected to the source of the second non-volatile transistor, so as to solve the problem that the non-volatile memory is incompatible with CMOS nodes and operating voltages.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to an in-situ storage NVSRAM unit based on a charge trap programming method. Background Art

[0002] With the rapid development of artificial intelligence and the Internet of Things, there is a growing demand for low-power, high-efficiency wearable devices and edge computing devices. These devices usually need to maintain low energy consumption in long standby states while being able to respond and process data quickly when needed. However, the increase in leakage current in modern deep submicron complementary metal oxide semiconductor (CMOS) processes leads to high sleep power consumption, which seriously restricts the endurance and performance of the device.

[0003] In order to solve this problem, non-volatile memories in related technologies (such as resistive random access memory RRAM and magnetoresistive random access memory MRAM) have been widely studied and applied. However, the above non-volatile memories not only need to use 2.7 times the minimum gate width to generate sufficient programming current to ensure data stability, but also have the problem of incompatibility between non-volatile memories and CMOS nodes and operating voltages. Summary of the invention

[0004] The present application provides an in-situ storage NVSRAM cell based on a charge trap programming method to solve the problem of incompatibility between non-volatile memory and CMOS nodes and operating voltages.

[0005] The present application provides an in-situ storage NVSRAM cell based on a charge trap programming method, comprising: an SRAM storage cell, a first non-volatile transistor, and a second non-volatile transistor;

[0006] The first non-volatile transistor and the second non-volatile transistor are both NMOS transistors whose gates are made of high-K dielectrics;

[0007] The SRAM storage cell includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor;

[0008] The sources of the first PMOS transistor and the second PMOS transistor are connected to the positive electrode of the programming source; the gate of the first PMOS transistor is connected to the source of the first NMOS transistor; the gate of the second PMOS transistor is connected to the source of the second NMOS transistor; the drain of the first NMOS transistor is connected to the first bit line through the third NMOS transistor; the drain of the second NMOS transistor is connected to the second bit line through the fourth NMOS transistor; the drain of the first PMOS transistor is connected to the source of the first non-volatile transistor; the drain of the second PMOS transistor is connected to the source of the second non-volatile transistor; the gates of the first NMOS transistor and the second NMOS transistor are connected to the enable port; the drains of the first non-volatile transistor and the second non-volatile transistor are connected to the negative electrode of the programming source; the SRAM storage unit is used to store volatile data; the first non-volatile transistor and the second non-volatile transistor are used to store non-volatile data.

[0009] The present application utilizes the charge trapping effect in high-k dielectrics to capture or release charges under the gates of the first non-volatile transistor and the second non-volatile transistor to change the conduction state of the first non-volatile transistor and the second non-volatile transistor, so that a standard NMOS transistor can be used as a non-volatile transistor, thereby solving the problem of incompatibility between non-volatile memory and CMOS nodes and operating voltages.

[0010] Optionally, the drain of the first PMOS transistor and the gate of the second PMOS transistor are connected to a second storage node; the drain of the second PMOS transistor and the gate of the first PMOS transistor are connected to a first storage node.

[0011] The above connection method can effectively realize bidirectional data transmission and maintenance of logic state, while improving the stability and efficiency of the circuit.

[0012] Optionally, the gate of the first non-volatile transistor is connected to the first bit line through the third NMOS transistor; the gate of the second non-volatile transistor is connected to the second bit line through the fourth NMOS transistor; and the gates of the third NMOS transistor and the fourth NMOS transistor are connected to a word line.

[0013] Since each non-volatile transistor can be individually controlled by a corresponding NMOS transistor to perform programming or erasing operations as needed, it helps to improve storage density and save chip area.

[0014] Optionally, the logic of data write or read operation is:

[0015] Control the positive electrode of the programming source to maintain at the power supply voltage; control the negative electrode of the programming source to maintain at the ground; control the enable port to be at a high level to turn on the third NMOS transistor and the fourth NMOS transistor, and control the word line to be turned on to write or read according to the data on the first bit line and the second bit line.

[0016] By controlling the positive electrode of the programming source to remain at the power supply voltage, it is possible to ensure that sufficient current flows through the programming path, thereby making the programming operation more stable and reliable. By controlling the negative electrode of the programming source to remain grounded, it is helpful to provide a stable reference point, reduce noise interference, and improve signal clarity. By controlling the enable port to be at a high level to turn on the third NMOS transistor and the fourth NMOS transistor, precise control of the in-situ storage NVSRAM cell can be achieved, which can not only improve the data transmission speed, but also reduce power consumption. By controlling the word line to be turned on to write or read according to the data on the first bit line and the second bit line, the utilization rate and overall performance of the in-situ storage NVSRAM cell can be improved.

[0017] Optionally, a sensing amplifier is further included; the sensing amplifier is connected to the first bit line and the second bit line respectively; the logic of the data programming operation is:

[0018] Controlling the first bit line and the second bit line to read volatile data stored in the SRAM storage unit, and outputting the volatile data to the sense amplifier output terminal;

[0019] Control the programming source positive electrode, the programming source negative electrode, and the enable port to be disconnected, so that the signals of the first storage node and the second storage node are disconnected;

[0020] controlling the word line according to the output value of the output terminal of the sense amplifier to adjust the threshold voltages of the first non-volatile transistor and the second non-volatile transistor;

[0021] If the output value of the output terminal of the sense amplifier is higher than a preset output value, the second non-volatile transistor is programmed, and the first non-volatile transistor is not programmed.

[0022] The data programming operation described in the present application implements a method for programming a non-volatile memory through a sensing amplifier and specific control logic, which helps to improve the accuracy and efficiency of the programming process and performs non-volatile storage of volatile data in the SRAM storage unit when power is off.

[0023] Optionally, the logic of the data recovery operation is:

[0024] The positive electrode of the programming source and the enable port are controlled to be turned on, and the negative electrode of the programming source is controlled to be turned off, so that no threshold voltage difference is formed between the first non-volatile transistor and the second non-volatile transistor, and the volatile data is restored to the SRAM storage unit.

[0025] The data recovery operation described in the present application implements a method for recovering a non-volatile memory through a sensing amplifier and specific control logic, which helps to improve the accuracy and efficiency of the recovery process and recover the volatile data in the SRAM storage unit when a call comes in.

[0026] Optionally, the logic of the data copy operation is:

[0027] Control the word line and enable port of the copy row to be turned on, and the word line of the paste row to be turned on;

[0028] Control the enable port of the paste row to be disconnected so that the data of the copy row is copied from the copy row to the paste row.

[0029] The logic of the data copy operation does not require reading the data first and then storing it row by row, thereby reducing the delay and power consumption of the intra-row copy operation.

[0030] Optionally, the gate of the first NMOS transistor is connected to a left enable port, and the gate of the second NMOS transistor is connected to a right enable port;

[0031] Full array Boolean logic operations are performed by controlling the left enable port, the right enable port, and the programming source anode.

[0032] The full array Boolean logic operations of the present application can be performed within the NVSRAM cell without losing the original data, thereby improving efficiency and eliminating the need for additional energy consumption to move data or perform additional calculations.

[0033] It can be seen from the above technical solution that the present application provides an in-situ storage NVSRAM cell based on a charge trap programming method, comprising: an SRAM storage cell, a first non-volatile transistor and a second non-volatile transistor; the SRAM storage cell comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; the source of the first PMOS transistor and the second PMOS transistor are connected to the positive electrode of the programming source; the gate of the first PMOS transistor is connected to the source of the first NMOS transistor; the gate of the second PMOS transistor is connected to the source of the second NMOS transistor; the drain of the first NMOS transistor is connected to the positive electrode of the programming source through the The third NMOS transistor is connected to the first bit line; the drain of the second NMOS transistor is connected to the second bit line through the fourth NMOS transistor; the drain of the first PMOS transistor is connected to the source of the first non-volatile transistor; the drain of the second PMOS transistor is connected to the source of the second non-volatile transistor; the gates of the first NMOS transistor and the second NMOS transistor are connected to the enable port; the drains of the first non-volatile transistor and the second non-volatile transistor are connected to the negative electrode of the programming source; the SRAM storage unit is used to store volatile data; the first non-volatile transistor and the second non-volatile transistor are used to store non-volatile data to solve the problem of incompatibility between non-volatile memory and CMOS nodes and operating voltages. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0035] Figure 1 A circuit diagram of an in-situ storage NVSRAM cell based on a charge trap programming method according to an embodiment of the present application;

[0036] Figure 2 A circuit diagram of an in-situ storage NVSRAM cell based on a charge trap programming method according to an embodiment of the present application performing a write and read operation;

[0037] Figure 3 A circuit diagram of an in-situ storage NVSRAM cell performing a programming recovery operation based on a charge trap programming method according to an embodiment of the present application;

[0038] Figure 4 A circuit diagram of an in-situ storage NVSRAM cell based on a charge trap programming method according to an embodiment of the present application performing an intra-row copy operation;

[0039] Figure 5 This is a circuit diagram of an in-situ storage NVSRAM cell based on a charge trap programming method according to an embodiment of the present application performing a full array Boolean logic operation. DETAILED DESCRIPTION

[0040] The embodiments will be described in detail below, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation methods described in the following embodiments do not represent all implementation methods consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application.

[0041] To solve the problem of incompatibility between non-volatile memory and CMOS nodes and operating voltage, see Figure 1 , the embodiment of the present application provides an in-situ storage NVSRAM cell based on a charge trap programming method, comprising: an SRAM storage cell, a first non-volatile transistor M3 and a second non-volatile transistor M4;

[0042] The first non-volatile transistor M3 and the second non-volatile transistor M4 are both NMOS transistors whose gates are made of high-K dielectrics;

[0043] The SRAM storage unit includes a first PMOS transistor M1, a second PMOS transistor M2, a first NMOS transistor M5, a second NMOS transistor M6, a third NMOS transistor M7 and a fourth NMOS transistor M8;

[0044] The sources of the first PMOS transistor M1 and the second PMOS transistor M2 are connected to the programming source positive electrode VDD_P; the gate of the first PMOS transistor M1 is connected to the source of the first NMOS transistor M5; the gate of the second PMOS transistor M2 is connected to the source of the second NMOS transistor M6; the drain of the first NMOS transistor M5 is connected to the first bit line BL through the third NMOS transistor M7; the drain of the second NMOS transistor M6 is connected to the second bit line BLB through the fourth NMOS transistor M8; the first PMOS transistor M1 is connected to the source of the first NMOS transistor M5; the drain of the second NMOS transistor M6 is connected to the second bit line BLB through the fourth NMOS transistor M8; the first PMOS transistor M1 is connected to the source of the first NMOS transistor M5; the drain of the first NMOS transistor M5 is connected to the first bit line BL through the third NMOS transistor M7; the drain of the second NMOS transistor M6 is connected to the second bit line BLB through the fourth NMOS transistor M8; the first PMOS transistor M1 is connected to the source of the first NMOS transistor M5; the gate of the second PMOS transistor M2 is connected to the source of the second NMOS transistor M6; the drain of the first NMOS transistor M5 is connected to the first bit line BL through the third NMOS transistor M7; the drain of the second NMOS transistor M6 is connected to the second bit line BLB through the fourth NMOS transistor M8; the first PMOS transistor M1 is connected to the source of the first NMOS transistor M5; the gate of ... The drain of the OS transistor M1 is connected to the source of the first non-volatile transistor M3; the drain of the second PMOS transistor M2 is connected to the source of the second non-volatile transistor M4; the gates of the first NMOS transistor M5 and the second NMOS transistor M6 are connected to the enable port EN; the drains of the first non-volatile transistor M3 and the second non-volatile transistor M4 are connected to the programming source negative electrode VSS_P; the SRAM storage unit is used to store volatile data; the first non-volatile transistor M3 and the second non-volatile transistor M4 are used to store non-volatile data.

[0045] It should be understood that NVSRAM (Non-Volatile SRAM) is a non-volatile static random access memory; SRAM is a static random access memory (Static Random-Access Memory) is a type of semiconductor memory. The SRAM storage unit is a standard 6T SRAM structure, and the first non-volatile transistor M3, the second non-volatile transistor M4, the first PMOS transistor M1, the second PMOS transistor M2, the first NMOS transistor M5, the second NMOS transistor M6, the third NMOS transistor M7 and the fourth NMOS transistor M8 can all be small-sized transistors to reduce power consumption. The SRAM storage unit is connected to a bit line and a peripheral circuit for data programming, recovery and error correction. The charge trap programming method is to program and erase the standard NMOS transistor through the charge trap mechanism, so as to adjust its threshold voltage Vth; specifically, the charge trap programming method utilizes the charge trapping effect in the high-K medium to capture or release the charge under the gate of the NMOS transistor to change the conduction state of the NMOS transistor, so that the standard NMOS transistor can be used as a non-volatile transistor (NVT), thereby solving the problem of incompatibility between non-volatile memory and CMOS nodes and operating voltages.

[0046] In some embodiments, the drain of the first PMOS transistor M1 and the gate of the second PMOS transistor M2 are connected to the second storage node QB; the drain of the second PMOS transistor M2 and the gate of the first PMOS transistor M1 are connected to the first storage node Q.

[0047] It should be understood that the above-mentioned cross-coupled structure forms a bistable circuit, and each PMOS transistor can serve as the load of the other party, so that the logic states on the two storage nodes can influence each other and remain stable, which also helps to improve the signal amplification ability and anti-interference ability, reduce power consumption and increase speed, and can effectively realize bidirectional data transmission and maintenance of logic state, while improving the stability and efficiency of the circuit.

[0048] In some embodiments, the gate of the first nonvolatile transistor M3 is connected to the first bit line BL through the third NMOS transistor M7; the gate of the second nonvolatile transistor M4 is connected to the second bit line BLB through the fourth NMOS transistor M8; and the gates of the third NMOS transistor M7 and the fourth NMOS transistor M8 are connected to the word line WL.

[0049] It should be understood that the gate of the first non-volatile transistor M3 is connected to the first bit line BL through the third NMOS transistor M7; the gate of the second non-volatile transistor M4 is connected to the second bit line BLB through the fourth NMOS transistor M8, and the state of each non-volatile transistor can be independently controlled by controlling the voltage on the word line WL. When the word line WL is activated, the NMOS transistor connected to the word line WL will be turned on, so that the gate potential of the corresponding non-volatile transistor changes, thereby affecting its threshold voltage.

[0050] Since each non-volatile transistor can be individually controlled by a corresponding NMOS transistor to perform programming or erasing operations as needed, it helps to improve storage density and save chip area.

[0051] In some embodiments, the logic of data writing or reading operation is:

[0052] Control the programming source positive electrode VDD_P to remain at the power supply voltage; control the programming source negative electrode VSS_P to remain grounded GND; control the enable port EN to be at a high level to turn on the third NMOS transistor M7 and the fourth NMOS transistor M8, and control the word line WL to be turned on to write or read according to the data on the first bit line BL and the second bit line BLB.

[0053] like Figure 2As shown, for the case of writing (Write) and reading (Read) "1", M4 can be set to "0" and M3 can be set to "1". By controlling the programming source positive electrode VDD_P to remain at the power supply voltage, it can be ensured that sufficient current flows through the programming path, making the programming operation more stable and reliable. By controlling the programming source negative electrode VSS_P to remain grounded GND, it helps to provide a stable reference point, reduce noise interference, and improve signal clarity. By controlling the enable port EN to be high to turn on the third NMOS transistor M7 and the fourth NMOS transistor M8, precise control of the in-situ storage NVSRAM cell can be achieved, which can not only improve the data transmission speed, but also reduce power consumption. By controlling the word line WL to be turned on to write or read according to the data on the first bit line BL and the second bit line BLB, not only the utilization rate of the in-situ storage NVSRAM cell can be improved, but also the overall performance of the storage system can be enhanced.

[0054] In some embodiments, a sensing amplifier SA is further included; the sensing amplifier SA is connected to the first bit line BL and the second bit line BLB respectively; the logic of the data programming operation is:

[0055] Controlling the first bit line BL and the second bit line BLB to read the volatile data stored in the SRAM storage unit, and outputting the volatile data to the output end of the sense amplifier SA;

[0056] See also Figure 3 In the case of programming (PRG) "1", the programming source positive electrode VDD_P, the programming source negative electrode VSS_P, and the enable port EN are controlled to be disconnected, so that the signals of the first storage node Q and the second storage node QB are disconnected;

[0057] Controlling the word line WL according to the output value of the output terminal of the sense amplifier SA to adjust the threshold voltages (Vth_P and Vth_N) of the first non-volatile transistor M3 and the second non-volatile transistor M4;

[0058] If the output value of the output terminal of the sense amplifier is higher than the preset output value, the second non-volatile transistor M4 is programmed, and the first non-volatile transistor M3 is not programmed.

[0059] It should be understood that the word line WL is used to select the memory cell to be programmed. If the output value of the output terminal of the sense amplifier is higher than the preset output value, the first bit line BL is 0V and no voltage difference is formed. At this time, the charge capture process in the second non-volatile transistor M4 begins, that is, programming, so that the threshold voltage Vth_N of the second non-volatile transistor M4 increases. Through this programming method, a threshold voltage difference △Vth is formed between the first non-volatile transistor M3 and the second non-volatile transistor M4, so that the volatile data in the SRAM memory cell is non-volatilely stored when the power is off.

[0060] In some embodiments, see Figure 3 In the case of Restore "1", the logic of the data recovery operation is:

[0061] The programming source positive electrode VDD_P and the enable port EN are controlled to be turned on, and the programming source negative electrode VSS_P is controlled to be turned off, so that no threshold voltage difference is formed between the first non-volatile transistor M3 and the second non-volatile transistor M4, and the volatile data is restored to the SRAM storage unit.

[0062] It should be understood that after the data programming operation is completed, if the first non-volatile transistor M3 and the second non-volatile transistor M4 need to be restored to a normal working state, a data recovery operation can be performed. In the recovery operation, the states of the first non-volatile transistor M3 and the second non-volatile transistor M4 will be used to restore the volatile data to the SRAM storage unit to ensure the integrity and accuracy of the data after power failure.

[0063] In some embodiments, the logic of the data copy operation is:

[0064] Control the word line WL[n] and enable ports EN_L[n] and EN_R[n] of the copy row to be turned on, and the word line WL[m] of the paste row to be turned on;

[0065] Control the enable ports EN_R[m] and EN_L[m] of the paste row to be disconnected so that the data of the copy row is copied from the copy row to the paste row.

[0066] It should be understood that see Figure 4, an example of copying (Copy) a copy row Q[n] to a paste row Q[m], a plurality of NVSRAM cells may be arranged to form a data array, the data array may include 31 first bit lines (BL[0]-BL

[31] ), 31 second bit lines (BLB[0]-BLB

[31] ) and 31 word lines (WL[0]-WL

[31] ), each NVSRAM cell connected to a word line is a row, when the data in the row is copied from the copy row Q[n] to the paste row Q[m], the logic of the data copy operation does not need to read the data first and then store it row by row, thereby reducing the delay and power consumption of the row copy operation.

[0067] In some embodiments, the gate of the first NMOS transistor M5 is connected to the left enable port EN_L, and the gate of the second NMOS transistor M6 is connected to the right enable port EN_R;

[0068] By controlling the left enable port EN_L, the right enable port EN_R and the programming source positive electrode VDD_P, a full array Boolean logic operation is performed.

[0069] It should be understood that the full array Boolean logic operation refers to the Boolean logic operation performed on the entire data array in computer memory or data processing. These operations include basic Boolean operations such as AND / NAND, OR / NOR, etc. Figure 5 , the full array Boolean logic operation of the present application can be performed in the NVSRAM cell without losing the original data, thereby improving efficiency. For example, when performing an AND / NAND operation, the input data is written through a control signal, the original data in the NVSRAM cell is ANDed with the input data, and the result is directly stored in the NVSRAM cell. During operation, the right enable port EN_R is set to "1", and the left enable port EN_L is equal to the input data. If the stored data is "1" and the input data is "0", the left enable port EN_L is "0". The result is that in-situ storage is performed by turning on the programming source positive electrode VDD_P, and the original data is stored in the non-volatile transistor. In-situ storage or OR / NOR operation is similar to AND / NAND operation. Different logic operations can be achieved by logically controlling the selection mode signal, which can realize in-situ processing of data, and no additional energy consumption is required to move data or perform additional calculations.

[0070] It can be seen from the above technical solution that the embodiment of the present application provides an in-situ storage NVSRAM cell based on a charge trap programming method, including: an SRAM storage cell, a first non-volatile transistor M3 and a second non-volatile transistor M4; the SRAM storage cell includes a first PMOS transistor M1, a second PMOS transistor M2, a first NMOS transistor M5, a second NMOS transistor M6, a third NMOS transistor M7 and a fourth NMOS transistor M8; the source of the first PMOS transistor M1 and the second PMOS transistor M2 are connected to the programming source positive electrode VDD_P; the gate of the first PMOS transistor M1 is connected to the source of the first NMOS transistor M5; the gate of the second PMOS transistor M2 is connected to the source of the second NMOS transistor M6; the drain of the first NMOS transistor M5 is connected to the programming source positive electrode VDD_P through the The third NMOS transistor M7 is connected to the first bit line BL; the drain of the second NMOS transistor M6 is connected to the second bit line BLB through the fourth NMOS transistor M8; the drain of the first PMOS transistor M1 is connected to the source of the first non-volatile transistor M3; the drain of the second PMOS transistor M2 is connected to the source of the second non-volatile transistor M4; the gates of the first NMOS transistor M5 and the second NMOS transistor M6 are connected to the enable port EN; the drains of the first non-volatile transistor M3 and the second non-volatile transistor M4 are connected to the programming source negative electrode VSS_P; the SRAM storage unit is used to store volatile data; the first non-volatile transistor M3 and the second non-volatile transistor M4 are used to store non-volatile data to solve the problem of incompatibility between non-volatile memory and CMOS nodes and operating voltages.

[0071] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the general concept of this application and do not constitute a limitation on the protection scope of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without creative work belong to the protection scope of this application.

Claims

1. An in-situ storage NVSRAM cell based on a charge trap programming method, characterized in that: include: An SRAM memory cell, a first non-volatile transistor, and a second non-volatile transistor; The first non-volatile transistor and the second non-volatile transistor are both NMOS transistors whose gates are made of high-K dielectrics; The SRAM storage cell includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth NMOS transistor; The sources of the first PMOS transistor and the second PMOS transistor are connected to the positive electrode of the programming source; the gate of the first PMOS transistor is connected to the source of the first NMOS transistor; the gate of the second PMOS transistor is connected to the source of the second NMOS transistor; the drain of the first NMOS transistor is connected to the first bit line through the third NMOS transistor; the drain of the second NMOS transistor is connected to the second bit line through the fourth NMOS transistor; the drain of the first PMOS transistor is connected to the source of the first non-volatile transistor; the drain of the second PMOS transistor is connected to the source of the second non-volatile transistor; The gates of the first NMOS transistor and the second NMOS transistor are connected to an enable port; the drains of the first non-volatile transistor and the second non-volatile transistor are connected to a negative electrode of a programming source; the SRAM storage unit is used to store volatile data; the first non-volatile transistor and the second non-volatile transistor are used to store non-volatile data.

2. The in-situ storage NVSRAM cell based on the charge trap programming method according to claim 1, characterized in that: The drain of the first PMOS transistor and the gate of the second PMOS transistor are connected to the second storage node; the drain of the second PMOS transistor and the gate of the first PMOS transistor are connected to the first storage node.

3. The in-situ storage NVSRAM cell based on the charge trap programming method according to claim 2, characterized in that: The gate of the first nonvolatile transistor is connected to the first bit line through the third NMOS transistor; the gate of the second nonvolatile transistor is connected to the second bit line through the fourth NMOS transistor; and the gates of the third NMOS transistor and the fourth NMOS transistor are connected to a word line.

4. The in-situ storage NVSRAM cell based on the charge trap programming method according to claim 3, characterized in that: The logic of data writing or reading operation is: Control the positive electrode of the programming source to maintain at the power supply voltage; control the negative electrode of the programming source to maintain at the ground; control the enable port to be at a high level to turn on the third NMOS transistor and the fourth NMOS transistor, and control the word line to be turned on to write or read according to the data on the first bit line and the second bit line.

5. The in-situ storage NVSRAM cell based on the charge trap programming method according to claim 3, characterized in that: Also includes a sense amplifier; the sense amplifier is connected to the first bit line and the second bit line respectively; the logic of the data programming operation is: Controlling the first bit line and the second bit line to read volatile data stored in the SRAM storage unit, and outputting the volatile data to the sense amplifier output terminal; Control the programming source positive electrode, the programming source negative electrode, and the enable port to be disconnected, so that the signals of the first storage node and the second storage node are disconnected; controlling the word line according to the output value of the output terminal of the sense amplifier to adjust the threshold voltages of the first non-volatile transistor and the second non-volatile transistor; If the output value of the output terminal of the sense amplifier is higher than a preset output value, the second non-volatile transistor is programmed, and the first non-volatile transistor is not programmed.

6. The in-situ storage NVSRAM cell based on the charge trap programming method according to claim 5, characterized in that: The logic of data recovery operation is: The positive electrode of the programming source and the enable port are controlled to be turned on, and the negative electrode of the programming source is controlled to be turned off, so that no threshold voltage difference is formed between the first non-volatile transistor and the second non-volatile transistor, and the volatile data is restored to the SRAM storage unit.

7. The in-situ storage NVSRAM cell based on the charge trap programming method according to claim 3, characterized in that: The logic of the data copy operation is: Control the word line and enable port of the copy row to be turned on, and the word line of the paste row to be turned on; Control the enable port of the paste row to be disconnected so that the data of the copy row is copied from the copy row to the paste row.

8. The in-situ storage NVSRAM cell based on the charge trap programming method according to claim 3, characterized in that: The gate of the first NMOS transistor is connected to the left enable port, and the gate of the second NMOS transistor is connected to the right enable port; Full array Boolean logic operations are performed by controlling the left enable port, the right enable port, and the programming source anode.

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