Packaging structure and chip

Abstract

The present application discloses a packaging structure and a chip, comprising: a substrate; a plurality of array-distributed pads, disposed on a first surface of the substrate; a plurality of capacitors, disposed on a second surface of the substrate, wherein the orthographic projection of each capacitor on the plane where the substrate is located at least partially overlaps with the orthographic projection of the target pad corresponding to each capacitor on the plane; and a plurality of metal vias corresponding to each capacitor, wherein each metal via is located in a gap between adjacently arranged pads, and the target pad is located in a first area surrounded by the plurality of metal vias. In this way, the arrangement of the metal vias fully utilizes the gaps in the original layout of the plurality of array-distributed pads, and capacitors are arranged in the orthographic projection area of ​​the pads on the plane where the substrate is located, that is, in an area where vias cannot be arranged on the second surface, so that as many capacitors as possible can be arranged on the second surface of the substrate, thereby improving the power supply performance on the substrate.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a packaging structure and a chip. Background Art

[0002] In chip packaging design, the power distribution network within the package structure generates power noise due to impedance in the electrical path. This noise can cause issues such as unclear high and low signal levels and signal jitter. Designers often address this noise by placing filter capacitors near the power pins. However, these capacitors occupy a significant amount of space on the substrate, making optimal placement of these capacitors a key research area for designers. Summary of the Invention

[0003] The present application proposes a packaging structure and a chip.

[0004] In a first aspect, an embodiment of the present application provides a packaging structure, comprising: a substrate, the substrate comprising a first surface and a second surface opposite to the first surface; a plurality of array-distributed pads, the plurality of pads being arranged on the first surface, and the distance between the centers of any two adjacent pads being a set distance; a plurality of capacitors, the plurality of capacitors being arranged on the second surface, and the orthographic projection of each capacitor on the plane where the substrate is located at least partially overlaps with the orthographic projection of the target pad corresponding to each capacitor on the plane; a plurality of metal through-holes corresponding to each capacitor, the plurality of metal through-holes passing through the first surface and the second surface, each capacitor being connected to the plurality of metal through-holes, each metal through-hole being located in the gap between adjacently arranged pads, the metal through-hole corresponding to each capacitor being a metal through-hole having a distance from each capacitor less than the set distance, and the target pad being located in the first area surrounded by the plurality of metal through-holes.

[0005] Optionally, each of the metal through holes is located in a second area surrounded by a minimum pad array unit, the minimum pad array unit includes two adjacent rows of pads and two adjacent columns of pads, and the number of pads in each row and each column of the minimum pad array unit is 2.

[0006] Optionally, each of the metal through holes is located in the middle of the second region corresponding thereto.

[0007] Optionally, each of the capacitors is located in the middle of a first area surrounded by the corresponding plurality of metal through holes.

[0008] Optionally, each of the capacitors includes a first side and a second side, the length of the first side is greater than the length of the second side, and the length of the first side is greater than the set distance.

[0009] Optionally, the set distance is 0.65 mm, the first side of each capacitor is 1.3 mm, and the second side of each capacitor is 0.5 mm.

[0010] Optionally, the number of the plurality of metal through holes corresponding to each capacitor is six, and the first area surrounded by the plurality of metal through holes includes four target pads.

[0011] Optionally, the packaging structure further includes a power supply, which is disposed on the first surface. The power supply includes a plurality of pins, and each of the pins is electrically connected to one of the pads.

[0012] Optionally, the multiple metal through-holes corresponding to each of the capacitors include multiple first through-holes and multiple second through-holes, the first electrode of each of the capacitors is electrically connected to the power supply through the multiple first through-holes, and the second electrode of each of the capacitors is grounded through the multiple second through-holes.

[0013] In a second aspect, an embodiment of the present application provides a chip including the above-mentioned packaging structure.

[0014] In the packaging structure provided by the embodiment of the present application, by arranging multiple capacitors on the second surface of the substrate, each capacitor is connected to the circuit on the first surface through its corresponding multiple metal through-holes, thereby avoiding the capacitors occupying the space of the first surface when solving the power supply noise problem on the substrate. At the same time, by arranging the metal through-holes in the gaps between adjacently arranged pads, the gaps in the original layout of the multiple array-distributed pads are fully utilized, and since the metal through-holes for penetrating the first surface and the second surface cannot be set in the area corresponding to the pads on the second surface, the positive projection of each capacitor on the plane of the substrate is at least partially overlapped by the pads in the area surrounded by its corresponding multiple metal through-holes, thereby fully utilizing the space of the substrate, so that as many capacitors as possible can be set on the second surface of the substrate, thereby improving the power supply performance on the substrate.

[0015] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A schematic structural diagram of a packaging structure provided in one embodiment of the present application is shown.

[0018] Figure 2 A schematic structural diagram of a packaging structure provided by another embodiment of the present application is shown.

[0019] Figure 3 A structural schematic diagram of a packaging structure provided in yet another embodiment of the present application is shown.

[0020] Figure 4 A schematic structural diagram of a chip provided in one embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the present invention, the following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0022] The terms "first," "second," and the like in this application are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0023] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0024] See also Figure 1 , Figure 1 The schematic diagram of the packaging structure 1 provided by an embodiment of the present application is shown below. Figure 1 The packaging structure 1 provided in the embodiment of the present application is described in detail. Figure 1 As shown, the packaging structure 1 of the present application includes a substrate 10 , a plurality of pads 20 distributed in an array, a plurality of capacitors 30 , and a plurality of metal through holes 40 corresponding to each capacitor 30 .

[0025] Optionally, the substrate 10 includes a first surface and a second surface opposite to the first surface, wherein the first surface of the substrate 10 can be regarded as the front surface of the substrate 10, and the second surface of the substrate 10 can be regarded as the back surface of the substrate 10. The first surface of the substrate 10 is provided with a plurality of array-distributed pads 20, and the distance between the centers of any two adjacent pads 20 is a set distance, the set distance being d. Various electronic components are usually provided on the first surface of the substrate 10 and packaged on the substrate 10 through the plurality of array-distributed pads 20, wherein, Figure 1 It is a top view of the package structure 1 when the first surface of the substrate 10 serves as the front surface of the substrate 10 in the package structure 1 .

[0026] In this embodiment, a plurality of capacitors 30 are disposed on the second surface of substrate 10. Capacitors 30 may be filter capacitors used to improve the performance of the power supply on substrate 10. Placing capacitors 30 on the second surface of substrate 10 eliminates the need to occupy additional space on the first surface of substrate 10, thereby minimizing the size of substrate 10 and reducing the manufacturing cost of substrate 10. Capacitors 30 may be dielectric layers formed from a combination of one or more materials selected from silicon oxide, silicon nitride, and silicon oxynitride. These dielectric layers have high strength, high temperature resistance, excellent comprehensive mechanical properties, and remarkable chemical corrosion resistance, thereby enhancing the performance and service life of capacitors 30.

[0027] Furthermore, the orthographic projection of each capacitor 30 on the plane where the substrate 10 is located at least partially overlaps with the orthographic projection of the target pad corresponding to each capacitor 30 on the plane, and the substrate 10 is also provided with a plurality of metal through-holes 40 corresponding to each capacitor 30. The plurality of metal through-holes 40 penetrate the first surface and the second surface, and each capacitor 30 is connected to the plurality of metal through-holes 40, so that each capacitor 30 provided on the second surface of the substrate 10 can be electrically connected to the circuit on the first surface through the plurality of metal through-holes 40 corresponding thereto. Among them, when the plurality of metal through-holes 40 used to connect the plurality of capacitors 30 on the second surface to the circuit on the first surface are provided on the substrate 10, the space required for the plurality of metal through-holes 40 to be provided on the substrate 10 is much smaller than the space required for the plurality of capacitors 30, but the plurality of metal through-holes 40 still need to occupy a certain space on the first surface for layout.

[0028] In this embodiment, each metal through-hole 40 is arranged to be located in the gap between adjacently arranged pads 20, the metal through-hole 40 corresponding to each capacitor 30 is a metal through-hole 40 whose distance from each capacitor 30 is less than a set distance, and the target pad corresponding to each capacitor 30 is located in the first area surrounded by the multiple metal through-holes 40 corresponding to each capacitor 30, so that the orthographic projection of each capacitor 30 on the plane where the substrate 10 is located can at least partially overlap with the orthographic projection of the target pad corresponding to each capacitor 30 on the plane.

[0029] Based on this, each capacitor 30 is combined with the layout of the multiple metal through-holes 40 corresponding to each capacitor 30. By designing each metal through-hole 40 to be located in the gap between adjacently arranged pads 20, the gaps in the original layout of the multiple array-distributed pads 20 are fully utilized, so that the multiple metal through-holes 40 do not need to occupy additional space on the first surface when they are arranged on the substrate 10. In addition, each capacitor 30 is designed to be located in the first area surrounded by the multiple metal through-holes 40 corresponding to each capacitor 30, so that the positive projection of each capacitor 30 and each pad 20 in the corresponding first area on the plane of the substrate 10 at least partially overlaps, so that the maximum number of capacitors 30 can be set without occupying the first surface of the substrate 10, and the layout and wiring space of the capacitors 30 is guaranteed, thereby improving the power supply performance on the substrate 10.

[0030] In this embodiment, by arranging multiple capacitors 30 on the second surface of the substrate 10, each capacitor 30 is connected to the circuit on the first surface through its corresponding multiple metal through-holes 40, thereby avoiding the capacitors 30 occupying the space of the first surface when solving the power supply noise problem on the substrate 10. At the same time, by arranging the metal through-holes 40 in the gaps between adjacently arranged pads 20, the gaps in the original layout of the multiple array-distributed pads 20 are fully utilized. Moreover, since the metal through-holes 40 for penetrating the first surface and the second surface cannot be set in the area corresponding to the pads 20 on the second surface, the orthographic projections of the pads 20 in the area surrounded by each capacitor 30 and its corresponding multiple metal through-holes 40 on the plane where the substrate 10 is located are at least partially overlapped, thereby fully utilizing the space of the substrate, so that as many capacitors 30 as possible can be set on the second surface of the substrate 10 to meet the power supply's requirement for the number of capacitors 30 as much as possible, thereby improving the power supply performance on the substrate 10.

[0031] See also Figure 2 , Figure 2 FIG. 1 shows a schematic diagram of a packaging structure provided by another embodiment of the present application. Figure 2 As shown, the packaging structure of the present application includes a substrate 10 , a plurality of pads 20 distributed in an array, a plurality of capacitors 30 , and a plurality of metal through holes 40 corresponding to each capacitor 30 .

[0032] In this embodiment, a plurality of pads 20 are provided in an array on the first surface of the substrate 10, a plurality of capacitors 30 are provided on the second surface of the substrate 10, and a plurality of metal vias 40 are provided on the substrate 10 that penetrate the first and second surfaces. Furthermore, the orthographic projection of each capacitor 30 on the plane on which the substrate 10 is located at least partially overlaps with the orthographic projection of the target pad corresponding to each capacitor 30 on the plane, and the target pad corresponding to each capacitor 30 is located in a first region 41 enclosed by the plurality of metal vias 40 corresponding to each capacitor 30.

[0033] Optionally, the pad 20 can be at least a spherical pad, that is, the present application can be applied to the context of a ball grid array (BGA) package. As an advanced semiconductor packaging technology, the ball grid array package is characterized by placing multiple miniature integrated circuit chips (usually one or more dies) on a ceramic substrate. Each chip is surrounded by metal balls as pins. These pins are directly connected to the pad 20 on the substrate 10, thereby achieving high-density, high-performance, multi-pin packaging of multiple electronic components on the substrate 10. In addition, this design provides a smaller size, higher reliability and better heat dissipation performance than traditional pin arrays.

[0034] Optionally, multiple array-distributed pads 20 can be divided into multiple minimum pad array units 21, the minimum pad array unit 21 including two adjacent rows of pads 20 and two adjacent columns of pads 20, and the number of pads 20 in each row of pads 20 and each column of pads 20 of the minimum pad array unit 21 is 2.

[0035] In this embodiment, when each metal through hole 40 is located in the gap between adjacently arranged pads 20, each metal through hole 40 can be located in the gap between four adjacently arranged pads 20 (i.e., the second area 22 surrounded by the minimum pad array unit 21), thereby making full use of the gaps in the original layout of multiple array-distributed pads 20.

[0036] In some embodiments, each metal through hole 40 can be located in the middle of the second area 22 surrounded by the corresponding minimum pad array unit 21, thereby ensuring the gap between each metal through hole 40 and the adjacent pad 20 to achieve a safe distance.

[0037] Optionally, each capacitor 30 may be located in the middle of a first region 41 surrounded by the corresponding plurality of metal through-holes 40 , thereby ensuring layout and routing space when the capacitors 30 are laid out based on the plurality of metal through-holes 40 connected thereto.

[0038] In this embodiment, the package structure further includes a power supply 50, which is disposed on the first surface. The power supply 50 includes a plurality of pins, each of which is electrically connected to a pad 20. Power integrity is an important indicator for measuring the waveform quality of the power supply 50. It can confirm whether the voltage and current at the source and destination of the power supply 50 meet the requirements. The design goal of power integrity is to control power noise within the operating range and provide a clean and stable voltage for the electronic components on the substrate 10. Among them, designers usually improve power integrity by disposing multiple capacitors 30 connected to the power supply 50 on the substrate 10. Since each capacitor 30 needs to be arranged separately, as the complexity of the circuit increases and the size of the electronic device decreases, the space on the first surface of the substrate 10 is often insufficient to install multiple capacitors 30.

[0039] Optionally, in the present application, multiple capacitors 30 connected to the power supply 50 are provided on the second surface of the substrate 10, without occupying additional space on the first surface of the substrate 10. The electronic components on the second surface of the substrate 10 are connected to the circuit on the second surface of the substrate 10 through multiple metal through-holes 40 that penetrate the first and second surfaces of the substrate 10, and when each capacitor 30 is connected to the multiple metal through-holes 40 corresponding thereto through a trace, the multiple metal through-holes 40 corresponding to each capacitor 30 include multiple first through-holes and multiple second through-holes. The first electrode of each capacitor 30 is electrically connected to the power supply 50 through the multiple first through-holes, that is, the first electrode of each capacitor 30 on the second surface is connected to the multiple first through-holes corresponding thereto through a trace, and is connected to the power supply 50 on the first surface through the multiple first through-holes that penetrate the first and second surfaces of the substrate 10, and the second electrode of each capacitor 30 is grounded through the multiple second through-holes.

[0040] Optionally, since the pins of the power supply 50 provided on the first surface are packaged on the substrate 10 through the pads 20, when the multiple capacitors 30 are connected to the power supply 50 through the corresponding multiple metal through-holes 40, by setting the metal through-hole 40 connected to each capacitor 30 to be located in the gap between the four adjacent pads 20 (i.e., the second area 22 surrounded by the minimum pad array unit 21), the capacitor 30 can be set near the pins of the power supply 50, shortening the lead length required to be set in the middle when the capacitor 30 is connected to the power supply 50 through the metal through-hole, thereby avoiding an increase in inductance during connection. In addition, when the capacitor 30 is connected to the power supply 50 through the corresponding multiple metal through-holes 40 provided in the second area 22, the number of the multiple metal through-holes 40 can be increased without occupying additional area of ​​the substrate 10, thereby reducing the impedance between the capacitor 30 and the power supply 50, improving the connectivity between the capacitor 30 and the power supply 50, and effectively improving the power integrity.

[0041] In this embodiment, the metal through-holes 40 for connecting the capacitors 30 are located in the gaps between the adjacent pads 20, which not only fully utilizes the gaps in the original layout of the multiple array-distributed pads 20, but also increases the number of metal through-holes 40 without occupying additional area of ​​the substrate 10. At the same time, since the metal through-holes 40 for penetrating the first surface and the second surface cannot be set in the area corresponding to the pads 20 on the second surface, each capacitor 30 can be located in the middle of the first area 41 surrounded by the multiple metal through-holes 40 corresponding to it, thereby ensuring the layout and wiring space when the capacitors 30 are laid out based on the multiple metal through-holes 40 connected to it, and the target pad corresponding to each capacitor 30 is located in its corresponding first area 41, making full use of the space of the substrate, so that as many capacitors 30 as possible can be set on the second surface of the substrate 10, thereby improving the power supply performance on the substrate 10.

[0042] See also Figure 3 , Figure 3 FIG. 1 shows a schematic diagram of a packaging structure provided by another embodiment of the present application. Figure 3 As shown, the packaging structure of the present application includes a substrate 10 , a plurality of pads 20 distributed in an array, a plurality of capacitors 30 , a plurality of metal through holes 40 corresponding to each capacitor 30 , and a power supply 50 .

[0043] In this embodiment, the first surface of the substrate 10 is provided with a plurality of array-distributed pads 20 and a power supply 50, the second surface of the substrate 10 is provided with a plurality of capacitors 30, and the substrate 10 is also provided with a plurality of metal through-holes 40 passing through the first surface and the second surface. Each capacitor 30 on the second surface is connected to the power supply 50 on the first surface through the corresponding plurality of metal through-holes 40.

[0044] Optionally, the distance between the centers of any two adjacent pads 20 among the plurality of pads 20 distributed in the array is a set distance, wherein the set distance includes but is not limited to 0.65 mm and 1.0 mm, and each capacitor 30 includes a first side and a second side, and the length of the first side is greater than the length of the second side. In addition, the length of the first side of the capacitor 30 is greater than the set distance (i.e., the distance between the centers of any two adjacent pads 20), that is, the orthographic projection of each capacitor 30 on the plane where the substrate 10 is located at least partially overlaps with the orthographic projections of at least four pads 20 on the plane. Since the smaller the size of the pad 20 on the substrate 10, the less material used for the pad 20, the lower the preparation cost of the pad 20, and the smaller the size of the pad 20, the smaller the corresponding set distance.

[0045] Based on this, when multiple capacitors 30 are set on the second surface of the substrate 10, since the area occupied by the pads 20 on the first surface cannot be set in the area corresponding to the second surface for penetrating the first surface and the second surface, by setting the orthographic projection of each capacitor 30 on the plane where the substrate 10 is located to at least partially overlap with the orthographic projection of the target pad corresponding to each capacitor 30 on the plane, the space of the substrate 10 is fully utilized. On the other hand, each metal through-hole 40 used to achieve electrical connection between the capacitor 30 and the power supply 50 is set in the gap between adjacent pads 20, making full use of the gaps in the original layout of the multiple small-sized pads 20 distributed in an array on the first surface. In this way, the maximum number of capacitors 30 can be set without affecting the original layout of the electronic components on the first surface of the substrate 10, and each capacitor 30 can be connected to the power supply 50 through as many metal through-holes 40 as possible, thereby improving the power supply performance on the substrate 10.

[0046] In some embodiments, the plurality of arrayed pads 20 are a plurality of spherical pad arrays, and the distance is set to 0.65 mm, i.e., the distance between the centers of any two adjacent pads 20 is 0.65 mm. Capacitor 30 includes a first side and a second side, and when the length of the first side of capacitor 30 is greater than the length of the second side, the first side of capacitor 30 is 1.3 mm and the second side of capacitor 30 is 0.5 mm, i.e., capacitor 30 is a 0402 capacitor 30 (capacitor 30 has a length of 1.3 mm and a width of 0.5 mm) or a 0204 capacitor 30 (capacitor 30 has a length of 0.5 mm and a width of 1.3 mm).

[0047] In this embodiment, the number of the multiple metal through holes 40 corresponding to each capacitor 30 is six, and the first area surrounded by the multiple metal through holes 40 includes four target pads, that is, each capacitor 30 corresponds to a minimum pad array unit. In addition, each metal through hole 40 is located in the middle of the second area surrounded by a corresponding minimum pad array unit, and the orthographic projection of each capacitor 30 on the plane where the substrate 10 is located and the orthographic projection of each pad 20 in the corresponding minimum pad array unit on the plane at least partially overlap. At this time, the multiple array-distributed pads 20 can be regularly arranged with as many capacitors 30 as possible in the area corresponding to the second surface, thereby improving the power supply performance on the substrate 10. Among them, the minimum pad array unit includes two adjacent rows of pads 20 and two adjacent columns of pads 20. The number of pads 20 in each row of pads 20 and each column of pads 20 of the minimum pad array unit is 2, that is, each minimum pad array unit includes four adjacent pads 20.

[0048] In this embodiment, when the metal through-holes 40 for penetrating the first surface and the second surface cannot be set in the area corresponding to the second surface of the pad 20, when the length of the first side of each capacitor 30 is greater than the length of the second side. And, when the length of the first side of the capacitor 30 is greater than the distance between the centers of any two adjacent pads 20, by setting the positive projection of each capacitor 30 on the plane where the substrate 10 is located and the positive projection of the target pad corresponding to each capacitor 30 on the plane at least partially overlap, the space of the substrate 10 is fully utilized, and each metal through-hole 40 used to realize the electrical connection between the capacitor 30 and the power supply 50 is set in the gap between adjacent pads 20, making full use of the gaps in the original layout of the multiple array-distributed small-sized pads 20 on the first surface. In this way, the maximum number of capacitors 30 can be set without affecting the original layout of the electronic components on the first surface of the substrate 10, and each capacitor 30 can be connected to the power supply 50 through as many metal through-holes 40 as possible, thereby improving the power supply performance on the substrate 10.

[0049] See also Figure 4 , Figure 4 FIG. 2 shows a schematic diagram of the structure of a chip 2 provided in an embodiment of the present application. Figure 4 As shown, the chip 2 provided in this embodiment includes the above-mentioned packaging structure 1.

[0050] In this embodiment, the chip 2 includes but is not limited to various types of field programmable gate arrays (FPGA), various types of graphic processing units (GPU), and various types of central processing units (CPU).

[0051] Optionally, a substrate is provided in the chip 2, and the first surface of the substrate includes a plurality of pads distributed in an array. When multiple capacitors are set to improve the power supply performance in the chip 2, the multiple capacitors are set on the second surface of the chip 2, and each capacitor is combined with the layout of the multiple metal through-holes corresponding to each capacitor, and each metal through-hole is set to be located in the gap between adjacent pads, and the target pad corresponding to each capacitor is located in the first area surrounded by the multiple metal through-holes corresponding to each capacitor, so that the orthographic projection of each capacitor on the plane where the substrate is located can at least partially overlap with the orthographic projection of the target pad corresponding to each capacitor on the plane. In this way, the gaps in the original layout of the multiple array-distributed pads are fully utilized, the maximum number of capacitors can be set without occupying the first surface of the substrate, and the layout and wiring space of the capacitors is guaranteed, thereby improving the power supply performance in the chip 2.

[0052] In the present application, the above-mentioned packaging structure 1 can be applied to the packaging design of chips 2 such as field programmable logic gate arrays, graphics processors and central processing units, and improves the capacitor layout problem in the design of chip 2. By combining each capacitor with the layout of multiple metal through-holes corresponding to each capacitor, the gaps in the original layout of multiple array-distributed pads are fully utilized, and the maximum number of capacitors can be set without occupying the first surface of the substrate, thereby achieving an improvement in the power supply performance of chip 2.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A packaging structure, characterized in that: The packaging structure includes: a substrate comprising a first surface and a second surface opposite to the first surface; A plurality of solder pads distributed in an array, wherein the plurality of solder pads are arranged on the first surface, and the distance between the centers of any two adjacent solder pads is a set distance; a plurality of capacitors, wherein the plurality of capacitors are disposed on the second surface, and an orthographic projection of each of the capacitors on the plane where the substrate is located at least partially overlaps with an orthographic projection of a target pad corresponding to each of the capacitors on the plane; Each of the capacitors corresponds to a plurality of metal through-holes, the plurality of metal through-holes passing through the first surface and the second surface, each of the capacitors is connected to the plurality of metal through-holes, each of the metal through-holes is located in a gap between adjacent pads, the metal through-hole corresponding to each of the capacitors is a metal through-hole whose distance from each of the capacitors is less than the set distance, and the target pad is located in a first area surrounded by the plurality of metal through-holes.

2. The packaging structure according to claim 1, wherein: Each of the metal through holes is located in a second area surrounded by a minimum pad array unit, the minimum pad array unit includes two adjacent rows of pads and two adjacent columns of pads, and the number of pads in each row and each column of the minimum pad array unit is 2.

3. The packaging structure according to claim 2, wherein: Each of the metal through holes is located in the middle of the second area corresponding to it.

4. The packaging structure according to claim 1, wherein: Each of the capacitors is located in the middle of a first area surrounded by the corresponding plurality of metal through holes.

5. The packaging structure according to claim 1, wherein: Each of the capacitors includes a first side and a second side, the length of the first side is greater than the length of the second side, and the length of the first side is greater than the set distance.

6. The packaging structure according to claim 5, wherein: The set distance is 0.65 mm, the first side of each capacitor is 1.3 mm, and the second side of each capacitor is 0.5 mm.

7. The packaging structure according to claim 6, wherein: The number of the plurality of metal through holes corresponding to each capacitor is six, and the first area surrounded by the plurality of metal through holes includes four target pads.

8. The packaging structure according to any one of claims 1 to 7, characterized in that: The packaging structure further includes a power supply, which is disposed on the first surface. The power supply includes a plurality of pins, and each of the pins is electrically connected to one of the pads.

9. The packaging structure according to claim 8, wherein: The multiple metal through-holes corresponding to each of the capacitors include multiple first through-holes and multiple second through-holes. The first electrode of each of the capacitors is electrically connected to the power supply through the multiple first through-holes, and the second electrode of each of the capacitors is grounded through the multiple second through-holes.

10. A chip, characterized in that: The package structure comprises the package structure according to any one of claims 1 to 9.

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