Semiconductor structure and preparation method thereof

Abstract

The present disclosure provides a semiconductor structure and a method for manufacturing the same, relating to the field of semiconductor technology, and intended to address the technical problem of conductive pads being damaged by etching through. The semiconductor structure comprises a substrate having a first trench, a capacitor, a conductive pad, and a first conductive plug; the capacitor is disposed within the first trench and includes a first electrode layer, a dielectric layer, and a second electrode layer stacked in sequence; the conductive pad is disposed on the substrate and electrically connected to the first electrode layer; the conductive pad includes a compensation layer and a conductive layer stacked in sequence; the first conductive plug is disposed on the substrate; an end of the first conductive plug proximate the substrate extends into the compensation layer and is spaced apart from a surface of the substrate proximate the compensation layer. The present disclosure increases the thickness of the conductive pad to prevent etching through the conductive pad and improves the contact area between the conductive pad and the first conductive plug.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the continuous improvement of chip integration, deep trench capacitors (DTCs) are being used more and more widely. For example, deep trench capacitors can be used in memory cells and silicon interposers to reduce noise in power and data signals.

[0003] In the related art, a conductive pad is typically formed to connect to one electrode plate of a deep trench capacitor, and then a conductive plug is used to electrically connect the conductive pad to the peripheral circuit. However, when preparing the conductive plug connected to the deep trench capacitor, the conductive pad is easily damaged. Summary of the Invention

[0004] In view of the above problems, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can reduce damage to the conductive pad and reduce the contact resistance between the conductive pad and the first conductive plug.

[0005] A first aspect of the present disclosure provides a semiconductor structure, comprising:

[0006] a substrate having a first trench therein;

[0007] A capacitor is disposed in the first trench and includes a first electrode layer, a dielectric layer, and a second electrode layer stacked in sequence;

[0008] a conductive pad, disposed on the substrate and electrically connected to the first electrode layer; wherein the conductive pad comprises a compensation layer and a conductive layer stacked;

[0009] A first conductive plug is disposed on the substrate; an end of the first conductive plug close to the substrate extends into the compensation layer and has a distance from a surface of the substrate close to the compensation layer.

[0010] In some embodiments, the conductive layer is disposed on the compensation layer, and a thickness of the compensation layer is greater than a thickness of the conductive layer.

[0011] In some embodiments, a diameter of the first conductive plug gradually decreases from the compensation layer toward the substrate.

[0012] In some embodiments, the semiconductor structure further includes a first dielectric layer, the first dielectric layer including a first sub-dielectric layer and a second sub-dielectric layer, the first sub-dielectric layer covers the inner wall of the first trench, and the second sub-dielectric layer is disposed on the substrate and connected to the first sub-dielectric layer;

[0013] The first electrode layer at least covers the first sub-dielectric layer.

[0014] In some embodiments, the second electrode layer includes a first sub-electrode layer and a second sub-electrode layer stacked together, and the first sub-electrode layer covers the dielectric layer;

[0015] The second sub-electrode layer is disposed in the area surrounded by the first sub-electrode layer, and a second conductive plug is disposed in the second sub-electrode layer.

[0016] A second aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0017] providing a substrate, and forming a first trench in the substrate;

[0018] forming a capacitor and a conductive pad, wherein the capacitor is disposed in the first trench and comprises a first electrode layer, a dielectric layer, and a second electrode layer stacked in sequence; the conductive pad is disposed on the substrate and electrically connected to the first electrode layer; wherein the conductive pad comprises a compensation layer and a conductive layer stacked in sequence;

[0019] A first conductive plug is formed, and the first conductive plug is disposed on the substrate; an end of the first conductive plug close to the substrate extends into the compensation layer, and a distance is provided between the first conductive plug and a surface of the substrate close to the compensation layer.

[0020] In some embodiments, the steps of forming the capacitor and the conductive pad include:

[0021] forming a dielectric material layer and a compensation material layer stacked on the substrate, wherein the dielectric material layer is disposed on the substrate;

[0022] A first electrode material layer, a dielectric layer and a second electrode layer are formed in the first groove, which are stacked in sequence. The first electrode material layer extends outside the first groove and covers the top surface of the compensation material layer. The dielectric layer and the second electrode layer are arranged in sequence on the first electrode material layer. There is a step surface between the first electrode material layer and the second electrode layer. The first electrode material layer and the compensation material layer covered by the second electrode layer constitute the first electrode layer, the first electrode material layer not covered by the second electrode layer constitutes a conductive layer, and the compensation material layer not covered by the second electrode layer constitutes a compensation layer.

[0023] In some embodiments, after the step of forming a stacked second sub-dielectric layer and a compensation layer on the substrate and before the step of forming the first electrode material layer in the first trench, the method further includes:

[0024] The substrate exposed in the first trench is oxidized to form a first sub-dielectric layer, and the first sub-dielectric layer is connected to the second sub-dielectric layer to form a first dielectric layer; wherein the thickness of the first sub-dielectric layer located on the sidewall of the first trench is less than the thickness of the first sub-dielectric layer located on the bottom wall of the first trench.

[0025] In some embodiments, the step of forming the first electrode material layer, the dielectric layer, and the second electrode layer stacked sequentially in the first trench includes:

[0026] forming a first electrode material layer on an inner wall of the first trench, wherein the first electrode material layer extends outside the first trench and covers the compensation material layer;

[0027] forming a dielectric material layer and a second electrode material layer stacked in sequence on the first electrode material layer;

[0028] At least part of the second electrode material layer, the dielectric material layer, the first electrode material layer and the compensation material layer located on one side of the first groove are removed, and a step surface is formed between the second electrode material layer and the first electrode material layer retained on one side of the first groove; wherein, the exposed first electrode material layer constitutes the conductive layer, the remaining first electrode material layer constitutes the first electrode layer, the retained dielectric material layer constitutes the dielectric layer, the retained second electrode material layer constitutes the second electrode layer, and the exposed compensation material layer constitutes the compensation layer.

[0029] In some embodiments, the step of forming the first conductive plug and simultaneously forming a second conductive plug, wherein the second conductive plug is connected to the second sub-electrode layer, includes:

[0030] forming a second dielectric layer, wherein the second dielectric layer covers the substrate and each film layer located on the substrate;

[0031] patterning the second dielectric layer to form a first contact hole and a second contact hole spaced apart in the second dielectric layer, wherein the first contact hole at least exposes a surface of the compensation layer facing away from the substrate, and the bottom of the second contact hole is located in the second sub-electrode layer;

[0032] A first conductive plug is formed in the first contact hole, and a second conductive plug is formed in the second contact hole.

[0033] In the semiconductor structure and fabrication method provided by the embodiments of the present disclosure, an improvement is made to the conductive pad, which includes a stacked compensation layer and a conductive layer. Specifically, the compensation layer is added to the conductive layer, thereby increasing the thickness of the conductive pad. When subsequently forming a contact hole to accommodate the first conductive plug, the conductive pad can serve as an etch stop layer, preventing the conductive pad from being etched through. This, in turn, prevents the first conductive plug from electrically connecting to other semiconductor devices within the substrate, thereby improving the yield of the semiconductor structure.

[0034] In addition, the bottom of the first conductive plug is located inside the conductive pad, and the bottom surface and part of the side surface of the first conductive plug are wrapped by the conductive pad, which can increase the contact area between the first conductive plug and the conductive pad, reduce the contact resistance between the first conductive plug and the conductive pad, and improve the performance of the semiconductor structure.

[0035] In addition to the technical problems solved by the embodiments of the present disclosure, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and the preparation method thereof provided by the embodiments of the present disclosure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0037] Figure 1 A schematic diagram of a semiconductor structure provided in the related art;

[0038] Figure 2 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0039] Figure 3 A diagram showing the relative positions of the conductive pad and the first conductive plug provided in an embodiment of the present disclosure;

[0040] Figure 4 A diagram of the relative positions of the conductive pad and the first conductive plug provided in the related art;

[0041] Figure 5 A process flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0042] Figure 6 A schematic diagram of forming a dielectric material layer and a compensation material layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0043] Figure 7 A schematic diagram of forming a first trench in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0044] Figure 8 A schematic diagram of forming a second sub-dielectric layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0045] Figure 9 Schematic diagram of forming a first electrode material layer in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0046] Figure 10 A schematic diagram of forming a dielectric material layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0047] Figure 11 Schematic diagram of forming a second electrode material layer in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0048] Figure 12 Schematic diagram of forming a second electrode material layer in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure Figure 2 ;

[0049] Figure 13 A schematic diagram of removing part of a film layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0050] Figure 14 A schematic diagram of forming a capacitor and a conductive pad in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0051] Figure 15 A schematic diagram of forming a second dielectric layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0052] Figure 16 A schematic diagram of forming a first conductive plug and a second conductive plug in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0053] Figure 17 A schematic diagram of forming a first dielectric layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0054] Figure 18 Schematic diagram of forming a first electrode material layer in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure Figure 2 ;

[0055] Figure 19 Schematic diagram of forming a compensation material layer in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure Figure 2 .

[0056] Reference numerals:

[0057] 1: substrate; 2: conductive pad; 3: insulating layer; 4: conductive plug;

[0058] 100: substrate; 110: first trench; 120: second trench;

[0059] 200: capacitor; 210: first electrode layer; 211: first electrode material layer; 230: dielectric layer; 231: dielectric material layer; 220: second electrode layer; 221: first sub-electrode layer; 222: second sub-electrode layer; 223: second electrode material layer; 2231: first layer; 2232: second layer;

[0060] 300: conductive pad; 310: compensation layer; 311: compensation material layer; 320: conductive layer;

[0061] 400: first conductive plug; 410: first surface; 420: second surface;

[0062] 500: first dielectric layer; 510: first sub-dielectric layer; 520: second sub-dielectric layer; 530: dielectric material layer;

[0063] 600: second conductive plug;

[0064] 700: second dielectric layer; 710: first contact hole; 720: second contact hole. DETAILED DESCRIPTION

[0065] As described in the background art, the problem that the conductive pad is easily damaged during the preparation of the conductive plug in the related art is found by the inventors through research. The reason for this problem is that, please refer to the attached Figure 1 The conductive pad 2 is thin in a direction perpendicular to the substrate 1. When etching the insulating layer 3 to form the contact hole, the thin conductive pad 2 cannot serve as an etch barrier, resulting in the contact hole penetrating the conductive pad 2 and even etching part of the substrate 1. The resulting conductive plug 4 may then penetrate the conductive pad 2 and extend into the substrate 1. This could damage the conductive pad 2 and potentially short-circuit the conductive plug 4 with other semiconductor devices within the substrate 1, reducing the yield of the semiconductor structure.

[0066] To address the above technical issues, embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same. By improving the conductive pad, the conductive pad includes a stacked compensation layer and a conductive layer. Specifically, the compensation layer is added to the conductive layer, thereby increasing the thickness of the conductive pad. When subsequently forming a contact hole to accommodate a first conductive plug, the conductive pad can serve as an etch-stop layer, preventing the conductive pad from being etched through. This prevents the first conductive plug from electrically connecting to other semiconductor devices within the substrate, thereby improving the yield of the semiconductor structure.

[0067] In addition, the bottom of the first conductive plug is located inside the conductive pad, and the bottom surface and part of the side surface of the first conductive plug are wrapped by the conductive pad, which can increase the contact area between the first conductive plug and the conductive pad, reduce the contact resistance between the first conductive plug and the conductive pad, and improve the performance of the semiconductor structure.

[0068] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.

[0069] Please refer to the attached Figure 2 The embodiments of the present disclosure provide a semiconductor structure that can be used as a semiconductor device in a dynamic random access memory (DRAM) or as a device in a silicon interposer.

[0070] The semiconductor structure includes a substrate 100, which is used to provide support for the film layer disposed thereon. When the semiconductor structure is used as a device in a dynamic random access memory (DRAM), the material of the substrate 100 may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. When the semiconductor structure is used as a device in a silicon interposer, the material of the substrate 100 may include silicon oxide or silicon nitride.

[0071] The substrate 100 has a first trench 110 (see the attached Figure 7), the depth direction of the first trench 110 is parallel to the direction perpendicular to the substrate 100. It should be noted that the width of the first trench 110 can be uniform along the direction from the top surface to the bottom surface of the substrate 100, or can gradually decrease. This embodiment is not specifically limited here.

[0072] The semiconductor structure also includes a capacitor 200, which is disposed within the first trench 110 so that the capacitor 200 constitutes a deep trench capacitor (DTC). When the capacitor 200 is used as part of a storage unit in a dynamic random access memory (DRAM), compared with the technical solution in the related art in which the capacitor 200 is disposed above the substrate 100, the volume of the dynamic random access memory can be reduced, thereby facilitating the development of the dynamic random access memory toward integration. When the capacitor 200 is used as a device in a silicon adapter board, it can reduce the noise of power signals and / or data signals to ensure the normal operation of chips such as processors and memories. In addition, it can also save space on the silicon adapter board, making it easier to set more or larger-sized silicon through-holes on the adapter board, thereby improving the signal transmission function of the adapter board.

[0073] It should be noted that the capacitor 200 may be partially located in the first trench 110 and partially located on the substrate 100 , so as to facilitate the connection between the electrode layer of the capacitor 200 and the conductive pad.

[0074] The capacitor 200 includes a first electrode layer 210, a dielectric layer 230, and a second electrode layer 220. The first electrode layer 210, the dielectric layer 230, and the second electrode layer 220 are stacked in sequence, with the first electrode layer 210 disposed adjacent to the inner wall of the first trench 110. The dielectric layer 230 conformally covers the first electrode layer 210, and the second electrode layer 220 conformally covers the dielectric layer 230. It should be noted that the first electrode layer 210 may be disposed solely on the inner wall of the first trench 110, or may extend beyond the first trench 110 and overlie the substrate 100.

[0075] In this embodiment, the first electrode layer 210 and the second electrode layer 220 are made of the same material and can both include titanium nitride. The first electrode layer 210 and the second electrode layer 220 are made of different materials. For example, the first electrode layer 210 includes titanium nitride, and the second electrode layer 220 includes a mixture of titanium nitride and polysilicon. The dielectric layer 230 is made of a material with a high dielectric constant K, which can increase the capacitance of the capacitor 200, thereby increasing the storage capacity of the capacitor or improving the noise removal capability of the capacitor. Among them, the material with a high dielectric constant K can include any one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5) and strontium titanium oxide (SrTiO3).

[0076] The semiconductor structure also includes a conductive pad 300, which is disposed on the substrate 100 and connected to the first electrode layer 210. The conductive pad 300 includes a compensation layer 310 and a conductive layer 320, which are stacked. In one example, the compensation layer 310 is disposed on the substrate 100, and the conductive layer 320 is disposed on the compensation layer 310. In another example, the conductive layer 320 is disposed on the substrate 100, and the compensation layer 310 is disposed on the conductive layer 320. The material of the compensation layer 310 can be the same as or different from the material of the conductive layer 320. For example, the material of the compensation layer 310 and the conductive layer 320 can both include titanium nitride.

[0077] As an example, the thickness of the compensation layer 310 is greater than that of the conductive layer 320. For example, the thickness of the compensation layer 310 is 2-3 times the thickness of the conductive layer 320. In one example, the thickness of the compensation layer 310 is between 40nm and 50nm, while the thickness of the conductive layer 320 is between 20nm and 30nm. This maximizes the thickness of the conductive pad 300, expands the process window for the contact hole, and ensures that the bottom of the contact hole stops well within the conductive pad 300. For example, the bottom of the contact hole is ensured to stop well within the compensation layer 310, avoiding etching through the conductive pad 300 and improving the device yield.

[0078] The first conductive plug 400 is disposed on the substrate 100 and extends in a direction perpendicular to the substrate 100. The end of the first conductive plug 400 proximal to the substrate 100 extends into the compensation layer 310, with a gap between the first conductive plug 400 and the surface of the substrate 100 proximal to the compensation layer 310. In other words, the first conductive plug 400 does not penetrate the conductive pad 300. It should be noted that when the compensation layer 310 is disposed on the conductive layer 320, the surface of the first conductive plug 400 facing the substrate 100 is flush with the surface of the compensation layer 310 facing the substrate 100. In other words, the bottom of the contact hole is located exactly at the interface between the compensation layer 310 and the conductive layer 320.

[0079] In this embodiment, the conductive pad 300 is improved to include a stacked compensation layer 310 and a conductive layer 320. That is, the compensation layer 310 is added to the conductive layer 320, thereby increasing the thickness of the conductive pad 300. When subsequently forming a contact hole for accommodating the first conductive plug 400, the conductive pad 300 can serve as an etch stop layer, ensuring that the bottom of the contact hole is located within the conductive pad 300. This prevents the conductive pad 300 from being etched through, thereby improving the process window for the first conductive plug 400 and thereby preventing electrical connection between the first conductive plug 400 and other semiconductor devices within the substrate 100, thereby improving the yield of the semiconductor structure.

[0080] Please refer to the attached Figure 3 , taking the case where the conductive layer 320 is disposed on the compensation layer 310 and the first conductive plug 400 extends into the compensation layer 310 as an example, the contact area between the conductive pad 300 and the first conductive plug 400 is described in detail.

[0081] Taking the cross section parallel to the substrate 100 as the cross section, the cross section of the first conductive plug 400 is circular. The cross section of the first conductive plug 400 and the conductive layer 320 facing away from the substrate 100 is the first surface 410. The diameter of the first surface 410 is d1. The surface of the first conductive plug 400 extending into the compensation layer 310 is the second surface 420. The diameter of the second surface 420 is d2. The contact area S between the first conductive plug 400 and the conductive pad 300 is equal to πd1. 2 +π(d1+d2)h1, where h1 is the vertical distance between the first surface 410 and the second surface 420, that is, the thickness of the conductive layer 320 and the partial thickness of the compensation layer 310.

[0082] Please refer to the attached Figure 4 In the related art, the first conductive plug 400 typically penetrates the conductive pad. Therefore, the contact area between the first conductive plug 400 and the conductive pad is the side surface of the region where the first conductive plug 400 faces the conductive pad. Given the relatively small thickness of the conductive pad, the difference in diameter between the top and bottom surfaces of the region where the first conductive plug 400 faces the conductive pad is very small, denoted as d3. Therefore, in the related art, the contact area between the first conductive plug 400 and the conductive pad is equal to π × d3 × h2, where j2 is the thickness of the conductive layer 320.

[0083] By comparing the above two formulas, the semiconductor structure provided by the embodiment of the present disclosure significantly increases the contact area between the first conductive plug 400 and the conductive pad 300, thereby reducing the contact resistance between the first conductive plug 400 and the conductive pad 300, and greatly improving the reliability of the device.

[0084] As one possible embodiment, the diameter of the first conductive plug 400 gradually decreases from the direction of the compensation layer 310 toward the substrate 100, that is, along the direction from the top surface of the substrate 100 toward the bottom surface of the substrate 100. In other words, when forming the contact hole, the process window becomes smaller and smaller. This reduces the risk of over-etching, avoids the bottom of the contact hole being located within the conductive pad 300, and prevents the conductive pad 300 from being etched through. This improves the process window of the first conductive plug 400, thereby preventing the first conductive plug 400 from being electrically connected to other semiconductor devices located within the substrate 100, and improving the yield of the semiconductor structure.

[0085] In one possible embodiment, the semiconductor structure includes a first dielectric layer 500. The first dielectric layer 500 includes a first sub-dielectric layer 510 and a second sub-dielectric layer 520. The first sub-dielectric layer 510 conformally covers the inner wall of the first trench 110 and is used to provide insulation between the first electrode layer 210 of the capacitor 200 and other semiconductor devices in the substrate 100. The thicknesses of the first sub-dielectric layer 510 and the second sub-dielectric layer 520 may be uniform or unequal.

[0086] The second sub-dielectric layer 520 is disposed on the substrate 100 and connected to the first sub-dielectric layer 510. In other words, the first dielectric layer 500 covers the inner wall of the first trench 110 and extends outside the first trench 110 to cover the substrate 100.

[0087] The first electrode layer 210 covers at least the first sub-dielectric layer 510. In one example, the first electrode layer 210 covers the first sub-dielectric layer 510, so that the capacitor 200 is disposed within the first trench 110. In another example, the first electrode layer 210 covers the first sub-dielectric layer 510 and also covers a portion of the second sub-dielectric layer 520. This can not only increase the storage capacity of the capacitor 200, but also facilitate the connection between the first electrode layer 210 and the conductive pad 300, thereby facilitating signal transmission within the semiconductor structure.

[0088] In this embodiment, the material of the first dielectric layer 500 includes silicon oxide, but is not limited thereto.

[0089] In one possible embodiment, the second electrode layer 220 includes a first sub-electrode layer 221 and a second sub-electrode layer 222, which are stacked. The first sub-electrode layer 221 covers the dielectric layer 230, and the second sub-electrode layer 222 is disposed within the region enclosed by the first sub-electrode layer 221. The first sub-electrode layer 221 is made of titanium nitride, and the second sub-electrode layer 222 is made of polycrystalline silicon.

[0090] A second conductive plug 600 is disposed within the second sub-electrode layer 222. In this embodiment, because the conductive pad 300 is made of titanium nitride and the second sub-electrode layer 222 is made of polysilicon, the two materials are different. This allows for selectively adjusting the etching selectivity when etching to form contact holes, thereby better controlling the depths of the first conductive plug 400 and the second conductive plug 600 and improving the performance of the semiconductor structure.

[0091] It should be noted that the semiconductor structure provided in the embodiment of the present disclosure further includes a second dielectric layer 700. The second dielectric layer 700 covers the substrate 100 and the devices located on the substrate 100. This configuration can achieve an insulating configuration for the first conductive plug 400 and the second conductive plug 600. The material of the second dielectric layer 700 includes, but is not limited to, silicon nitride.

[0092] Please refer to the attached Figure 5 The present disclosure also provides a method for preparing a semiconductor structure, comprising the following steps:

[0093] Step S100: providing a substrate and forming a first trench in the substrate.

[0094] For example, a first trench 110 is formed in the substrate 100 by a patterning process, wherein the depth direction of the first trench 110 is perpendicular to the substrate 100. The patterning process may be a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process.

[0095] It should be noted that, when the semiconductor structure of this embodiment is a partial structure of a dynamic random access memory (DRAM), the first trench 110 may be formed in the active region.

[0096] Step S200: forming a capacitor and a conductive pad, wherein the capacitor is arranged in the first trench, and the capacitor includes a first electrode layer, a dielectric layer, and a second electrode layer stacked in sequence; the conductive pad is arranged on the substrate and electrically connected to the first electrode layer; wherein the conductive pad includes a compensation layer and a conductive layer stacked.

[0097] It should be noted that in this embodiment, the compensation layer 310 of the conductive pad 300 can be located below or above the conductive layer 320. The different locations of the compensation layer 310 and the conductive layer 320 require different steps.

[0098] In one possible embodiment, the conductive layer 320 is disposed on the compensation layer 310. The preparation steps are as follows: a dielectric material layer 530 and a compensation material layer 311 are stacked on a substrate 100, wherein the dielectric material layer 530 is disposed on the substrate 100. The compensation material layer 311 is disposed on a surface of the dielectric material layer 530 facing away from the substrate 100. It should be noted that the dielectric material layer 530 and the compensation material layer 311 can be formed by directly depositing them on the substrate 100 after forming the first trench 110. Alternatively, they can be formed simultaneously during the formation of the first trench 110.

[0099] For example, please refer to the attached Figure 6 , a dielectric material layer 530 and a compensation material layer 311 are sequentially stacked on the substrate 100 using a physical vapor deposition (PVD) process. In this embodiment, the compensation material layer 311 is formed using the PVD process, which ensures that the compensation material layer 311 can be formed to a relatively large thickness, thereby maximizing the thickness of the subsequently formed conductive pad 300.

[0100] Afterwards, please refer to the attached Figure 7 The compensation material layer 311 , the dielectric material layer 530 and the substrate 100 are patterned to form a first trench 110 in the substrate 100 . The remaining dielectric material layer 530 constitutes the second sub-dielectric layer 520 .

[0101] Afterwards, please refer to the attached Figure 8 The substrate 100 exposed in the first trench 110 is oxidized to form a first sub-dielectric layer 510. The first sub-dielectric layer 510 is connected to the second sub-dielectric layer 520 to form the first dielectric layer 500. In this embodiment, by directly oxidizing the substrate 100, the first sub-dielectric layer 510 of a certain thickness can be formed only on the inner wall of the first trench 110. This eliminates the need to form a film layer of a certain thickness on the compensation layer 310. This reduces the step of removing the film layer on the compensation layer 310, thereby simplifying the process and reducing production costs.

[0102] In this embodiment, the thickness of the first sub-dielectric layer 510 located on the sidewalls of the first trench 110 is less than the thickness of the first sub-dielectric layer 510 located on the bottom wall of the first trench 110. When a voltage is applied to the capacitor, the potential tends to accumulate at the bottom of the first trench 110. Therefore, in this embodiment, the thickness of the first sub-dielectric layer 510 located on the bottom wall of the first trench 110 is greater.

[0103] Afterwards, please refer to the attached Figure 9 To the attached Figure 14A first electrode material layer 211, a dielectric layer 230, and a second electrode layer 220 are formed in sequence in the first trench 110. The first electrode material layer 211 extends outside the first trench 110 and covers the top surface of the compensation material layer 311. The dielectric layer 230 and the second electrode layer 220 are sequentially arranged on the first electrode material layer 211. There is a step surface between the first electrode material layer 211 and the second electrode layer 220. The first electrode material layer 211 and the compensation material layer 311 covered by the second electrode layer 220 constitute the first electrode layer 210, and the compensation material layer 311 not covered by the second electrode layer 220 constitutes the compensation layer 310.

[0104] For example, please refer to the attached Figure 9 A first electrode material layer 211 is formed on the inner wall of the first trench 110 using an atomic layer deposition process. The first electrode material layer 211 extends outside the first trench 110 and covers the compensation material layer 311. In this embodiment, the first electrode material layer 211 is formed using an atomic layer deposition process, which can improve the uniformity of the first electrode material layer 211 and thereby improve the step coverage of the first electrode material layer 211.

[0105] Afterwards, please refer to the attached Figure 10 To the attached Figure 12 Continuing to use the atomic layer deposition process, a dielectric material layer 231 and a second electrode material layer 223 are sequentially stacked on the first electrode material layer 211. The second electrode material layer 223 fills the area surrounded by the dielectric material layer 231. The dielectric material layer 231 conformally covers the first electrode material layer 211.

[0106] The second electrode material layer 223 may include a double-layer structure. Exemplarily, the second electrode material layer 223 includes a first layer 2231 and a second layer 2232, wherein the first layer 2231 conformally covers the dielectric material layer 231. The first layer 2231 surrounds the second trench 120 within the first trench. Subsequently, a second layer 2232 is formed within the second trench 120 using a physical vapor deposition process. The second layer 2232 completely fills the second trench 120, extends outside the second trench 120, and covers the first layer 2231. In this embodiment, the material of the first layer 2231 includes titanium nitride, and the material of the second layer 2232 includes polysilicon.

[0107] Afterwards, please refer to the attached Figure 13 and attached Figure 14, at least part of the second electrode material layer 223, the dielectric material layer 231, the first electrode material layer 211 and the compensation material layer 311 located on one side of the first trench 110 are removed, and a step surface is formed between the second electrode material layer 223 and the first electrode material layer 211 retained on one side of the first trench 110; wherein, the exposed first electrode material layer 211 constitutes the conductive layer 320, the remaining first electrode material layer 211 constitutes the first electrode layer 210, the retained dielectric material layer 231 constitutes the dielectric layer 230, the retained second electrode material layer 223 constitutes the second electrode layer 220, and the exposed compensation material layer 311 constitutes the compensation layer 310.

[0108] For example, please refer to the attached Figure 13 , a first etching process is used to remove part of the second electrode material layer 223, the dielectric material layer 231, the first electrode material layer 211, the compensation material layer 311, and the second sub-dielectric layer 520. Figure 14 A second etching process is then used to remove portions of the second electrode material layer 223 and the dielectric material layer 231, so that the remaining second electrode material layer 223 constitutes the second electrode layer 220, and the remaining dielectric material layer 231 constitutes the dielectric layer 230. At this point, a step surface exists between the second electrode layer 220 and the remaining first electrode material layer 211. That is, a portion of the first electrode material layer 211 is located directly below the second electrode layer 220, and the remaining portion of the first electrode material layer 211 is not blocked by the second electrode layer 220.

[0109] Therefore, the first electrode material layer 211 and the compensation material layer 311 covered by the second electrode layer 220 constitute the first electrode layer 210, the first electrode material layer 211 not covered by the second electrode layer 220 constitutes the conductive layer 320, and the compensation material layer 311 not covered by the second electrode layer 220 constitutes the compensation layer 310. The stacked compensation layer 310 and the conductive layer 320 constitute the conductive pad 300.

[0110] Step S300: forming a first conductive plug, wherein the first conductive plug is disposed on a substrate; an end of the first conductive plug close to the substrate extends into the compensation layer and has a distance from a surface of the substrate close to the compensation layer.

[0111] Please refer to the attached Figure 15 , forming a second dielectric layer 700, the second dielectric layer 700 covers the substrate 100 and each film layer located on the substrate 100, and the top surface of the second dielectric layer 700 is higher than the top surface of the second electrode layer 220. The material of the second dielectric layer 700 includes silicon nitride, but is not limited thereto.

[0112] Please refer to the attached Figure 16The second dielectric layer 700 is patterned to form first contact holes 710 and second contact holes 720 spaced apart in the second dielectric layer 700. The first contact holes 710 expose at least the surface of the compensation layer 310 facing away from the substrate 100. That is, the bottom of the first contact hole 710 is the top surface of the compensation layer 310, and the bottom of the second contact hole 720 is located within the compensation layer 310. The bottom of the second contact hole 720 is located within the second sub-electrode layer 222.

[0113] Afterwards, continue to refer to the attached Figure 2 Conductive material is deposited in the first contact hole 710 and the second contact hole 720 using a deposition process to form a first conductive plug 400 in the first contact hole 710 and a second conductive plug 600 in the second contact hole 720. In this step, the second conductive plug 600 connected to the second sub-electrode layer 222 can be formed simultaneously with the first conductive plug 400, thereby simplifying the preparation process of the first conductive plug 400 and the second conductive plug 600. The first conductive plug 400 and the second conductive plug 600 are made of the same material, both comprising metal tungsten.

[0114] When forming the first contact hole 710 and the second contact hole 720, given the relatively large thickness of the conductive pad 300, the process window for the first contact hole 710 can be expanded to ensure that the bottom of the first contact hole 710 is preferably located within the conductive pad 300. For example, the bottom of the first contact hole 710 is preferably located within the compensation layer 310 to avoid etching through the conductive pad 300, thereby improving the yield of the device. In one possible embodiment, the compensation layer 310 is disposed on the conductive layer 320, and its preparation steps are as follows:

[0115] Please refer to the attached Figure 17 A dielectric material layer is formed on the inner wall of the first trench 110 using an atomic deposition process. The dielectric material layer extends outside the first trench 110 and covers the substrate 100. The dielectric material layer on the inner wall of the first trench 110 constitutes a first sub-dielectric layer 510, and the dielectric material layer on the substrate 100 constitutes a second sub-dielectric layer 520.

[0116] Afterwards, please refer to the attached Figure 18 , forming a first electrode material layer 211 on the dielectric material layer.

[0117] Afterwards, please refer to the attached Figure 19 , forming a compensation material layer 311 , the compensation material layer 311 is located on the surface of the first electrode material layer 211 on the substrate 100 .

[0118] You can refer to the attached Figure 10 To the attached Figure 16The preparation is performed, and thus, in the formed conductive pad 300 , the conductive layer 320 is located between the compensation layer 310 and the substrate 100 .

[0119] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0120] In the description of this specification, reference to terms such as "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0121] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: a substrate having a first trench therein; a capacitor disposed in the first trench and comprising a first electrode layer, a dielectric layer, and a second electrode layer stacked in sequence, the second electrode layer comprising a first sub-electrode layer and a second sub-electrode layer stacked in sequence, the first sub-electrode layer covering the dielectric layer; and the second sub-electrode layer disposed within an area enclosed by the first sub-electrode layer; a conductive pad, disposed on the substrate and electrically connected to the first electrode layer; wherein the conductive pad comprises a compensation layer and a conductive layer stacked; a first conductive plug, the first conductive plug being disposed on the substrate; an end of the first conductive plug close to the substrate extending into the compensation layer and having a distance therebetween from a surface of the substrate close to the compensation layer; A second conductive plug is provided in the second sub-electrode layer.

2. The semiconductor structure according to claim 1, wherein: The conductive layer is disposed on the compensation layer, and a thickness of the compensation layer is greater than a thickness of the conductive layer.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The diameter of the first conductive plug gradually decreases from the compensation layer to the substrate.

4. The semiconductor structure according to claim 1 or 2, characterized in that: The semiconductor structure further includes a first dielectric layer, the first dielectric layer including a first sub-dielectric layer and a second sub-dielectric layer, the first sub-dielectric layer covers the inner wall of the first trench, and the second sub-dielectric layer is disposed on the substrate and connected to the first sub-dielectric layer; The first electrode layer at least covers the first sub-dielectric layer.

5. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate, and forming a first trench in the substrate; A capacitor and a conductive pad are formed, wherein the capacitor is disposed in the first trench and includes a first electrode layer, a dielectric layer, and a second electrode layer stacked in sequence, wherein the second electrode layer includes a first sub-electrode layer and a second sub-electrode layer stacked in sequence, wherein the first sub-electrode layer covers the dielectric layer; the second sub-electrode layer is disposed in an area enclosed by the first sub-electrode layer; the conductive pad is disposed on the substrate and electrically connected to the first electrode layer; wherein the conductive pad includes a compensation layer and a conductive layer stacked in sequence; forming a first conductive plug, wherein the first conductive plug is disposed on the substrate; an end of the first conductive plug close to the substrate extends into the compensation layer and has a distance from a surface of the substrate close to the compensation layer; A second conductive plug is formed, wherein the second conductive plug is disposed in the second sub-electrode layer.

6. The method for preparing a semiconductor structure according to claim 5, wherein: The steps of forming the capacitor and the conductive pad include: forming a dielectric material layer and a compensation material layer stacked on the substrate, wherein the dielectric material layer is disposed on the substrate; A first electrode material layer, a dielectric layer and a second electrode layer are formed in the first groove, which are stacked in sequence. The first electrode material layer extends outside the first groove and covers the top surface of the compensation material layer. The dielectric layer and the second electrode layer are arranged in sequence on the first electrode material layer. There is a step surface between the first electrode material layer and the second electrode layer. The first electrode material layer and the compensation material layer covered by the second electrode layer constitute the first electrode layer, the first electrode material layer not covered by the second electrode layer constitutes a conductive layer, and the compensation material layer not covered by the second electrode layer constitutes a compensation layer.

7. The method for preparing a semiconductor structure according to claim 6, wherein: After the step of forming a stacked second sub-dielectric layer and a compensation layer on the substrate and before the step of forming the first electrode material layer in the first trench, the method further includes: The substrate exposed in the first trench is oxidized to form a first sub-dielectric layer, and the first sub-dielectric layer is connected to the second sub-dielectric layer to form a first dielectric layer; wherein the thickness of the first sub-dielectric layer located on the sidewall of the first trench is less than the thickness of the first sub-dielectric layer located on the bottom wall of the first trench.

8. The method for preparing a semiconductor structure according to claim 7, wherein: The step of forming the first electrode material layer, the dielectric layer, and the second electrode layer stacked in sequence in the first trench comprises: forming a first electrode material layer on an inner wall of the first trench, wherein the first electrode material layer extends outside the first trench and covers the compensation material layer; forming a dielectric material layer and a second electrode material layer stacked in sequence on the first electrode material layer; At least part of the second electrode material layer, the dielectric material layer, the first electrode material layer and the compensation material layer located on one side of the first groove are removed, and a step surface is formed between the second electrode material layer and the first electrode material layer retained on one side of the first groove; wherein, the exposed first electrode material layer constitutes the conductive layer, the remaining first electrode material layer constitutes the first electrode layer, the retained dielectric material layer constitutes the dielectric layer, the retained second electrode material layer constitutes the second electrode layer, and the exposed compensation material layer constitutes the compensation layer.

9. The method for preparing a semiconductor structure according to claim 7, wherein: The step of forming the first conductive plug simultaneously forms a second conductive plug connected to the second sub-electrode layer, comprising: forming a second dielectric layer, wherein the second dielectric layer covers the substrate and each film layer located on the substrate; patterning the second dielectric layer to form a first contact hole and a second contact hole spaced apart in the second dielectric layer, wherein the first contact hole at least exposes a surface of the compensation layer facing away from the substrate, and the bottom of the second contact hole is located in the second sub-electrode layer; A first conductive plug is formed in the first contact hole, and a second conductive plug is formed in the second contact hole.

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