A semiconductor package structure and a forming method thereof

Abstract

The embodiments of the present disclosure disclose a semiconductor package structure and a forming method thereof. The semiconductor package structure comprises a substrate and a plurality of chips. The substrate comprises a recess and a substrate via. The recess and the substrate via both penetrate the substrate along a vertical direction. The substrate via is located outside the recess. The plurality of chips are stacked in the recess along the vertical direction and are electrically connected to corresponding substrate vias and are communicatively interconnected through the substrate vias.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a semiconductor packaging structure and a method for forming the same. Background Technology

[0002] 3D chip packaging technology involves stacking two or more chips vertically within a single packaging structure. This improves many chip performance aspects, such as size, weight, speed, yield, and power consumption. However, there are still areas for optimization in 3D chip packaging technologies, requiring further improvements in product performance and cost reduction. Summary of the Invention

[0003] In view of this, the present disclosure provides a semiconductor packaging structure and a method for forming the same, which can improve product performance and save costs.

[0004] The technical solution of this disclosure embodiment is implemented as follows:

[0005] This disclosure provides a semiconductor packaging structure, comprising: a substrate, the substrate including a groove and a via; both the groove and the via penetrate the substrate in a vertical direction; the via is located outside the groove; a plurality of chips are stacked in the groove in the vertical direction and electrically connected to the corresponding via; the plurality of chips are interconnected through the via.

[0006] In some embodiments, the semiconductor package structure further includes: two redistribution layers; the two redistribution layers are respectively located on the front and back sides of the substrate; each chip is electrically connected to a corresponding via of the substrate through a corresponding redistribution layer.

[0007] In some embodiments, the plurality of chips include: a first chip and a second chip; the front side of the first chip faces the same direction as the front side of the substrate and is electrically connected to the redistribution layer located on the front side of the substrate via conductive bumps; the front side of the second chip faces the same direction as the back side of the substrate and is electrically connected to the redistribution layer located on the back side of the substrate via conductive bumps.

[0008] In some embodiments, the plurality of chips include: a first chip, a second chip, a third chip, and a fourth chip stacked sequentially; the first chip and the second chip are stacked in a staggered manner along a first direction; the third chip and the fourth chip are stacked in a staggered manner along the first direction; the first direction is perpendicular to the vertical direction; the front faces of the first chip and the second chip are aligned with the front face of the substrate; the front faces of the third chip and the fourth chip are aligned with the back face of the substrate.

[0009] In some embodiments, the front side of the first chip is electrically connected to the redistribution layer located on the front side of the substrate via conductive bumps; the front side of the second chip is electrically connected to the redistribution layer located on the front side of the substrate via conductive pillars; the front side of the third chip is electrically connected to the redistribution layer located on the back side of the substrate via conductive pillars; and the front side of the fourth chip is electrically connected to the redistribution layer located on the back side of the substrate via conductive bumps.

[0010] In some embodiments, adjacent chips are bonded together by an adhesive film.

[0011] In some embodiments, an insulating layer is filled between the inner wall of the groove and the sidewalls of the plurality of chips.

[0012] In some embodiments, the number of substrates is multiple; the multiple substrates are stacked along the vertical direction; a molding compound is filled between adjacent substrates; and the chips located in different substrates and adjacent to each other are bonded and electrically connected.

[0013] In some embodiments, both the adhesive film and the encapsulating material comprise: resin and filler; wherein the filler is silicon oxide or aluminum oxide; the filler content of the encapsulating material is greater than the filler content of the adhesive film; and the filler volume of the encapsulating material is smaller than the filler volume of the adhesive film.

[0014] In some embodiments, the coefficient of thermal expansion of the molding compound is greater than that of the substrate.

[0015] This disclosure also provides a method for forming a semiconductor package structure, the method comprising: providing a substrate; etching the substrate to form a groove; the groove penetrating the substrate in a vertical direction; stacking a plurality of chips in the groove in the vertical direction; forming a substrate via in the substrate; the substrate via penetrating the substrate in the vertical direction and located outside the groove; electrically connecting the plurality of chips to corresponding substrate vias; and interconnecting the plurality of chips through the substrate vias.

[0016] In some embodiments, electrically connecting a plurality of the chips to corresponding substrate vias includes: forming a first redistribution layer on the front side of the substrate to electrically connect a portion of the chips to the corresponding substrate vias; wherein the front side of a portion of the chips faces the same direction as the front side of the substrate; thinning the back side of the substrate to expose another portion of the chips; wherein the front side of the other portion of the chips faces the same direction as the back side of the substrate; and forming a second redistribution layer on the back side of the substrate to electrically connect another portion of the chips to the corresponding substrate vias.

[0017] In some embodiments, stacking a plurality of the chips in the groove along the vertical direction includes: implanting a first chip into the groove and bonding the first chip to the bottom surface of the groove with an adhesive film; sequentially implanting the remaining chips into the groove and bonding adjacent chips with an adhesive film; and filling an insulating layer between the inner wall of the groove and the sidewalls of the plurality of chips.

[0018] In some embodiments, after electrically connecting the plurality of chips to the corresponding substrate vias, the forming method further includes: performing a dicing process on the substrate; hot-press bonding the substrate to a substrate; wherein the hot-press bonding position is according to the position of the substrate vias; and forming a molding compound surrounding the substrate by an injection molding process.

[0019] In some embodiments, the number of substrates is multiple; thermally bonding the substrates to the substrate includes: thermally bonding the first substrate to the substrate; sequentially stacking the remaining chips on the first substrate, and thermally bonding adjacent substrates.

[0020] Therefore, this disclosure provides a semiconductor packaging structure and its formation method. The semiconductor packaging structure includes a substrate and multiple chips. The substrate includes recesses and vias. Both the recesses and vias penetrate the substrate vertically. The vias are located outside the recesses. Multiple chips are stacked vertically in the recesses and electrically connected to corresponding vias, and are interconnected through the vias. In this way, multiple chips achieve vertical interconnection (i.e., three-dimensional package interconnection) through the vias, that is, inter-chip communication interconnection is achieved without forming vias through the chips. Thus, on the one hand, it is not necessary to reserve area in the chip for vias and the KOZ (exclusion zone) near the vias, which can reduce the chip size and increase DPW (die count); on the other hand, it can simplify the process and save costs. Attached Figure Description

[0021] Figure 1 A schematic diagram of the semiconductor packaging structure provided in the embodiments of this disclosure. Figure 1 ;

[0022] Figure 2 A schematic diagram of the semiconductor packaging structure provided in the embodiments of this disclosure. Figure 2 ;

[0023] Figure 3 A schematic diagram of the semiconductor packaging structure provided in the embodiments of this disclosure. Figure 3 ;

[0024] Figure 4 A schematic diagram of the semiconductor packaging structure provided in the embodiments of this disclosure. Figure 4 ;

[0025] Figure 5 A schematic diagram of the semiconductor packaging structure provided in the embodiments of this disclosure. Figure 5 ;

[0026] Figure 6 A schematic diagram of the semiconductor packaging structure provided in the embodiments of this disclosure. Figure 6 ;

[0027] Figure 7 A schematic diagram of the semiconductor packaging structure provided in the embodiments of this disclosure. Figure 7 ;

[0028] Figure 8 Flowchart of the method for forming a semiconductor package structure provided in the embodiments of this disclosure Figure 1 ;

[0029] Figure 9 Flowchart of the method for forming a semiconductor package structure provided in the embodiments of this disclosure Figure 2 ;

[0030] Figure 10 Flowchart of the method for forming a semiconductor package structure provided in the embodiments of this disclosure Figure 3 ;

[0031] Figure 11 Schematic diagram of the method for forming a semiconductor packaging structure provided in the embodiments of this disclosure Figure 1 ;

[0032] Figure 12 Schematic diagram of the method for forming a semiconductor packaging structure provided in the embodiments of this disclosure Figure 2 ;

[0033] Figure 13 Schematic diagram of the method for forming a semiconductor packaging structure provided in the embodiments of this disclosure Figure 3 ;

[0034] Figure 14 Schematic diagram of the method for forming a semiconductor packaging structure provided in the embodiments of this disclosure Figure 4 ;

[0035] Figure 15 Schematic diagram of the method for forming a semiconductor packaging structure provided in the embodiments of this disclosure Figure 5 ;

[0036] Figure 16 Schematic diagram of the method for forming a semiconductor packaging structure provided in the embodiments of this disclosure Figure 6 ;

[0037] Figure 17Schematic diagram of the method for forming a semiconductor packaging structure provided in the embodiments of this disclosure Figure 7 . Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0039] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0040] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0042] The following is an explanation of some terms used in the embodiments of this disclosure:

[0043] RDL (Re-distributed Layer): A wiring pattern formed on the surface of a chip that rearranges the chip's I / O ports.

[0044] TSV (Through Silicon Via): A structure that uses vertical through-holes for electrical connection.

[0045] KOZ (Keep Out Zone): The region adjacent to a particular semiconductor structure. To avoid interference, no other semiconductor structures can be placed in the KOZ.

[0046] DPW (Die Per Wafer): refers to the number of dies that can be cut from each wafer.

[0047] FO (Fan-out): A packaging method where the solder joints can be set beyond the area of ​​the bare die, providing more I / O solder joints.

[0048] Figure 1 This is a schematic diagram of an optional semiconductor packaging structure provided in an embodiment of this disclosure. Figure 1 This is a sectional view. For example... Figure 1 As shown, the semiconductor package structure includes: a substrate 10 and multiple chips (i.e., ... Figure 1 (First chip 201 and second chip 202 in the process).

[0049] refer to Figure 1 The substrate 10 includes a groove 101 and a substrate via 11, wherein both the groove 101 and the substrate via 11 penetrate the substrate 10 along the vertical direction Z, and the substrate via 11 is located outside the groove 101. Multiple chips (i.e., the first chip 201 and the second chip 202) are stacked in the groove 101 along the vertical direction Z and are electrically connected to the corresponding substrate via 11; the multiple chips are interconnected through the substrate via 11.

[0050] In this embodiment of the disclosure, reference is made to Figure 1 The substrate 10 can be made of a semiconductor material, such as a silicon substrate. Correspondingly, the substrate via 11 can be a TSV. The substrate via 11 can be filled with conductive materials such as copper, tungsten, or polysilicon to interconnect multiple chips (i.e., the first chip 201 and the second chip 202).

[0051] In this embodiment of the disclosure, the semiconductor material used in the substrate 10 can be the same as the semiconductor material used in multiple chips (i.e., the first chip 201 and the second chip 202). In this way, the stress caused by the difference in CTE (coefficient of thermal expansion) between the various structures can be eliminated, thereby avoiding warpage.

[0052] In this embodiment of the disclosure, reference continues to be made to Figure 1 The groove 101 penetrates the substrate 10 in the vertical direction Z, and the first chip 201 and the second chip 202 are implanted in the groove 101. The substrate through hole 11 is located outside the groove 101, that is, the substrate through hole 11 is located outside the first chip 201 and the second chip 202, and no through hole is formed inside the first chip 201 and the second chip 202.

[0053] It should be noted that forming vias within the chip, especially during the packaging process where these vias need to be exposed on the back of the chip, incurs higher costs and increases process complexity. Furthermore, forming vias within the chip requires reserving space within the chip for the vias and the surrounding KOZ (Knock-Up Zone), thus occupying more chip area and hindering the reduction of chip size.

[0054] It is understood that in this embodiment of the present disclosure, multiple chips achieve vertical communication interconnection (i.e., three-dimensional packaged interconnection) through substrate vias. This eliminates the need to form vias throughout the chip to achieve inter-chip communication interconnection. Therefore, on the one hand, it eliminates the need to reserve area in the chip for vias and the KOZ area near the vias, allowing for a reduction in chip size and improved DPW; on the other hand, it simplifies the manufacturing process and saves costs.

[0055] Meanwhile, in this embodiment, the TSV is placed within the silicon substrate, eliminating the need to consider the impact of the TSV on internal chip components. Fabricating a larger diameter TSV within the silicon substrate reduces the TSV's aspect ratio, simplifies the manufacturing process, and also results in lower resistance in the overall circuit, thus reducing device power consumption. Furthermore, since the TSV is not within the chip, the impact of TSV heat generation on the chip is also mitigated.

[0056] Meanwhile, if the TSV structure is fabricated in each chip, a TSV exposure process is required for each chip. Due to the thinness of individual chips, the stress during the TSV exposure process increases the risk of warping and fragmentation. However, the embodiments of this disclosure only require a single TSV exposure process on the back side of the substrate. By stacking multiple chips (e.g., two or four chips) together to increase the overall thickness, and then performing the TSV back-side exposure process, the risk of chip fragmentation is reduced, the chip warping problem is improved, and the TSV exposure process requirement is reduced by 50%, simplifying the process and improving product yield.

[0057] In some embodiments of this disclosure, reference is made to Figure 1 The semiconductor package structure also includes two redistribution layers 301 and 302. The two redistribution layers 301 and 302 are located on the front and back sides of the substrate 10, respectively, wherein redistribution layer 301 is located on the front side of the substrate 10 and redistribution layer 302 is located on the back side of the substrate 10.

[0058] In this embodiment of the disclosure, reference continues to be made to Figure 1 The first chip 201 is electrically connected to the corresponding substrate via 11 through a redistribution layer 301, and the second chip 202 is electrically connected to the corresponding substrate via 11 through a redistribution layer 302. In other words, each chip is electrically connected to the corresponding substrate via 11 through a corresponding redistribution layer.

[0059] Figure 2 This is a schematic diagram of an optional semiconductor packaging structure provided in an embodiment of this disclosure. Figure 2 This is a top view. Figure 2 The routing diagram of redistribution layer 301 is shown in the example.

[0060] refer to Figure 2 The redistribution layer 301 electrically connects the ports on the first chip 201 to the corresponding substrate vias 11. The wiring pattern of the redistribution layer 302 can be found in [reference needed]. Figure 2 Understand the wiring diagram of the medium-heavy wiring layer 301.

[0061] It should be noted that, in Figure 2 In this configuration, the redistribution layer 301 connects each port on the first chip 201 to a substrate via 11 on the same side. However, the wiring pattern of the redistribution layer 301 can be adjusted as needed and is not limited to... Figure 2 The wiring pattern shown, for example, redistributes each port on the first chip 201 to a substrate via 11 on the opposite side, without limitation.

[0062] Understandably, by using a redistribution layer, each chip is electrically connected to a corresponding via in the substrate to achieve communication interconnection between the chips. This eliminates the need to form vias throughout the chip to achieve inter-chip communication interconnection. Therefore, on the one hand, it eliminates the need to reserve area in the chip for vias and the KOZ area near them, allowing for a reduction in chip size and improved DPW (Distribution Power W). On the other hand, it eliminates the need for the related processes of forming vias in the chip, thus simplifying the process and saving costs.

[0063] At the same time, by using a redistribution layer, the ports on the chip can be rearranged, so the ports on the chip can be designed to be more compact, thereby reducing the size of the chip.

[0064] In this embodiment of the disclosure, reference is made to Figure 1 The front side of the first chip 201 faces the same direction as the front side of the substrate 10 and is electrically connected to the redistribution layer 301 on the front side of the substrate 10 via conductive bumps 401. The front side of the second chip 202 faces the same direction as the back side of the substrate 10 and is electrically connected to the redistribution layer 302 on the back side of the substrate 10 via conductive bumps (or pads) 401.

[0065] Figure 4 and Figure 5 These are schematic diagrams of two other optional semiconductor packaging structures provided in the embodiments of this disclosure. Figure 4 and Figure 5 All are sectional views.

[0066] like Figure 4 or Figure 5As shown, the multiple chips include: a first chip 201, a second chip 202, a third chip 203, and a fourth chip 204 stacked sequentially. The first chip 201 and the second chip 202 are stacked in a staggered manner along a first direction X. The third chip 203 and the fourth chip 204 are also stacked in a staggered manner along the first direction X. The first direction X is perpendicular to the vertical direction Z. The front faces of the first chip 201 and the second chip 202 are aligned with the front face of the substrate 10. The front faces of the third chip 203 and the fourth chip 204 are aligned with the back face of the substrate 10.

[0067] In this embodiment of the disclosure, reference continues to be made to Figure 4 or Figure 5 The front side of the first chip 201 is electrically connected to the redistribution layer 301 on the front side of the substrate 10 via conductive bumps 401. The front side of the second chip 202 is electrically connected to the redistribution layer 301 on the front side of the substrate 10 via conductive posts 402. The front side of the third chip 203 is electrically connected to the redistribution layer 302 on the back side of the substrate 10 via conductive posts 402. The front side of the fourth chip 204 is electrically connected to the redistribution layer 302 on the back side of the substrate 10 via conductive bumps 401.

[0068] It should be noted that, Figure 4 In the semiconductor package structure shown, the projections of the second chip 202 and the third chip 203 along the vertical direction Z coincide; that is, the second chip 202 and the third chip 203 are not stacked in a staggered manner along the first direction X. Figure 5 In the semiconductor packaging structure shown, the second chip 202 and the third chip 203 are also stacked in a staggered manner along the first direction X; that is, any two adjacent chips among the multiple chips 201 to 204 are stacked in a staggered manner along the first direction X.

[0069] Figure 5 In the semiconductor package structure shown, the transmission path length between the first chip 201 and the third chip 203 is the same as the transmission path length between the second chip 202 and the fourth chip 204. That is, both sets of transmission paths include conductive bumps 401 and conductive pillars 402, thus ensuring that the lengths of the two sets of transmission paths are consistent.

[0070] As is understandable, multiple chips are stacked in recesses within the substrate, with adjacent chips staggered. Simultaneously, these chips are electrically connected to the redistribution layer via conductive bumps or pillars, and further electrically connected to corresponding substrate vias to achieve communication interconnection. This enables three-dimensional packaging of multiple chips, improving integration and product performance.

[0071] In some embodiments of this disclosure, reference is made to Figures 3 to 5In any of the accompanying drawings, adjacent chips are bonded together by an adhesive film 501. The adhesive film 501 includes resin and filler; the filler can be silicon oxide (SiO) or aluminum oxide (AlO). The adhesive film 501 has a heat insulation function, thus ensuring that the heat generated by each chip does not affect each other, thereby ensuring stable operating conditions for each chip.

[0072] In some embodiments of this disclosure, reference is made to Figures 3 to 5 In any of the accompanying drawings, an insulating layer 502 is filled between the inner wall of the groove and the sidewalls of the multiple chips. The insulating layer 502 can be made of polyimide (PI). The insulating layer 502 needs to have better filling performance, meaning that the filler volume of the insulating layer 502 is smaller than the filler volume of the adhesive film 501, and the filler content of the insulating layer 502 is also smaller than the filler content of the adhesive film 501.

[0073] Understandably, filling the sidewalls of the chip with insulating layer 502 serves two purposes: firstly, it prevents short circuits; secondly, it protects each chip from the stress of the substrate 10.

[0074] In this embodiment of the disclosure, the front side (circuit layer) of a portion of the chips faces the same direction as the front side of the substrate, while the front side (circuit layer) of another portion of the chips faces the same direction as the back side of the substrate. That is, some chips are disposed with their front side facing upwards, and others with their front side facing downwards. For example, in... Figure 1 and Figure 3 In the example, the first chip 201 is positioned with its front facing upwards, and the second chip 202 is positioned with its front facing downwards; for example, in... Figure 4 and Figure 5 In this configuration, the first chip 201 and the second chip 202 are arranged with their front faces upwards, while the third chip 203 and the fourth chip 204 are arranged with their front faces downwards. This arrangement ensures that the circuit layers on different chips are spaced far apart, thereby reducing signal crosstalk between the chips.

[0075] In this embodiment of the disclosure, each chip is electrically connected to a substrate via a redistribution layer to form a signal interconnect, and the redistribution layer extends outward from the chip. For example, in Figure 1 and Figure 3 In the first chip 201, the redistribution layer 301 is electrically connected to the substrate via 11 through a redistribution layer 301, which extends outward from the first chip 201; for example, in Figure 4 and Figure 5In this configuration, the fourth chip 204 is electrically connected to the substrate via 11 via a redistribution layer 302, which extends outward from the fourth chip 204. This increases the spacing between the substrate vias 11, thereby reducing signal crosstalk. Simultaneously, because the substrate vias 11 are relatively far from the chip, the heat generated by the substrate vias 11 has a smaller impact on the chip.

[0076] Combination Figure 3 and Figure 6 The redistribution layer 301 is located on the surface of the insulating layer 502. That is, the redistribution layer 301 extends on the insulating layer 502, with its two ends connecting to the corresponding chip and the substrate via 11, respectively, thereby enabling signal transmission. Simultaneously, the redistribution layer 301 has a large surface area, therefore it generates a significant amount of heat. Due to the poor thermal conductivity of the insulating layer 502 and the high thermal conductivity (greater than that of the insulating layer 502) of the molding compound 503, and because the redistribution layer 301 is in direct contact with the molding compound 503, the heat generated by the redistribution layer 301 dissipates outwards from the molding compound 503, thus reducing the impact of heat on the chip.

[0077] like Figure 6 As shown, in some embodiments, the insulating layer 502 is made of, for example, polyimide, and the encapsulation material 503 is made of, for example, a molding material. Polyimide is formed by combining a resin material with a small amount of filler, while the molding material is formed by combining a resin material with a large amount of filler. Resin materials have good flowability but poor thermal conductivity. Therefore, the encapsulation material 503 has more filler (silicon oxide) than the insulating layer 502, resulting in greater thermal conductivity for the encapsulation material 503. Simultaneously, since the gap between the first chip 201 and the sidewall of the first groove 101 is small, only a few micrometers to tens of micrometers, a smaller filler volume can be added to the resin material to better fix the first chip 201. That is, the filler volume in the insulating layer 502 is smaller than the filler volume in the encapsulation material 503, thereby increasing the flowability of the insulating layer 502 and providing better gap-filling ability.

[0078] In some embodiments, reference Figure 3 The first chip 201 and the second chip 202 can be the same type of chip, such as both being dynamic random access memory (DRAM) or static random access memory (SRAM). In other embodiments, the first chip 201 and the second chip 202 can also be different types of chips; for example, the first chip 201 is a memory chip, and the second chip 202 is a control chip. When the first chip 201 and the second chip 202 are different types of chips, the substrate via 11 can provide the same power signal to both.

[0079] In some embodiments of this disclosure, reference is made to Figure 6 or Figure 7 In a semiconductor packaging structure, there are multiple substrates 10. These substrates 10 are stacked vertically in a Z-direction. Adjacent substrates 10 are filled with a molding compound 503. Chips located within different substrates 10 and adjacent to each other are bonded together and electrically connected.

[0080] It should be noted that, Figure 6 and Figure 7 In the example shown, there are two bases 10. More bases 10 can be stacked on top of this; that is, the number of bases 10 is not limited to two. Their structure and connection relationships can be found in [reference needed]. Figure 6 and Figure 7 Examples.

[0081] In this embodiment of the disclosure, reference is made to Figure 6 Chips 202 and 203 are located in two different substrates and are electrically connected by bonding, with the bonding location situated at the via 11 in the substrate. Simultaneously, chips 201 and 202 are electrically connected through corresponding vias 11, and chips 203 and 204 are also electrically connected through corresponding vias 11. In this way, communication interconnection can be achieved between chips 201, 202, 203, and 204.

[0082] In this embodiment of the disclosure, reference is made to Figure 7 Chips 202 and 203 are located on two different substrates and are electrically connected by bonding, with the bonding location situated at the conductive bump 401. Simultaneously, chips 201 and 202 are electrically connected through corresponding substrate vias 11, and chips 203 and 204 are also electrically connected through corresponding substrate vias 11. Thus, communication interconnection can be achieved between chips 201, 202, 203, and 204. Since chips 202 and 203 are relatively close to the conductive bump 401, therefore, [the following is used]... Figure 7 The illustrated structure can shorten interconnection paths, reduce loop resistance, and improve operating efficiency.

[0083] Understandably, multiple substrates 10 are stacked, and the chips in different substrates 10 are electrically connected to each other through bonding; at the same time, within each substrate 10, different chips are electrically connected through corresponding substrate vias 11. In this way, three-dimensional packaging of multiple chips is achieved, resulting in high performance with a small package size.

[0084] Meanwhile, the bonding position can be located at the position of the substrate via 11, and the substrate via 11 is located on the outside of the chip (any one of chips 201 to 204). That is, an FO type package is adopted, thus the setting range of bonding solder joints is larger, and more solder joints can be set, which is more advantageous for chip design.

[0085] In some embodiments of this disclosure, reference is made to Figure 6 or Figure 7 Both the adhesive film 501 and the molding compound 503 include resin and filler. The filler may be silicon dioxide or aluminum oxide.

[0086] It should be noted that in the adhesive film 501 and the molding compound 503, the resin is the base material, and the filler is added to the base material in a certain proportion.

[0087] In some embodiments of this disclosure, reference is made to Figure 6 or Figure 7 The filler content of the molding compound 503 is greater than that of the adhesive film 501. The higher filler content of the molding compound 503 results in a lower resin content. Since resin has poor heat dissipation capabilities, the molding compound 503 exhibits superior heat dissipation. This allows for better heat dissipation in the semiconductor packaging structure.

[0088] In some embodiments of this disclosure, reference is made to Figure 6 or Figure 7 The filler volume of the molding compound 503 is smaller than that of the adhesive film 501. A smaller filler volume results in better material flowability; therefore, the molding compound 503 exhibits superior flowability. This allows the molding compound 503 to fill more effectively, preventing gaps caused by incomplete filling.

[0089] In some embodiments of this disclosure, reference is made to Figure 6 or Figure 7 The coefficient of thermal expansion (CTE) of the molding compound 503 is greater than that of the substrate 10. Since there is a large contact area between the molding compound 503 and the substrate 10, and the molding compound 503 has a larger CTE, the substrate 10 can suppress the warping of the molding compound 503.

[0090] Figure 8 This is an optional process diagram illustrating a method for forming a semiconductor package structure according to an embodiment of this disclosure. For example... Figure 8 As shown, the method for forming a semiconductor package structure includes steps S101 to S105, which will be explained in conjunction with each step.

[0091] It should be noted that, Figures 11 to 17The structure of a semiconductor package during its formation process is shown, illustrating and clearly demonstrating the steps of the semiconductor package formation method.

[0092] S101, Provides the substrate.

[0093] In this embodiment of the disclosure, reference is made to Figure 11 The substrate 10 can be made of semiconductor materials, such as silicon. The semiconductor material used in the substrate 10 can be the same as the semiconductor material used in the subsequently implanted chip. This can eliminate the stress caused by the difference in CTE between the various structures, thereby avoiding warpage.

[0094] S102, Etch the substrate to form a groove; the groove penetrates the substrate vertically.

[0095] In this embodiment of the disclosure, reference is made to Figure 12 A groove 101 can be etched first on the front side of the substrate 10; then, combined with Figure 15 After thinning the back side of the substrate 10, the groove 101 can penetrate the substrate 10 in the vertical direction Z.

[0096] S103. Stack multiple chips vertically in the groove.

[0097] In this embodiment of the disclosure, combined with Figure 12 and Figure 13 After etching the groove 101, multiple chips (i.e., the first chip 201 and the second chip 202) can be stacked in the groove 101 along the vertical direction Z.

[0098] S104. Form a substrate through hole in the substrate; the substrate through hole penetrates the substrate vertically and is located outside the groove.

[0099] In this embodiment of the disclosure, combined with Figure 13 and Figure 14 A via 11 can be formed in the substrate 10. The via 11 is located outside the groove 101, meaning it is located outside multiple chips (i.e., the first chip 201 and the second chip 202). Figure 15 After the back side of the substrate 10 is thinned, the substrate through hole 11 can penetrate the substrate 10 in the vertical direction Z.

[0100] In this embodiment of the disclosure, combined with Figure 13 and Figure 14 First, openings can be formed at the pads of the first chip 201 and at the corresponding positions of the substrate via 11. Then, the substrate via 11 can be formed. The substrate via 11 can be filled with conductive materials such as copper, tungsten, or polysilicon to interconnect the various chips.

[0101] S105. Connect multiple chips electrically to corresponding substrate vias; the multiple chips communicate and interconnect through the substrate vias.

[0102] In this embodiment of the disclosure, reference is made to Figure 15 Multiple chips (i.e., the first chip 201 and the second chip 202) are electrically connected to corresponding substrate vias 11 and interconnected through the substrate vias 11. In this way, inter-chip communication interconnection is achieved without forming vias through the chip; thus, on the one hand, it is not necessary to reserve area in the chip for vias and the KOZ area near the vias, which can reduce the chip size and improve DPW; on the other hand, it can simplify the process and save costs.

[0103] In some embodiments of this disclosure, it is possible to... Figure 9 The shown S201 to S203 are implemented to achieve this. Figure 8 S105, shown below, will be explained in conjunction with each step.

[0104] S201. A first wiring layer is formed on the front side of the substrate to electrically connect a portion of the chips to corresponding substrate vias; wherein the front side of a portion of the chips faces the same direction as the front side of the substrate.

[0105] In this embodiment of the disclosure, reference is made to Figure 14 On the front side of the substrate 10, one end of the substrate via 11 is exposed. A first redistribution layer 301 can be formed on the front side of the substrate 10 to electrically connect the first chip 201 to the corresponding end of the substrate via 11. The first redistribution layer 301 is electrically connected to the pads of the first chip 201; the front side of the first chip 201 faces the same direction as the front side of the substrate 10.

[0106] S202. Thin the back side of the substrate to expose another part of the chip; wherein the front side of the other part of the chip faces the same direction as the back side of the substrate.

[0107] In this embodiment of the disclosure, combined with Figure 14 and Figure 15 The back side of the substrate 10 can be thinned to expose the second chip 202 and the other end of the substrate via 11. The front side of the second chip 202 faces the same direction as the back side of the substrate 10.

[0108] S203. A second wiring layer is formed on the back side of the substrate to electrically connect another part of the chip to the corresponding substrate via.

[0109] In this embodiment of the disclosure, reference is made to Figure 15A second wiring layer 302 can be formed on the back side of the substrate 10 to electrically connect the second chip 202 to the other end of the corresponding substrate via 11. The second wiring layer 302 is electrically connected to the pads of the second chip 202.

[0110] Understandably, by using a redistribution layer, each chip is electrically connected to a corresponding via in the substrate to achieve communication interconnection between the chips. This eliminates the need to form vias throughout the chip to achieve inter-chip communication interconnection. Therefore, on the one hand, it eliminates the need to reserve area in the chip for vias and the KOZ area near them, allowing for a reduction in chip size and improved DPW (Distribution Power W). On the other hand, it eliminates the need for the related processes of forming vias in the chip, thus simplifying the process and saving costs.

[0111] In some embodiments of this disclosure, it can be implemented via S301 to S303. Figure 8 S103, shown below, will be explained in conjunction with each step.

[0112] S301. The first chip is implanted into the groove, and an adhesive film is used to bond the first chip to the bottom surface of the groove.

[0113] In this embodiment of the disclosure, combined with Figure 12 and Figure 13 First, the second chip 202 (i.e., the first chip) located below can be implanted into the groove 101, and then the adhesive film 501 can be used to bond the second chip 202 to the bottom surface of the groove 101. The adhesive film 501 includes resin and filler; wherein, the filler can be silicon oxide (SiO) or aluminum oxide (AlO).

[0114] S302. The remaining chips are then sequentially implanted into the grooves to bond adjacent chips together with the adhesive film.

[0115] In this embodiment of the disclosure, the following continues to be combined Figure 12 and Figure 13 After the second chip 202 (i.e. the first chip) is implanted, the first chip 201 (i.e. the remaining chips) located above can be implanted into the groove 101 so that the adhesive film 501 can bond the first chip 201 and the second chip 202.

[0116] Understandably, the adhesive film 501 has a heat insulation function, which ensures that the heat generated by multiple chips will not affect each other, thereby ensuring the stable operation of multiple chips.

[0117] S303. An insulating layer is filled between the inner wall of the groove and the sidewalls of the multiple chips.

[0118] In this embodiment of the disclosure, the following continues to be combined Figure 12 and Figure 13After bonding multiple chips (i.e., the first chip 201 and the second chip 202), an insulating layer 502 can be filled between the inner wall of the groove 101 and the sidewalls of the multiple chips. The material of the insulating layer 502 can be PI.

[0119] Understandably, filling the sidewalls of multiple chips with insulating layer 502 serves two purposes: firstly, it prevents short circuits; secondly, it protects the multiple chips from the stress of the substrate 10.

[0120] In some embodiments of this disclosure, in Figure 8 Following S105 shown, the forming method further includes Figure 10 S106 to S108 shown will be explained in conjunction with each step.

[0121] S106. Perform a dicing process on the substrate.

[0122] S107. The substrate and the base plate are thermally bonded; wherein the thermal bonding position is determined according to the position of the through hole in the substrate.

[0123] S108. A molding compound is formed to surround the substrate through injection molding process.

[0124] In this embodiment of the disclosure, reference is made to Figure 16 After the various structures on the substrate 10 are formed, the substrate 10 can be diced to cut it out. Then, the substrate 10 is thermally compressed and bonded to the substrate 60 (TCB), with the TCB position determined according to the location of the through-holes 11 in the substrate. Finally, a molding compound 503 surrounding the substrate 10 can be formed using an injection molding process.

[0125] In this embodiment of the disclosure, reference continues to be made to Figure 16 Both the adhesive film 501 and the molding compound 503 include resin and filler. The resin is the base material, and the filler is added to the base material in a certain proportion. The filler can be silicon dioxide or aluminum oxide.

[0126] In some embodiments of this disclosure, the filler content of the molding compound 503 is greater than that of the adhesive film 501. A higher filler content in the molding compound 503 results in a lower resin content. Since resin has poor heat dissipation capabilities, the molding compound 503 exhibits superior heat dissipation. This allows for better heat dissipation in the semiconductor packaging structure.

[0127] In some embodiments of this disclosure, the filler volume of the molding compound 503 is smaller than the filler volume of the adhesive film 501. A smaller filler volume results in better material flowability; therefore, the molding compound 503 exhibits superior flowability. This allows the molding compound 503 to fill more effectively, preventing gaps caused by incomplete filling.

[0128] In some embodiments of this disclosure, the number of substrates is multiple, which can be achieved through steps S401 to S402. Figure 10 S107, shown below, will be explained in conjunction with each step.

[0129] S401, The first substrate is thermally bonded to the substrate.

[0130] S402. Stack the remaining chips sequentially on the first substrate and thermally bond the adjacent substrates together.

[0131] In this embodiment of the disclosure, reference is made to Figure 17 The first substrate 10 (i.e., the bottommost substrate 10) can be thermo-bonded to the substrate 60. Then, a second substrate 10 can be stacked on top of the first substrate 10 and thermo-bonded to the first substrate 10, wherein the bonding location can be located at the substrate via 11. In this way, more substrates 10 can be stacked.

[0132] Understandably, multiple substrates 10 are stacked, and the chips in different substrates 10 are electrically connected to each other through bonding; at the same time, within each substrate 10, different chips are electrically connected through corresponding substrate vias 11. In this way, three-dimensional packaging of multiple chips is achieved, resulting in high performance with a small package size.

[0133] Meanwhile, the bonding position can be located at the position of the substrate via 11, and the substrate via 11 is located on the outside of the chip (any one of chips 201 to 204). That is, an FO type package is adopted, thus the setting range of bonding solder joints is larger, and more solder joints can be set, which is more advantageous for chip design.

[0134] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0135] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0136] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor package structure, comprising: The semiconductor package structure comprises: a substrate, the substrate comprising a recess and a substrate via hole; the recess and the substrate via hole both penetrating the substrate along a vertical direction; the substrate via hole is located outside the recess; a plurality of chips stacked in the recess along the vertical direction and electrically connected to the corresponding substrate via hole; the plurality of chips are communicatively interconnected through the substrate via hole; the inner wall of the recess and the sidewall of the plurality of chips are filled with an insulating layer; the semiconductor package structure further comprises two redistribution layers; the two redistribution layers are respectively located on the front surface and the back surface of the substrate; each chip is electrically connected to the corresponding substrate via hole through the corresponding redistribution layer; a plastic encapsulation material surrounds the substrate, and the plastic encapsulation material directly contacts the redistribution layer; the thermal conductivity of the plastic encapsulation material is greater than the thermal conductivity of the insulating layer.

2. The semiconductor package structure of claim 1, wherein, The plurality of chips comprises a first chip and a second chip; the front surface of the first chip is consistent with the front surface of the substrate in orientation, and is electrically connected to the redistribution layer located on the front surface of the substrate through a conductive bump; the front surface of the second chip is consistent with the back surface of the substrate in orientation, and is electrically connected to the redistribution layer located on the back surface of the substrate through a conductive bump.

3. The semiconductor package structure of claim 1, wherein, The plurality of chips comprises a first chip, a second chip, a third chip and a fourth chip stacked in sequence; the first chip and the second chip are stacked in a first direction; the third chip and the fourth chip are stacked in the first direction; the first direction is perpendicular to the vertical direction; the front surface of the first chip and the front surface of the second chip are consistent with the front surface of the substrate in orientation; the front surface of the third chip and the front surface of the fourth chip are consistent with the back surface of the substrate in orientation.

4. The semiconductor package structure according to claim 3, wherein the front surface of the first chip is electrically connected to the redistribution layer located on the front surface of the substrate through a conductive bump; the front surface of the second chip is electrically connected to the redistribution layer located on the front surface of the substrate through a conductive pillar; the front surface of the third chip is electrically connected to the redistribution layer located on the back surface of the substrate through a conductive pillar; the front surface of the fourth chip is electrically connected to the redistribution layer located on the back surface of the substrate through a conductive bump.

5. The semiconductor package structure of any one of claims 1 to 4, wherein, The adjacent chips are adhered to each other through an adhesive film.

6. The semiconductor package structure of claim 5, wherein, The number of the substrate is a plurality; the plurality of substrates are stacked along the vertical direction; the adjacent substrates are filled with the plastic encapsulation material; the chips located in different substrates and adjacent to each other are bonded to each other for electrical connection.

7. The semiconductor package structure according to claim 6, wherein the adhesive film and the plastic encapsulation material both comprise resin and filler; the filler is silicon oxide or aluminum oxide; the filler content of the plastic encapsulation material is greater than the filler content of the adhesive film; the filler volume of the plastic encapsulation material is less than the filler volume of the adhesive film.

8. The semiconductor package structure of claim 7, wherein, The coefficient of thermal expansion of the plastic encapsulation material is greater than the coefficient of thermal expansion of the substrate.

9. A method of forming a semiconductor package structure, comprising: The method comprises: providing a substrate; etching the substrate to form a groove; the groove penetrates the substrate along a vertical direction; stacking a plurality of chips in the groove along the vertical direction; forming a substrate via in the substrate; the substrate via penetrates the substrate along the vertical direction and is located outside the groove; electrically connecting a plurality of the chips to corresponding substrate vias; the plurality of chips are communicatively interconnected through the substrate vias; electrically connecting a plurality of the chips to corresponding substrate vias, comprising: forming a first redistribution layer on a front surface of the substrate to electrically connect a portion of the chips to corresponding substrate vias; wherein a front surface of a portion of the chips is aligned with the front surface of the substrate; thinning a back surface of the substrate to expose another portion of the chips; wherein a front surface of another portion of the chips is aligned with the back surface of the substrate; forming a second redistribution layer on the back surface of the substrate to electrically connect another portion of the chips to corresponding substrate vias; after electrically connecting a plurality of the chips to corresponding substrate vias, the forming method further comprises: performing a dicing process on the substrate; thermally bonding the substrate to a substrate; wherein the position of thermal bonding is in accordance with the position of the substrate via; forming a plastic encapsulation material surrounding the substrate through an injection molding process; the plastic encapsulation material is in direct contact with the first redistribution layer and the second redistribution layer; stacking a plurality of the chips in the groove along the vertical direction, comprising: implanting a first one of the chips into the groove to adhere the first one of the chips to a bottom surface of the groove using an adhesive film; sequentially implanting the remaining ones of the chips into the groove to adhere adjacent ones of the chips using the adhesive film; filling an insulating layer between an inner wall of the groove and a sidewall of the plurality of chips; the thermal conductivity of the plastic encapsulation material is greater than the thermal conductivity of the insulating layer.

10. The method of forming of claim 9, wherein, the number of the substrates is a plurality; thermally bonding the substrate to the substrate, comprising: thermally bonding a first one of the substrates to the substrate; sequentially stacking the remaining ones of the substrates on top of the first one of the substrates and thermally bonding adjacent ones of the substrates.

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