A timing calibration loop, control method and digital-to-analog converter

Abstract

The present invention discloses a timing calibration loop, a control method and a digital-to-analog converter. The timing calibration loop includes: a clock generation module for generating a frequency division signal and at least two clock signals of different phases; at least two input modules synchronize each initial data signal according to the frequency division signal to generate a first data signal; at least two sampling modules output at least two second data signals of different phases; an adjustment module generates a first test signal according to the frequency division signal; and generates at least two second test signals of different phases according to the first test signal and the clock signal; and controls the timing shift of the frequency division signal according to the second test signal to generate a frequency division signal after timing shift; the frequency division signal after timing shift is used to synchronize the first data signal, and outputs the synchronized second data signal through the sampling module; the output module synthesizes the synchronized second data signal into an output signal. The technical solution provided by the embodiment of the present invention has a good timing adjustment effect.

Description

Technical Field

[0001] The present invention relates to the technical field of timing detection, and in particular to a timing calibration loop, a control method and a digital-to-analog converter. Background Art

[0002] Digital to Analog Converters (DAC) are components that convert discrete digital signals into continuous analog signals. They are widely used in communications, satellites, radars, electronic countermeasures, aerospace, instrumentation, etc. As modern society's requirements for information capacity increase, digital to analog converters also have higher requirements for data transmission rates.

[0003] As the data signal rate continues to increase, the intervals between adjacent clocks are getting smaller and smaller. When synthesizing data signals, the transition edges of data signals may deflect and jitter, which can easily cause sampling metastable states and data order confusion. The prior art generally expands the timing constraint range by adding a large number of triggers or latches. This will increase circuit delays and deteriorate the quality of clock transmission. Therefore, the prior art has a poor effect on timing adjustment. Summary of the invention

[0004] The invention provides a timing calibration loop, a control method and a digital-to-analog converter to solve the problem of poor timing adjustment effect.

[0005] According to one aspect of the present invention, there is provided a timing calibration loop, comprising:

[0006] A clock generation module, used for generating a frequency-divided signal and at least two clock signals with different phases;

[0007] at least two input modules connected to the clock generation module, the input modules being used to receive initial data signals and synchronize the initial data signals according to the frequency division signal to generate a first data signal;

[0008] At least two sampling modules, connected to the input module and the clock generation module, and configured to output at least two second data signals with different phases according to the first data signal and the clock signal;

[0009] an adjusting module, connected to the clock generating module, and configured to generate a first test signal according to the frequency-divided signal; and generate at least two second test signals with different phases according to the first test signal and the clock signal; and control the timing shift of the frequency-divided signal according to the second test signal to generate a frequency-divided signal after the timing shift; wherein the phase of the first test signal is determined by the phase of the frequency-divided signal, and the phase of the second test signal is determined by the phase of the clock signal;

[0010] The frequency-divided signal after the timing shift is used to synchronize the first data signal, and outputs at least two synchronized second data signals of different phases through the sampling module;

[0011] An output module is connected to the sampling module and the clock generating module, and is used to synthesize at least two synchronized second data signals into an output signal.

[0012] Optionally, the adjustment module includes:

[0013] an input unit, connected to the clock generation module, and used for transmitting the first test signal; the phase of the first test signal is the same as the phase of the first data signal;

[0014] at least two first sampling units, connected to the input unit and the clock generation module, and configured to output at least two second test signals of different phases according to the first test signal and the clock signal; the phases of at least two second test signals respectively correspond one-to-one to the phases of at least two second data signals;

[0015] at least one second sampling unit, connected to the first sampling unit, and configured to generate a determination signal according to the second test signal;

[0016] A control unit is connected to the second sampling unit and is used to generate a control signal according to the judgment signal to control the clock generation module to perform timing adjustment on the frequency-divided signal.

[0017] Optionally, the control unit comprises:

[0018] a logic gate, connected to the second sampling unit, and configured to receive the determination signal;

[0019] A finite state machine is connected between the logic gate and the clock generation module, and is used to generate the control signal according to the judgment signal.

[0020] Optionally, the clock generation module includes:

[0021] A frequency division unit, used to generate the frequency division signal;

[0022] a phase interpolation unit connected to the frequency division unit and the control unit, and configured to adjust the timing of the frequency division signal according to the control signal;

[0023] A phase delay unit, connected to the sampling module, and configured to generate at least two clock signals with different phases;

[0024] A pulse trigger unit is connected to the output module and is used to provide a clock pulse signal to the output module.

[0025] Optionally, the input module, the output module and the input unit include: a multiplexer;

[0026] The output module combines at least two of the second data signals into one output signal according to the clock pulse signal.

[0027] Optionally, the number of the input modules is four; the number of the sampling modules is four; and the clock signal includes: a 0° clock signal, a 90° clock signal, a 180° clock signal and a 270° clock signal.

[0028] According to another aspect of the present invention, a control method for a timing calibration loop is provided, which is applied to the timing calibration loop described in any embodiment of the present invention, and the method comprises:

[0029] converting the first test signal into at least two second test signals having different phases;

[0030] A control signal is generated according to the second test signal to control the timing shift of the frequency-divided signal.

[0031] Optionally, generating a control signal according to the second test signal to control the timing shift of the frequency division signal includes:

[0032] Generate a first judgment signal according to the second test signal of 0° clock and the second test signal of 180° clock, and generate a second judgment signal according to the second test signal of 90° clock and the second test signal of 270° clock;

[0033] The control signal is updated according to the first judgment signal and the second judgment signal to control the timing shift of the frequency division signal.

[0034] Optionally, the step of generating the control signal according to the second test signal to control the timing shift of the frequency division signal comprises:

[0035] The timing of the frequency-divided signal is locked, and at least two of the second data signals are combined into one output signal and output.

[0036] According to another aspect of the present invention, there is provided a digital-to-analog converter, comprising: the timing calibration loop described in any embodiment of the present invention.

[0037] The technical solution provided by the embodiment of the present invention can generate multiple second test signals with different phases by sampling the first test signal through the setting of the adjustment module, and the relative timing position of the first data signal and the clock signal can be determined by detecting the relative timing position relationship of the second test signals. When the timing position is wrong, the first data signal with the correct timing is obtained by controlling the timing movement of the frequency division signal. The embodiment of the present invention does not need to change the original timing constraints. The timing calibration of the first data signal can be achieved through real-time sampling of the first test signal and real-time detection of the second test signal, and feedback adjustment. Therefore, the timing adjustment of the present invention does not need to change the original timing constraints, will not lead to an increase in circuit delay, and enables the circuit to have a higher clock transmission quality and a better adjustment effect.

[0038] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 is a schematic diagram of the structure of a timing calibration loop provided according to an embodiment of the present invention;

[0041] Figure 2 is a schematic diagram of the structure of another timing calibration loop provided according to an embodiment of the present invention;

[0042] Figure 3 is a waveform diagram of a timing detection provided according to an embodiment of the present invention;

[0043] Figure 4 is another waveform diagram of timing detection provided according to an embodiment of the present invention;

[0044] Figure 5 is a schematic diagram of the structure of another timing calibration loop provided according to an embodiment of the present invention;

[0045] Figure 6 is a flow chart of a control method of a timing calibration loop provided according to an embodiment of the present invention;

[0046] Figure 7 is a flow chart of another method for controlling a timing calibration loop provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0048] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0049] An embodiment of the present invention provides a timing calibration loop. Figure 1 A schematic diagram of the structure of a timing calibration loop provided by an embodiment of the present invention. Figure 1The timing calibration loop includes: at least two input modules 1, a clock generation module 4, at least two sampling modules 2, an adjustment module 5 and an output module 3. The clock generation module 4 is used to generate a frequency division signal and at least two clock signals of different phases. The input module 1 is connected to the clock generation module 4, and the input module 1 is used to receive the initial data signal, and synchronize each initial data signal according to the frequency division signal to generate a first data signal. The sampling module 2 is connected to the input module 1 and the clock generation module 4, and is used to output at least two second data signals of different phases according to the first data signal and the clock signal. The adjustment module 5 is connected to the clock generation module 4, and is used to generate a first test signal according to the frequency division signal; and generate at least two second test signals of different phases according to the first test signal and the clock signal; and control the timing shift of the frequency division signal according to the second test signal to generate the frequency division signal after the timing shift. Among them, the phase of the first test signal is determined by the phase of the frequency division signal, and the phase of the second test signal is determined by the phase of the clock signal. The frequency division signal after the timing shift is used to synchronize the first data signal, and output at least two synchronized second data signals of different phases through the sampling module 2. The output module 3 is connected to the sampling module 2 and the clock generating module 4, and is used for combining at least two synchronized second data signals into one output signal.

[0050] Among them, the clock generation module 4 inputs a frequency division signal to the input module 1, and the frequency division signal can be a 2-frequency division signal, which can align the transition edges of the initial data signals transmitted by each input module 1 and generate a first data signal, which is equivalent to the same phase of each first data signal. The first data signal passes through the sampling module 2 and is sampled by clock signals of different phases to generate a second data signal of different phases. Among them, the clock signals of different phases are provided by the clock generation module 4. After the second data signal is input to the output module 3, the clock generation module 4 can provide a clock pulse signal to the output module 3, and the second data signal can be resampled and synthesized into an output signal through the clock pulse signal. The rate of the output signal is related to the number of the second data signals. For example, when the output module 3 inputs 4 second data signals, the output signal is an output signal of 4 times the rate. Through this setting method, the output of a high-speed output signal is achieved.

[0051] Because the transition edge of the first data signal may be skewed and jittered, when the clock signal samples the first data signal, the selected signal may not be the first data signal in the target timing, but the first data signal in the previous timing or the next timing. If the first data signal is sampled by the sampling module 2 and the second test signal is output, when the output signal is synthesized, it is easy to cause sampling metastable state and data order confusion. Therefore, it is necessary to judge the timing position of the first test signal and the relative timing position of the clock signal. When the relative timing position of the first test signal and the clock signal is wrong, the timing of the first data signal can be adjusted by adjusting the timing shift of the frequency division signal. Since the timing of the clock signal remains unchanged, the relative timing relationship between the first data signal and the clock signal is adjusted.

[0052] Specifically, the adjustment module 5 receives the frequency division signal sent by the clock generation module 4, and can generate a first test signal with the same phase as the first data signal according to the frequency division signal. Exemplarily, the first test signal can be a slow signal, so as to ensure the accuracy of the first test signal acquisition. While inputting the clock signal to the sampling module 2, the clock generation module 4 also inputs the same clock signal into the adjustment module 5. The adjustment module 5 samples the first test signal according to the clock signal to generate a second test signal with a different phase. Because the second test signal and the second data signal are both sampled and generated by the same clock signal, the phase of the second test signal can be used to reflect the phase of the second data signal. The adjustment module 5 can use the phase data of the second test signal to determine whether there is an abnormality in the relative timing relationship between the first data signal and the clock signal. Exemplarily, when there is an abnormality in the relative timing relationship between the first data signal and the clock signal, a control signal can be generated according to the second data signal and the timing shift of the frequency division signal can be controlled. The first data signal with the correct timing is obtained through the frequency division signal after the timing shift, and the synchronized second data signal is output through the sampling module 2. The output module 3 synthesizes at least two synchronized second data signals into an output signal and outputs it.

[0053] The technical solution provided by the embodiment of the present invention can generate a plurality of second test signals with different phases by sampling the first test signal through setting the adjustment module 5, so as to determine the relative timing position relationship between the first data signal and the clock signal. When the relative timing position relationship is wrong, the timing movement of the frequency division signal is controlled by the control signal, so as to obtain the correct relative timing position relationship between the first data signal and the clock signal. The embodiment of the present invention does not need to change the original timing constraints, and can achieve the timing calibration of the first data signal through real-time sampling of the first test signal and real-time detection of the second test signal, and feedback adjustment. Therefore, the timing adjustment of the present invention does not need to change the original timing constraints, will not lead to an increase in circuit delay, and enables the circuit to have a higher clock transmission quality and a better adjustment effect.

[0054] Figure 2 A schematic diagram of another timing calibration loop structure provided by an embodiment of the present invention. Figure 2 On the basis of the above embodiments, optionally, the adjustment module includes: an input unit 51, at least two first sampling units 52, at least one second sampling unit 53 and a control unit 54. The input unit 51 is connected to the clock generation module 4, and is used to transmit a first test signal; the phase of the first test signal is the same as the phase of the first data signal. The first sampling unit 52 is connected to the input unit 51 and the clock generation module 4, and is used to output at least two second test signals with different phases according to the first test signal and the clock signal; the phases of the at least two second test signals correspond to the phases of the at least two second data signals one by one. The second sampling unit 53 is connected to the first sampling unit 52, and is used to generate a judgment signal according to the second test signal. The control unit 54 is connected to the second sampling unit 53, and is used to generate a control signal according to the judgment signal, and control the clock generation module 4 to adjust the timing of the frequency division signal.

[0055] in, Figure 2The structure of the timing calibration loop of 4 input modules 1, 4 sampling modules 2, 4 first sampling units 52 and 2 second sampling units 53 is exemplarily shown. The clock generation module 4 can output a 0° clock signal, a 90° clock signal, a 180° clock signal and a 270° clock signal. The clock generation module 4 inputs the frequency division signal to the input module 1 and the input unit 51, and the first data signal A, the first data signal B, the first data signal C, the first data signal D and the first test signal Q of the same phase can be obtained. The sampling module 2, the first sampling unit 52 and the second sampling unit 53 can be a D flip-flop, and the D flip-flop obtains the second data signal a aligned to the 0° clock edge according to the first data signal A and the 0° clock signal sampling, obtains the second data signal b aligned to the 90° clock edge according to the first data signal B and the 90° clock signal sampling, obtains the second data signal c aligned to the 180° clock edge according to the first data signal C and the 180° clock signal sampling, and obtains the second data signal d aligned to the 270° clock edge according to the first data signal D and the 270° clock signal sampling. A second test signal q1 aligned to a 0° clock edge, a second test signal q2 aligned to a 90° clock edge, a second test signal q3 aligned to a 180° clock edge, and a second test signal q4 aligned to a 270° clock edge can also be obtained based on the first test signal Q and different clock signals.

[0056] Therefore, the second test signal q1 has the same phase as the second data signal a, and the second test signal q1 can be used to reflect the phase of the second data signal a; the second test signal q2 has the same phase as the second data signal b, and the second test signal q2 can be used to reflect the phase of the second data signal b; the second test signal q3 has the same phase as the second data signal c, and the second test signal q3 can be used to reflect the phase of the second data signal c; the second test signal q4 has the same phase as the second data signal d, and the second test signal q4 can be used to reflect the phase of the second data signal d. By detecting and judging each second test signal, the timing detection of each second data signal can be achieved.

[0057] Figure 3 A waveform diagram of a timing detection provided by an embodiment of the present invention, Figure 4 Another waveform diagram of timing detection provided by an embodiment of the present invention. Figure 2-Figure 4 Optionally, the clock generation module 4 outputs a 0° clock signal and a 180° clock signal as an example for explanation, refer to Figure 3, the transition edge of the first test signal Q is not between the 0° clock signal and the 180° clock signal, the first sampling unit 52 samples the first test signal Q at the first rising edge of the 0° clock signal CK_0 and generates the second test signal q1, and the second test signal q1 is inverted to a high level; the first sampling unit 52 samples the first test signal Q at the first rising edge of the 180° clock signal CK_180 and generates the second test signal q3, and the second test signal q3 is inverted to a high level. Because the second test signal q1 is first inverted to a high level, and the second test signal q3 is then inverted to a high level, therefore, the determination signal LOCK1 generated by sampling the second test signal q1 with the second test signal q3 is a high level.

[0058] refer to Figure 4 , the transition edge of the first test signal Q is between the 0° clock signal and the 180° clock signal. The first rising edge of the 0° clock signal CK_0 cannot be sampled because the first test signal Q is at a low level. The first sampling unit 52 samples the first test signal Q at the second rising edge of the 0° clock signal CK_0 and generates the second test signal q1, which is inverted to a high level. The first sampling unit 52 samples the first test signal Q at the first rising edge of the 180° clock signal CK_180 and generates the second test signal q3, which is inverted to a high level. Because the second test signal q3 is first inverted to a high level, and the second test signal q1 is then inverted to a high level, the determination signal LOCK1 generated by sampling the second test signal q1 with the second test signal q3 is at a low level.

[0059] The embodiment of the present invention can also reflect the relative timing relationship between the transition edge of the first test signal Q and the 90° clock signal CK_90 and the 270° clock signal CK_270 through the judgment signal LOCK0. Combined with the output of the judgment signal LOCK0 and the judgment signal LOCK1, the relative timing position of the transition edge of the first data signal Q relative to the clock signal can be obtained: when LOCK1 is 0 and LOCK0 is 1, the transition edge of the first data signal is between the adjacent rising edges of CK_0~CK_90; when LOCK1 is 0 and LOCK0 is 0, the transition edge of the first data signal is between the adjacent rising edges of CK_90~CK_180; when LOCK1 is 1 and LOCK0 is 0, the transition edge of the first data signal is between the adjacent rising edges of CK_180~CK_270; when LOCK1 is 1 and LOCK0 is 1, the transition edge of the first data signal is between the adjacent rising edges of CK_270~CK_0. The control unit 54 can generate a control signal according to the judgment signal, and control the clock generation module 4 to adjust the timing of the frequency-divided signal, so as to recalibrate the timing of the first data signal A, the first data signal B, the first data signal C, the first data signal D and the first test signal Q, and finally ensure that the transition edge of the first data signal is located between the adjacent rising edges of CK_270~CK_0. This ensures that when the clock samples the first data signal, the selected signal is the first data signal within the target timing.

[0060] Continue to refer Figure 2 On the basis of the above embodiments, optionally, the control unit 54 includes: a finite state machine 541, which is connected between the second sampling unit 53 and the clock generation module 4 and is used to generate a control signal according to the judgment signal.

[0061] Among them, the finite-state machine 541 (FSM) can generate a control signal according to the judgment signal to control the timing of the frequency division signal to move forward, backward or not move.

[0062] Specifically, the judgment signal LOCK0 can be used to reflect whether the transition edge of the first test signal Q is located between the adjacent sampling edges of the 90° clock signal CK_90 and the 270° clock signal CK_270, and the judgment signal LOCK1 can be used to reflect whether the transition edge of the first test signal Q is located between the adjacent sampling edges of the 0° clock signal CK_0 and the 180° clock signal CK_180. In the finite state machine 541, the control signal is updated according to the judgment signal LOCK0 and the judgment signal LOCK1. Since the control signal controls the timing of the frequency division signal, the update of the control signal can make the timing of the frequency division signal move forward, the timing of the frequency division signal move backward, or the timing of the frequency division signal remain unchanged. Among them, the timing remains unchanged when the timing is locked.

[0063] Exemplarily, when the judgment signal LOCK0 is at a high level and the judgment signal LOCK1 is at a low level, the control signal will control the timing of the frequency-divided signal to move forward; when the judgment signal LOCK0 is at a low level and the judgment signal LOCK01 is at a low level, the control signal will control the timing of the frequency-divided signal to move backward; when the judgment signal LOCK0 is at a low level and the judgment signal LOCK1 is at a high level, the control signal will control the timing of the frequency-divided signal to move backward; when the judgment signal LOCK0 is at a high level and the judgment signal LOCK1 is at a high level, the control signal remains unchanged and the timing of the frequency-divided signal is locked.

[0064] Figure 5 A schematic diagram of the structure of another timing calibration loop provided by an embodiment of the present invention. Figure 5 On the basis of the above embodiments, optionally, the clock generation module includes: a frequency division unit 41, a phase interpolation unit 42, a phase delay unit 43 and a pulse trigger unit 44. The frequency division unit 41 is used to generate a frequency division signal; the phase interpolation unit 42 is connected to the frequency division unit 41 and the control unit 54, and is used to adjust the timing of the frequency division signal according to the control signal; the phase delay unit 43 is connected to the sampling module 2, and is used to generate at least two clock signals with different phases; the pulse trigger unit 44 is connected to the output module 3, and is used to provide a clock pulse signal to the output module 3.

[0065] The frequency division unit 41 is used to convert the input signal of the clock generation module into a frequency division signal, and the frequency division unit 41 can be a two-frequency division unit. The frequency division signal is input into the input module 1 and the input unit 51 through the phase interpolation unit 42. The control signal can control the phase interpolation unit 42 to perform the timing shift of the frequency division signal, and the phase interpolation unit 42 can be an adder.

[0066] Exemplarily, the control signal PI for adjusting the timing of the frequency division signal is a four-bit signal, and the phase interpolation unit 42 updates the control signal at the next moment by combining the control signal at the previous moment with the four-bit signal generated according to the judgment signal LOCK0 and the judgment signal LOCK1. Specifically refer to the following formula:

[0067] PI （n） =PI （n-1） +ADD;

[0068] Among them, PI （n-1） is the control signal output by the phase interpolation unit 42 at the previous moment, ADD is a four-bit signal generated according to the judgment signal LOCK0 and the judgment signal LOCK1, PI （n） It is the timing adjustment signal of the frequency division signal at the current moment.

[0069] Exemplarily, when the frequency division signal needs to be controlled to be shifted forward in timing, ADD is 0001; when the frequency division signal needs to be controlled to be shifted backward in timing, ADD is 1111; when the frequency division signal needs to be controlled to be locked in timing, ADD is 0000.

[0070] After completing the timing adjustment of the frequency division signal, the relative timing position relationship between the first data signal and the clock signal is correct, the correct second data signal is sampled and output and input into the output module 3, and the output module 3 synthesizes an output signal according to the clock pulse signal provided by the pulse trigger unit 44.

[0071] Continue to refer Figure 5 On the basis of the above embodiments, optionally, the input module 1, the output module 3 and the input unit 51 include: a multiplexer; the output module 3 combines at least two second data signals into one output signal according to the clock pulse signal.

[0072] Among them, the multiplexer is a circuit device that can select one or more signals from multiple input signals for output. Exemplarily, the input module 1 and the input unit 51 can be a two-way multiplexer, and the output module 3 can be a four-way multiplexer. When the output module 3 includes four input signals of the second data signal a, the second data signal b, the second data signal c and the second data signal d, the pulse trigger unit 44 provides four non-overlapping clock pulse signals to the output module 3, and the second data signal a, the second data signal b, the second data signal c and the second data signal d are sampled by the four clock pulse signals, and can be synthesized into a 4-times-rate output signal.

[0073] The embodiment of the present invention further provides a control method for a timing calibration loop, which is applied to the timing calibration loop provided by any embodiment of the present invention and has the same beneficial effects as the timing calibration loop provided by any of the above embodiments. Figure 6 A flow chart of a control method for a timing calibration loop provided by an embodiment of the present invention. Figure 6 , the method comprising:

[0074] S110 , converting the first test signal into at least two second test signals with different phases.

[0075] The first test signal has the same phase as the first data signal, and each second test signal corresponds to a second data signal with the same phase. Therefore, by detecting the timing of the second test signal, it can be determined whether there is an abnormality in the relative timing relationship between the first data signal and the clock signal.

[0076] S120 , generating a control signal according to the second test signal to control the timing shift of the frequency-divided signal.

[0077] Among them, when there is an abnormality in the relative timing relationship between the transition edge of the first test signal and the sampling edge of the multi-phase clock signal, it will be reflected in the timing of the second test signal. The control signal can control the timing movement of the divided signal to adjust the transition edge of the first data signal to the correct timing, thereby ensuring the correct sampling of the second data signal.

[0078] The technical solution provided by the embodiment of the present invention can determine the relative timing position relationship between the jump edge of the first data signal and the sampling edge of the multi-phase clock signal by detecting the phase of the second test signal. When the timing position is wrong, the first data signal with the correct timing is obtained by controlling the timing movement of the frequency division signal. The embodiment of the present invention does not need to change the original timing constraints. Through real-time sampling of the first test signal and real-time detection of the second test signal, and feedback adjustment, the timing calibration of the first data signal can be achieved. Therefore, the timing adjustment method provided by the present invention does not need to change the original timing constraints, will not lead to an increase in circuit delay, and enables the circuit to have a higher clock transmission quality and a better adjustment effect.

[0079] Based on the above embodiments, optionally, S120, generating a control signal according to the second test signal to control the timing shift of the frequency division signal includes:

[0080] A first judgment signal is generated according to the second test signal of the 0° clock and the second test signal of the 180° clock, and a second judgment signal is generated according to the second test signal of the 90° clock and the second test signal of the 270° clock. A control signal is updated according to the first judgment signal and the second judgment signal to control the timing shift of the frequency division signal.

[0081] Among them, the first test signal Q can obtain a second test signal with different phases through multi-phase clock signal sampling. When the transition edge of the first test signal Q is not between the adjacent sampling edges of the 0° clock signal CK_0 and the 180° clock signal CK_180, the first judgment signal generated by the second test signal of the 180° clock sampling the second test signal of the 0° clock is high level; when the transition edge of the first test signal Q is between the adjacent sampling edges of the 0° clock signal CK_0 and the 180° clock signal CK_180, the first judgment signal generated by the second test signal of the 180° clock sampling the second test signal of the 0° clock will be low level. Combined with the first judgment signal and the second judgment signal, it can be judged whether there is an abnormality in the relative timing position relationship between the transition edge of the first data signal and the sampling edge of the multi-phase clock signal. And the timing movement of the frequency division signal is controlled by updating the control signal through the judgment signal, so as to calibrate the timing of the transition edge of the first data signal, and then output the correct second data signal through the multi-phase clock signal sampling, so that when the output signal is synthesized, there will be no problem of data sequence confusion.

[0082] Based on the above embodiments, optionally, after S120, generating a control signal according to the second test signal to control the timing shift of the frequency division signal, the method includes: locking the timing of the frequency division signal, and synthesizing at least two second data signals into an output signal and outputting the output signal.

[0083] Among them, when the relative timing position relationship between the jump edge of the first test signal and the sampling edge of the multi-phase clock signal is correct, the adjustment module can lock the timing of the frequency-divided signal. At this time, the timing of the first data signal is the correct timing. The sampling module can sample the first data signal and the clock signal to generate a second data signal, and the various second data signals are synthesized into an output signal through the adjustment module and output.

[0084] Figure 7 A flowchart of another control method for a timing calibration loop provided by an embodiment of the present invention. Figure 7 Based on the above embodiments, optionally, the method includes:

[0085] S210, sampling a low-speed jump signal through a frequency-divided signal to obtain a first test signal.

[0086] S220 , sampling the first test signal through four clock signals with different phases to obtain a second test signal with four different phases.

[0087] S230. Generate a control signal according to the second test signal.

[0088] S240: Determine whether it is necessary to adjust the timing of the frequency division signal. If necessary, execute S260; if not, execute S250.

[0089] S250, the timing of the frequency division signal is locked.

[0090] S260, controlling the timing adjustment of the frequency division signal.

[0091] The technical solution provided by the embodiment of the present invention requires that after the timing adjustment of a frequency-divided signal is completed, the timing of the second test signal needs to be continuously detected until the timing of the frequency-divided signal is locked. At this time, the relative timing position relationship between the transition edge of the first data signal and the sampling edge of the multi-phase clock signal is correct, thereby forming a detection and calibration loop with high reliability.

[0092] An embodiment of the present invention further provides a digital-to-analog converter, including the timing calibration loop provided by any embodiment of the present invention, which has the same beneficial effects as the timing calibration loop provided by any of the above embodiments, and will not be described in detail here.

[0093] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0094] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A timing calibration loop, characterized in that: include: A clock generation module, used for generating a frequency-divided signal and at least two clock signals with different phases; at least two input modules connected to the clock generation module, the input modules being used to receive initial data signals and synchronize the initial data signals according to the frequency division signal to generate a first data signal; At least two sampling modules, connected to the input module and the clock generation module, and configured to output at least two second data signals with different phases according to the first data signal and the clock signal; an adjusting module, connected to the clock generating module, and configured to generate a first test signal according to the frequency-divided signal; and generate at least two second test signals with different phases according to the first test signal and the clock signal; and control the timing shift of the frequency-divided signal according to the second test signal to generate a frequency-divided signal after the timing shift; wherein the phase of the first test signal is determined by the phase of the frequency-divided signal, and the phase of the second test signal is determined by the phase of the clock signal; The frequency-divided signal after the timing shift is used to synchronize the first data signal, and outputs at least two synchronized second data signals of different phases through the sampling module; An output module is connected to the sampling module and the clock generating module, and is used to synthesize at least two synchronized second data signals into an output signal.

2. The timing calibration loop according to claim 1, characterized in that: The adjustment module comprises: an input unit, connected to the clock generation module, and used for transmitting the first test signal; the phase of the first test signal is the same as the phase of the first data signal; at least two first sampling units, connected to the input unit and the clock generation module, and configured to output at least two second test signals of different phases according to the first test signal and the clock signal; the phases of at least two second test signals respectively correspond one-to-one to the phases of at least two second data signals; at least one second sampling unit, connected to the first sampling unit, and configured to generate a determination signal according to the second test signal; A control unit is connected to the second sampling unit and is used to generate a control signal according to the judgment signal to control the clock generation module to perform timing adjustment on the frequency-divided signal.

3. The timing calibration loop according to claim 2, characterized in that: The control unit comprises: A finite state machine is connected between the second sampling unit and the clock generating module, and is used to generate the control signal according to the determination signal.

4. The timing calibration loop according to claim 2, wherein: The clock generation module comprises: A frequency division unit, used to generate the frequency division signal; a phase interpolation unit, connected to the frequency division unit and the control unit, and configured to adjust the timing of the frequency division signal according to the control signal; A phase delay unit, connected to the sampling module, and configured to generate at least two clock signals of different phases; A pulse trigger unit is connected to the output module and is used to provide a clock pulse signal to the output module.

5. The timing calibration loop according to claim 4, characterized in that: The input module, the output module and the input unit include: a multiplexer; The output module combines at least two of the second data signals into one output signal according to the clock pulse signal.

6. The timing calibration loop according to claim 1, wherein: The number of the input modules is four; the number of the sampling modules is four; the clock signals include: a 0° clock signal, a 90° clock signal, a 180° clock signal and a 270° clock signal.

7. A control method for a timing calibration loop, characterized in that: Applied to the timing calibration loop according to any one of claims 1 to 6, the method comprising: converting the first test signal into at least two second test signals having different phases; A control signal is generated according to the second test signal to control the timing shift of the frequency-divided signal.

8. The control method of the timing calibration loop according to claim 7, characterized in that: The step of generating a control signal according to the second test signal to control the timing shift of the frequency division signal comprises: Generate a first judgment signal according to the second test signal of 0° clock and the second test signal of 180° clock, and generate a second judgment signal according to the second test signal of 90° clock and the second test signal of 270° clock; The control signal is updated according to the first judgment signal and the second judgment signal to control the timing shift of the frequency division signal.

9. The control method of the timing calibration loop according to claim 7, characterized in that: The step of generating the control signal according to the second test signal to control the timing shift of the frequency division signal comprises: The timing of the frequency-divided signal is locked, and at least two of the second data signals are combined into one output signal and output.

10. A digital-to-analog converter, characterized in that: include: The timing calibration loop as claimed in any one of claims 1 to 6.

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