Data transmission method and device based on FPGA and network equipment

Abstract

The application provides a data transmission method and device based on FPGA and network equipment. The application obtains SerDes data corresponding to each second FPGA through a first IO transmission module in a first FPGA deployed in the network equipment, and performs first IO processing on the SerDes data to obtain a plurality of groups of target user data. For the SerDes data corresponding to each second FPGA, the target user data is transmitted to the second FPGA through N IO pins determined according to the transmission rate of the single IO pin, and is processed and restored to the SerDes data corresponding to the second FPGA by a second IO transmission module of the second FPGA. The SerDes data is sent through SerDes in the second FPGA. The total SerDes rate that cannot be realized by a single FPGA is realized by splicing a plurality of FPGAs, and high-rate data transmission is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a data transmission method and device based on FPGA and network equipment. BACKGROUND

[0002] High-bandwidth data transmission through a field-programmable gate array (FPGA) is usually implemented through a serializer-deserializer (SerDes). However, the total rate of the SerDes of the FPGA cannot exceed the limit of 500 Gbps, and a higher rate of data transmission cannot be achieved through the FPGA. SUMMARY

[0003] Therefore, the present application provides a data transmission method and device based on FPGA and network equipment to achieve high-rate data transmission through the FPGA.

[0004] The technical scheme provided by the present application is as follows:

[0005] According to the embodiment of the first aspect of the present application, a data transmission method based on FPGA is provided, which is applied to network equipment; the network equipment is deployed with a first FPGA and at least one second FPGA; the first FPGA is connected to each second FPGA through an IO pin; the first FPGA is deployed with a first IO transmission module; each second FPGA is deployed with a second IO transmission module; the method comprises:

[0006] For each obtained SerDes data corresponding to a second FPGA, the first IO transmission module deployed in the first FPGA is used to perform first IO processing on the SerDes data corresponding to the second FPGA to obtain a plurality of groups of target user data; the first IO processing refers to: performing packing processing on the SerDes data corresponding to the second FPGA and adding the check information corresponding to the SerDes data to obtain reference user data, performing scrambling on the reference user data, and grouping the scrambled reference user data to obtain a plurality of groups of target user data;

[0007] The transmission rate of a single IO pin is determined, and based on the IO data transmission mode, it is determined that the SerDes data corresponding to the second FPGA needs to occupy N IO pins;

[0008] Each target user data is sent to a second FPGA corresponding to the SerDes data of the first FPGA through N IO pins according to a transmission rate of the single IO pin, so that the second IO transmission module in the second FPGA performs second IO processing on the received target user data to obtain the SerDes data corresponding to the second FPGA and sends the SerDes data through the SerDes in the second FPGA; the second IO processing is the inverse process of the first IO processing.

[0009] Optionally, the first FPGA further deploys an Ethernet processing module; the Ethernet processing module is used for converting user side data into SerDes data allowed to be transmitted through a serial transceiver SerDes; the method further includes:

[0010] The Ethernet processing module in the first FPGA converts the received user side data into target SerDes data, and sends the SerDes data corresponding to the first FPGA in the target SerDes data through the SerDes in the first FPGA; the target SerDes data includes the SerDes data corresponding to the first FPGA and the SerDes data corresponding to each second FPGA;

[0011] The Ethernet processing module in the first FPGA forwards the SerDes data corresponding to each second FPGA in the target SerDes data to the first IO transmission module.

[0012] Optionally, the maximum data amount allowed to be transmitted by the SerDes in the first FPGA at a time is M, the data size of the target SerDes data is greater than the M, and the data size of the SerDes data corresponding to the first FPGA is the M.

[0013] Optionally, the SerDes data corresponding to the second FPGA is packaged and the check information corresponding to the SerDes data is added to obtain reference user data, including:

[0014] The SerDes data corresponding to the second FPGA is packaged according to the obtained data bit width and clock frequency to obtain parallel signal data;

[0015] Each group of data is encoded to obtain the check code corresponding to the group of data according to a preset size;

[0016] Each group of data and the check code corresponding to each group of data are spliced to obtain the reference user data.

[0017] Optionally, the reference user data after scrambling is grouped to obtain multiple groups of target user data, including:

[0018] determining a number of groups of target user data according to a number of IO pins included in the first FPGA;

[0019] grouping the scrambled reference user data according to the number of groups of target user data;

[0020] for each group of data, inserting an alignment marker of a second specified length every first specified length of data to obtain target user data;

[0021] The alignment marker is used to align each group of target user data when transmitting the target user data, and the alignment markers inserted in different groups of target user data are different, and the alignment markers inserted in the same group of target user data are the same.

[0022] Optionally, the determination of the transmission rate of a single IO pin and the determination of the N IO pins occupied by the SerDes data corresponding to the second FPGA based on the IO data transmission mode include:

[0023] determining a transmission rate of each group of target user data according to a target total rate and the number of groups of target user data; the target total rate is determined according to a sum of data sizes of the SerDes data corresponding to each second FPGA;

[0024] determining a transmission rate of a single IO pin according to the transmission rate of each group of target user data and an IO number corresponding to each group of target user data; the IO number corresponding to each group of target user data is determined according to the number of groups of target user data, a maximum transmission rate of an IO pin of the first FPGA, and the target total rate;

[0025] determining the N IO pins occupied by the SerDes data corresponding to the second FPGA according to the IO number corresponding to each group of target user data and the IO data transmission mode.

[0026] Optionally, the second IO processing refers to:

[0027] merging the received multiple groups of target user data to obtain scrambled reference user data, and descrambling the scrambled reference user data to obtain reference user data;

[0028] checking the check information included in the reference user data, and restoring the reference user data to the SerDes data corresponding to the second FPGA in a case where the check is successful.

[0029] Optionally, the merging of the received multiple groups of target user data to obtain scrambled reference user data includes:

[0030]

[0030] setting a designated mark for a start bit position of the alignment mark of each group of target user data, and deleting the alignment mark of each group of target user data;

[0031] buffering the target user data from which the alignment mark is deleted;

[0032] In a case where the target user data are all buffered, merging the groups of target user data according to the position of the designated mark to obtain reference user data after scrambling.

[0033] According to an embodiment of the second aspect of the present application, a data transmission device based on FPGA is provided, which is applied to a network device; the network device is deployed with a first FPGA and at least one second FPGA; each second FPGA is connected to the first FPGA through an IO pin; the first FPGA is deployed with a first IO transmission module; each second FPGA is deployed with a second IO transmission module; the device comprises:

[0034] a processing unit configured to, for each second FPGA corresponding SerDes data obtained, perform first IO processing on the second FPGA corresponding SerDes data through the first IO transmission module deployed in the first FPGA to obtain a plurality of groups of target user data; the first IO processing refers to: performing packing processing on the second FPGA corresponding SerDes data and adding the check information corresponding to the SerDes data to obtain reference user data, scrambling the reference user data, and grouping the reference user data after scrambling to obtain a plurality of groups of target user data;

[0035] a determination unit configured to determine the transmission rate of a single IO pin and determine the N IO pins required by the second FPGA corresponding SerDes data based on the IO data transmission mode;

[0036] a transmission unit configured to, through the N IO pins, send each target user data to the second FPGA corresponding to the SerDes data according to the transmission rate of the single IO pin, so that the second IO transmission module in the second FPGA performs second IO processing on the received each target user data to obtain the second FPGA corresponding SerDes data and transmits the SerDes data through the SerDes in the second FPGA; the second IO processing is the inverse process of the first IO processing.

[0037] According to the embodiment of the third aspect of the present application, a network device is provided, wherein the network device is deployed with a first FPGA and at least one second FPGA; the first FPGA is connected with each second FPGA through IO pins; the first FPGA is deployed with a first IO transmission module; each second FPGA is deployed with a second IO transmission module, and the network device is configured to perform the method of the first aspect.

[0038] As can be seen from the above technical solutions, the first IO transmission module in the first FPGA deployed in the network device performs first IO processing on the obtained SerDes data corresponding to each second FPGA to obtain a plurality of groups of target user data. For the SerDes data corresponding to each second FPGA, the transmission rate of a single IO pin and the number N of pins to be occupied are determined. Further, the target user data is transmitted to the second FPGA through the determined N IO pins according to the transmission rate of the single IO pin, and the target user data is processed and restored to the SerDes data corresponding to the second FPGA by the second IO transmission module of the second FPGA, and the SerDes data is sent by the SerDes in the second FPGA. The total SerDes rate that cannot be realized by a single FPGA is realized by splicing a plurality of FPGAs, and high-rate data transmission is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0039] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0040] Figure 1 A schematic diagram of connection between a first FPGA and a plurality of second FPGAs in a network device according to an embodiment of the present application is shown.

[0041] Figure 2 A flowchart of a data transmission method based on FPGA according to an embodiment of the present application is shown.

[0042] Figure 3 A schematic diagram of a 800Gbps Ethernet scheme realized by two FPGAs according to an embodiment of the present application is shown.

[0043] Figure 4 A schematic diagram of a first IO transmission module and a second IO transmission module according to an embodiment of the present application is shown.

[0044] Figure 5 A schematic diagram of an IO transmission module structure according to an embodiment of the present application is shown.

[0045] Figure 6 A schematic diagram of an IO transmission module structure in a transmission layer according to an embodiment of the present application is shown.

[0046] Figure 7 A structure diagram of an IO transmission module in a link layer is provided in the embodiments of the present application.

[0047] Figure 8 A method for inserting an alignment mark is provided in the embodiments of the present application.

[0048] Figure 9 A structure diagram of an IO transmission module in a link layer is provided in the embodiments of the present application.

[0049] Figure 10 A structure diagram of a network device is provided in the embodiments of the present application.

[0050] Figure 11 A structure diagram of a data transmission device based on FPGA is provided in the embodiments of the present application. DETAILED DESCRIPTION

[0051] In order to make the technical solution provided by the embodiments of the present application better understood by those skilled in the art, and make the above-mentioned purposes, features and advantages of the embodiments of the present application more apparent and easy to understand, the technical solutions in the embodiments of the present application are further described in detail below with reference to the drawings.

[0052] Please refer to Figure 1 , Figure 1 A structure diagram of a network device in which a first FPGA (Field-Programmable Gate Array) and a plurality of second FPGAs are connected through IO (Input / Output) pins is provided in the embodiments of the present application.

[0053] As shown in Figure 1 , the network device is deployed with a first FPGA and a plurality of second FPGAs, wherein the first FPGA is connected with each second FPGA through IO pins, the first FPGA is deployed with a first IO transmission module, and each second FPGA is deployed with a second IO transmission module.

[0054] Based on the connection mode of the first FPGA and the plurality of second FPGAs in the above network device, the embodiments of the present application propose a data transmission method based on FPGA, so as to realize high-speed data transmission through FPGA.

[0055] Please refer to Figure 2 , Figure 2 A flow chart of a data transmission method based on FPGA is provided in the embodiments of the present application.

[0056] In the embodiments, the method is applied to the network device shown in Figure 1 .

[0057] As an embodiment, the network device described above can include a data center switch, a router, a network interface card, a network acceleration card, and the like, which need FPGA to support high-rate data transmission, and the present application does not limit this.

[0058] As shown in Figure 2 the specific steps of the method can include:

[0059] Step 201, for the obtained serial transceiver SerDes data corresponding to each second FPGA, the first IO processing module deployed in the first FPGA is used to perform first IO processing on the SerDes data corresponding to the second FPGA to obtain a plurality of groups of target user data.

[0060] In this embodiment, in the case that the SerDes rate supported by the single FPGA cannot reach the target total rate that needs to be reached, the first FPGA can forward the SerDes data that needs to be transmitted to a plurality of second FPGAs, and the first FPGA obtains SerDes data corresponding to each second FPGA. The SerDes data corresponding to each second FPGA actually refers to the SerDes data sent by the second FPGA.

[0061] As an embodiment, the SerDes data corresponding to each second FPGA can be determined according to the target total rate that needs to be reached and the SerDes rate supported by each second FPGA.

[0062] Before executing the FPGA-based data transmission method proposed in the present application, the type and number of second FPGAs that need to be deployed can be determined in advance according to the SerDes rate supported by each second FPGA and the target total rate that needs to be reached.

[0063] For example, assuming that the target total rate that needs to be reached is 800Gbps, and the maximum SerDes total rate supported by the first type of FPGA is 448Gbps, and the maximum SerDes total rate supported by the second type of FPGA is 224Gbps, it indicates that if the first type of FPGA is selected, two pieces of the first type of FPGA need to be deployed as the second FPGA to send SerDes data to reach the target total rate of 800Gbps, and if the second type of FPGA is selected, four pieces of the FPGA need to be deployed as the second FPGA to send SerDes data to reach the target total rate of 800Gbps.

[0064] In the embodiment, the target total rate is 800 Gbps, i.e., 800 G bits of SerDes data are transmitted per second, and the 800 G bits of SerDes data to be transmitted per second are allocated to multiple second FPGAs for transmission, and each second FPGA corresponds to a part of the SerDes data.

[0065] As a preferred embodiment, the second FPGA corresponding to the SerDes data can be configured for the second FPGA according to the maximum capacity threshold of the second FPGA for transmitting the SerDes data, so as to fully utilize the resources of each second FPGA.

[0066] In the embodiment, the first FPGA also deploys an Ethernet processing module; the Ethernet processing module is configured to convert user-side data into SerDes data allowed to be transmitted through a serial transceiver SerDes, and the first IO transmission module is deployed between the Ethernet processing module and the IO pin of the first FPGA.

[0067] In the embodiment, the Ethernet processing module can specifically include a media access control (MAC) module and a physical coding sublayer (PCS) module, wherein the MAC module can be configured to encapsulate user-side data (such as an IP data packet) into an Ethernet frame, add necessary header information (such as a source address, a destination address, and a frame type) and control information (such as flow control and error detection code), etc.; and the PCS module can be configured to perform coding processing on the Ethernet frame to ensure the effectiveness of the signal and improve the transmission rate.

[0068] As an embodiment, the Ethernet processing module can further include a forward error correction module (FEC) configured to add redundant information to the data to detect and correct errors in transmission.

[0069] In the embodiment, the processing process of the Ethernet processing module on the user-side data is a common method in the related art, which will not be described herein.

[0070] When data transmission is implemented by using an FPGA, the FPGA processes the received user-side data by using an Ethernet processing module to obtain SerDes data that can be transmitted through a physical medium, and transmits the SerDes data by using a SerDes in the FPGA. In the embodiment, due to the limitation of the total rate of the SerDes of a single FPGA, the processing of the SerDes data cannot be completed by using a single FPGA, and multiple FPGAs are required to process the SerDes data.

[0071] In the embodiment, after the first FPGA converts the user-side data into SerDes data through the Ethernet processing module, the first FPGA can serve as a forwarding device of the SerDes data, that is, the first FPGA forwards the received SerDes data to other second FPGAs, and transmits the SerDes data through the serial transceiver SerDes in each second FPGA.

[0072] As an embodiment, the first FPGA itself can also have a SerDes data transmission function, that is, the first FPGA itself has a serial transceiver SerDes. In this case, the method can further include:

[0073] Converting the received user-side data into target SerDes data through the Ethernet processing module in the first FPGA, and transmitting the SerDes data corresponding to the first FPGA in the target SerDes data through the SerDes in the first FPGA; the target SerDes data includes the SerDes data corresponding to the first FPGA and the SerDes data corresponding to each second FPGA;

[0074] Forwarding the SerDes data corresponding to each second FPGA in the target SerDes data to the first IO transmission module through the Ethernet processing module in the first FPGA.

[0075] In the embodiment, after the received user-side data is converted into target SerDes data through the Ethernet processing module in the first FPGA, the target SerDes data is divided into two parts, that is, the SerDes data corresponding to the first FPGA and the SerDes data corresponding to each second FPGA.

[0076] In the embodiment, the SerDes data corresponding to the first FPGA in the target SerDes data can be transmitted through the SerDes in the first FPGA, and the SerDes data corresponding to each second FPGA in the target SerDes data can be forwarded to the first IO transmission module through the Ethernet processing module, so as to realize high-speed transmission of data through the first FPGA and at least one second FPGA.

[0077] As an embodiment, the maximum data amount allowed to be transmitted by the SerDes in the first FPGA at one time is M, the data size of the target SerDes data is greater than M, the data size of the SerDes data corresponding to the first FPGA is M, and the SerDes data corresponding to each second FPGA is the target SerDes data other than the SerDes data corresponding to the first FPGA.

[0078] It is easy to understand that in the case that the data size of the target SerDes data is greater than the maximum data amount M of the SerDes single-time allowed transmission in the first FPGA, the processing and transmission of the SerDes data cannot be completed by the first FPGA alone, and in this case, the SerDes data with a transmission data amount of M (i.e., the SerDes data corresponding to the first FPGA) can be transmitted by the first FPGA, and the target SerDes data other than the SerDes data corresponding to the first FPGA can be transmitted by each second FPGA as the SerDes data corresponding to each second FPGA.

[0079] As an embodiment, the maximum data amount of the SerDes single-time allowed transmission in the first FPGA is M, and the data size of the SerDes data corresponding to the first FPGA is not greater than M, and the SerDes data other than the SerDes data corresponding to the first FPGA can be transmitted by each second FPGA as the SerDes data corresponding to each second FPGA.

[0080] In this embodiment, the size of the SerDes data corresponding to the first FPGA and the SerDes data corresponding to each second FPGA that need to be transmitted can also be configured for the first FPGA and the second FPGA in advance, and it is only required to satisfy that the data size of the SerDes data corresponding to the first FPGA is not greater than the maximum data amount M of the SerDes single-time allowed transmission in the first FPGA.

[0081] In this embodiment, for the SerDes data corresponding to each second FPGA, the first FPGA can perform first IO processing on the SerDes data corresponding to the second FPGA through the deployed first IO transmission module to obtain a plurality of groups of target user data.

[0082] In this embodiment, the first IO processing refers to performing packaging processing on the SerDes data corresponding to the second FPGA and adding the check information corresponding to the SerDes data to obtain reference user data, performing scrambling on the reference user data, and grouping the scrambled reference user data to obtain a plurality of groups of target user data.

[0083] In this embodiment, the first IO module and the second IO module both support three layers, i.e., a Transport transmission layer, a Link link layer, and a PHY IO physical interface layer.

[0084] In the transmission layer, the first IO module can perform packaging processing on each SerDes data corresponding to the second FPGA and add the check information corresponding to the SerDes data to obtain reference user data.

[0085] As an embodiment, the specific method of packing the SerDes data corresponding to each second FPGA and adding the check information corresponding to the SerDes data to obtain the reference user data can include:

[0086] For the SerDes data corresponding to each second FPGA, the SerDes data corresponding to the second FPGA is packed according to the obtained data bit width and clock frequency to obtain parallel signal data;

[0087] The parallel signal data is grouped according to a preset size, and each group of data is encoded to obtain the check code corresponding to the group of data.

[0088] Each group of data is spliced with the check code corresponding to each group of data to obtain the reference user data.

[0089] In this embodiment, in the transport layer, the SerDes data corresponding to each second FPGA can be packed according to the obtained data bit width and clock frequency to obtain parallel signal data, and the parallel signal data can be grouped according to a preset size.

[0090] As an embodiment, for the SerDes data corresponding to each second FPGA, a data bit width of 1024 bits and a clock frequency of 402.83203125 MHz can be used in the transport layer, and the SerDes data corresponding to the second FPGA is packed together to form a parallel signal data, that is, 1024 bits of data are processed each time, and 402.83203125M times of processing are performed per second.

[0091] For the 1024 bits of data processed each time, the data can be grouped according to a preset size, such as 64 bits per group, for a total of 16 groups. The specific grouping method can be that the 0th bit of data in the 1024 bits of data is included in the 1st group, the 1st bit of data is included in the 2nd group, …, the 15th bit of data is included in the 16th group, and the 16th bit of data is included in the 1st group, and so on.

[0092] After grouping, each group of data can be encoded according to a specified encoding method to obtain the check code corresponding to each group of data.

[0093] As an embodiment, the encoding method can be an error correction code (ECC), a cyclic redundancy check code (CRC), or a convolution code, and the present application does not limit this.

[0094] Further, the parallel signal data can be reorganized, and each group of data can be spliced with the corresponding check code of each group of data, such as reorganizing the original parallel signal data into group 1 + corresponding check code of group 1 + group 2 + corresponding check code of group 2 + … + group 16 + corresponding check code of group 16, to obtain reference user data.

[0095] In the link layer, the first IO module can scramble the reference user data and group the scrambled reference user data to obtain a plurality of groups of target user data.

[0096] In this embodiment, long 0 and long 1 may occur in the reference user data, which may cause DC imbalance of the data transmitted on the final IO pin. To avoid the occurrence of long 0 or long 1 in the reference user data, the reference user data needs to be scrambled.

[0097] In this embodiment, the reference user data can be processed according to a preset method to avoid the occurrence of long 0 and long 1 in the reference user data.

[0098] As an example, a self-synchronous scrambler can be used to scramble the reference user data, such as processing the reference user data in the form of a polynomial to obtain scrambled reference user data.

[0099] As an example, the specific method of grouping the scrambled reference user data to obtain a plurality of groups of target user data can include:

[0100] determining the number of groups of target user data according to the number of IO pins included in the first FPGA;

[0101] grouping the scrambled reference user data according to the number of groups of target user data;

[0102] for each group of data, inserting a second specified length of alignment marker every first specified length of data to obtain target user data;

[0103] The alignment marker is used to align each group of target user data when transmitting the target user data. The alignment markers inserted in different groups of target user data are different, and the alignment markers inserted in the same group of target user data are the same.

[0104] In this embodiment, the number of groups of target user data can be determined according to the number of IO pins included in the first FPGA. Specifically, the number of groups of target user data ranges from 1 to the number of IO pins included in the first FPGA.

[0105] As an embodiment, the first FPGA comprises 500 IO pins, and the number of groups of the target user data ranges from 1 to 500. When determining the number of groups, an integer can be selected from 1 to 500 as the number of groups, for example, 64.

[0106] It should be noted that after the number of groups is selected, the selected number of groups needs to be further verified to determine whether the selected number of groups is appropriate. Taking the number of groups as 64 as an example, 64 groups of target user data are finally obtained. According to the obtained target total rate (for example, 400 Gbps), the average transmission rate of each group of target user data can be determined, that is, 400 / 64=6.25 Gbps. Further, according to the maximum transmission rate of a single IO pin of the first FPGA (for example, 2 Gbps), it can be determined that each group of target user data needs to be transmitted through at least how many IO pins, that is, 6.25 / 2=3.125, and after rounding up, it is 4.

[0107] For the FPGA device, the data of up to 64 IOs can be directly aligned. To ensure that the data in each group of target user data is aligned, each group of target user data can be transmitted through at most 64 IO pins.

[0108] Therefore, in the above example, the number of IO pins corresponding to each group of target user data should be selected from [4, 64]. If the number of IO pins finally determined according to the preselected number of groups is greater than 64, it indicates that the selection of the number of groups is inappropriate, and the selection of the number of groups needs to be adjusted.

[0109] In this embodiment, after the number of groups is selected, the scrambled reference user data can be grouped according to the number of groups of the target user data.

[0110] Further, for each group of data, a second specified length of alignment markers are inserted every first specified length of data to obtain the target user data.

[0111] In this embodiment, the alignment markers corresponding to each group of data are configured for the group of data. The alignment marker is a specified length of identification data, which is used to align the groups of target user data when the target user data is transmitted. The alignment markers inserted by different groups of target user data are different, and the alignment markers inserted by the same group of target user data are the same.

[0112] In this embodiment, for each group of scrambled reference user data, an alignment marker is inserted every first specified length of data.

[0113] It should be noted that the second specified length cannot be too short to avoid the case that the reference user data after scrambling is repeated easily, causing misidentification of the alignment mark.

[0114] Meanwhile, it should be noted that the length of the first specified length and the second specified length is set to avoid the percentage of the effective data bandwidth in the final target user data being too low. Specifically, the minimum value of the effective data bandwidth in the target user data can be solved in advance according to the IO pin number calculation formula, which is as follows:

[0115]

[0116] Wherein, S is the data amount of the SerDes data corresponding to each second FPGA, M is the number of IO pins required, K is the transmission rate of a single IO pin, and P is the percentage of the effective data bandwidth. Among them, S*1.03125 is the above-mentioned target total rate.

[0117] By substituting the maximum transmission rate of a single IO pin and the total number of IO pins of the FPGA into the above formula, the minimum value P of P can be solved. min It is easy to understand that when setting the first specified length and the second specified length, the percentage of the effective data bandwidth in the final target user data cannot be lower than P min .

[0118] The alignment mark selection and insertion will be described below through specific embodiments, which will not be described here.

[0119] So far, the description of step 201 is ended, and step 202 is executed.

[0120] Step 202, determine the transmission rate of a single IO pin and determine the N IO pins occupied by the SerDes data corresponding to the second FPGA based on the IO data transmission mode.

[0121] In the physical interface layer, for the SerDes data corresponding to each second FPGA, the first IO module can determine the transmission rate of a single IO pin and determine the N IO pins occupied by the SerDes data corresponding to the second FPGA based on the IO data transmission mode.

[0122] Specifically, according to the target total rate and the group number of the target user data, the transmission rate of each group of target user data is determined; the target total rate is determined according to the sum of the data sizes of the SerDes data corresponding to each second FPGA;

[0123] According to the transmission rate of each group of target user data and the number of IOs corresponding to each group of target user data, the transmission rate of a single IO pin is determined; the number of IOs included in each group of target user data is determined according to the number of groups of target user data, the maximum transmission rate of the IO pin of the first FPGA, and the target total rate;

[0124] According to the number of IOs corresponding to each group of target user data and the IO data transmission mode, the N IO pins occupied by the SerDes data corresponding to the second FPGA are determined.

[0125] In the embodiment, the process of determining the transmission rate of each group of target user data according to the target total rate and the number of groups of target user data has been described above, and will not be repeated here.

[0126] Further, the transmission rate of a single IO pin can be determined by dividing the transmission rate of each group of target user data by the number of IOs included in each group of target user data, wherein the determination method of the number of IOs included in each group of target user data has been described above, and will not be repeated here.

[0127] In addition, the N IO pins occupied by the SerDes data corresponding to each second FPGA can also be determined according to the number of IOs corresponding to each group of target user data and the IO data transmission mode, wherein the IO data transmission mode can be determined according to the percentage of effective data bandwidth.

[0128] As an example, if it is determined according to the percentage of effective data bandwidth that the IO transmission data adopts the DDR mode, each group of target user data contains a pair of differential clock CK and 16 pairs of differential data DQ during transmission, a total of 34 IO pins are required, and 16 groups of target user data require 34*16 IO pins.

[0129] Thus, the description of step 202 ends, and step 203 is executed.

[0130] In step 203, each target user data is sent to the second FPGA corresponding to the SerDes data through the N IO pins according to the transmission rate of a single IO pin, so that the second IO transmission module in the second FPGA performs second IO processing on the received target user data to obtain the SerDes data corresponding to the second FPGA and sends the SerDes data through the SerDes in the second FPGA.

[0131] In the embodiment, after the transmission rate of the single IO pin and the N IO pins required by the SerDes data corresponding to the second FPGA are determined by the first IO module for the SerDes data corresponding to each second FPGA, the target user data can be sent to the corresponding second FPGA according to the transmission rate of the single IO pin through the N IO pins, so that the second IO transmission module in the second FPGA performs the second IO processing on the received target user data to obtain the SerDes data corresponding to the second FPGA and transmits the SerDes data corresponding to the second FPGA through the SerDes in the second FPGA.

[0132] In the embodiment, the second IO processing is the inverse process of the first IO processing as a whole.

[0133] Specifically, the second IO processing can include:

[0134] For the SerDes data corresponding to each second FPGA, the received multiple groups of target user data are merged to obtain reference user data after scrambling, and the reference user data after scrambling is descrambled to obtain reference user data.

[0135] The reference user data is checked for the check information included in the reference user data, and the reference user data is restored to the SerDes data corresponding to the second FPGA in the case of successful check.

[0136] As an embodiment, the method of merging the received multiple groups of target user data to obtain reference user data after scrambling can include:

[0137] The start bit position of the alignment mark of each group of target user data is set as a specified mark, and the alignment mark of each group of target user data is deleted;

[0138] The target user data after deleting the alignment mark is cached;

[0139] In the case that the target user data is cached, the multiple groups of target user data are merged according to the position of the specified mark to obtain reference user data after scrambling.

[0140] The method of merging the received multiple groups of target user data to obtain reference user data after scrambling will be described in the specific embodiments below, and will not be described here.

[0141] Thus, the description of step 203 ends.

[0142] Thus, the description of the FPGA-based data transmission method in the embodiment ends. Figure 2

[0143] ​The application obtains SerDes data corresponding to each second FPGA through a first IO transmission module in a first FPGA deployed in a network device, performs first IO processing on the obtained SerDes data, obtains a plurality of groups of target user data, determines the transmission rate of a single IO pin and the number N of pins to be occupied for SerDes data corresponding to each second FPGA, further transmits the obtained target user data to the second FPGA through the determined N IO pins according to the transmission rate of the single IO pin, processes and restores the SerDes data corresponding to the second FPGA through a second IO transmission module of the second FPGA, and transmits the SerDes data through SerDes in the second FPGA, so that the total SerDes rate that cannot be realized by a single FPGA is realized through splicing of a plurality of FPGAs, and high-rate data transmission is achieved.

[0144] The scheme for realizing single-port 800Gbps Ethernet through two FPGAs provided by the application is introduced below through a specific embodiment.

[0145] Embodiment 1

[0146] Please refer to Figure 3 , Figure 3 The scheme for realizing 800Gbps Ethernet through two FPGAs provided by the embodiment of the application is shown in the following figure.

[0147] As shown in Figure 3 , taking the data transmission rate to be reached as 800Gbps as an example, that is, 800G bits of data need to be transmitted per second, in this embodiment, the 800G data to be transmitted per second is divided into two parts, 400G data is transmitted and received by SerDes of one FPGA (referred to as first FPGA), and the other 400G data is transmitted to another FPGA (referred to as second FPGA) through IO pins of the first FPGA and is forwarded by SerDes of the second FPGA, that is, the first FPGA itself can also perform SerDes transmission.

[0148] Before data transmission through IO pins, the type and number of FPGAs to be used can be determined in advance.

[0149] Specifically, according to the different SerDes rates supported by FPGAs, there are currently 56G and 112G SerDes, and 4 (112G) or 8 (56G) SerDes are needed for one FPGA to splice a complete 800G Ethernet interface, and the number of SerDes needed can determine the type and number of FPGAs to be spliced.

[0150] The first FPGA converts the user side data into SerDes data allowed to be transmitted through a serial transceiver SerDes through an 800G Ethernet processing module, sends 400G (SerDes data corresponding to the first FPGA) data in the first FPGA through the SerDes, and sends another 400G (SerDes data corresponding to the second FPGA) data to the first IO transmission module to be forwarded to the second FPGA through the IO pin after the SerDes data corresponding to the second FPGA is processed by the first IO transmission module, and then sent by the SerDes of the second FPGA.

[0151] The process of transmitting data through the IO pin is introduced below.

[0152] In this embodiment, the data conversion between the user side data and the physical IO pin is realized by the first IO transmission module in the FPGA, so as to ensure the correctness of data transmission.

[0153] Please refer to Figure 4 , Figure 4 The first IO transmission module and the second IO transmission module provided by the embodiment of the application are shown in the schematic diagram.

[0154] As shown in Figure 4 , the first FPGA and the second FPGA are both deployed with an IO transmission module, the IO transmission module deployed by the first FPGA is referred to as the first IO transmission module, and the IO transmission module deployed by the second FPGA is referred to as the second IO transmission module.

[0155] Further, please refer to Figure 5 , Figure 5 The structure of the IO transmission module provided by the embodiment of the application is shown in the schematic diagram.

[0156] As shown in Figure 5 , the IO transmission module supports the Transport transmission layer, the Link link layer and the PHY IO physical interface layer.

[0157] In the data sending direction, in the Transport transmission layer, the user side data can be combined and corresponding check information can be added, in the Link link layer, the received data can be scrambled and processed by channel, and in the PHY IO physical layer, the data can be distributed to the interfaces of each IO pin and sent out.

[0158] The specific implementation mechanism of the sending direction is described below.

[0159] 1) Transport transmission layer

[0160] Please refer to Figure 6 ,Figure 6 The structure diagram of the IO transmission module provided by the embodiment of the present application in the transmission layer.

[0161] As shown in the figure, in the case of receiving SerDes data, the SerDes data is all packaged together to form a parallel signal data. Figure 6

[0162] In the embodiment, the data bit width is 1024 bits, and the clock frequency is 402.83203125 MHz, so that each beat data is 1024 bits.

[0163] Each beat data (1024 bits) is grouped according to each 64-bit data as a group to obtain 16 groups, and the data in each group is respectively ECC encoded. 64-bit data in each group will generate an 8-bit ECC check code, so a total of 16 groups of 128-bit ECC check codes will be generated.

[0164] Among them, the method for grouping data is:

[0165] The first group: bit[0, 16, 32, 16*n,...]

[0166] The second group: bit[1, 17, 33, 16*n+1,...] ...

[0168] The mth group: bit[m-1, 16+m-1, 32+m-1, 16*n+m-1,...]

[0169] Among them, m is the number of groups, and in the embodiment, m is 16. The value range of the integer n is [0, 63].

[0170] After determining the grouping and the corresponding ECC check code of each group, the generated ECC check code and the beat data are reorganized, and each group of data and the corresponding ECC check data are organized together to merge into 1152-bit data (recorded as original data).

[0171] For example, the structure of the finally merged 1152-bit data is: the first group of 64-bit data, the first group of 8-bit check code, the second group of 64-bit data, the second group of 8-bit check code,..., the sixteenth group of 64-bit data, and the sixteenth group of 8-bit check code.

[0172] Based on this, the 1152-bit data obtained by grouping the data and the check code is obtained.

[0173] 2) Link layer

[0174] Please refer to​Figure 7 , Figure 7 The structure diagram of the IO transmission module in the link layer is provided for the embodiment of the present application.

[0175] As shown in Figure 7 , after receiving 1152bit original data, since the original data may include long 0, long 1 and the like, which will cause the DC imbalance of the data transmitted on the final IO pin, in order to avoid the long 0 or long 1 in the original data, the original data needs to be scrambled.

[0176] For example, a self-synchronous scrambler can be used for scrambling, and the scrambling generation polynomial can be:

[0177] G(x) = 1 + x 39 + x 58

[0178] After completing the scrambling of the original data, the scrambled data is obtained. Further, the scrambled data is grouped.

[0179] Since there are many IO pins, the data needs to be distributed to each IO pin. For the FPGA device, generally, the data of 64 IOs can be directly aligned, in the present example, the data is divided into 16 groups, each group being 72bit, and each group including 16 IOs, in combination with the actual data transmission bandwidth requirement.

[0180] It should be noted that since each group includes 16 IOs, which is less than 64 IOs, the alignment can be automatically performed, and the data between groups can be aligned through the alignment marker. Specifically, a 72bit alignment marker can be inserted every 20480*8 bytes of data in each group of data, and only the alignment markers at the same position in different groups need to be sent at the same time to ensure the alignment of the sent data.

[0181] Please refer to Figure 8 , Figure 8 The alignment marker insertion method provided for the embodiment of the present application is shown in the structure diagram.

[0182] As shown in Figure 8 , for each group of data, a 72bit alignment marker is inserted every 20480*8 bytes of data.

[0183] For example, the definition of the alignment marker of the sixteen groups of data can be as shown in Table 1:

[0184]

[0185]

[0186] Table 1

[0187] It should be noted that the definition of the alignment mark above is only exemplary, and the value of the alignment mark and the corresponding relationship with the group number can be defined according to actual needs, and the present application does not limit this.

[0188] Based on this, the data added with the alignment mark is obtained.

[0189] 3) PHY IO physical interface layer

[0190] Since 1152bit (1024bit data + 128bit check) data is divided into 16 groups, each group has 72bit, so the bandwidth of each group is about 29Gbps (400*1.03125*(1152 / 1024) / 16), and the number of IOs in each group is 16, so the IO rate is about 1.82Gbps (29 / 16). The IO transmission data adopts the DDR mode: each group contains a pair of differential clock CK, 16 pairs of differential data DQ, a total of 34 (1*2+16*2) IO pins are needed, and further through the corresponding IO pins, the second FPGA corresponding SerDes data is sent to the second FPGA.

[0191] At this point, the SerDes data sending process of the first FPGA is completed.

[0192] After the second FPGA receives the data sent from the IO pins of the first FPGA, the received multiple groups of target user data can be merged to obtain the scrambled reference user data, and the scrambled reference user data is descrambled to obtain the reference user data.

[0193] Please refer to Figure 9 , Figure 9 The IO transmission module provided by the embodiment of the present application is a schematic diagram of the processing process in the receiving direction of the link layer.

[0194] As Figure 9 shown, in the link layer, the specific processing process of each module is as follows:

[0195] First, the received data is processed by bitslip to slide the bit position. Since the parallel bit positions are not necessarily consistent with the transmission when the received data is operated by the serial-to-parallel operation in the physical layer (that is, the start bit positions of each group of alignment marks are aligned and sent at the same time, which are not necessarily received at the same time), it is necessary to slide the bits according to the alignment mark to make the start bit positions of each group of alignment marks in the same position.

[0196] Further, the alignment marker is detected by marker check, and the start bit position of the detected alignment marker is returned to the previous bitslip module to perform a slip bit operation, so as to ensure that the start bit position of the alignment marker is at the highest bit of the output parallel data. Meanwhile, the alignment marker is deleted, and a corresponding marker is marked at the start bit position of the alignment marker, and data buffering is performed through the buffer module.

[0197] The markers of all groups of data in the buffer are detected by the out control module, and it is judged whether all groups of data are arrived and aligned, and when the condition is met, all groups of data are output in parallel to obtain the reference user data after scrambling.

[0198] After obtaining the reference user data after scrambling, the reference user data after scrambling is descrambled according to the scrambling mode to obtain the reference user data.

[0199] Further, the check information included in the reference user data is checked, and in the case of successful check, the reference user data is restored to the SerDes data corresponding to the second FPGA.

[0200] The SerDes data corresponding to the second FPGA is sent through the SerDes of the second FPGA, and the first FPGA and the second FPGA simultaneously perform data transmission and reception, so as to realize 800Gbps transmission of Ethernet.

[0201] Thus, the description of embodiment 1 is ended.

[0202] Please refer to Figure 10 , Figure 10 is a schematic structural diagram of a network device according to an embodiment of the present application. As shown in Figure 10 , the network device is deployed with a first FPGA and at least one second FPGA; the first FPGA is connected with each second FPGA through an IO pin; the first FPGA is deployed with a first IO transmission module; each second FPGA is deployed with a second IO transmission module, and the network device can be used to execute the method proposed in the above embodiments.

[0203] Please refer to Figure 11 , Figure 11 is a structural diagram of a data transmission device based on FPGA according to an embodiment of the present application, and the device is applied to a network device; the network device is deployed with a first FPGA and at least one second FPGA; the first FPGA is connected with each second FPGA through an IO pin; the first FPGA is deployed with a first IO transmission module; each second FPGA is deployed with a second IO transmission module. As shown in Figure 11As shown, the FPGA-based data transmission device can include a processing unit 1101, a determination unit 1102, and a transmission unit 1103. Specifically, the device includes:

[0204] The processing unit 1101 is configured to, for the SerDes data corresponding to each second FPGA that has been obtained, perform first IO processing on the SerDes data corresponding to the second FPGA by a first IO transmission module deployed in the first FPGA to obtain a plurality of groups of target user data; the first IO processing refers to: performing packaging processing on the SerDes data corresponding to the second FPGA and adding the check information corresponding to the SerDes data to obtain reference user data, performing scrambling on the reference user data, and grouping the scrambled reference user data to obtain a plurality of groups of target user data;

[0205] The determination unit 1102 is configured to determine the transmission rate of a single IO pin and determine the N IO pins that need to be occupied by the SerDes data corresponding to the second FPGA based on the IO data transmission mode;

[0206] The transmission unit 1103 is configured to, by the N IO pins, send each target user data to the second FPGA corresponding to the SerDes data according to the transmission rate of a single IO pin, so that a second IO processing is performed on each target user data received by a second IO transmission module in the second FPGA to obtain the SerDes data corresponding to the second FPGA, and the SerDes data is transmitted by a SerDes in the second FPGA; the second IO processing is the reverse process of the first IO processing.

[0207] Optionally, the first FPGA further deploys an Ethernet processing module; the Ethernet processing module is configured to convert user-side data into SerDes data that allows transmission by a serial transceiver SerDes; the processing unit 1101 is further configured to:

[0208] convert, by the Ethernet processing module in the first FPGA, the received user-side data into target SerDes data, and transmit, by a SerDes in the first FPGA, the SerDes data corresponding to the first FPGA in the target SerDes data; the target SerDes data includes the SerDes data corresponding to the first FPGA and the SerDes data corresponding to each second FPGA;

[0209] forward, by the Ethernet processing module in the first FPGA, the SerDes data corresponding to each second FPGA in the target SerDes data to the first IO transmission module.

[0210] Optionally, a maximum data amount allowed to be transmitted by the SerDes in the first FPGA is M, a data size of the target SerDes data is greater than M, and a data size of the SerDes data corresponding to the first FPGA is M.

[0211] Optionally, the processing unit 1101 is specifically configured to:

[0212] According to the obtained data width and clock frequency, the SerDes data corresponding to the second FPGA is packaged to obtain parallel signal data.

[0213] The parallel signal data is grouped according to a preset size, and each group of data is encoded to obtain a check code corresponding to the group of data.

[0214] The reference user data is obtained by splicing each group of data and the check code corresponding to each group of data.

[0215] Optionally, the processing unit 1101 is specifically configured to:

[0216] The number of groups of target user data is determined according to the number of IO pins included in the first FPGA.

[0217] The reference user data after scrambling is grouped according to the number of groups of target user data.

[0218] For each group of data, a second specified length of alignment marker is inserted every first specified length of data to obtain target user data.

[0219] The alignment marker is used to align each group of target user data when transmitting the target user data, different groups of target user data have different alignment markers, and the same group of target user data has the same alignment marker.

[0220] Optionally, the determination unit 1102 is specifically configured to:

[0221] The transmission rate of each group of target user data is determined according to the target total rate and the number of groups of target user data; the target total rate is determined according to the sum of the data sizes of the SerDes data corresponding to each second FPGA.

[0222] The transmission rate of a single IO pin is determined according to the transmission rate of each group of target user data and the number of IOs corresponding to each group of target user data; the number of IOs included in each group of target user data is determined according to the number of groups of target user data, the maximum transmission rate of the IO pin of the first FPGA, and the target total rate.

[0223] The N IO pins required by the SerDes data corresponding to the second FPGA are determined according to the number of IOs corresponding to each group of target user data and the IO data transmission mode.

[0224] Optionally, the second IO processing refers to:

[0225] merging the received multiple groups of target user data to obtain reference user data after scrambling, and descrambling the reference user data after scrambling to obtain reference user data;

[0226] checking the check information included in the reference user data, and restoring the reference user data to SerDes data corresponding to the second FPGA in the case of successful check.

[0227] Optionally, the transmission unit 1103 is specifically configured to:

[0228] setting a designated mark to the start bit position of the alignment mark of each group of target user data, and deleting the alignment mark of each group of target user data;

[0229] buffering the target user data after deleting the alignment mark;

[0230] In the case that the target user data is buffered, merging the multiple groups of target user data according to the position of the designated mark to obtain reference user data after scrambling.

[0231] Thus, the description of the data transmission device based on FPGA in the Figure 11 is completed.

[0232] Correspondingly, in the embodiment, the application also provides a computer readable storage medium, and the computer readable storage medium stores a plurality of computer instructions, and the computer instructions can implement the method disclosed in the above examples of the application when executed.

[0233] For example, the computer readable storage medium can be RAM (Random Access Memory, random access memory), volatile memory, non-volatile memory, flash memory, storage drive (such as hard drive), solid state disk, any type of storage disk (such as optical disk, DVD, etc.), or similar storage medium, or combination thereof.

[0234] The above is only a preferred embodiment of the application, and is not intended to limit the application. For those skilled in the art, the application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall be included in the scope of protection of the application.

Claims

1. A data transmission method based on FPGA, characterized in that, This method is applied to a network device; the network device is equipped with a first FPGA and at least one second FPGA; the first FPGA is connected to each second FPGA via I / O pins; the first FPGA is equipped with a first I / O transmission module; Each of the second FPGAs is equipped with a second I / O transfer module; the method includes: For each SerDes data corresponding to the second FPGA that has been obtained, the first IO transmission module deployed in the first FPGA performs first IO processing on the SerDes data corresponding to the second FPGA to obtain multiple sets of target user data; the first IO processing refers to: packaging the SerDes data corresponding to the second FPGA and adding the verification information corresponding to the SerDes data to obtain reference user data, scrambling the reference user data and grouping the scrambled reference user data to obtain multiple sets of target user data. Determine the transmission rate of a single IO pin and, based on the IO data transmission method, determine the N IO pins required for the SerDes data corresponding to the second FPGA; Through N IO pins, each target user data is sent to the second FPGA corresponding to the SerDes data according to the transmission rate of the single IO pin. The second IO transmission module in the second FPGA performs second IO processing on the received target user data to obtain the SerDes data corresponding to the second FPGA and sends the SerDes data through the SerDes in the second FPGA. The second IO processing is the reverse process of the first IO processing.

2. The method according to claim 1, characterized in that, The first FPGA also deploys an Ethernet processing module; the Ethernet processing module is used to convert user-side data into SerDes data that can be transmitted via a serial transceiver SerDes; the method further includes: The received user-side data is converted into target SerDes data by the Ethernet processing module in the first FPGA, and the SerDes data corresponding to the first FPGA in the target SerDes data is sent through the SerDes in the first FPGA; the target SerDes data includes the SerDes data corresponding to the first FPGA and the SerDes data corresponding to each second FPGA. The Ethernet processing module in the first FPGA forwards the SerDes data corresponding to each second FPGA in the target SerDes data to the first IO transmission module.

3. The method according to claim 2, characterized in that, The maximum amount of data that can be transmitted in a single SerDes in the first FPGA is M, the data size of the target SerDes data is greater than M, and the data size of the SerDes data corresponding to the first FPGA is M.

4. The method according to claim 1, characterized in that, The SerDes data corresponding to the second FPGA is packaged and the corresponding verification information is added to obtain reference user data, including: Based on the obtained data bit width and clock frequency, the SerDes data corresponding to the second FPGA is packaged to obtain parallel signal data; The parallel signal data is grouped according to a preset size, and each group of data is encoded to obtain the check code corresponding to that group of data. The reference user data is obtained by concatenating each set of data with its corresponding check code and then reorganizing the data.

5. The method according to claim 1, characterized in that, The process of grouping the scrambled reference user data to obtain multiple sets of target user data includes: The number of target user data groups is determined based on the number of I / O pins included in the first FPGA; The scrambled reference user data is grouped according to the number of groups of the target user data. For each set of data, an alignment marker of a second specified length is inserted every first specified length of data to obtain the target user data; The alignment mark is used to align the target user data groups when transmitting target user data. Different alignment marks are inserted for different groups of target user data, while the same alignment mark is inserted for the same group of target user data.

6. The method according to claim 5, characterized in that, The process of determining the transmission rate of a single IO pin and determining the N IO pins required for the SerDes data corresponding to the second FPGA based on the IO data transmission method includes: The transmission rate of each group of target user data is determined based on the target total rate and the number of groups of target user data; the target total rate is determined based on the sum of the data sizes of the SerDes data corresponding to each second FPGA. The transmission rate of a single I / O pin is determined based on the transmission rate of each group of target user data and the number of I / O pins corresponding to each group of target user data; the number of I / O pins included in each group of target user data is determined based on the number of groups of target user data, the maximum transmission rate of the I / O pins of the first FPGA, and the target total rate. The number of IO pins required for the SerDes data corresponding to the second FPGA is determined based on the number of IO pins and the IO data transmission method for each group of target user data.

7. The method according to claim 5, characterized in that, The second I / O processing refers to: The received multiple sets of target user data are merged to obtain scrambled reference user data, and the scrambled reference user data is descrambled to obtain the reference user data. The verification information included in the reference user data is verified, and if the verification is successful, the reference user data is restored to the SerDes data corresponding to the second FPGA.

8. The method according to claim 7, characterized in that, The step of merging multiple sets of received target user data to obtain scrambled reference user data includes: Set the start bit position of the alignment mark for each group of target user data to the specified mark, and delete the alignment mark for each group of target user data; Cache the target user data to remove alignment markers; Once all target user data has been cached, multiple sets of target user data are merged according to the location of the specified marker to obtain scrambled reference user data.

9. A data transmission device based on FPGA, characterized in that, This device is used in a network device; the network device is equipped with a first FPGA and at least one second FPGA; the first FPGA is connected to each second FPGA via I / O pins; the first FPGA is equipped with a first I / O transmission module; Each of the second FPGAs is equipped with a second I / O transmission module; the device includes: The processing unit is used to perform first IO processing on the SerDes data corresponding to each second FPGA obtained through the first IO transmission module deployed in the first FPGA to obtain multiple sets of target user data. The first IO processing refers to: packaging the SerDes data corresponding to the second FPGA and adding the corresponding verification information of the SerDes data to obtain reference user data, scrambling the reference user data, and grouping the scrambled reference user data to obtain multiple sets of target user data. The determination unit is used to determine the transmission rate of a single IO pin and, based on the IO data transmission method, determine the N IO pins required for the SerDes data corresponding to the second FPGA. The transmission unit is used to send each target user data to the second FPGA corresponding to the SerDes data through N IO pins according to the transmission rate of the single IO pin. The second IO transmission module in the second FPGA performs second IO processing on the received target user data to obtain the SerDes data corresponding to the second FPGA and sends the SerDes data through the SerDes in the second FPGA. The second IO processing is the reverse process of the first IO processing.

10. A network device, characterized in that, The network device is configured with a first FPGA and at least one second FPGA; the first FPGA is connected to each second FPGA via I / O pins; the first FPGA is configured with a first I / O transmission module; each second FPGA is configured with a second I / O transmission module, and the network device is configured to perform the method as described in any one of claims 1 to 8.

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