Audio controller test system, method, device, medium and program product

Abstract

The invention relates to the technical field of semiconductor finished product testing, and discloses an audio controller testing system, method and device, a medium and a program product. The system comprises a first to-be-tested chip, a second to-be-tested chip and debugging equipment, the first to-be-tested chip is connected with the second to-be-tested chip, so that the first to-be-tested chip and the second to-be-tested chip are mutually tested, mutual test results are generated, and the mutual test results comprise a first test result and a second test result; the debugging device is connected with the first to-be-tested chip and the second to-be-tested chip, and is used for receiving a first test result sent by the first to-be-tested chip and a second test result sent by the second to-be-tested chip, and determining audio test results of the first to-be-tested chip and the second to-be-tested chip based on the first test result and the second test result. By implementing the technical scheme of the invention, the comprehensive function test of the audio controller can be realized, and meanwhile, the test efficiency of the audio controller is effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor finished product testing, and in particular to a testing system, method, equipment, medium and program product of an audio controller. Background Art

[0002] Semiconductor Final Test (FT) is the final test performed after the chip is packaged to ensure the correctness of the chip function. For an integrated chip (System on Chip, SOC) with an I2S (Inter-IC Sound) audio controller, the test methods in the FT stage include internal self-loopback and external self-loopback modes.

[0003] However, in the internal self-loop mode, the control clock is generated by the chip itself, and the data does not pass through the pins, so the pin function cannot be verified. The external self-loop mode allows the control clock to be provided internally or externally, and the data is output through the pins and then returned to the receiving end, but it cannot fully cover the module functions. In addition, the external clock method requires the SOC chip to control the external chip, which increases the test complexity. Summary of the invention

[0004] In view of this, the present invention provides a test system, method, device, medium and program product for an audio controller to solve the problems of insufficient function testing and low test efficiency of I2S audio controller in current chip production testing.

[0005] In a first aspect, the present invention provides a test system for an audio controller, comprising: a first chip to be tested, the first chip to be tested comprising a first audio control interface; a second chip to be tested, the second chip to be tested comprising a second audio control interface, the first audio control interface being connected to the second audio control interface so that the first chip to be tested and the second chip to be tested can perform mutual testing and generate mutual testing results, the mutual testing results comprising first test results and second test results; a debugging device, comprising a first interface and a second interface, the first interface being connected to the first chip to be tested, and the second interface being connected to the second chip to be tested; the debugging device is used to receive a first test result sent by the first chip to be tested through the first interface, receive a second test result sent by the second chip to be tested through the second interface, and determine the audio test results of the first chip to be tested and the second chip to be tested based on the first test result and the second test result.

[0006] The audio controller test system provided by the embodiment of the present invention can achieve mutual testing by connecting the audio control interfaces of the first chip to be tested and the second chip to be tested, thereby improving the comprehensiveness and accuracy of the test. The system can automatically generate mutual test results, including the first test results and the second test results, reducing manual intervention and potential human errors. The debugging device receives the test results of the two chips to be tested through the first interface and the second interface respectively, making data collection faster and more efficient. Based on the test results of the two chips, the system can comprehensively evaluate the functional status of its audio controller to ensure that all possible functional points are covered and avoid omissions. By testing the two chips at the same time, the system significantly improves the test efficiency and reduces the overall test time.

[0007] In an optional implementation, the debugging device sends a first control mode to a first chip under test via a first interface, and sends a second control mode to a second chip under test via a second interface; the first control mode and the second control mode are master-slave control modes.

[0008] The audio controller test system provided by the embodiment of the present invention has a master-slave control mode that enables the system to flexibly configure and manage multiple chips to be tested, thereby improving the controllability and coordination of the test process. Through the respective control modes, the working state of the chip can be adjusted in real time during the test process, and the test requirements and changes can be quickly responded to.

[0009] In an optional embodiment, a first chip to be tested and a second chip to be tested perform mutual testing to generate mutual testing results, including: the first chip to be tested generates a first pseudo-random number sequence according to a first control mode, and sends the first pseudo-random number sequence to the second chip to be tested; the second chip to be tested generates a second pseudo-random number sequence according to a second control mode, and sends the second pseudo-random number sequence to the first chip to be tested; the first chip to be tested compares the first pseudo-random number sequence and the second pseudo-random number sequence to generate a first test result, and sends the first test result to a debugging device; the second chip to be tested compares the second pseudo-random number sequence with the first pseudo-random number sequence to generate a second test result, and sends the second test result to the debugging device.

[0010] The audio controller test system provided by the embodiment of the present invention can comprehensively evaluate the performance of two chips by mutually generating and comparing pseudo-random number sequences, ensuring their stability and compatibility under different control modes. The generation and comparison of pseudo-random number sequences can provide more reliable test data, reduce human interference and deviations in the test process, and thus improve the accuracy of the results. The design of mutual testing enables the two chips to provide instant feedback on each other's performance, identify problems in a timely manner and make adjustments, thereby improving the overall test efficiency. The mutual comparison between the first and second chips to be tested can effectively verify their respective functions and performance, ensuring that each chip can operate normally under different working conditions.

[0011] In an optional embodiment, the first chip under test generates a first pseudo-random number sequence according to a first control mode, including: based on the connection between the first audio control interface and the second audio control interface, handshaking the first chip under test and the second chip under test; if the handshake between the first chip under test and the second chip under test is successful, the first chip under test generates a first pseudo-random number sequence according to preset pseudo-random number generation parameters and the first control mode.

[0012] In the audio controller test system provided by the embodiment of the present invention, the handshake process ensures that the communication between the first chip to be tested and the second chip to be tested is reliable, and subsequent operations are performed only after the connection is successfully established, thereby reducing potential errors. Through handshake confirmation, it can be ensured that the two chips are tested in the same working state, avoiding inaccurate test results due to inconsistent states.

[0013] In an optional embodiment, the second chip under test generates a second pseudo-random number sequence according to a second control mode, including: based on the connection between the first audio control interface and the second audio control interface, handshaking the first chip under test and the second chip under test; if the handshake between the first chip under test and the second chip under test is successful, the second chip under test generates a second pseudo-random number sequence according to preset pseudo-random number generation parameters and the second control mode.

[0014] In the audio controller test system provided by the embodiment of the present invention, the handshake mechanism ensures that the connection between the second chip to be tested and the first chip to be tested is stable, and the pseudo-random number sequence is generated only after the connection is confirmed to be successful, thereby reducing communication errors. Successful handshakes and effective parameter settings help to improve the quality of the generated pseudo-random number sequence, thereby enhancing the reliability and accuracy of the test results.

[0015] In an optional embodiment, a handshake is performed on the first chip to be tested and the second chip to be tested, including: the first chip to be tested sends first preset data to the second chip to be tested according to a preset number of times; the second chip to be tested sends first preset data to the first chip to be tested according to a preset number of times; when it is determined that the first chip to be tested and the second chip to be tested have both received the first preset data, the first chip to be tested sends second preset data to the second chip to be tested according to the preset number of times; the second chip to be tested sends second preset data to the first chip to be tested according to the preset number of times.

[0016] The audio controller test system provided by the embodiment of the present invention ensures the stable connection between the first chip to be tested and the second chip to be tested through a two-way data exchange and confirmation mechanism, thereby reducing the possibility of communication errors. The preset number of sending and receiving mechanisms provides multiple confirmation opportunities, further ensuring that the two chips are tested in the same state, thereby improving the reliability of the handshake. After confirming that both parties have received the preset data, subsequent data exchange is performed, thereby ensuring the data consistency of both parties and reducing errors caused by asynchrony.

[0017] In an optional embodiment, the debugging device sends a first control mode to a first chip under test through a first interface, and sends a second control mode to a second chip under test through a second interface, including: the debugging device sets the first interface to a first level, and sets the second interface to a second level, so that the first chip under test configures the first control mode according to the first level, and the second chip under test configures the second control mode according to the second level.

[0018] The audio controller test system provided by the embodiment of the present invention can clearly distinguish and control the behavior of each chip under test by setting different levels, thereby ensuring the accuracy of signal transmission. Two chips under test can receive control instructions at the same time, thereby improving configuration efficiency and shortening test preparation time.

[0019] In an optional embodiment, based on the first test result and the second test result, the audio test results of the first chip to be tested and the second chip to be tested are determined, including: performing a first stage test on the first chip to be tested according to the first control mode and the second chip to be tested according to the second control mode to obtain the first stage test result; if the first stage test result indicates that the first chip to be tested and the second chip to be tested pass the test, the first chip to be tested is configured to the second control mode and the second chip to be tested is configured to the first control mode; the first chip to be tested in the second control mode and the second chip to be tested in the first control mode shake hands; if the handshake is successful, the first chip to be tested generates parameters according to a preset pseudo-random number. Generate a third pseudo-random number sequence, and send the third pseudo-random number sequence to the second chip under test; the second chip under test generates a fourth pseudo-random number sequence according to preset pseudo-random number generation parameters, and sends the fourth pseudo-random number sequence to the first chip under test; the first chip under test compares the third pseudo-random number sequence with the fourth pseudo-random number sequence to obtain a third test result, and the second chip under test compares the fourth pseudo-random number sequence with the third pseudo-random number sequence to obtain a fourth test result; according to the third test result and the fourth test result, determine whether the second stage test of the first chip under test and the second chip under test passes; if the second stage test passes, determine that the first chip under test and the second chip under test are in a normal state.

[0020] The audio controller test system provided by the embodiment of the present invention can effectively identify and eliminate potential problems and improve the systematicness and accuracy of the test by dividing the test into a first stage and a second stage. The control mode of the chip to be tested is dynamically adjusted according to the test results of the first stage, which enhances the adaptability and flexibility of the system and enables the test process to be optimized for different situations. By comparing the test results of different stages, possible problems can be more clearly identified and targeted troubleshooting can be performed. Through multiple rounds of data interaction and comparison, the performance of the chip can be comprehensively evaluated to ensure the functional integrity of the chip in different scenarios.

[0021] In a second aspect, the present invention provides a testing method for an audio controller, which is applied to a testing system for an audio controller of the first aspect or any corresponding embodiment thereof, comprising: controlling a first audio control interface of a first chip to be tested to connect with a second audio control interface of a second chip to be tested, so that the first chip to be tested and the second chip to be tested perform mutual testing and generate mutual testing results; obtaining mutual testing results between the first chip to be tested and the second chip to be tested, the mutual testing results including a first test result and a second test result; and determining audio test results of the first chip to be tested and the second chip to be tested based on the first test result and the second test result.

[0022] The audio controller test method provided by the embodiment of the present invention can comprehensively evaluate the mutual compatibility and cooperative working ability of two chips through mutual testing, thereby ensuring the reliability of the overall system performance. The process of obtaining the mutual test results can be carried out in real time, which helps to identify problems and make adjustments in a timely manner, thereby improving the response speed of the test. The inclusion of the first test result and the second test result provides a basis for two-way verification and enhances the reliability of the test results. By integrating mutual testing, repeated testing and unnecessary steps can be avoided, thereby improving the efficiency of the overall test process.

[0023] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the test method of the audio controller of the second aspect mentioned above by executing the computer instructions.

[0024] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the audio controller testing method of the second aspect.

[0025] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions, wherein the computer instructions are used to enable a computer to execute the audio controller testing method of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 is a structural block diagram of a test system for an audio controller according to an embodiment of the present invention;

[0028] Figure 2 is a structural block diagram of another audio controller test system according to an embodiment of the present invention;

[0029] Figure 3 is a structural block diagram of a test system for another audio controller according to an embodiment of the present invention;

[0030] Figure 4 is a flow chart of a method for testing an audio controller according to an embodiment of the present invention;

[0031] Figure 5 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0033] During the semiconductor product testing phase, the integrated chip (System on Chip, SOC) with an I2S audio controller needs to be tested for its function. The current common method is to configure the I2S audio controller to internal self-loop or external self-loop mode, that is, the SOC chip verifies the module function through the I2S audio controller's self-transmitting and self-receiving data.

[0034] In the internal self-loop mode, the control clock is generated inside the chip, and the data does not pass through the chip pins. This method cannot verify whether the chip pins function normally. In the external self-loop mode, the control clock can be generated inside the chip or provided externally, and the data is output through the chip pins and then returned to its own receiving port. However, this method does not cover all the functions of the module, such as the inability to switch between host mode and slave mode. In addition, if an external clock is used, the SOC chip needs to control the external chip, which increases the complexity of the test process.

[0035] In view of this, the technical solution of the present invention interconnects the I2S audio controller interfaces of the two SOC chips to be tested, and the debugging device indicates the working mode of the two chips. The two chips to be tested send data to each other through the I2S audio controller and verify the received data, thereby detecting whether the function of the audio controller is normal. At the same time, the two SOC chips to be tested can be tested at the same time, and the functions can be fully verified, thereby greatly improving the test efficiency.

[0036] In this embodiment, a test system for an audio controller is provided. Figure 1 As shown, the system includes: a first chip to be tested 1, a second chip to be tested 2 and a debugging device 3.

[0037] The first chip under test 1 includes a first audio control interface.

[0038] The first chip under test 1 refers to the first audio control chip to be tested in the system. The first audio control interface refers to the interface on the first chip under test 1 for communicating audio data with the second chip under test 2, which can implement a specific communication protocol (such as I2S) for transmitting audio signals and control information. Specifically, the audio control interface may include multiple signal lines such as data input, data output, and clock signal to ensure that audio data can be efficiently and accurately transmitted between devices.

[0039] Specifically, Figure 2 As shown, when the first chip to be tested 1 is a SOC chip, the SOC chip includes a central processing unit (CPU), a memory, an audio control circuit (audio controller), and an input and output interface GPIO. The SOC chip is connected to the second chip to be tested 2 through the first audio control interface (such as I2S interface) corresponding to the audio control circuit, and is connected to the debugging device 3 through the input and output interface GPIO.

[0040] The second chip under test 2 includes a second audio control interface, and the first audio control interface is connected to the second audio control interface so that the first chip under test 1 and the second chip under test 2 can perform mutual testing to generate mutual testing results, which include first test results and second test results.

[0041] The second chip under test 2 is the second audio control chip to be tested in the system. The second audio control interface refers to the interface on the second chip under test 2, which is used to communicate audio data with the first chip under test 1. The second audio control interface is connected to the first audio control interface of the first chip under test 1, through which data and control signals can be transmitted. Like the first audio control interface, the second audio control interface can also implement a specific communication protocol (such as I2S).

[0042] The mutual test result refers to the result generated by the interactive test between the first chip under test 1 and the second chip under test 2. Specifically, the mutual test result includes a first test result and a second test result, wherein the first test result is a test result generated by the first chip under test 1, and the second test result is a test result generated by the second chip under test 2.

[0043] The debugging device 3 includes a first interface and a second interface, the first interface is connected to the first chip to be tested 1, and the second interface is connected to the second chip to be tested 2; the debugging device 3 is used to receive a first test result sent by the first chip to be tested 1 through the first interface, receive a second test result sent by the second chip to be tested 2 through the second interface, and determine the audio test results of the first chip to be tested 1 and the second chip to be tested 2 based on the first test result and the second test result.

[0044] The debugging device 3 is a hardware device for performing audio testing and data collection, for example, it can be an automatic test equipment (ATE). The debugging device 3 is connected to the first chip to be tested 1 and the second chip to be tested 2, and can receive and process the test results from the chips. The first interface refers to the connection interface between the debugging device 3 and the first chip to be tested 1, which is used to receive the test results from the first chip to be tested, and can be a data transmission interface, such as I2S, SPI or other communication protocols. The second interface refers to the connection interface between the debugging device 3 and the second chip to be tested 2, which is similar to the first interface and is used to receive the test results from the second chip to be tested. Specifically, the debugging device 3 receives the first test result sent by the first chip to be tested 1 through the first interface. The second test result sent by the second chip to be tested 2 is received through the second interface. The debugging device 3 analyzes the received first test result and the second test result to determine the audio test results of the first chip to be tested 1 and the second chip to be tested 2.

[0045] For example, Figure 3 As shown, when the first chip under test 1 (C1) and the second chip under test 2 (C2) are both SOC chips, the debugging device 3 is an automatic test device ATE, and the communication protocol between the two chips under test is I2S, the first audio control interface includes I2S_SDOUT and I2S_SDIN, the second audio control interface includes I2S_SDIN and I2S_SDOUT, and the first chip under test 1 and the second chip under test 2 realize data transmission between each other through I2S_SDOUT and I2S_SDIN. The first interface includes GPIO_O1 and GPIO_I1, and the second interface includes GPIO_O2 and GPIO_I2. The debugging device 3 realizes data transmission with the first chip under test 1 through GPIO_O1 and GPIO_I1, and realizes data transmission with the second chip under test 2 through GPIO_O2 and GPIO_I2. In addition, the debugging device 3 also includes a first power supply interface Power1 and a second power supply interface Power2. The debugging device 3 supplies power to the first chip under test 1 through Power1 and supplies power to the second chip under test 2 through Power2, so that the first chip under test 1 and the second chip under test 2 start running.

[0046] The audio controller test system provided by the embodiment of the present invention can achieve mutual testing by connecting the audio control interfaces of the first chip to be tested and the second chip to be tested, thereby improving the comprehensiveness and accuracy of the test. The system can automatically generate mutual test results, including the first test results and the second test results, reducing manual intervention and potential human errors. The debugging device receives the test results of the two chips to be tested through the first interface and the second interface respectively, making data collection faster and more efficient. Based on the test results of the two chips, the system can comprehensively evaluate the functional status of its audio controller to ensure that all possible functional points are covered and avoid omissions. By testing the two chips at the same time, the system significantly improves the test efficiency and reduces the overall test time.

[0047] In an optional implementation, the debugging device 3 sends a first control mode to the first chip under test 1 through a first interface, and sends a second control mode to the second chip under test 2 through a second interface; the first control mode and the second control mode are master-slave control modes.

[0048] The first control mode refers to the operation mode of the first chip under test 1, which can be configured as a master control mode or a slave control mode. Specifically, if the first control mode sent by the debugging device 3 to the first chip under test 1 through the first interface is the master control mode, the first chip under test 1 is responsible for sending audio signals, controlling data transmission, sending clock signals, etc. If the first control mode sent by the debugging device 3 to the first chip under test 1 through the first interface is the slave control mode, the first chip under test 1 is responsible for receiving audio signals from the second chip under test 2, controlling data transmission, and sending clock signals.

[0049] The second control mode refers to the operation mode of the second chip under test 2, for example, it can also be configured as a master control mode or a slave control mode. However, the second control mode is different from the first control mode, and the first control mode and the second control mode together constitute a master-slave control mode, that is, the first chip under test 1 is in the master control mode and the second chip under test 2 is in the slave control mode, or the first chip under test 1 is in the slave control mode and the second chip under test 2 is in the master control mode.

[0050] The audio controller test system provided by the embodiment of the present invention has a master-slave control mode that enables the system to flexibly configure and manage multiple chips to be tested, thereby improving the controllability and coordination of the test process. Through the respective control modes, the working state of the chip can be adjusted in real time during the test process, and the test requirements and changes can be quickly responded to.

[0051] In an optional embodiment, the first chip under test 1 and the second chip under test 2 perform mutual testing to generate mutual testing results, including: the first chip under test 1 generates a first pseudo-random number sequence according to a first control mode, and sends the first pseudo-random number sequence to the second chip under test 2; the second chip under test 2 generates a second pseudo-random number sequence according to a second control mode, and sends the second pseudo-random number sequence to the first chip under test 1; the first chip under test 1 compares the first pseudo-random number sequence and the second pseudo-random number sequence to generate a first test result, and sends the first test result to the debugging device 3; the second chip under test 2 compares the second pseudo-random number sequence with the first pseudo-random number sequence to generate a second test result, and sends the second test result to the debugging device 3.

[0052] The first pseudo-random number sequence is a sequence generated by the first chip under test 1, for example, it can be generated based on a specific algorithm (such as a linear feedback shift register, a Mersenne twister algorithm, etc.) and an initial seed value. The first pseudo-random number sequence is used to test the receiving capability, data processing capability and data integrity of the second chip under test 2.

[0053] The second pseudo-random number sequence is a sequence generated by the second chip under test 2, and the generation process is similar to that of the first pseudo-random number sequence. The second pseudo-random number sequence is used to test the receiving capability, data processing capability and data integrity of the first chip under test 1.

[0054] The first test result is the result generated by comparing the first pseudo-random number sequence generated by the first chip under test 1 with the second pseudo-random number sequence received. Specifically, the result can be a simple "pass" or "fail", or more detailed information, such as the number of error bits found during the comparison or specific data mismatch bits.

[0055] The second test result is the result generated by comparing the second pseudo-random number sequence generated by the second chip under test 2 with the received first pseudo-random number sequence. Similarly, the result may be "passed" or "failed", or provide detailed information about the comparison, such as the number of error bits found.

[0056] The first test result and the second test result are used to evaluate the effectiveness of communication and data processing between the first chip under test 1 and the second chip under test 2, and are sent to the debugging device 3 for recording and analysis.

[0057] Specifically, the first chip under test 1 generates a first pseudo-random number sequence according to the first control mode, and sends the generated first pseudo-random number sequence to the second chip under test 2 through the first audio control interface. The second chip under test 2 generates a second pseudo-random number sequence according to the second control mode, and sends the generated second pseudo-random number sequence to the first chip under test 1 through the second audio control interface.

[0058] The first chip under test 1 compares the received second pseudo-random number sequence with the first pseudo-random number sequence generated by itself one by one to verify the integrity and correctness of the data transmission. According to the comparison result, the first chip under test 1 generates a first test result.

[0059] Similarly, the second chip under test 2 receives the first pseudo-random number sequence sent by the first chip under test 1, and compares the received first pseudo-random number sequence with the second pseudo-random number sequence generated by itself. The second chip under test 2 generates a second test result according to the comparison result.

[0060] The first chip under test 1 generates the first test result through a specified interface (such as Figure 3 The GPIO_O interface on the C1 chip in the middle) is sent to the debugging device 3 for recording and analysis.

[0061] Similarly, the second chip under test 2 generates the second test result through a specified interface (such as Figure 3 The GPIO_O interface on the C2 chip in the middle) is sent to the debugging device 3 for recording and analysis.

[0062] The audio controller test system provided by the embodiment of the present invention can comprehensively evaluate the performance of two chips by mutually generating and comparing pseudo-random number sequences, ensuring their stability and compatibility under different control modes. The generation and comparison of pseudo-random number sequences can provide more reliable test data, reduce human interference and deviations in the test process, and thus improve the accuracy of the results. The design of mutual testing enables the two chips to provide instant feedback on each other's performance, identify problems in a timely manner and make adjustments, thereby improving the overall test efficiency. The mutual comparison between the first and second chips to be tested can effectively verify their respective functions and performance, ensuring that each chip can operate normally under different working conditions.

[0063] In an optional embodiment, the first chip under test 1 generates a first pseudo-random number sequence according to a first control mode, including: based on the connection between the first audio control interface and the second audio control interface, the first chip under test 1 and the second chip under test 2 shake hands; if the handshake between the first chip under test 1 and the second chip under test 2 is successful, the first chip under test 1 generates a first pseudo-random number sequence according to preset pseudo-random number generation parameters and the first control mode.

[0064] After the first chip under test 1 is configured as the first control mode and the second chip under test 2 is configured as the second control mode, the test program of the first chip under test 1 will access its own audio controller to configure parameters such as data sampling rate and data width. For example, the data sampling rate and data width can be selected according to the specifications of the audio controller, and the more commonly used parameters, such as the sampling rate is 96KHz and the data width is 24Bits. The second chip under test 2 executes the same process.

[0065] After the configuration is completed, the first chip under test 1 and the second chip under test 2 enter the handshake process. During the handshake process, the first chip under test 1 and the second chip under test 2 will exchange some specific information (such as version number, capability parameters, etc.) to confirm that they are compatible with each other and meet the required communication conditions. If the handshake process is successful, it means that the communication link between the first chip under test 1 and the second chip under test 2 is well established, and the two parties can perform subsequent data exchange; if the handshake fails, the handshake is repeated.

[0066] After the handshake is successful, the first chip to be tested 1 will continue to generate a pseudo-random number sequence. Specifically, the first chip to be tested 1 uses a set of preset pseudo-random number generation parameters, which may include a seed value, a generation algorithm type, a generated sequence length, etc. Among them, the selection of pseudo-random number generation parameters directly affects the randomness and quality of the generated pseudo-random number sequence. The first chip to be tested 1 generates a first pseudo-random number sequence according to the preset pseudo-random number generation parameters and the first control mode determined to be used. The first pseudo-random number sequence will be a random digital sequence with a uniform distribution characteristic, which is suitable for testing and verification. Further, the first pseudo-random number sequence is stored in the memory of the first chip to be tested 1.

[0067] For example, Figure 3 As shown, the test program of the first chip under test 1 (C1) can send the first pseudo-random sequence to its own audio controller through the internal bus through DMA or Memory access mode, and the audio controller sends data in sequence, and the data is sent to the second chip under test 2 (C2) through I2S_SDOUT after parallel-to-serial conversion. The audio controller of the second chip under test 2 receives data through I2S_SDIN and performs serial-to-parallel conversion on the data.

[0068] In the audio controller test system provided by the embodiment of the present invention, the handshake process ensures that the communication between the first chip to be tested and the second chip to be tested is reliable, and subsequent operations are performed only after the connection is successfully established, thereby reducing potential errors. Through handshake confirmation, it can be ensured that the two chips are tested in the same working state, avoiding inaccurate test results due to inconsistent states.

[0069] In an optional embodiment, the second chip under test 2 generates a second pseudo-random number sequence according to a second control mode, including: based on the connection between the first audio control interface and the second audio control interface, handshaking the first chip under test 1 and the second chip under test 2; if the handshake between the first chip under test 1 and the second chip under test 2 is successful, the second chip under test 2 generates a second pseudo-random number sequence according to preset pseudo-random number generation parameters and the second control mode.

[0070] After the handshake is successful, the second chip to be tested 2 continues to generate a pseudo-random number sequence. Specifically, the second chip to be tested 2 uses a set of preset parameters to generate pseudo-random numbers. These parameters may include a seed value, the type of generation algorithm (such as a linear feedback shift register (LFSR) or a Mersenne twister algorithm), and the length of the generated sequence. Once the second chip to be tested 2 determines the pseudo-random number generation parameters and control mode used, it will start to generate a second pseudo-random number sequence. This process can be achieved by the internal algorithm configured by the second chip to be tested 2. The second pseudo-random number sequence is stored in the memory of the second chip to be tested 2.

[0071] The first pseudo-random number sequence generated by the first chip under test 1 should be completely identical to the second pseudo-random number sequence generated by the second chip under test 2 .

[0072] The first pseudo-random number sequence and the second pseudo-random number sequence can be standardized according to a preset data width to ensure that the generated pseudo-random number sequence matches the data width required by the system or test, thereby avoiding errors caused by inconsistent data width in subsequent processing and comparison.

[0073] In the audio controller test system provided by the embodiment of the present invention, the handshake mechanism ensures that the connection between the second chip to be tested and the first chip to be tested is stable, and the pseudo-random number sequence is generated only after the connection is confirmed to be successful, thereby reducing communication errors. Successful handshakes and effective parameter settings help to improve the quality of the generated pseudo-random number sequence, thereby enhancing the reliability and accuracy of the test results.

[0074] In an optional embodiment, a handshake is performed on the first chip under test 1 and the second chip under test 2, including: the first chip under test 1 sends first preset data to the second chip under test 2 according to a preset number of times; the second chip under test 2 sends first preset data to the first chip under test 1 according to a preset number of times; when it is determined that the first chip under test 1 and the second chip under test 2 have both received the first preset data, the first chip under test 1 sends second preset data to the second chip under test 2 according to the preset number of times; the second chip under test 2 sends second preset data to the first chip under test 1 according to the preset number of times.

[0075] The preset number of times refers to the specific number of times each chip under test (first chip under test 1 and second chip under test 2) sends and receives data during the handshake process. This is a preset parameter that can be determined during the system design phase. Specifically, by specifying the number of times data is sent and received, the communication between the two chips is ensured to be stable and reliable. A larger number can be selected to reduce the impact of errors and interference (for example, 16 times, 8 times, etc.).

[0076] The first preset data refers to a specific data packet exchanged between the first chip under test 1 and the second chip under test 2 in the initial stage of the handshake process. Specifically, the data packet may be a fixed byte sequence including a specific command or identifier.

[0077] The second preset data is another specific data packet exchanged between the first chip under test 1 and the second chip under test 2 after confirming that the first preset data is successfully received. The second preset data has content different from the first preset data.

[0078] For example, after accessing its own audio controller, the test program of the first chip under test 1 continuously sends a specific data A1 (first preset data) to the second chip under test 2. When the second chip under test 2 receives 16 A1s in succession, the test program changes the data to be sent to A2 (second preset data), and the number of data sent is also 16.

[0079] At the same time, after accessing its own audio controller, the test program of the second chip under test 2 continues to send A1 (first preset data) to the first chip under test 1. When the first chip under test 1 receives 16 A1s in succession, the test program changes the data sent to A2 (second preset data), and the number of sent data is also 16.

[0080] When the first chip under test 1 receives 8 A2s in succession and the second chip under test 2 receives 8 A2s in succession, it means that the handshake between the first chip under test 1 and the second chip under test 2 is successful, and the next step can be entered to perform the pseudo-random data sending verification process. If the handshake process fails, the handshake process will be repeated. If the handshake process fails multiple times, it means that there is a problem in the test, and the error is reported through a specific interface (such as Figure 3 The GPIO_O interface in the test chip is reported to the debugging device 3. After receiving the error message, the debugging device 3 terminates the test process and determines that the functions of the two chips to be tested are abnormal. The debugging device 3 turns off the power of the two chips to be tested.

[0081] The audio controller test system provided by the embodiment of the present invention ensures the stable connection between the first chip to be tested and the second chip to be tested through a two-way data exchange and confirmation mechanism, thereby reducing the possibility of communication errors. The preset number of sending and receiving mechanisms provides multiple confirmation opportunities, further ensuring that the two chips are tested in the same state, thereby improving the reliability of the handshake. After confirming that both parties have received the preset data, subsequent data exchange is performed, thereby ensuring the data consistency of both parties and reducing errors caused by asynchrony.

[0082] In an optional embodiment, the debugging device 3 sends a first control mode to the first chip under test 1 through a first interface, and sends a second control mode to the second chip under test 2 through a second interface, including: the debugging device 3 sets the first interface to a first level, and sets the second interface to a second level, so that the first chip under test 1 configures the first control mode according to the first level, and the second chip under test 2 configures the second control mode according to the second level.

[0083] The first level refers to the voltage state output by the first interface of the debugging device 3. The second level refers to the voltage state output by the second interface of the debugging device 3. The voltage state can be a high level (for example, +3.3V or +5V) or a low level (for example, 0V). Among them, the high level is used to configure the chip under test to the host mode, in which the chip under test will output a clock signal. The low level is used to configure the chip under test to the slave mode, in which the chip under test will passively receive the clock signal from the host.

[0084] Specifically, the debugging device 3 sets the first interface to the first level to control the working mode of the first chip under test 1. The debugging device 3 sets the second interface to the second level to control the working mode of the second chip under test 2.

[0085] For example, Figure 3 As shown, if the GPIO_O1 of the first chip under test 1 is set to a high level, the first chip under test 1 will be configured as a host mode, which means that the first chip under test 1 will actively output a clock signal (i.e., I2S_MCLK, I2S_BCLK, and I2S_LRCLK output three clock signals). When the first level is set to a high level, the GPIO_O2 of the second chip under test 2 is set to a low level, then the second chip under test 2 will be configured as a slave mode, and will passively receive the clock signal sent from the first chip under test 1.

[0086] The audio controller test system provided by the embodiment of the present invention can clearly distinguish and control the behavior of each chip under test by setting different levels, thereby ensuring the accuracy of signal transmission. Two chips under test can receive control instructions at the same time, thereby improving configuration efficiency and shortening test preparation time.

[0087] In an optional embodiment, based on the first test result and the second test result, the audio test results of the first chip to be tested 1 and the second chip to be tested 2 are determined, including: performing a first stage test on the first chip to be tested 1 according to the first control mode and the second chip to be tested 2 according to the second control mode to obtain the first stage test result; if the first stage test result indicates that the first chip to be tested 1 and the second chip to be tested 2 pass the test, the first chip to be tested 1 is configured to the second control mode and the second chip to be tested 2 is configured to the first control mode; the first chip to be tested 1 in the second control mode and the second chip to be tested 2 in the first control mode shake hands; if the handshake is successful, the first chip to be tested 1 generates a parameter according to a preset pseudo-random number. The first chip under test 1 generates a third pseudo-random number sequence according to the preset pseudo-random number generation parameters, and sends the third pseudo-random number sequence to the second chip under test 2; the second chip under test 2 generates a fourth pseudo-random number sequence according to the preset pseudo-random number generation parameters, and sends the fourth pseudo-random number sequence to the first chip under test 1; the first chip under test 1 compares the third pseudo-random number sequence with the fourth pseudo-random number sequence to obtain a third test result, and the second chip under test 2 compares the fourth pseudo-random number sequence with the third pseudo-random number sequence to obtain a fourth test result; according to the third test result and the fourth test result, determine whether the second stage test of the first chip under test 1 and the second chip under test 2 passes; if the second stage test passes, determine that the first chip under test 1 and the second chip under test 2 are in a normal state.

[0088] In the first phase of the test, the first chip to be tested 1 is configured as a host mode, which means that it will be responsible for sending clock signals and controlling data transmission. The second chip to be tested 2 is configured as a slave mode, and it will passively receive the signal sent by the first chip to be tested 1. The first chip to be tested 1 and the second chip to be tested 2 run the test program according to preset conditions and perform a handshake process to ensure normal communication. If the handshake is successful, the first chip to be tested 1 and the second chip to be tested 2 will continue to generate and send pseudo-random number sequences for subsequent verification. After the test is completed, the debugging device 3 receives the test results of the first phase. If both the first chip to be tested 1 and the second chip to be tested 2 pass the test, it means that their functions are normal and the system will continue to enter the second phase of the test. If the test fails, the test process is terminated. The debugging device 3 stops supplying power to the first chip to be tested 1 and the second chip to be tested 2.

[0089] In the second phase test, the first chip under test 1 is configured as a slave mode, and the second chip under test 2 is configured as a master mode. This means that the second chip under test 2 is now responsible for sending the clock signal, and the first chip under test 1 is passively receiving it. A new handshake process is performed to ensure that the communication between the first chip under test 1 and the second chip under test 2 is normal under the new master-slave configuration. The first chip under test 1 generates a third pseudo-random number sequence according to the preset pseudo-random number generation parameters, and the second chip under test 2 also generates a fourth pseudo-random number sequence according to the same parameters. The first chip under test 1 sends the third pseudo-random number sequence to the second chip under test 2, and the second chip under test 2 sends the fourth pseudo-random number sequence to the first chip under test 1. The first chip under test 1 compares the fourth pseudo-random number sequence it receives with the third pseudo-random number sequence it generates, and obtains a third test result. The second chip under test 2 also compares the third pseudo-random number sequence it receives with the fourth pseudo-random number sequence it generates, and obtains a fourth test result. The debugging device 3 determines whether the second phase test of the first chip under test 1 and the second chip under test 2 passes according to the third test result and the fourth test result.

[0090] After completing the two-stage test, the debugging device 3 outputs a test report based on the test results to determine whether the audio controller functions of the first chip under test 1 and the second chip under test 2 are normal. If the functions are normal, both chips under test pass the test. If the functions are abnormal, the two chips under test need to be tested again to confirm whether the functions are normal.

[0091] For the chips that failed the test, retest them. Select a chip C0 with normal audio controller function, and perform the above functional test process on the first chip to be tested 1 and the second chip to be tested 2 respectively. When the test passes, the first chip to be tested 1 and the second chip to be tested 2 are judged to be normal. When the test fails, the first chip to be tested 1 and the second chip to be tested 2 are judged to be abnormal.

[0092] like Figure 3 As shown, the debugging device is ATE, the first chip to be tested is C1, and the second chip to be tested is C2. After C1, C2 and ATE are interconnected, ATE starts the I2S audio controller test, first setting GPIO_O1 to a high level, that is, setting C1 to the host mode, and setting GPIO_O2 to a low level, that is, setting C2 to the slave mode. ATE turns on the power supply of C1 and C2, and C1 and C2 start running.

[0093] C1 runs the I2S audio controller test program and first detects the level of GPIO_I. When GPIO_I is detected as high, the test program configures the I2S interface to host mode, and when GPIO_I is detected as low, the I2S interface is configured to slave mode. Currently, ATE's GPIO_O1 is high, so C1's test program configures C1's I2S interface to host mode. C2 runs the same I2S audio controller test program as C1. Currently, ATE's GPIO_O2 is low, so C2's test program configures C2's I2S interface to slave mode.

[0094] The test program of C1 accesses the I2S audio controller and configures the data sampling rate and data width. C2 executes the same process.

[0095] After the configuration is completed, the handshake process begins. The test programs of C1 and C2 access the I2S audio controller and continuously send out a specific data A1. When the receiving end receives 16 A1s in succession, the test program changes the sent data to A2, and the number of sent data is 16. When 8 A2s are received in succession, it means that the handshake between C1 and C2 is successful, and you can proceed to the next step to perform the pseudo-random data sending verification process. If the handshake process fails, the handshake process will be repeated. If the handshake process fails multiple times, it means that there is a problem in the test, and the error is reported to ATE through the GPIO_O interface. After receiving the error message, ATE will terminate the test process and determine that the functions of the two chips under test are abnormal. ATE turns off the power of the chip.

[0096] The test programs of C1 and C2 calculate a certain amount of data according to the preset data width and pseudo-random number generation parameters, and store the data in the memory. The data generated by C1 and C2 are exactly the same. The test programs of C1 and C2 send the pseudo-random sequence to the I2S audio controller through the internal bus through DMA or memory access, and the I2S audio controller sends the data in sequence. After the data is converted from parallel to serial, it is sent to the receiving end through I2S_SDOUT.

[0097] The receiving end of the I2S audio controller receives data through I2S_SDIN and performs serial-to-parallel conversion on the data. After receiving a certain amount of data, the I2S audio controller notifies the CPU to read the data.

[0098] After obtaining the received data, the test programs of C1 and C2 compare it with the pseudo-random sequence in the memory and make statistics on the comparison results.

[0099] When data reception is complete and verification is complete, the C1 and C2 test programs send the test results to the ATE device through GPIO_O. ATE receives the first-stage test results. If the test passes, it enters the second-stage test process. If the test fails, the test process is terminated.

[0100] At the beginning of the second phase of testing, ATE sets GPIO_O1 to low level, that is, sets C1 to slave mode, and sets GPIO_O2 to high level, that is, sets C2 to master mode. The subsequent test steps are the same as above, so they will not be repeated here.

[0101] After completing the two-stage test, ATE outputs a test report based on the test results to determine whether the I2S audio controller functions of C1 and C2 are normal. If the functions are normal, both chips under test pass the test. If the functions are abnormal, the two chips under test need to be tested again to confirm whether the functions are normal.

[0102] Furthermore, data mining can be performed on the test results, and the test data can be analyzed using machine learning algorithms to automatically identify potential problems or performance bottlenecks and provide improvement suggestions. Specifically, during the test process, it is necessary to collect all relevant test data of the first chip to be tested 1 and the second chip to be tested 2, including pseudo-random number sequences, data of the handshake process, and test results of each stage (first test results and second test results). These data are stored in a database for subsequent analysis and model training.

[0103] Perform statistical analysis on the test results to identify basic indicators such as the percentage of passed and failed tests, success rate, etc. By analyzing the test results, use machine learning algorithms to identify abnormal data points. For example, if a chip performs abnormally in a certain test, it can be quickly identified and marked. Extract features from the test results, such as test pass rate, test time at each stage, response time, etc., which will be used as input to the model.

[0104] According to the test results, a suitable machine learning algorithm is selected and the model is trained to predict the chip's performance and test results. Using the trained model, potential problems or performance bottlenecks can be automatically identified, and key factors affecting chip performance can be identified by analyzing different test phases and results. Once a problem is identified, improvement suggestions can be automatically generated, such as adjusting test parameters, optimizing control modes, or changing the method of pseudo-random number generation. By analyzing historical test data, the system can continuously optimize the test process and parameter configuration to ensure the effectiveness and accuracy of each test.

[0105] The audio controller test system provided by the embodiment of the present invention can effectively identify and eliminate potential problems and improve the systematicness and accuracy of the test by dividing the test into a first stage and a second stage. The control mode of the chip to be tested is dynamically adjusted according to the test results of the first stage, which enhances the adaptability and flexibility of the system and enables the test process to be optimized for different situations. By comparing the test results of different stages, possible problems can be more clearly identified and targeted troubleshooting can be performed. Through multiple rounds of data interaction and comparison, the performance of the chip can be comprehensively evaluated to ensure the functional integrity of the chip in different scenarios.

[0106] According to an embodiment of the present invention, an embodiment of a testing method for an audio controller is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0107] In this embodiment, a test method for an audio controller is provided, which can be used in the test system for the audio controller. Figure 4 is a flow chart of a method for testing an audio controller according to an embodiment of the present invention. Figure 4 As shown, the process includes the following steps:

[0108] Step S101 , controlling a first audio control interface of a first chip under test to connect with a second audio control interface of a second chip under test, so that the first chip under test and the second chip under test perform mutual testing and generate mutual testing results.

[0109] Connect the first audio control interface of the first chip to be tested with the second audio control interface of the second chip to be tested, so that the two chips can communicate and exchange data directly, laying the foundation for subsequent tests. Through the connection, the first chip to be tested and the second chip to be tested can send and receive audio data to each other, thereby performing mutual verification tests. In this process, the chips will run their respective test programs to ensure that they function normally in terms of audio data transmission and processing. Through mutual testing, the first chip to be tested and the second chip to be tested will generate their own test results as the output of the mutual test.

[0110] Step S102: obtaining a mutual test result between the first chip to be tested and the second chip to be tested, where the mutual test result includes a first test result and a second test result.

[0111] After the test is completed, the mutual test result between the first chip to be tested and the second chip to be tested is obtained, wherein the first test result is the test feedback from the first chip to be tested, and the second test result is the test feedback from the second chip to be tested.

[0112] Step S103: determining audio test results of the first chip to be tested and the second chip to be tested based on the first test result and the second test result.

[0113] A comprehensive analysis is performed based on the first test result and the second test result. Specifically, a series of pre-set standards are obtained, and the first test result and the second test result are analyzed based on the pre-set standards to obtain audio test results of the first chip to be tested and the second chip to be tested.

[0114] The audio controller test method provided by the embodiment of the present invention can comprehensively evaluate the mutual compatibility and cooperative working ability of two chips through mutual testing, thereby ensuring the reliability of the overall system performance. The process of obtaining the mutual test results can be carried out in real time, which helps to identify problems and make adjustments in a timely manner, thereby improving the response speed of the test. The inclusion of the first test result and the second test result provides a basis for two-way verification and enhances the reliability of the test results. By integrating mutual testing, repeated testing and unnecessary steps can be avoided, thereby improving the efficiency of the overall test process.

[0115] The embodiment of the present invention also provides a computer device for executing the above Figure 4 The test method of the audio controller is shown.

[0116] See also Figure 5 , Figure 5 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 5 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 5 A processor 10 is taken as an example.

[0117] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0118] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0119] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0120] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0121] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 5 The example of connecting through bus is taken in the following.

[0122] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0123] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0124] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0125] In the description of this specification, the description with reference to the terms "this embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0126] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0127] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0128] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0129] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A test system for an audio controller, characterized in that: The system comprises: A first chip to be tested, wherein the first chip to be tested comprises a first audio control interface; A second chip to be tested, wherein the second chip to be tested comprises a second audio control interface, and the first audio control interface is connected to the second audio control interface, so that the first chip to be tested and the second chip to be tested perform mutual testing and generate mutual testing results, wherein the mutual testing results comprise first test results and second test results; A debugging device comprises a first interface and a second interface, wherein the first interface is connected to the first chip to be tested, and the second interface is connected to the second chip to be tested; the debugging device is used to receive the first test result sent by the first chip to be tested through the first interface, receive the second test result sent by the second chip to be tested through the second interface, and determine the audio test results of the first chip to be tested and the second chip to be tested based on the first test result and the second test result.

2. The system according to claim 1, characterized in that The debugging device sends a first control mode to the first chip under test through the first interface, and sends a second control mode to the second chip under test through the second interface; the first control mode and the second control mode are master-slave control modes.

3. The system according to claim 2, characterized in that The first chip to be tested and the second chip to be tested perform mutual testing and generate mutual testing results, including: The first chip under test generates a first pseudo-random number sequence according to the first control mode, and sends the first pseudo-random number sequence to the second chip under test; The second chip under test generates a second pseudo-random number sequence according to the second control mode, and sends the second pseudo-random number sequence to the first chip under test; The first chip under test compares the first pseudo-random number sequence with the second pseudo-random number sequence to generate a first test result, and sends the first test result to the debugging device; The second chip under test compares the second pseudo-random number sequence with the first pseudo-random number sequence to generate a second test result, and sends the second test result to the debugging device.

4. The system according to claim 3, characterized in that The first chip under test generates a first pseudo-random number sequence according to the first control mode, including: Based on the connection between the first audio control interface and the second audio control interface, handshaking is performed on the first chip to be tested and the second chip to be tested; If the first chip under test shakes hands with the second chip under test successfully, the first chip under test generates the first pseudo-random number sequence according to preset pseudo-random number generation parameters and the first control mode.

5. The system according to claim 3, characterized in that The second chip under test generates a second pseudo-random number sequence according to the second control mode, including: Based on the connection between the first audio control interface and the second audio control interface, handshaking is performed on the first chip to be tested and the second chip to be tested; If the first chip under test and the second chip under test shake hands successfully, the second chip under test generates the second pseudo-random number sequence according to preset pseudo-random number generation parameters and the second control mode.

6. The system according to claim 4 or 5, characterized in that: The handshaking of the first chip to be tested and the second chip to be tested comprises: The first chip under test sends first preset data to the second chip under test at a preset number of times; The second chip under test sends the first preset data to the first chip under test according to the preset number of times; When it is determined that both the first chip under test and the second chip under test have received the first preset data, the first chip under test sends the second preset data to the second chip under test according to the preset number of times; the second chip under test sends the second preset data to the first chip under test according to the preset number of times.

7. The system according to claim 2, characterized in that The debugging device sends a first control mode to the first chip under test through the first interface, and sends a second control mode to the second chip under test through the second interface, including: The debugging device sets the first interface to a first level and the second interface to a second level, so that the first chip under test configures the first control mode according to the first level and the second chip under test configures the second control mode according to the second level.

8. The system according to claim 1, characterized in that The step of determining audio test results of the first chip to be tested and the second chip to be tested based on the first test result and the second test result includes: Perform a first-stage test on the first chip under test according to a first control mode and on the second chip under test according to a second control mode to obtain a first-stage test result; If the first stage test result indicates that the first chip under test and the second chip under test pass the test, the first chip under test is configured to the second control mode, and the second chip under test is configured to the first control mode; The first chip under test in the second control mode and the second chip under test in the first control mode perform handshake; If the handshake is successful, the first chip under test generates a third pseudo-random number sequence according to the preset pseudo-random number generation parameters, and sends the third pseudo-random number sequence to the second chip under test, and the second chip under test generates a fourth pseudo-random number sequence according to the preset pseudo-random number generation parameters, and sends the fourth pseudo-random number sequence to the first chip under test; The first chip under test compares the third pseudo-random number sequence with the fourth pseudo-random number sequence to obtain a third test result, and the second chip under test compares the fourth pseudo-random number sequence with the third pseudo-random number sequence to obtain a fourth test result; Determine whether the second stage test of the first chip to be tested and the second chip to be tested passes according to the third test result and the fourth test result; If the second stage test passes, it is determined that the first chip to be tested and the second chip to be tested are in a normal state.

9. A method for testing an audio controller, characterized in that: A test system for an audio controller according to any one of claims 1 to 8, wherein the method comprises: Controlling the first audio control interface of the first chip to be tested to connect with the second audio control interface of the second chip to be tested, so that the first chip to be tested and the second chip to be tested perform mutual testing and generate mutual testing results; Acquire the mutual test result between the first chip to be tested and the second chip to be tested, wherein the mutual test result includes a first test result and a second test result; Based on the first test result and the second test result, audio test results of the first chip under test and the second chip under test are determined.

10. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the test method of the audio controller according to claim 9 by executing the computer instructions.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the audio controller testing method according to claim 9.

12. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to cause a computer to execute the audio controller testing method according to claim 9.

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