A radar signal processing simulation platform and simulation method

Abstract

A radar signal processing simulation platform and simulation method. A radar signal processing simulation platform and simulation method capable of reducing signal interference and enhancing communication stability are provided. It includes a radar display and control workstation and a signal processing server connected in communication, and also includes a signal generation and transmission unit; the signal generation and transmission unit includes a situation solving unit, a signal generating unit, a microwave unit and a data transmission unit; the data transmission unit includes FPGA1; the situation solving unit includes DSP and FPGA2; the signal generating unit includes three DRFMs, denoted as DRFM1, DRFM2 and DRFM3; the synthesizer is used to synthesize the target signal and the clutter signal into an echo signal and input it into DRFM2, and DRFM2 then outputs the echo signal to FPGA2; the FPGA2 is used to send the radar signal and the echo signal to FPGA1, and the FPGA1 is used to send the radar signal and the echo signal to the signal processing server. The present invention can effectively reduce signal distortion.

Description

Technical Field

[0001] The present invention relates to the field of radar technology, and in particular to a radar signal processing simulation platform and a simulation method. Background Art

[0002] Whether it is military radar or civilian radar, signal processing plays a vital role in modern radar systems, which determines the overall performance of the radar. In order to facilitate the research or training of radar signal processing, radar simulation using simulation systems has become an important means.

[0003] Radar simulation systems are usually divided into three categories: (1) physical simulation, also known as physical simulation, refers to simulation based on physical models; (2) mathematical simulation, also known as computer simulation, refers to simulation based on digital models; (3) mathematical-physical simulation, also known as semi-physical simulation, refers to simulation that combines physical models and mathematical models. This type of simulation is the main method used in practical applications.

[0004] In mathematical-physical simulation technology, the key premise is how to generate radar signals, target signals and clutter signals that are close to the actual application environment. Since the simulation platform needs to generate radar signals, target signals, clutter signals and echo signals synthesized by target signals and clutter signals at the same time, how to effectively generate the above signals and avoid mutual interference is the key to the simulation platform. The focus of radar signal processing is to process and analyze the radar echo signal, so the performance of AD sampling of the echo intermediate frequency signal is crucial to the subsequent signal processing effect of the present invention. The purpose of the simulation platform is to enable users to deeply understand the characteristics of radar signals and radar signal processing algorithms, so how to display the results of the intermediate process, display the situation, and select the algorithm is also the key to the realization of the simulation platform.

[0005] Chinese patent CN112578346A discloses a broadband radar target echo signal simulation system and simulation method, which includes a main control machine, a signal processor and a radio frequency machine; the radio frequency machine includes an up-conversion module, a signal synthesis module and a down-conversion module. The up-conversion module first up-converts the target signal and the radar signal; then the target signal is sent to the signal synthesis module, the radar signal is sent to the complex electromagnetic environment simulation device to simulate the clutter, and the clutter is sent to the signal synthesis module; finally, the signal synthesis module synthesizes the target signal and the clutter signal, down-converts the frequency, and then inputs the signal acquisition module of the signal processor. The technical solution in this document has two defects: first, the clutter signal is generated through two-stage transmission of the signal generation module-up-conversion module-complex electromagnetic environment simulation device, and the risk of signal interference is high; second, there is no feedback verification design for the radar signal, and there is a risk of error and poor communication reliability.

[0006] Therefore, how to improve the fidelity and reliability of signal transmission has become a technical problem that needs to be solved urgently. Summary of the invention

[0007] In view of the above problems, the present invention provides a radar signal processing simulation platform and a simulation method which can reduce signal interference and enhance communication stability.

[0008] The technical solution of the present invention is:

[0009] A radar signal processing simulation platform includes a radar display and control workstation and a signal processing server connected in communication.

[0010] It also includes a signal generation and transmission unit; the signal generation and transmission unit includes a situation solving unit, a signal generating unit, a microwave unit and a data transmission unit;

[0011] The data transmission unit includes FPGA1;

[0012] The situation solving unit includes DSP and FPGA2;

[0013] The microwave unit includes a synthesizer;

[0014] The signal generating unit includes three DRFMs, denoted as DRFM1, DRFM2 and DRFM3;

[0015] The DSP is used to receive the working parameters from the radar display and control workstation, solve and send them to the FPGA2; the FPGA2 is used to send the radar parameters, target parameters and clutter parameters generated by the working parameters to DRFM1, DRFM2 and DRFM3 respectively;

[0016] The DRFM1 is used to generate a radar signal and feed it back to the FPGA2;

[0017] The DRFM2 is used to generate a target signal and input it into the synthesizer, and the DRFM3 is used to generate a clutter signal and input it into the synthesizer;

[0018] The synthesizer is used to synthesize the target signal and the clutter signal into an echo signal and input it into DRFM2, and DRFM2 then inputs the echo signal to FPGA2; the FPGA2 is used to send the radar signal and the echo signal to FPGA1, and the FPGA1 is used to send the radar signal and the echo signal to the signal processing server.

[0019] The microwave unit is also provided with an up-conversion module, which is used to receive the radar signal of the DRFM1 and perform up-conversion processing on it; the up-conversion module is connected with an SMA radio frequency interface.

[0020] The DRFM includes an FPGA, an EEPROM, an SRAM, a D / A converter, an A / D converter, and a clock generator;

[0021] The FPGA is used as the main processor of the DRFM, the EEPROM and SRAM are used for program and data storage, the D / A converter and A / D converter are used for digital-to-analog conversion and analog-to-digital conversion respectively, and the clock generator is used to generate a clock signal.

[0022] The A / D converter uses the ADS5500 chip; in the reference clock input circuit of the ADS5500 chip, an adjustable resistor Rt is connected in series between the first-level clock input terminal CLKP and the second-level clock input terminal CLKM of the ADS5500 chip.

[0023] The analog clock input circuit of the ADS5500 chip includes a transformer T1 and two bandpass filters;

[0024] The analog signal is input from the primary of T1, and is output from the secondary of T1 in two ways to the two bandpass filters respectively;

[0025] A bandpass filter includes a resistor R1, an inductor L1 and a capacitor C1. The inductor L1 and the capacitor C1 are connected in parallel and then connected in series with the resistor R1. The analog signal flows into the resistor R1 side of the bandpass filter and is then output to the INP port of the ADS5500 chip.

[0026] Another bandpass filter includes a resistor R2, an inductor L2 and a capacitor C2. The inductor L2 and the capacitor C2 are connected in parallel and then connected in series with the resistor R2. The analog signal flows into the resistor R2 side of the bandpass filter and is then output to the INM port of the ADS5500 chip.

[0027] A deburring filter is also connected in series between the two bandpass filters;

[0028] The deburring filter includes a resistor R3, a capacitor C3 and a resistor R4 which are connected in series in sequence, and R3 = R4.

[0029] The analog clock input circuit is also provided with a low-pass filter;

[0030] The low-pass filter includes capacitor C4, capacitor C5 and resistor R6. Capacitor C4 and capacitor C5 are connected in parallel and then connected in series with resistor R6. One end of the low-pass filter is connected to the center tap of the secondary of T1, and the other end is connected to the CM port of the ADS5500 chip.

[0031] A radar signal processing simulation method comprises the following steps:

[0032] 1) The radar display and control workstation defines the working parameters and sends them to the DSP of the situation solving unit;

[0033] 2) DSP calculates the working parameters and sends them to FPGA2;

[0034] 3) FPGA2 sends the radar parameters, target parameters, and clutter parameters in the working parameters to three DRFMs, denoted as DRFM1, DRFM2, and DRFM3; DRFM1 generates a radar signal and feeds it back to FPGA2; DRFM2 generates a target signal and inputs it into a synthesizer, and DRFM3 generates a clutter signal and inputs it into a synthesizer;

[0035] 4) The synthesizer synthesizes the target signal and the clutter signal into an echo signal and inputs it into DRFM2. DRFM2 samples and down-converts the echo signal and then inputs it into FPGA2;

[0036] 5) FPGA2 sends the radar parameters and echo signals, collectively referred to as signal data, to FPGA1, and FPGA1 sends the signal data to the signal processing server;

[0037] 6) The signal processing server processes the signal data and sends the processing results to the radar display and control workstation for display.

[0038] In step 6), the signal processing steps of the signal processing server are:

[0039] S1, read signal data;

[0040] S2, determine whether pulse compression processing is required, if yes, perform pulse compression processing; if no, directly enter S3;

[0041] S3, determine whether MTI processing is required, if yes, select the MTI order and perform MTI processing; if no, directly enter S4;

[0042] S4, determine whether MTD processing is required, if yes, select the MTD order and perform MTD processing; if no, directly enter S5;

[0043] S5. Select CFAR type and perform CFAR processing;

[0044] S6, dot formation;

[0045] S7, track correlation, the processing results are sent to the radar display and control workstation for display.

[0046] A radar signal processing simulation platform and simulation method of the present invention respectively sends the working parameters set by the host computer to three DRFMs, which are used to generate radar signals, target signals and clutter signals respectively. The three signals are independent of each other, without indirect transmission, and have strong anti-interference performance. At the same time, the simulation platform design also reduces the hardware complexity. The present invention also performs feedback verification design for radar signals, sends radar parameters to DRFM1 through FPGA2, and DRFM1 generates radar signals and feeds them to FPGA2 after sampling and down-conversion processing; this loop feedback can enhance the stability and fault tolerance of the communication system and ensure stable and reliable communication.

[0047] On the other hand, in the simulation platform of the present invention, the reference clock input circuit and the analog clock input circuit of the ADC in the DRFM are innovatively designed; the reference clock input circuit effectively improves the performance of the ADC clock input end by connecting an adjustable resistor to the chip; the analog clock input circuit adopts a dual-bandpass filter coupling and burr absorption circuit structure to achieve the removal of out-of-band signals. This structure has better amplitude and phase balance characteristics than traditional circuits, thereby improving the sampling accuracy of the signal and effectively reducing signal distortion. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a structural schematic diagram of the present invention,

[0049] Figure 2 It is a schematic diagram of the principle of the present invention.

[0050] Figure 3 is a principle block diagram of the data transmission unit in the present invention,

[0051] Figure 4 It is a principle block diagram of the situation solving unit in the present invention,

[0052] Figure 5 is a principle block diagram of the motherboard in the present invention,

[0053] Figure 6 is a principle block diagram of DRFM2 in an embodiment of the present invention,

[0054] Figure 7 is a schematic diagram of the structure of the ADS5500 chip in the present invention,

[0055] Figure 8 is a graph showing the relationship between the impedance and frequency of the ADC input pin in the present invention,

[0056] Fig. 9 is the reference clock input circuit of the ADC in the present invention,

[0057] Fig.10 It is the analog clock input circuit of ADC in the prior art.

[0058] Fig.11 is the analog clock input circuit of the ADC in the present invention,

[0059] Fig.12 is a schematic diagram of the center frequency and bandwidth of the bandpass filter in the present invention,

[0060] Fig.13 is a schematic diagram of the structure of the display control software in the present invention,

[0061] Fig.14 is a schematic diagram of the structure of a canceller in the prior art,

[0062] Fig.15 It is a flow chart of signal processing in the present invention. DETAILED DESCRIPTION

[0063] The following is combined with Figure 1-15 , further illustrating the present invention.

[0064] Relevant terms in the present invention: FPGA is field programmable gate array; DRFM is digital radio frequency module; DSP is digital signal processor; DDR is double rate synchronous dynamic random access memory; EEPROM is electrically erasable programmable read-only memory; SRAM is static random access memory; ADC is the abbreviation of A / D converter; MTI refers to moving target indication; MTD refers to moving target detection; CFAR refers to constant false alarm rate.

[0065] A radar signal processing simulation platform of the present invention comprises a radar display and control workstation and a signal processing server which are communicatively connected; the radar display and control workstation is used for battle situation setting and situation display; the signal processing server is used for receiving radar signal data and echo signal data, performing signal processing and feature analysis, and sending the processing results to the radar display and control workstation for display;

[0066] It also includes a signal generation and transmission unit; the signal generation and transmission unit includes a situation solving unit, a signal generation unit, a microwave unit and a data transmission unit;

[0067] The data transmission unit includes FPGA1 and DDR, and is also provided with an SFP+ interface and a PCIE interface; the DDR is used for data buffering, the SFP+ interface is used to receive radar signal data and echo signal data from the situation solving unit, and the PCIE interface is used to transmit data to the signal processing server;

[0068] The situation solving unit includes DSP and FPGA2; the situation solving unit is used to receive working parameters, solve the distance, posture, speed and other information of each simulation cycle according to the simulation beat, and send the solved parameters;

[0069] The microwave unit includes a synthesizer and a clock unit, and the clock unit is used to generate a clock signal;

[0070] The signal generation unit includes three DRFMs, denoted as DRFM1, DRFM2, and DRFM3;

[0071] DSP is used to receive the working parameters from the radar display and control workstation, solve and send them to FPGA2; FPGA2 is used to send the radar parameters, target parameters and clutter parameters generated by the working parameters to DRFM1, DRFM2 and DRFM3 respectively;

[0072] DRFM1 is used to generate radar signals and feed them back to FPGA2;

[0073] DRFM2 is used to generate the target signal and input it into the synthesizer, and DRFM3 is used to generate the clutter signal and input it into the synthesizer;

[0074] The synthesizer is used to synthesize the target signal and the clutter signal into an echo signal and input it into DRFM2. DRFM2, which receives the echo signal, then inputs the echo signal to FPGA2. FPGA2 is used to send the radar signal and the echo signal to FPGA1. FPGA1 is used to send the radar signal and the echo signal to the signal processing server.

[0075] Embodiment: The echo signal synthesized by the synthesizer is transmitted to FPGA2 via DRFM2. The principle block diagram of DRFM2 is shown in FIG. Figure 6 . The 200MHz clock signal generated by the microwave unit is sent to DRFM2. The 200MHz clock signal is used by the clock generator to generate the clock signal required for the operation of each chip of DRFM2 (including FPGA, EEPROM, SRAM, etc.). The FPGA of DRFM2 receives the target parameters sent by FPGA2 of the situation solving unit to generate the target signal. After the target signal is converted into an analog signal by the D / A converter, it is sent to the microwave unit through the SMA interface for synthesizing the echo signal. The 25±5MHz echo signal synthesized by the target signal and the clutter signal by the microwave unit is sent to the signal input matching circuit for coupling, and then sent to the A / D converter for sampling. The sampled echo signal is sent to the FPGA of DRFM2 for down-conversion to the echo baseband signal. The echo baseband signal is then sent to FPGA2 of the situation solving unit, and then transmitted to the signal processing server through FPGA1 for signal processing. The final processing result is displayed on the radar display and control workstation.

[0076] The situation solving unit, DRFM1, DRFM2, and DRFM3 are all installed on the motherboard, and the signal transmission is carried out through the motherboard. For the principle block diagram of the motherboard, see Figure 5The motherboard mainly includes: 1) power generation circuit, which is mainly used as the working power supply of each chip and provides +12V power supply for the microwave unit; 2) network interface circuit, which is used for communication between DSP and host computer; 3) optical fiber interface circuit, which is used to transmit the echo signal of the signal generation unit to the data transmission unit; 4) program download port, which is used for program download; 5) level conversion circuit, which is used for internal circuit level conversion; 6) microwave unit control interface, which is used to send the generated TTL level frequency control code to the microwave unit; 7) data interface circuit, which is used for data transmission between the situation solving unit and each DRFM; 8) status indication circuit, which is used to indicate the working status of the situation solving unit.

[0077] DRFM1 also has a built-in sampling module and a down-conversion module; the sampling module and the down-conversion module are used to sample and down-convert radar signals respectively.

[0078] The microwave unit is also provided with an up-conversion module, which is used to receive the radar signal of DRFM1 and perform up-conversion processing on it; the up-conversion module is connected to an SMA RF interface. The SMA RF interface is connected to an external interface via an RF cable for signal testing or as a signal source for other devices.

[0079] DRFM includes FPGA, EEPROM, SRAM, D / A converter, A / D converter and clock generator; FPGA is used as the main processor of DRFM, EEPROM and SRAM are used for program and data storage, D / A converter and A / D converter are used for digital-to-analog conversion and analog-to-digital conversion respectively, and clock generator is used to generate clock signal.

[0080] The A / D converter, or ADC, uses the ADS5500 chip. Figure 7 Among them, Timing Circuity is the timing circuit, CLKOUT is the clock output, S&H is the sample and hold, 14-bit pipeline ADC Core is the 14-bit pipeline ADC core, Digital Error Correction is the digital error correction, Output Control is the output control, Internal Reference is the internal reference, Control Logic is the control logic, and Serial Programming Register is the serial programming register.

[0081] Analysis of the impact of ADC clock jitter on A / D sampling:

[0082] ADC signal-to-noise ratio (SNR) ADC [dBc] is limited by three factors, namely quantization noise, thermal noise and clock jitter; the signal-to-noise ratio caused by the three is SNR QuantizationNoise 、SNR Thermal Noise 、SNR Jitter Quantization noise and thermal noise usually affect the signal-to-noise ratio at low input frequencies, while clock jitter affects the signal-to-noise ratio at high input frequencies. The calculation formula for the signal-to-noise ratio is

[0083]

[0084] The calculation formula for the signal-to-noise ratio caused by clock jitter is:

[0085] SNR Jitter =-20·log(2π·f in ·T Jirrer )

[0086] Among them, f in is the input frequency; T Jitter is the total clock jitter, which has two parts: external clock jitter T Jitter,ext and internal aperture jitter T Aperture_ADC ,Right now

[0087]

[0088] External clock jitter can be minimized by using a high-quality clock source and a bandpass filter at the clock input during sampling. Increasing the clock conversion rate can improve internal aperture jitter. As the input signal frequency increases, a poor clock jitter performance will reduce the signal-to-noise ratio of the entire system. ADC clock jitter is often described by aperture jitter and aperture instability, which have similar meanings. Aperture instability refers to the unstable change from sampling cycle to cycle during the ADC encoding process. It has three effects on the system. The first is to increase system noise; the second is to bring phase instability to the sampled signal itself; and the third is to bring mutual interference to the ADC encoding. In RF or IF sampling, low jitter of the ADC clock is very important because its A / D sampling has a similar analog mixing function, which is equivalent to multiplying the input signal with the sampling clock. And time domain multiplication is convolution in the frequency domain, which is equivalent to convolving the spectrum of the sampling clock with the spectrum of the input signal. Aperture instability manifests as broadband noise, and broadband noise will appear on the spectrum of the sampling clock. After sampling, the signal spectrum is folded around the sampling frequency, so this broadband noise raises the noise floor of the ADC output. Just like the requirements for the local oscillator in an analog mixer, in sampling systems that require very high dynamic range and very high input signal frequencies, the ADC clock must have very low jitter.

[0089] Analysis of the impact of phase noise on A / D sampling: Phase noise and clock jitter have slightly different impacts on A / D sampling, but the final impact is very similar. The main difference between them is that clock jitter is broadband noise, evenly distributed around the sampling clock frequency; while phase noise is non-evenly distributed, the closer to the main frequency, the greater the phase noise, and the farther from the main frequency, the smaller the phase noise. Just like clock jitter, the smaller the phase noise, the better.

[0090] Analysis of the impact of spurious-free dynamic range on A / D sampling: Although current high-performance A / D sampling chips can provide high resolution and low noise, designers may find it difficult to achieve the rated SNR performance on the data sheet. It may be even more difficult to achieve the best spurious-free dynamic range (SFDR), that is, to achieve a clean noise floor without spurs in the system signal chain. Spurious signals may originate from unreasonable circuits around the ADC, or they may be caused by external interference in a harsh working environment. Spurious-free dynamic range represents the minimum power signal that can be distinguished from a large interference signal. For current high-resolution, precision ADCs, SFDR is generally mainly composed of the dynamic range between the fundamental frequency and the second or third harmonic of the fundamental frequency. However, due to other factors, spurs may be generated and limit the performance of the system. These spurs can be divided into input frequency-related spurs and fixed frequency spurs. Input frequency-related spurs are related to harmonics or nonlinear characteristics.

[0091] ADC reference clock input circuit design:

[0092] As can be seen from the above, clock jitter has a crucial impact on sampling performance. For high input frequency sampling, a clock source with very low jitter is generally used, and ideally a 50% duty cycle should be provided. Therefore, in addition to having high requirements for the frequency conversion circuit that generates a 100MHz clock, the clock input circuit design of the A / D sampling chip is also very important.

[0093] The ADS5500 clock inputs can be driven with either a differential clock signal or a single-ended clock input with little or no performance difference between the two configurations. However, for best performance, it is preferred to drive the clock inputs differentially, thus reducing sensitivity to common-mode noise. In this case, it is preferred to use 0.01 μF capacitors to connect the two clock inputs to the differential input clock signal. The differential resistance and differential capacitance at the ADC inputs vary nonlinearly, Figure 8 shows the impedance Z across the ADC input pins in (Z in =R in / / C in ) changes. Therefore, when designing the ADC clock input circuit, the ADC input impedance must be considered. Figure 8Chinese: Differential Resistance—Differential Resistance, Differential Capacitance—Differential Capacitance.

[0094] In the present invention, in the reference clock input circuit of the ADS5500 chip, an adjustable resistor Rt is externally connected between the first-stage clock input terminal CLKP and the second-stage clock input terminal CLKM of the ADS5500 chip. The resistance value of the adjustable resistor Rt can be adjusted according to the clock frequency used in the actual circuit to improve the performance of the reference clock input terminal. Fig. 9 .

[0095] ADC analog clock input circuit design:

[0096] The use of a differential input topology at the analog input of the A / D sampling improves the common-mode rejection ratio and also results in a very high available input bandwidth, which is particularly important for high-frequency (IF) or undersampling applications. The ADS5500 requires that each analog input port (INP, INM) be externally biased around the common-mode level of the internal circuit (CM, pin 17). For full-scale differential inputs, each differential line of the input signal (pins 19 and 20) swings symmetrically between VCM+0.575V and VCM-0.575V. This means that each input is driven by a signal up to VCM±0.575V, so the maximum differential signal for each input is 1.15Vpp, and the total differential input signal swing is 2.3Vpp. The maximum swing is determined by two reference voltages: the top reference voltage (REFP, pin 29) and the bottom reference voltage (REFM, pin 30). The ADS5500 achieves optimal performance when the analog inputs are driven differentially. For the analog clock input circuit of the ADC in the prior art, see Fig.10 , where: AC Signal Source—AC signal source. The single-ended signal is fed into the primary winding of the RF transformer. Since the input signal must be biased toward the common-mode voltage of the internal circuit, the common-mode voltage (VCM) from the ADS5500 is connected to the center tap of the secondary winding. The ADS5500 chip manual also provides instructions on how to place R IN and C IN , to isolate the signal source from the switching inputs of the ADC, and implement a low-pass RC filter to limit the input noise in the ADC. Any mismatch between the differential lines of the inputs will result in performance degradation at high input frequencies, mainly characterized by the increase of even-order harmonics. In this case, special attention should be paid to maintain as much electrical symmetry as possible between the two inputs.

[0097] In the present invention, the analog clock input circuit of the ADS5500 chip includes a transformer T1 and two bandpass filters, see Fig.11; T1 uses MINI-AT224-1A high-frequency pulse transformer with a transformation ratio of 1:1, and its maximum pass frequency is 500MHz;

[0098] The analog signal is input from the primary of T1 and output from the secondary of T1 in two ways to two bandpass filters respectively;

[0099] The input-output relationship of a bandpass filter is:

[0100]

[0101] The amplitude ratio T of the output of the bandpass filter to its input is:

[0102]

[0103] Among them, V out is the filter output voltage, V in is the filter input voltage, j is a complex unit, ω is the angular frequency, L is the inductance, C is the capacitance, and R is the resistance.

[0104] The bandwidth of a bandpass filter is generally defined as the amplitude ratio of The difference between the upper and lower frequencies when T = 0.707, see Fig.12 . Where f0 is the center frequency, Δf 3dB That is, the upper and lower frequency difference when T = 0.707. Quality factor Q = f0 / Δf 3dB .

[0105] For example, if the input signal is 25±5MHz, f0=25MHz, Δf 3dB =10MHz. L=2.7nH、C=15nF。 Then according to the upper and lower frequency angular frequency ω 3dB formula:

[0106] or

[0107] R can be taken as 1Ω; where -L is the lower frequency of the bandwidth, and +L is the upper frequency of the bandwidth.

[0108] See also Fig.11, one bandpass filter includes a resistor R1, an inductor L1 and a capacitor C1. After the inductor L1 and the capacitor C1 are connected in parallel, they are connected in series with the resistor R1; the analog signal flows into the resistor R1 side of the bandpass filter and is then output to the INP port of the ADS5500 chip. Another bandpass filter includes a resistor R2, an inductor L2 and a capacitor C2. After the inductor L2 and the capacitor C2 are connected in parallel, they are connected in series with the resistor R2; the analog signal flows into the resistor R2 side of the bandpass filter and is then output to the INM port of the ADS5500 chip.

[0109] A deburring filter is also connected in series between the two bandpass filters to absorb sampling glitches and optimize input impedance; the deburring filter includes a resistor R3, a capacitor C3 and a resistor R4 connected in series in sequence, and R3 = R4, to ensure symmetrical absorption of the two input terminals of the ADC. R3 and R4 can take values ​​of 30 to 51Ω, and C3 can take values ​​of 22 to 33Pf, which can be adjusted according to actual conditions.

[0110] The analog clock input circuit is also provided with a low-pass filter, which is used as a circuit reference point between the transformer and the sampling chip; the low-pass filter includes capacitor C4, capacitor C5 and resistor R6, and capacitor C4 and capacitor C5 are connected in parallel and then connected in series with resistor R6; one end of the low-pass filter is connected to the center tap of the secondary of T1, and the other end is connected to the CM port of the ADS5500 chip.

[0111] The implementation results show that the A / D sampling circuit in this case has a high sampling accuracy for the echo signal, with very little signal distortion, which improves the reliability of the processing results of the subsequent signal processing algorithm.

[0112] The radar display and control workstation is equipped with display control software; the display control software includes parameter configuration software unit, situation display software unit, waveform monitoring software unit, data management software unit, interface communication software unit and system control software unit.

[0113] The parameter configuration unit includes radar parameter settings, target parameter settings, clutter parameter settings, signal processing parameter settings, etc. Radar parameter settings include: (1) various inter-pulse and intra-pulse waveform parameter settings, such as the frequency agility points of inter-pulse frequency agility signals, the number of pulse groups and frequency agility points of pulse group frequency agility signals, and the parameter settings of intra-pulse non-modulation, various linear frequency modulation and nonlinear frequency modulation signals, and various phase coded signals; (2) Radar working mode settings, such as whether the radar works in tracking state or scanning state (such as circular scanning, fan scanning, etc.); (3) Antenna parameter settings, such as antenna gain, sidelobe level, scanning speed and beam width, etc. Target parameter settings include: target azimuth and elevation position, target distance, heading, speed, radar cross-section (RCS), fluctuation characteristics (such as Swerling1~4 model, etc.), start and end time, etc. The clutter parameter settings include clutter azimuth, azimuth range, statistical model (such as lognormal distribution, Weibull distribution, K distribution, Rayleigh distribution, etc.), power spectrum model (such as Gaussian spectrum, full polar spectrum, Cauchy spectrum, etc.). The signal processing parameter settings include: (1) signal processing algorithm selection, such as pulse compression, MTI, etc.; (2) algorithm type selection, such as the order of MTI can be selected between 2 and 5, the order of MTD can be selected between 4, 8, 16, 32, 64, the type of CFAR, etc.

[0114] The situation display software unit and the waveform monitoring software unit include the following contents: radar track display; radar transmission signal I, Q orthogonal dual channel display; radar echo signal I, Q orthogonal dual channel display; radar transmission signal envelope display; radar echo signal envelope display; radar transmission signal spectrum display; radar echo signal spectrum display; pulse compression signal processing result display; MTI signal processing result display; MTD signal processing result display; CFAR signal processing result display; feature analysis signal processing result display, etc. The present invention has an intermediate data output interface in the key links of the above-mentioned process, such as matched filtering (pulse compression), clutter suppression, coherent accumulation, target detection, and feature analysis, for analysis of the intermediate processing process. At the same time, the present invention can store the data of the above-mentioned original signal and the output result in the signal processing server, which can be directly called when analysis is needed, greatly facilitating the algorithm development of scientific researchers.

[0115] A radar signal processing simulation method comprises the following steps:

[0116] 1) The radar display and control workstation defines the working parameters and sends them to the DSP of the situation solving unit;

[0117] 2) DSP calculates the working parameters and sends them to FPGA2;

[0118] 3) FPGA2 sends the radar parameters, target parameters, and clutter parameters in the working parameters to three DRFMs, denoted as DRFM1, DRFM2, and DRFM3; DRFM1 generates a radar signal and feeds it back to FPGA2; DRFM2 generates a target signal and inputs it into a synthesizer, and DRFM3 generates a clutter signal and inputs it into a synthesizer;

[0119] 4) The synthesizer synthesizes the target signal and the clutter signal into an echo signal and inputs it into DRFM2. DRFM2 that receives the echo signal samples and down-converts the echo signal and then inputs it into FPGA2;

[0120] 5) FPGA2 sends the radar parameters and echo signals, collectively referred to as signal data, to FPGA1, and FPGA1 sends the signal data to the signal processing server;

[0121] 6) The signal processing server processes the signal data and sends the processing results to the radar display and control workstation for display.

[0122] In step 3), DRFM1 generates a radar signal, which is sampled and down-converted before being fed back to FPGA 2. This loop structure is used to perform feedback verification on radar signal data and improve the stability of the communication system.

[0123] In step 6), the signal processing steps of the signal processing server are:

[0124] S1, read signal data;

[0125] S2, judging whether pulse compression processing is required according to whether the signal data is a pulse compression signal, if so, performing pulse compression processing; if not, directly entering S3;

[0126] S3, determine whether MTI processing is required, if yes, select the MTI order and perform MTI processing; if no, directly enter S4;

[0127] S4, determine whether MTD processing is required, if yes, select the MTD order and perform MTD processing; if no, directly enter S5;

[0128] S5. Select CFAR type and perform CFAR processing;

[0129] S6, forming a dot trace, i.e. forming a dot trace according to information such as the distance, direction, and speed of the detection signal;

[0130] S7. The track-related points that are about to be dispersed are clustered according to distance, azimuth, etc. The new points formed after the point clustering form the track, and the processing results are sent to the radar display and control workstation for display.

[0131] It is generally believed that there is a contradiction between the range and distance resolution of simple pulse radar. Radar transmission energy E = Pτ, where P is the transmission power and τ is the pulse width. If the radar detection distance is long, a larger transmission energy is required. There are two ways to increase the transmission energy: (1) increase the transmission power, but this is limited by the power tolerance of the radar transmitting device; (2) increase the pulse width, but a larger pulse width reduces the radar range resolution. Because the radar range resolution δ = c / 2B, where c is the speed of light, which is a constant, the radar range resolution δ is inversely proportional to the bandwidth B. The larger B is, the smaller δ is, that is, the higher the radar range resolution. For simple pulse radar, B = 1 / τ. Therefore, according to the above radar range resolution formula, it can be seen that the range resolution of simple pulse radar δ = cτ / 2. It can be seen that although increasing the pulse width will increase the radar range, it will also reduce the range resolution.

[0132] Pulse compression technology has solved the contradiction between the range and distance resolution of conventional pulse radars: when the radar transmits, it transmits wide pulses to increase the average power of the transmission and ensure a large range; when receiving, it receives narrow pulses through the pulse compression network to ensure high distance resolution. Therefore, a pulse compression radar should be a matched filter system, that is, it requires the transmitted signal to have a nonlinear phase spectrum, and at the same time, a compression network that matches the spectrum of the transmitted signal is set in the receiver to make the wide pulse transmission signal (that is, the echo signal at the input end of the receiver) become a narrow pulse to maintain good distance resolution. According to the intra-pulse modulation method, pulse compression radar signals are mainly divided into three types: frequency-modulated pulse compression signals, phase-coded pulse compression signals, and mixed modulation pulse compression signals. General frequency-modulated pulse compression signals include linear frequency modulation and various nonlinear frequency modulation signals (such as triangle wave frequency modulation, sine wave frequency modulation, etc.), and phase-coded pulse compression signals include two-phase encoding, four-phase encoding, etc.

[0133] When processing radar signals, we must first know whether it is a simple pulse radar or a pulse compression radar. If it is a simple pulse radar, matched filtering is not required, but if it is a pulse compression radar, matched filtering must be performed first.

[0134] MTI is a frequency domain filter, equivalent to a high-pass filter, used to suppress fixed targets and slow clutter. For a single-cancellation MTI filter, the echo of the first transmitted pulse is subtracted from the echo of the second transmitted pulse to remove fixed targets and slow clutter, while retaining the information of moving targets. The waveform of amplitude vibration can be seen through the video display. MTD is a bandpass filter group, which can be implemented with an FIR group, but is generally implemented with FFT, that is, FFT processing is performed on the same distance units of echo signals of different pulse groups. The output of MTI is a high-pass filtered continuous spectrum after suppressing the spectrum near zero frequency, and the spectrum range is f L ~PRF, fL is the cutoff frequency at the left end of the high-pass filter; while the output of MTD is to divide the spectrum between 0 and PRF into N (N is the number of pulses processed at one time, and the size is determined by factors such as beam width and antenna scanning speed) equally spaced discrete spectrum lines 0, PRF / N, 2*PRF / N, …, (N-1)*PRF / N, the purpose of which is to facilitate the suppression of ground clutter of moving platforms that are not located near the 0 frequency. This is the most essential difference between MTI and MTD. In addition, MTD also adds one or more motion clutter maps in its implementation, so that the radar can detect large targets flying tangentially when the platform is moving; and MTD also achieves long-term storage and delay by using digital signal processing, which greatly increases the linear dynamic range of signal processing compared to MTI. The two are completely different in implementation. It can be said that MTD is a more advanced moving target detection technology than MTI, and can completely replace MTI, but due to the simple implementation of MTI, it is still widely used in existing ground radars.

[0135] The selection of algorithm type is explained by taking the MTI order as an example. The clutter canceller is one of the earliest and most commonly used MTI filters. According to the number of cancellations, it can be divided into two-pulse cancellation (also known as primary cancellation), three-pulse cancellation (also known as secondary cancellation) and multi-pulse cancellation. The commonly used ones are generally five-pulse cancellation (also known as fourth-order cancellation) and below. The structure of the canceller in the prior art can be found in Fig.13 The output y of the canceller can be expressed as:

[0136]

[0137] K is the number of cancellers, x is the input, n is the number of pulses, ωi is the coefficient of the canceller, and

[0138]

[0139] That is, for the first cancellation (K=1), [ω0,ω1]=[1,-1]; for the second cancellation (K=2), [ω0,ω1,ω2]=[1,-2,1]; for the third cancellation (K=3), [ω0,ω1,ω2,ω3]=[1,-3,3,1]; for the fourth cancellation (K=4), [ω0,ω1,ω2,ω3,ω4]=[1,-4,6,-4,1]. Therefore, by selecting different MTI orders, we can select different MTI processing algorithms and compare their clutter suppression effects, thereby deepening our understanding of the MTI algorithm.

[0140] Therefore, when processing radar signals, the MTI algorithm or the MTD algorithm can be selected according to needs, or both algorithms can be used, or neither of them can be used, and the sampled echo signal (applicable to simple pulse radar) or the matched filtered signal (applicable to pulse compression radar) can directly enter the CFAR signal processing link.

[0141] CFAR is to detect the above output and judge whether the target exists. CFAR detection is a set of technologies dedicated to providing predictable detection and false alarm in actual interference environment, also known as adaptive threshold detection. In practical applications, according to various interference environments, many CFAR methods have been developed, such as unit average CFAR (CA-CFAR), various improved unit average CFAR (such as unit average small CFAR, i.e. SOCA-CFAR, unit average large CFAR, i.e. GOCA-CFAR), ordered statistical CFAR (OS-CFAR), adaptive CFAR, etc. You can choose according to your needs.

[0142] Regarding the contents disclosed in this case, there are a few points that need to be explained:

[0143] (1) The implementation methods disclosed in this case are only examples. Technical solutions implemented by other equivalent alternative technical means fall within the protection scope of this case;

[0144] (2) In the absence of conflict, the technical features disclosed in this case can be combined with each other to obtain new embodiments;

[0145] The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. Any modifications and changes made to certain technical features therein by those skilled in the art based on the contents disclosed in this case should all be within the protection scope of this case.

Claims

1. A radar signal processing simulation platform, comprising a radar display and control workstation and a signal processing server connected in communication, characterized in that: It also includes a signal generation and transmission unit; the signal generation and transmission unit includes a situation solving unit, a signal generating unit, a microwave unit and a data transmission unit; The data transmission unit includes FPGA1; The situation solving unit includes DSP and FPGA2; The microwave unit includes a synthesizer; The signal generating unit includes three DRFMs, denoted as DRFM1, DRFM2 and DRFM3; The DSP is used to receive the working parameters from the radar display and control workstation, solve and send them to the FPGA2; the FPGA2 is used to send the radar parameters, target parameters and clutter parameters generated by the working parameters to DRFM1, DRFM2 and DRFM3 respectively; The DRFM1 is used to generate a radar signal and feed it back to the FPGA2; The DRFM2 is used to generate a target signal and input it into the synthesizer, and the DRFM3 is used to generate a clutter signal and input it into the synthesizer; The synthesizer is used to synthesize the target signal and the clutter signal into an echo signal and input it to DRFM2, and DRFM2 then outputs the echo signal to FPGA2; the FPGA2 is used to send the radar signal and the echo signal to FPGA1, and the FPGA1 is used to send the radar signal and the echo signal to the signal processing server; The DRFM includes an FPGA, an EEPROM, an SRAM, a D / A converter, an A / D converter, and a clock generator; The FPGA is used as the main processor of the DRFM, the EEPROM and SRAM are used for program and data storage, the D / A converter and A / D converter are used for digital-to-analog conversion and analog-to-digital conversion respectively, and the clock generator is used to generate a clock signal.

2. A radar signal processing simulation platform according to claim 1, characterized in that: The microwave unit is also provided with an up-conversion module, which is used to receive the radar signal of the DRFM1 and perform up-conversion processing on it; the up-conversion module is connected with an SMA radio frequency interface.

3. A radar signal processing simulation platform according to claim 1, characterized in that: The A / D converter uses the ADS5500 chip; in the reference clock input circuit of the ADS5500 chip, an adjustable resistor Rt is connected in series between the first-level clock input terminal CLKP and the second-level clock input terminal CLKM of the ADS5500 chip.

4. A radar signal processing simulation platform according to claim 3, characterized in that: The analog clock input circuit of the ADS5500 chip includes a transformer T1 and two bandpass filters; The analog signal is input from the primary of T1, and is output from the secondary of T1 in two ways to the two bandpass filters respectively; A bandpass filter includes a resistor R1, an inductor L1 and a capacitor C1. The inductor L1 and the capacitor C1 are connected in parallel and then connected in series with the resistor R1. The analog signal flows into the resistor R1 side of the bandpass filter and is then output to the INP port of the ADS5500 chip. Another bandpass filter includes a resistor R2, an inductor L2 and a capacitor C2. The inductor L2 and the capacitor C2 are connected in parallel and then connected in series with the resistor R2. The analog signal flows into the resistor R2 side of the bandpass filter and is then output to the INM port of the ADS5500 chip.

5. A radar signal processing simulation platform according to claim 4, characterized in that: A deburring filter is also connected in series between the two bandpass filters; The deburring filter includes a resistor R3, a capacitor C3 and a resistor R4 which are connected in series in sequence, and R3=R4.

6. A radar signal processing simulation platform according to claim 5, characterized in that: The analog clock input circuit is also provided with a low-pass filter; The low-pass filter includes capacitor C4, capacitor C5 and resistor R6. Capacitor C4 and capacitor C5 are connected in parallel and then connected in series with resistor R6. One end of the low-pass filter is connected to the center tap of the secondary of T1, and the other end is connected to the CM port of the ADS5500 chip.

7. A radar signal processing simulation method, characterized in that: The following steps are involved: 1) The radar display and control workstation defines the working parameters and sends them to the DSP of the situation solving unit; 2) DSP calculates the working parameters and sends them to FPGA2; 3) FPGA2 sends the radar parameters, target parameters, and clutter parameters in the working parameters to three DRFMs, denoted as DRFM1, DRFM2, and DRFM3; DRFM1 generates a radar signal and feeds it back to FPGA2; DRFM2 generates a target signal and inputs it into the synthesizer, and DRFM3 generates a clutter signal and inputs it into the synthesizer; 4) The synthesizer synthesizes the target signal and the clutter signal into an echo signal and inputs it into DRFM2. DRFM2 samples and down-converts the echo signal and then inputs it into FPGA2. 5) FPGA2 sends radar parameters and echo signals, collectively referred to as signal data, to FPGA1, and FPGA1 sends the signal data to the signal processing server; 6) The signal processing server processes the signal data and sends the processing results to the radar display and control workstation for display; In step 6), the signal processing steps of the signal processing server are: S1, read signal data; S2, determining whether pulse compression processing is required, and if so, performing pulse compression processing; If not, go directly to S3; S3, determining whether MTI processing is required, if so, selecting the MTI order and performing MTI processing; If not, go directly to S4; S4, determine whether MTD processing is required, if yes, select the MTD order and perform MTD processing; if no, directly enter S5; S5. Select CFAR type and perform CFAR processing; S6, dot formation; S7, track correlation, the processing results are sent to the radar display and control workstation for display.

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