Semiconductor memory device

Abstract

A semiconductor memory device includes: a bit line including a metal and extending in a first direction on a substrate; a channel structure on the bit line including a first channel pattern extending in a second direction, and a second channel pattern spaced apart from the first channel pattern in the first direction and extending in the second direction; a liner film between the bit line channel structures and including the metal; a first word line between the first channel pattern and the second channel pattern, the first word line extending in the second direction; a second word line between the first channel pattern and the second channel pattern and extending in a second direction, the second word line being spaced apart from the first word line in the first direction; and first and second capacitors on the first and second channel patterns, respectively, and connected to the first and second channel patterns.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a vertical channel transistor (VCT). Background Art

[0002] There is a need to increase the integration level of semiconductor memory devices to meet the excellent performance and low price required by consumers. In the case of semiconductor memory devices, since the integration level is an important factor in determining the price of the product, it is particularly necessary to increase the integration level.

[0003] In the case of two-dimensional or planar semiconductor memory devices, the integration level is mainly determined by the area occupied by the unit memory cell and is therefore greatly affected by the level of fine pattern formation technology. However, because ultra-expensive devices are required to miniaturize the pattern, the integration level of two-dimensional semiconductor memory devices is increasing, but still limited. Therefore, a semiconductor memory device including a vertical channel transistor having a channel extending in a vertical direction is proposed. Summary of the invention

[0004] Embodiments of the inventive concept provide semiconductor memory devices having improved integration and electrical characteristics.

[0005] However, aspects of the inventive concept are not limited to those set forth herein. The above and other aspects of the inventive concept will become more apparent to those skilled in the art to which the inventive concept pertains by referring to the detailed description given below.

[0006] An embodiment of the present invention provides a semiconductor memory device, comprising: a bit line, comprising a metal and extending along a first direction on a substrate; a channel structure on the bit line, the channel structure comprising a first channel pattern extending along a second direction, and the channel structure comprising a second channel pattern spaced apart from the first channel pattern along the first direction and extending along the second direction; a liner film between the bit line and the channel structure, the liner film comprising the metal; a first word line, between the first channel pattern and the second channel pattern, the first word line extending along the second direction; a second word line, between the first channel pattern and the second channel pattern, the second word line extending along the second direction, the second word line spaced apart from the first word line in the first direction; and a first capacitor and a second capacitor, respectively on the first channel pattern and the second channel pattern, and respectively connected to the first channel pattern and the second channel pattern.

[0007] An embodiment of the present inventive concept also provides a semiconductor memory device, comprising: a bit line extending along a first direction on a substrate; a protruding insulating pattern on the substrate, the protruding insulating pattern comprising a channel groove exposing the bit line, the protruding insulating pattern extending in a second direction intersecting the first direction; a liner film on an upper surface of the exposed bit line; a channel structure extending along a lower surface and a side surface of the channel groove, the channel structure comprising a first channel pattern and a second channel pattern spaced apart from the first channel pattern in the first direction; a first word line and a second word line on the channel structure, the first word line and the second word line being spaced apart from each other in the first direction and each extending in the second direction; a gate insulating film between the first channel pattern and the first word line, and the gate insulating film between the second channel pattern and the second word line; and a first capacitor and a second capacitor, respectively on the first channel pattern and the second channel pattern, the first capacitor and the second capacitor being connected to the first channel pattern and the second channel pattern, respectively.

[0008] An embodiment of the present inventive concept also provides a semiconductor memory device, which includes: a peripheral gate structure on a substrate; a bit line, which is on the peripheral gate structure and extends in a first direction; a protruding insulating pattern on the substrate, the protruding insulating pattern includes a channel trench exposing the bit line, and the protruding insulating pattern extends in a second direction intersecting the first direction; a channel structure in the channel trench, the channel structure includes a horizontal portion and a first vertical portion and a second vertical portion protruding from the horizontal portion; a liner film between the bit line and the horizontal portion of the channel structure, the liner film includes a nitride; a first word line on the channel structure, the first word line extends in the second direction; a second word line on the channel structure, the second word line extends in the second direction, and the second word line is spaced apart from the first word line in the first direction; a gate insulating film, between the first vertical portion of the channel structure and the first word line and between the second vertical portion of the channel structure and the second word line; a gate separation pattern on the horizontal portion of the channel structure, the gate separation pattern separates the first word line and the second word line; and a first capacitor and a second capacitor on the channel structure, the first capacitor and the second capacitor being connected to the first vertical portion of the channel structure and the second vertical portion of the channel structure, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features of the present disclosure will become more apparent in light of the following description of example embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 are layout diagrams for explaining a semiconductor memory device according to some example embodiments.

[0011] Figure 2 It is along Figure 1 Cross-sectional views taken along lines AA and BB.

[0012] Figure 3 It is along Figure 1 Cross-sectional view taken at CC and DD.

[0013] Figure 4 yes Figure 2 An enlarged view of part P.

[0014] Figure 5 , Figure 6 , Figure 7 and Figure 8 They are Figure 4 A magnified view of part Q.

[0015] Fig. 9 and Fig.10 yes Figure 2 An enlarged view of part P.

[0016] Fig.11 2 is a diagram for explaining a semiconductor memory device according to some example embodiments.

[0017] Fig.12 2 is a diagram for explaining a semiconductor memory device according to some example embodiments.

[0018] Fig.13 , Fig.14 , Fig.15 , Fig.16 and Fig.17 2 is a diagram for explaining a semiconductor memory device according to some example embodiments.

[0019] Fig.18 , Fig.19 and Fig. 20 2 is a diagram for explaining a semiconductor memory device according to some example embodiments.

[0020] Fig.21 , Fig. 22 , Fig.23 and Fig.24 2 is a diagram for explaining a semiconductor memory device according to some example embodiments.

[0021] Fig.25 , Fig.26 , Fig. 27 , Fig.28 , Fig.29 , Fig.30 , Fig.31 , Fig.32 , Fig.33 , Fig.34 , Fig.35 , Fig.36 , Fig.37 , Fig.38 and Fig.39are diagrams for explaining a method of manufacturing a semiconductor memory device according to some example embodiments.

[0022] Fig.40 , Fig.41 , Fig.42 , Fig.43 , Fig.44 and Fig.45 are diagrams for explaining a method of manufacturing a semiconductor memory device according to some example embodiments. DETAILED DESCRIPTION

[0023] When used in this specification, the term "at least one of A, B, and C" and similar language (e.g., "at least one selected from the group consisting of A, B, and C") may be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C, such as, for example, ABC, AB, BC, and AC.

[0024] Figure 1 are layout diagrams for explaining a semiconductor memory device according to some example embodiments. Figure 2 It is along Figure 1 Cross-sectional views taken along lines AA and BB. Figure 3 It is along Figure 1 Cross-sectional view taken at CC and DD. Figure 4 yes Figure 2 An enlarged view of part P. Figures 5 to 8 They are Figure 4 A magnified view of part Q. Fig. 9 and Fig.10 yes Figure 2 An enlarged view of part P.

[0025] A semiconductor memory device according to some example embodiments of the inventive concepts may include a memory cell including a vertical channel transistor (VCT).

[0026] Reference Figures 1 to 12 , a semiconductor memory device according to some example embodiments may include a peripheral gate structure PG, a bit line BL, word lines WL1 and WL2 , a channel structure AP_ST, a liner film 174 , a protruding insulating pattern 175 , and a data storage pattern DSP.

[0027] The substrate 100 may be a silicon substrate, or may include other materials such as, but not limited to, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0028] The peripheral gate structure PG may be disposed on the substrate 100. The substrate 100 may include a cell array region and a peripheral circuit region. The peripheral gate structure PG may be disposed above the cell array region and the peripheral circuit region. In other words, a portion of the peripheral gate structure PG is disposed in the cell array region of the substrate 100, and the rest of the peripheral gate structure PG may be disposed in the peripheral circuit region of the substrate 100.

[0029] The peripheral gate structure PG may be included in a sensing transistor, a transfer transistor, a driving transistor, etc. Types of transistors provided in the cell array region and the peripheral circuit region may vary depending on a design layout of a semiconductor memory device.

[0030] The peripheral gate structure PG may include a peripheral gate insulating film 215, a peripheral lower conductive pattern 223, and a peripheral upper conductive pattern 225. The peripheral gate insulating film 215 may include a silicon oxide film, a silicon oxynitride film, a high dielectric constant insulating film having a dielectric constant higher than that of the silicon oxide film, or a combination thereof. The high dielectric constant insulating film may include, for example, but not limited to, at least one of a metal oxide, a metal oxynitride, a metal silicon oxide, and a metal silicon oxynitride.

[0031] The peripheral lower conductive pattern 223 and the peripheral upper conductive pattern 225 may each include a conductive material. For example, the peripheral lower conductive pattern 223 and the peripheral upper conductive pattern 225 may each include at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material (2D material), a metal, and a metal alloy. Although the peripheral gate structure PG is shown as including a plurality of conductive patterns, some example embodiments are not limited thereto.

[0032] In a semiconductor device according to some example embodiments, the two-dimensional material may be a metal material and / or a semiconductor material. The 2D material may include a 2D allotrope or a 2D compound, and may include, but is not limited to, graphene, molybdenum disulfide (MoS 2 ), Molybdenum diselenide (MoSe 2 ), tungsten diselenide (WSe 2 ) and tungsten disulfide (WS 2 Because the above-mentioned 2D materials are listed only as examples, the 2D materials that may be included in the semiconductor memory device of some example embodiments are not limited to the above-mentioned materials.

[0033] The first lower peripheral insulating film 227 and the second lower peripheral insulating film 228 are disposed on the substrate 100. The first lower peripheral insulating film 227 and the second lower peripheral insulating film 228 may each be made of an insulating material.

[0034] The first peripheral wiring 241a and the peripheral contact plug 241b may be disposed in the first peripheral lower insulating film 227 and the second peripheral lower insulating film 228. Although the first peripheral wiring 241a and the peripheral contact plug 241b are shown as being different films, some example embodiments are not limited thereto. The boundary between the first peripheral wiring 241a and the peripheral contact plug 241b may be indistinguishable. The first peripheral wiring 241a and the peripheral contact plug 241b each include a conductive material.

[0035] The first and second peripheral upper insulating films 261 and 262 may be disposed on the first peripheral wiring 241a and the peripheral contact plug 241b. The first and second peripheral upper insulating films 261 and 262 may each be made of an insulating material.

[0036] The second peripheral wiring 243 and the peripheral via plug 242 are provided on the first peripheral wiring 241a. The peripheral via plug 242 may be provided in the first upper peripheral insulating film 261. The second peripheral wiring 243 may be provided in the second upper peripheral insulating film 262.

[0037] The second peripheral wiring 243 and the peripheral via plug 242 may be connected to the first peripheral wiring 241a. The peripheral via plug 242 may connect the first peripheral wiring 241a and the second peripheral wiring 243. The second peripheral wiring 243 and the peripheral via plug 242 each include a conductive material. Although the second peripheral wiring 243 and the peripheral via plug 242 are shown as being different films from each other, some example embodiments are not limited thereto. The boundary between the second peripheral wiring 243 and the peripheral via plug 242 may be indistinguishable.

[0038] The third, fourth, and fifth peripheral upper insulating films 263, 264, and 265 may be sequentially disposed on the second peripheral wiring 243. The third, fourth, and fifth peripheral upper insulating films 263, 264, and 265 may each be made of an insulating material.

[0039] The fourth peripheral upper insulating film 264 may be made of an insulating material different from the insulating materials of the third peripheral upper insulating film 263 and the fifth peripheral upper insulating film 265. For example, although the fourth peripheral upper insulating film 264 may be made of an oxide-based insulating material, and the third peripheral upper insulating film 263 and the fifth peripheral upper insulating film 265 may be made of a nitride-based insulating material, other example embodiments are not limited thereto.

[0040] The cell connection plug 244 may be provided in the third peripheral upper insulating film 263, the fourth peripheral upper insulating film 264, and the fifth peripheral upper insulating film 265. The cell connection plug 244 may be connected to the second peripheral wiring 243. The cell connection plug 244 includes a conductive material. Unlike the illustrated example, a peripheral upper insulating film made of a single film may be provided in the cell connection plug 244.

[0041] The bit line BL is disposed on the peripheral gate structure PG. For example, the bit line BL may be disposed on the fifth peripheral upper insulating film 265. For example, the bit line BL may contact the fifth peripheral upper insulating film 265.

[0042] The bit lines BL may extend longer in the second direction D2. Adjacent bit lines BL may be spaced apart in the first direction D1. The bit lines BL include long sidewalls extending in the second direction D2 and short sidewalls extending in the first direction D1.

[0043] Although not shown, each bit line BL may extend from the cell array region to the peripheral circuit region. An end portion of each bit line BL may be disposed on the peripheral circuit region of the substrate 100.

[0044] Each bit line BL may be disposed on the cell connection plug 244. Each bit line BL may be connected to the cell connection plug 244. Each bit line BL may include, for example, at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbon nitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material, a metal, and a metal alloy. Although each bit line BL is illustrated as a single film, some example embodiments are not limited thereto.

[0045] The cell lower insulating film 171 may be disposed on the fifth peripheral upper insulating film 265. The cell lower insulating film 171 is disposed between the bit lines BL spaced apart in the first direction D1. The cell lower insulating film 171 may be made of an insulating material.

[0046] The protruding insulating pattern 175 is disposed on the bit line BL and the lower cell insulating film 171. The lower cell etch stop film 173 may be disposed between the protruding insulating pattern 175 and the lower cell insulating film 171. The protruding insulating pattern 175 and the lower cell etch stop film 173 may each be made of an insulating material. The lower cell etch stop film 173 may include a material having an etching selectivity relative to the protruding insulating pattern 175. For example, the protruding insulating pattern 175 may be made of an oxide-based insulating material, but is not limited thereto. Unlike the illustrated example, the lower cell etch stop film 173 may not be disposed between the protruding insulating pattern 175 and the lower cell insulating film 171.

[0047] The protruding insulating pattern 175 may include a plurality of channel trenches CH_T. Each channel trench CH_T may extend long in the first direction D1. Adjacent channel trenches CH_T may be spaced apart in the second direction D2.

[0048] Each channel trench CH_T crosses the bit line BL. One channel trench CH_T may expose a plurality of bit lines BL adjacent in the first direction D1.

[0049] The bottom surface of each channel trench CH_T may be defined by the bit line BL and the lower cell insulating film 171. The sidewall of each channel trench CH_T may be defined by the protruding insulating pattern 175 and the lower cell etch stop film 173. At least a portion of the sidewall of the channel trench CH_T may be a sidewall 175SW of the protruding insulating pattern. When the lower cell etch stop film 173 is not provided, the sidewall of each channel trench CH_T may be defined by the protruding insulating pattern 175.

[0050] The liner film 174 may be disposed on the upper surface BL_US of the bit line BL. The liner film 174 may be in contact with the upper surface BL_US of the bit line BL. The liner film 174 may extend in the second direction D2 along the upper surface BL_US of the bit line BL. The liner film 174 may be disposed in the channel trench CH_T. The liner film 174 may be disposed between the bit line BL and a horizontal portion AP_STH of a channel structure AP_ST to be described later. Here, the upper surface BL_US of the bit line BL is a surface on which a channel structure AP_ST to be described later is formed.

[0051] The liner film 174 and the lower unit etch stop film 173 may completely cover the upper surface BL_US of the bit line BL. Specifically, the bit line BL may include a first portion BL1 overlapping the protruding insulating pattern 175 along the third direction D3 and a second portion BL2 other than the first portion BL1. The lower unit etch stop film 173 may be disposed on the first portion BL1 of the bit line BL. The liner film 174 may be disposed on the second portion BL2 of the bit line BL.

[0052] The liner film 174 may include a metal nitride. When the bit line BL includes, for example, a first metal element (eg, a first element), the liner film 174 may include a metal nitride including the first metal element (eg, nitrogen as a second element).

[0053] exist Figure 5 In the embodiment, the upper surface BL_US of the bit line BL may be flat. For example, the upper surface BL1_US of the first portion BL1 of the bit line BL and the upper surface BL2_US of the second portion BL2 may be disposed on the same plane. Here, the upper surface BL2_US of the second portion BL2 of the bit line BL may be a surface of the upper surface BL_US of the bit line BL that contacts the liner film 174.

[0054] Although the upper surface 174_US of the liner film 174 is shown to be coplanar with the upper surface of the lower cell etch stop film 173 , some example embodiments are not limited thereto. For example, the upper surface 174_US of the liner film 174 may be disposed higher or lower than the upper surface of the lower cell etch stop film 173 .

[0055] exist Figure 6 , the upper surface BL1_US of the first portion BL1 of the bit line BL may be higher than the upper surface BL2_US of the second portion BL2. A portion of the liner film 174 may overlap the first portion BL1 of the bit line BL in the second direction D2. The upper surface 174_US of the liner film 174 may be higher than the upper surface BL1_US of the first portion BL1 of the bit line BL.

[0056] exist Figure 7 In the embodiment of the present invention, the liner film 174 may include a protruding portion 174P. The protruding portion 174P of the liner film 174 may be disposed in the first portion BL1 of the bit line BL. The protruding portion 174P of the liner film 174 may be disposed between the first portion BL1 of the bit line BL and the lower cell etch stop film 173. The protruding portion 174P of the liner film 174 may overlap the lower cell etch stop film 173 and the protruding insulating pattern 175 in the third direction D3.

[0057] exist Figure 8 , the upper surface 174_US of the liner film 174 may be coplanar with the upper surface BL1_US of the first portion BL1 of the bit line BL. In other words, the height up to the upper surface BL1_US of the first portion BL1 of the bit line BL may be the same as the height up to the upper surface 174_US of the liner film 174 based on the lower surface of the bit line BL (e.g., from the lower surface of the bit line BL).

[0058] Refer again Figures 1 to 10 , a channel structure AP_ST may be disposed on each bit line BL. The channel structure AP_ST may be disposed on the liner film 174. The channel structure AP_ST may cover the liner film 174. The channel structure AP_ST may be connected to the bit line BL through the liner film 174. A plurality of channel structures AP_ST may be connected to one bit line BL. A plurality of channel structures AP_ST disposed on one bit line BL are spaced apart in the second direction D2.

[0059] The channel structure AP_ST may be disposed in a channel trench CH_T extending in the first direction D1. A plurality of channel structures AP_ST may be disposed in a single channel trench CH_T. The plurality of channel structures AP_ST disposed in the channel trench CH_T are spaced apart in the first direction D1.

[0060] For example, the channel structure AP_ST may be two-dimensionally arranged along first and second directions D1 and D2 crossing each other. Although not limited thereto, in some example embodiments, the first direction D1 may be orthogonal to the second direction D2 along the same flat surface, and the third direction D3 may extend in a vertical direction from the flat surface.

[0061] The channel structure AP_ST may extend along the sidewall and the bottom surface of the channel trench CH_T. In a cross section taken along the second direction D2, the channel structure AP_ST may have a 'U' shape.

[0062] The channel structure AP_ST may include a horizontal portion AP_STH, a first vertical portion AP_STV1, and a second vertical portion AP_STV2. The first vertical portion AP_STV1 and the second vertical portion AP_STV2 of the channel structure may protrude from the horizontal portion AP_STH of the channel structure in the third direction D3.

[0063] The horizontal portion AP_STH of the channel structure may extend along the bottom surface of the channel trench CH_T and the upper surface 174_US of the liner film 174. The horizontal portion AP_STH of the channel structure may extend along the upper surface 174_US of the liner film 174 in a cross section taken along the second direction D2. The horizontal portion AP_STH of the channel structure may be connected to the bit line BL through the liner film 174. For example, the horizontal portion AP_STH of the channel structure and the liner film 174 may be sequentially disposed on the upper surface BL_US of the bit line BL.

[0064] The first and second vertical portions AP_STV1 and AP_STV2 of the channel structure may extend along sidewalls of the channel trench CH_T. In a cross section taken along the second direction D2 , the first and second vertical portions AP_STV1 and AP_STV2 of the channel structure may each extend along sidewalls 175SW of the protruding insulating pattern 175 .

[0065] The channel structure AP_ST may include an oxide semiconductor material. The channel structure AP_ST may include, for example, a metal oxide. As an example, the channel structure AP_ST may be an amorphous metal oxide film. As another example, the channel structure AP_ST may be a polycrystalline metal oxide film. As another example, the channel structure AP_ST may be in a state of a combination of an amorphous metal oxide film and a polycrystalline metal oxide film. As another example, the channel structure AP_ST may be a CAAC (c-axis oriented crystallization) metal oxide film.

[0066] The channel structure AP_ST may include, for example but not limited to, at least one of the following: indium oxide, tin oxide, zinc oxide, In-Zn-based oxide (IZO), Sn-Zn-based oxide, Al-Zn-based oxide, Zn-Mg-based oxide, Sn-Mg-based oxide, In-Mg-based oxide, In-Ga-based oxide (IGO), In-Ga-Zn-based oxide (IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-P In-R-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide and In-Hf-Al-Zn-based oxide.

[0067] Here, In-Ga-Zn-based oxide means an oxide having In, Ga and Zn as main components, but does not mean the ratio of In, Ga and Zn. That is, taking IGZO (Indium Gallium Zinc Oxide) as an example, the channel structure AP_ST may include IGZO (Indium Gallium Zinc Oxide, In x Ga y Zn z O). IGZO (In:Ga:Zn=1:1:1) containing indium, gallium and zinc in the same ratio may be an In-Ga-Zn based oxide. Ga-rich IGZO may have a higher gallium ratio than IGZO (In:Ga:Zn=1:1:1) and a lower indium ratio than IGZO (In:Ga:Zn=1:1:1). Ga-rich IGZO may also be an In-Ga-Zn based oxide. In addition, In-rich IGZO may have a higher indium ratio than IGZO (In:Ga:Zn=1:1:1) and a lower gallium ratio than IGZO (In:Ga:Zn=1:1:1). In-rich IGZO may also be an In-Ga-Zn based oxide.

[0068] Although the above description has been made using IGZO, some example embodiments are not limited thereto. The above description may be applied when the channel structures AP_ST each include a ternary or higher metal oxide. In addition, when the channel structure AP_ST includes an In-Ga-Zn-based oxide, the channel structure AP_ST may further include doped metal elements other than In, Ga, and Zn.

[0069] The channel structure AP_ST may include a first channel pattern AP1, a second channel pattern AP2, and a connection channel pattern AP_CP. The connection channel pattern AP_CP connects the first channel pattern AP1 and the second channel pattern AP2. The first channel pattern AP1 and the second channel pattern AP2 are spaced apart in the second direction D2.

[0070] The first channel pattern AP1, the second channel pattern AP2, and the connection channel pattern AP_CP are disposed on the bit line BL and the liner film 174. The first channel pattern AP1 and the second channel pattern AP2 are connected to the bit line BL. The first channel pattern AP1 and the second channel pattern AP2 may contact the upper surface 174_US of the liner film 174. The liner film 174 may be disposed between the connection channel pattern AP_CP and the bit line BL.

[0071] The first channel pattern AP1 may include a portion of the horizontal portion AP_STH of the channel structure and a first vertical portion AP_STV1 of the channel structure. A portion of the horizontal portion AP_STH of the channel structure may be a horizontal portion of the first channel pattern AP1. The first vertical portion AP_STV1 of the channel structure may be a vertical portion of the first channel pattern AP1.

[0072] The second channel pattern AP2 may include another portion of the horizontal portion AP_STH of the channel structure and a second vertical portion AP_STV2 of the channel structure. Another portion of the horizontal portion AP_STH of the channel structure may be a horizontal portion of the second channel pattern AP2. The second vertical portion AP_STV2 of the channel structure may be a vertical portion of the second channel pattern AP2.

[0073] The connection channel pattern AP_CP includes the remaining portion of the horizontal portion AP_STH of the channel structure.

[0074] The first channel pattern AP1, the second channel pattern AP2, and the connection channel pattern AP_CP may be distinguished based on a first word line WL1 and a second word line WL2 which will be described later. Figure 4, the first word line WL1 will be described as an example. The first word line WL1 may include an inner wall facing the sidewall 175SW of the protruding insulating pattern and an outer wall opposite to the inner wall in the second direction D2. The boundary between the first channel pattern AP1 and the connection channel pattern AP_CP may be an extension line of the outer wall of the first word line WL1 extending in the third direction D3.

[0075] The first word line WL1 and the second word line WL2 may be disposed on the channel structure AP_ST. The first word line WL1 and the second word line WL2 may be disposed in the channel trench CH_T.

[0076] Each of the first word line WL1 and the second word line WL2 may extend in the first direction D1. The first word line WL1 and the second word line WL2 may be alternately arranged in the second direction D2. The first word line WL1 is spaced apart from the second word line WL2 in the second direction D2.

[0077] The first word line WL1 and the second word line WL2 are spaced apart from the bit line BL in the third direction D3. The first word line WL1 and the second word line WL2 cross the bit line BL.

[0078] The first word line WL1 and the second word line WL2 are disposed on the horizontal portion AP_STH of the channel structure. The first word line WL1 and the second word line WL2 are disposed between the first vertical portion AP_STV1 and the second vertical portion AP_STV2 of the channel structure.

[0079] The first word line WL1 is disposed on the first channel pattern AP1. The second word line WL2 is disposed on the second channel pattern AP2. The first word line WL1 and the second word line WL2 are disposed between the first channel pattern AP1 and the second channel pattern AP2. The first channel pattern AP1 is closer to the first word line WL1 than the second word line WL2. The second channel pattern AP2 is closer to the second word line WL2 than the first word line WL1.

[0080] Each of the first word line WL1 and the second word line WL2 may have a width in the second direction D2. The width of the first word line WL1 in a portion overlapping the channel structure AP_ST along the third direction D3 may be different from the width of the first word line WL1 in a portion not overlapping the channel structure AP_ST. The width of the second word line WL2 in a portion overlapping the channel structure AP_ST along the third direction D3 may be different from the width of the second word line WL2 in a portion not overlapping the channel structure AP_ST.

[0081] For example, each of the first word line WL1 and the second word line WL2 may include a first portion WLa of the word line and a second portion WLb of the word line. The width of the first portion WLa of the word line in the second direction D2 may be smaller than the width of the second portion WLb of the word line in the second direction D2. As an example, the first portion WLa of the word line may be disposed on the channel structure AP_ST. The first portion WLa of the word line may be disposed on the first channel pattern AP1 and the second channel pattern AP2.

[0082] Each of the first word line WL1 and the second word line WL2 may include first portions WLa of the word line and second portions WLb of the word line alternately disposed along the first direction D1. Each channel structure AP_ST may be disposed between second portions WLb of the word line adjacent along the first direction D1. In the first word line WL1, each first active pattern AP1 may be disposed between second portions WLb of the word line adjacent along the first direction D1. In the second word line WL2, each second active pattern AP2 may be disposed between second portions WLb of the word line adjacent along the first direction D1.

[0083] The channel structure AP_ST is not disposed under the second portion WLb of the word line. A height of the first portion WLa of the word line is less than a height of the second portion WLb of the word line.

[0084] The first word line WL1 and the second word line WL2 include a conductive material, and may include, for example, at least one of doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, metal, and metal alloy.

[0085] The first word line WL1 and the second word line WL2 may include an upper surface WL_US and a lower surface opposite to each other in the third direction D3. The lower surfaces of the first word line WL1 and the second word line WL2 face the bit line BL.

[0086] exist Figure 4 In the embodiment, the upper surfaces WL_US of the first word line WL1 and the second word line WL2 may be plane. Fig. 9 In the embodiment, the upper surfaces WL_US of the first word line WL1 and the second word line WL2 may be convex. Fig.10 In the embodiment, upper surfaces WL_US of the first word line WL1 and the second word line WL2 may be concave-rounded.

[0087] Based on the upper surface of the bit line BL, the upper surface WL_US of the first word line WL1 and the second word line WL2 may be higher than the uppermost portion of the vertical portions AP_STV1 and AP_STV2 of the channel structure. The uppermost portions of the channel patterns AP1 and AP2 may be the uppermost portions of the vertical portions AP_STV1 and AP_STV2 of the channel structure. A height H1 from the upper surface BL_US of the bit line BL to the uppermost portion of the vertical portions AP_STV1 and AP_STV2 of the channel structure may be less than a height H2 from the upper surface BL_US of the bit line BL to the upper surface WL_US of the first word line WL1 and the second word line WL2.

[0088] The gate insulating film GOX may be disposed between the first word line WL1 and the channel structure AP_ST and between the second word line WL2 and the channel structure AP_ST. The gate insulating film GOX may be disposed between the first word line WL1 and the first active pattern AP1 and between the second word line WL2 and the second active pattern AP2. The gate insulating film GOX may extend in the first direction D1 together with the first word line WL1 and the second word line WL2.

[0089] The gate insulating film GOX may extend along the first vertical portion AP_STV1 of the channel structure. The gate insulating film GOX may extend along the second vertical portion AP_STV2 of the channel structure. In the semiconductor memory device according to some example embodiments, the gate insulating film GOX may not be disposed on a horizontal portion AP_STH of the channel structure that does not overlap with the first word line WL1 and the second word line WL2 along the third direction D3. From the perspective of the cross-sectional view, the gate insulating film GOX between the first word line WL1 and the channel structure AP_ST may be separated from the gate insulating film GOX between the second word line WL2 and the channel structure AP_ST.

[0090] The gate insulating film GOX may include a silicon oxide film, a silicon oxynitride film, a high dielectric constant insulating film having a higher dielectric constant than the silicon oxide film, or a combination thereof.

[0091] A portion of the gate insulating film GOX may protrude beyond the upper surfaces WL_US of the first and second word lines WL1 and WL2 in the third direction D3. A portion of the gate insulating film GOX may protrude beyond the uppermost portions of the vertical portions AP_STV1 and AP_STV2 of the channel structures in the third direction D3.

[0092] A height H4 from the upper surface BL_US of the bit line BL to the uppermost portion GOX_UUS of the gate insulating film may be greater than a height H1 from the upper surface BL_US of the bit line BL to the uppermost portion of the vertical portions AP_STV1 and AP_STV2 of the channel structures. A height H4 from the upper surface of the bit line BL to the uppermost portion GOX_UUS of the gate insulating film may be greater than a height H2 from the upper surface of the bit line BL to the upper surfaces WL_US of the word lines WL1 and WL2.

[0093] The gate separation pattern GSS may be disposed on the bit line BL and the cell lower insulating film 171. The gate separation pattern GSS may be disposed inside the channel trench CH_T. The gate separation pattern GSS may be disposed on the channel structure AP_ST, the first word line WL1, and the second word line WL2.

[0094] In a semiconductor memory device according to some example embodiments, a gate separation pattern GSS may be in contact with a channel structure AP_ST. The gate separation pattern GSS may be disposed on the connection channel pattern AP_CP. The gate separation pattern GSS may be in contact with a horizontal portion AP_STH of the channel structure. The gate separation pattern GSS may be spaced apart from the bit line BL in the third direction D3.

[0095] The gate separation pattern GSS may be disposed between the first and second word lines WL1 and WL2 adjacent in the second direction D2. The first and second word lines WL1 and WL2 may be separated by the gate separation pattern GSS. The gate separation pattern GSS may extend in the first direction D1 between the first and second word lines WL1 and WL2.

[0096] The first word line WL1 may be disposed between the gate separation pattern GSS and the channel structure AP_ST. The second word line WL2 may be disposed between the gate separation pattern GSS and the channel structure AP_ST. The first word line WL1 may be disposed between the gate separation pattern GSS and the first channel pattern AP1. The second word line WL2 may be disposed between the gate separation pattern GSS and the second channel pattern AP2.

[0097] The gate separation pattern GSS may include a horizontal portion and a protruding portion. The protruding portion of the gate separation pattern GSS may protrude from the horizontal portion of the gate separation pattern GSS toward the bit line BL in the third direction D3. The protruding portion of the gate separation pattern GSS may be closer to the bit line BL than the horizontal portion of the gate separation pattern GSS. The horizontal portion of the gate separation pattern GSS may be disposed on the upper surface WL_US of the first word line WL1 and the second word line WL2. In a cross-sectional view, the gate separation pattern GSS may have a "T" shape.

[0098] The gate separation pattern GSS may include a gate separation pad 151, a gate separation filling film 153, and a gate separation capping film 155. The gate separation pad 151 may extend along the upper surface WL_US of the first word line WL1 and the second word line WL2 and the outer wall of the first word line WL1 and the second word line WL2. The gate separation pad 151 may extend along the horizontal portion AP_STH of the channel structure. The gate separation pad 151 may contact the connection channel pattern AP_CP. The gate separation pad 151 may extend along the gate insulation film GOX protruding beyond the upper surface WL_US of the first word line WL1 and the second word line WL2. Unlike the illustrated example, in some example embodiments, the gate separation pad 151 may not extend along the gate insulation film GOX protruding beyond the upper surface WL_US of the first word line WL1 and the second word line WL2.

[0099] The gate separation filling film 153 may be disposed on the gate separation liner 151. The gate separation capping film 155 may be disposed on the gate separation filling film 153. The gate separation liner 151, the gate separation filling film 153, and the gate separation capping film 155 may each be made of an insulating material. Unlike the illustrated example, in some example embodiments, the gate separation pattern GSS may be a single film.

[0100] The upper surface GSS_US of the gate separation pattern may be disposed at the same height as the upper surface of the protruding insulating pattern 175 based on the upper surface of the bit line BL, but is not limited thereto.

[0101] A height H3 from the upper surface BL_US of the bit line BL to the upper surface GSS_US of the gate separation pattern may be greater than a height H1 from the upper surface BL_US of the bit line BL to the uppermost portion of the vertical portions AP_STV1 and AP_STV2 of the channel structures. A height H3 from the upper surface BL_US of the bit line BL to the upper surface GSS_US of the gate separation pattern may be greater than a height H2 from the upper surface BL_US of the bit line BL to the upper surfaces WL_US of the word lines WL1 and WL2.

[0102] The height H3 from the upper surface BL_US of the bit line BL to the upper surface GSS_US of the gate separation pattern is shown to be the same as the height H4 from the upper surface BL_US of the bit line BL to the uppermost portion GOX_UUS of the gate insulation film, but is not limited thereto.

[0103] The landing pad LP may be disposed on the channel structure AP_ST. The landing pad LP is connected to the first vertical portion AP_STV1 of the channel structure and the second vertical portion AP_STV2 of the channel structure.

[0104] The landing pad LP may be disposed on the first and second channel patterns AP1 and AP2. The landing pad LP is connected to the first and second channel patterns AP1 and AP2.

[0105] From a planar perspective, the landing pad LP may have various shapes such as a circle, an oval, a rectangle, a square, a diamond, and a hexagon.

[0106] The landing pad LP may include a horizontal portion LP_H and a protruding portion LP_P. The horizontal portion LP_H of the landing pad may be disposed on the upper surface of the protruding insulating pattern 175 and the upper surface GSS_US of the gate separation pattern. The protruding portion LP_P of the landing pad may protrude from the horizontal portion LP_H of the landing pad toward the bit line BL in the third direction D3.

[0107] Based on the upper surface BL_US of the bit line BL, the lowermost portion of the landing pad LP may be lower than the upper surface GSS_US of the gate separation pattern. In other words, the protruding portion LP_P of the landing pad is disposed between the protruding insulating pattern 175 and the gate separation pattern GSS. The height from the upper surface BL_US of the bit line BL to the lowermost portion of the landing pad LP may be less than the height H4 from the upper surface BL_US of the bit line BL to the uppermost portion GOX_UUS of the gate insulation film.

[0108] The pad separation insulating pattern 235 may be disposed between the landing pads LP. From a plane perspective, the landing pads LP may be arranged in a matrix along the first direction D1 and the second direction D2. The upper surface of the landing pad LP may be coplanar with the upper surface of the pad separation insulating pattern 235, but is not limited thereto.

[0109] The landing pad LP includes a conductive material, such as doped polysilicon, conductive metal nitride, conductive metal silicon nitride, metal carbonitride, conductive metal silicide, conductive metal oxide, two-dimensional material, metal, and metal alloy.

[0110] The data storage patterns DSP may be respectively disposed on the landing pads LP. The data storage pattern DSP may be connected to the first vertical portion AP_STV1 and the second vertical portion AP_STV2 of the channel structure. The data storage pattern DSP may be connected to each of the first channel pattern AP1 and the second channel pattern AP2.

[0111] The data storage patterns DSP may be arranged in a matrix form along the first direction D1 and the second direction D2, such as Figure 1 The data storage pattern DSP may completely or partially overlap the landing pad LP in the third direction D3. The data storage pattern DSP may contact the entirety or a portion of the upper surface of the landing pad LP.

[0112] As an example, the data storage pattern DSP may be a capacitor. The first channel pattern AP1 may be connected to the first capacitor. The second channel pattern AP2 may be connected to the second capacitor.

[0113] The data storage pattern DSP may include a capacitor dielectric film 253 interposed between a storage electrode 251 and a plate electrode 255. In this case, the storage electrode 251 may be in contact with the landing pad LP. The first channel pattern AP1 may be connected to a first capacitor including the storage electrode 251, the capacitor dielectric film 253, and the plate electrode 255, and the second channel pattern AP2 may be connected to a second capacitor including another storage electrode 251, the capacitor dielectric film 253, and the plate electrode 255. From a plane perspective, the storage electrode 251 may have various shapes such as a circle, an ellipse, a rectangle, a square, a diamond, and a hexagon. The data storage pattern DSP may completely overlap or partially overlap with the landing pad LP. The data storage pattern DSP may be in contact with all or part of the upper surface of the landing pad LP. The storage electrode 251 may penetrate the upper cell etch stop film 247. The upper cell etch stop film 247 may be made of an insulating material.

[0114] In contrast, in some example embodiments, the data storage pattern DSP may be a variable resistance pattern that can be switched between two resistance states by an electric pulse applied to the storage element. For example, the data storage pattern DSP may include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material.

[0115] Fig.11 2 is a diagram for explaining a semiconductor memory device according to some example embodiments. Fig.12 is a diagram for explaining a semiconductor memory device according to some example embodiments. Figures 1 to 10 For reference, Fig.11 and Fig.12 yes Figure 2 An enlarged view of part P.

[0116] Reference Fig.12 , in the semiconductor memory device according to some example embodiments, the gate separation pattern GSS may not contact the channel structure AP_ST.

[0117] For example, a portion of the gate insulating film GOX may be disposed between the gate separation pattern GSS and the channel structure AP_ST. From the perspective of the cross-sectional view, in some example embodiments, the gate insulating film GOX between the first word line WL1 and the channel structure AP_ST may be connected to the gate insulating film GOX between the second word line WL2 and the channel structure AP_ST, such as, for example Fig.12 shown.

[0118] Reference Fig.11 In a semiconductor device according to some example embodiments, the channel structure AP_ST may include a first metal oxide pattern 111 and a second metal oxide pattern 112 .

[0119] The first metal oxide pattern 111 may extend along a bottom surface and a sidewall of the channel trench CH_T. The first metal oxide pattern 111 may be in contact with the liner film 174 .

[0120] The second metal oxide pattern 112 may be disposed on the first metal oxide pattern 111. The second metal oxide pattern 112 may extend along a bottom surface and a sidewall of the channel trench CH_T.

[0121] Each of the first metal oxide pattern 111 and the second metal oxide pattern 112 may include an oxide semiconductor material.

[0122] In a semiconductor memory device according to some example embodiments, the first metal oxide pattern 111 and the second metal oxide pattern 112 may each include an amorphous metal oxide. A composition of the first metal oxide pattern 111 may be different from a composition of the second metal oxide pattern 112 .

[0123] As an example, the first metal oxide pattern 111 and the second metal oxide pattern 112 may include materials different from each other. The composition of the first metal oxide pattern 111 may be different from that of the second metal oxide pattern 112 .

[0124] As another example, the first metal oxide pattern 111 and the second metal oxide pattern 112 may include the same material. For example, the first metal oxide pattern 111 and the second metal oxide pattern 112 may include IGZO (Indium Gallium Zinc Oxide, In x Ga y Zn z However, composition ratios of indium (In), gallium (Ga), and zinc (Zn) included in IGZO may be different in the first and second metal oxide patterns 111 and 112.

[0125] As another example, the first metal oxide pattern 111 and the second metal oxide pattern 112 may each include doped indium zinc oxide (IZO). Impurities doped into the IZO (indium zinc oxide) in the first metal oxide pattern 111 may be different from impurities doped into the IZO (indium zinc oxide) in the second metal oxide pattern 112. In this case, the composition of the first metal oxide pattern may be different from the composition of the second metal oxide pattern 112.

[0126] In a semiconductor memory device according to some example embodiments, one of the first metal oxide pattern 111 and the second metal oxide pattern 112 may include an amorphous metal oxide, and the other may include CAAC (c-axis aligned crystallization) IGZO.

[0127] Figures 13 to 17 is a diagram for explaining a semiconductor memory device according to some example embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 10 The points described are different.

[0128] As a reference, Fig.13 are layout diagrams for explaining a semiconductor memory device according to some example embodiments. Fig.14 It is along Fig.13 Cross-sectional views taken along lines AA and BB. Fig.15 It is along Fig.13 Cross-sectional view taken at CC and DD. Fig.16 and Fig.17 yes Fig.14 An enlarged view of part P.

[0129] Reference Figures 13 to 17 , in the semiconductor memory device according to some example embodiments, the first channel pattern AP1 and the second channel pattern AP2 spaced apart in the second direction D2 are not connected to each other inside the channel trench CH_T.

[0130] The first channel pattern AP1 may include a horizontal portion AP1_H extending along an upper surface of the bit line BL and a vertical portion AP1_V extending along a sidewall 175SW of the protruding insulating pattern. The vertical portion AP1_V of the first channel pattern may protrude from the horizontal portion AP1_H of the first channel pattern in the third direction D3.

[0131] The second channel pattern AP2 may include a horizontal portion AP2_H extending along the upper surface of the bit line BL and a vertical portion AP2_V extending along the sidewall 175SW of the protruding insulating pattern. The vertical portion AP2_V of the second channel pattern may protrude from the horizontal portion AP2_H of the second channel pattern in the third direction D3.

[0132] The gate separation pattern GSS may contact the upper surface 174_US of the liner film 174 . The horizontal portion AP2_H of the second channel pattern and the horizontal portion AP1_H of the first channel pattern may be spatially separated by the gate separation pattern GSS. The gate separation liner 151 may contact the liner film 174 .

[0133] exist Fig.17In the embodiment, the gate separation pattern GSS may separate the liner films 174 . The liner films 174 may be spaced apart in the second direction D2 . The liner films 174 may be separated by the gate separation pattern GSS . The gate separation liner 151 may be disposed between the spaced apart liner films 174 .

[0134] The liner film 174 may partially cover the upper surface BL_US of the bit line BL. The liner film 174 may be disposed between the bit line BL and the horizontal portion AP1_H of the first channel pattern AP1. The liner film 174 may be disposed between the bit line BL and the horizontal portion AP2_H of the second channel pattern AP2.

[0135] The bit line BL may include a first portion BL1 and a second portion BL2. The second portion BL2 of the bit line BL may include a first sub-region and a second sub-region. The first sub-region may be a region where the bit line BL, the first channel pattern AP1, and the second channel pattern AP2 overlap in the third direction D3. The second sub-region may be a remaining region of the second portion BL2 except the first sub-region. The liner film 174 may be disposed on the first sub-region, but may not be disposed on the second sub-region.

[0136] The gate separation pattern GSS may contact the upper surface BL_US of the bit line BL. The horizontal portion AP2_H of the second channel pattern and the horizontal portion AP1_H of the first channel pattern may be spatially separated by the gate separation pattern GSS. The gate separation liner 151 may contact the liner film 174 .

[0137] Figures 18 to 20 is a diagram for explaining a semiconductor memory device according to some example embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 10 The points described are different.

[0138] As a reference, Fig.18 are layout diagrams for explaining a semiconductor memory device according to some example embodiments. Fig.19 It is along Fig.18 Cross-sectional views taken along lines AA and BB. Fig. 20 It is along Fig.18 Cross-sectional view taken at CC and DD.

[0139] Reference Figures 18 to 20 , the semiconductor memory device according to some example embodiments may further include a shielding structure 180 .

[0140] The shielding structure 180 may extend in the second direction D2. The shielding structure 180 may be spaced apart from the bit lines BL in the first direction D1. The shielding structure 180 may be alternately arranged with the bit lines BL in the first direction D1.

[0141] The shielding structure 180 may be disposed inside the lower cell insulating film 171. An upper surface of the shielding structure 180 may be lower than an upper surface BL_US of the bit line BL.

[0142] As an example, the shielding structure 180 may include a conductive material. As another example, the shielding structure 180 may include a conductive material and may include air gaps or voids within the conductive material.

[0143] Figure 21 to Figure 24 is a diagram for explaining a semiconductor memory device according to some example embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 10 The points described are different.

[0144] Reference Fig.21 In a semiconductor memory device according to some example embodiments, the first channel pattern AP1 and the second channel pattern AP2 may be alternately arranged in a diagonal direction with respect to the first direction D1 and the second direction D2. Here, the diagonal direction may be parallel to the upper surface of the substrate 100.

[0145] The channel structure AP_ST may be formed to be twisted in a diagonal direction. From a plane perspective, the first channel pattern AP1, the second channel pattern AP2, and the connection channel pattern AP_CP may each have a parallelogram shape or a rhombus shape.

[0146] Reference Fig. 22 , in the semiconductor memory device according to some example embodiments, the landing pads LP and the data storage patterns DSP may be arranged in a zigzag form or a honeycomb form from a plane perspective.

[0147] Reference Fig.23 , in the semiconductor memory device according to some example embodiments, the data storage pattern DSP may be disposed to be misaligned with the landing pad LP from a plane perspective.

[0148] Each of the data storage patterns DSP may be in contact with a portion of the landing pad LP.

[0149] Reference Fig.24 In the semiconductor memory device according to some example embodiments, each of the landing pads LP disposed on the first and second channel patterns AP1 and AP2 may have a semicircular shape or a semi-elliptical shape from a plane perspective.

[0150] From a planar perspective, the landing pads LP may be disposed symmetrically to each other.

[0151] Figures 25 to 39 are diagrams for explaining a method of manufacturing a semiconductor memory device according to some example embodiments.

[0152] Reference Figure 25 to Figure 27 , a peripheral gate structure PG may be formed on the substrate 100 .

[0153] A first peripheral wiring 241 a and a peripheral contact plug 241 b may be formed on the substrate 100 .

[0154] Peripheral upper insulating films 261, 262, 263, 264 and 265 may be sequentially formed on the first peripheral wiring 241a and the peripheral contact plug 241b. Second peripheral wiring 243, peripheral via plug 242 and cell connection plug 244 may be formed inside the peripheral upper insulating films 261, 262, 263, 264 and 265.

[0155] Then, a bit line BL may be formed on the fifth peripheral upper insulating film 265. The bit line BL may extend long in the second direction D2 on the substrate 100. A cell lower insulating film 171 may be formed on the fifth peripheral upper insulating film 265. The cell lower insulating film 171 may expose an upper surface of the bit line BL.

[0156] Reference Fig.28 and Fig.29 , a protruding insulating pattern 175 may be formed on the substrate 100. For example, the protruding insulating pattern 175 may be formed on the bit line BL and the under-cell insulating film 171.

[0157] The under-cell etch stop film 173 may be formed between the protruding insulating pattern 175 and the under-cell insulating film 171 , but is not limited thereto.

[0158] The protruding insulating pattern 175 may include a plurality of channel trenches CH_T extending in the first direction D1. The channel trenches CH_T may cross the bit lines BL. The channel trenches CH_T may expose the bit lines BL.

[0159] Reference Fig.30 and Fig.31 , a liner film 174 may be formed on the upper surface BL_US of the bit line BL.

[0160] For example, the liner film 174 may be formed on the upper surface BL_US of the bit line BL exposed by the channel trench CH_T by a plasma nitridation process. The plasma nitridation process may include, for example but not limited to, any one of a physical vapor deposition (PVD) method, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, and an ion implantation method.

[0161] The liner film 174 and the under-cell etch stop film 173 may completely cover the upper surface BL_US of the bit line BL.

[0162] Reference Fig.32 and Fig.33, a pre-channel structure AP_P may be formed along the sidewall and bottom surface of the channel trench CH_T. The pre-channel structure AP_P may be formed on the liner film 174. The pre-channel structure AP_P may be formed along the sidewall and upper surface of the protruding insulating pattern 175. The liner film 174 may be disposed between the pre-channel structure AP_P and the upper surface BL_US of the bit line BL.

[0163] Reference Fig.34 and Fig.35 , a sacrificial film 30 may be formed on the pre-channel structure AP_P.

[0164] The sacrificial film 30 may be formed on the pre-channel structure AP_P. The sacrificial film 30 may fill the channel trench CH_T. The sacrificial film 30 may be, but is not limited to, one of an insulating material and a silicon oxide film formed using a SOG (Spin On Glass) technique.

[0165] A mask pattern (not shown) may then be formed on the sacrificial film 30 and the pre-channel structure AP_P. The sacrificial film 30 and the pre-channel structure AP_P may be etched using the mask pattern as an etching mask. The pre-channel structure AP_P and the sacrificial film 30 may be removed from the under-cell insulating film 171. As a result, the sacrificial film 30 and the pre-channel structure AP_P may each be spaced apart from each other in the first direction D1.

[0166] Reference Fig.36 and Fig.37 , the sacrificial film 30 is removed, and a pre-gate insulating film GOX_P and a pre-word line WL_P may be formed.

[0167] For example, the sacrificial film 30 is removed and the pre-channel structure AP_P, a portion of the lower cell insulating film 171, and a portion of the protruding insulating pattern 175 may be exposed. Subsequently, a pre-gate insulating film GOX_P and a pre-word line WL_P may be sequentially formed on the pre-channel structure AP_P, the lower cell insulating film 171, and the protruding insulating pattern 175.

[0168] The pre-gate insulating film GOX_P can be formed by but is not limited to using at least one of physical vapor deposition (PVD) technology, thermal chemical vapor deposition (thermal CVD) technology, low pressure chemical vapor deposition (LP-CVD) technology, plasma enhanced chemical vapor deposition (PE-CVD) technology or atomic layer deposition (ALD) technology.

[0169] Reference Fig.38 and Fig.39 , a channel structure AP_ST, a first word line WL1, and a second word line WL2 may be formed.

[0170] For example, an anisotropic etching process may be performed on the pre-word line WL_P. When the anisotropic etching process is performed on the pre-word line WL_P, the pre-word line WL_P is removed, and the first word line WL1 and the second word line WL2 may be formed on the upper surface of the protruding insulating pattern 175. In addition, the pre-gate insulating film GOX_P and the pre-channel structure AP_P are removed, and each of the gate insulating film GOX and the channel structure AP_ST may be formed on the upper surface of the protruding insulating pattern 175.

[0171] In some example embodiments, a portion of the gate insulating film GOX may be etched when performing the anisotropic etching process on the pre-word line WL_P. Thus, the gate insulating film GOX between the first word line WL1 and the channel structure AP_ST may be separated from the gate insulating film GOX between the second word line WL2 and the channel structure AP_ST.

[0172] In some example embodiments, when the anisotropic etching process is performed on the pre-word line WL_P, the channel structure AP_ST between the first word line WL1 and the second word line WL2 may be etched. Therefore, the channel structure AP_ST may be divided into Fig.14 In addition, a portion of the upper surface 174_US of the liner film 174 may be exposed.

[0173] In some example embodiments, when the anisotropic etching process is performed on the pre-word line WL_P, the channel structure AP_ST and the liner film 174 between the first word line WL1 and the second word line WL2 may be etched. Thus, a portion of the upper surface BL_US of the bit line BL may be exposed.

[0174] Reference Fig.39 , a gate separation pattern GSS may be formed on the first word line WL1 and the second word line WL2. The gate separation pattern GSS may fill the channel trench CH_T.

[0175] For example, the gate separation liner 151 may be formed along the outline of the first word line WL1 and the outline of the second word line WL2 . The gate separation liner 151 may also be formed on the upper surface of the protruding insulating pattern 175 .

[0176] A pre-fill film may be formed on the gate separation liner 151. The pre-fill film may also be formed on the upper surface of the protruding insulating pattern 175. A gate separation filling film 153 may be formed on the gate separation liner 151 by removing a portion of the pre-fill film.

[0177] A pre-capping film may be formed on the gate separation filling film 153. The pre-capping film may also be formed on the upper surface of the protruding insulating pattern 175. The gate separation capping film 155 may be formed by removing a portion of the pre-capping film. While the gate separation capping film 155 is formed, the gate separation liner 151 and the pre-capping film formed on the upper surface of the protruding insulating pattern 175 may be removed.

[0178] Reference Figure 2 and Figure 3 By removing a portion of the channel structure AP_ST, the uppermost portion of the channel structure AP_ST may become lower than the upper surface of the protruding insulating pattern 175. Subsequently, a pre-landing pad film may be formed on the protruding insulating pattern 175, the gate separation pattern GSS, and the channel structure AP_ST. By patterning the pre-landing pad film, a landing pad LP may be formed on the channel structure AP_ST.

[0179] The data storage pattern DSP may then be formed on the landing pad LP. The data storage pattern DSP may be connected to the channel structure AP_ST and may be formed on the gate separation pattern GSS.

[0180] Figures 40 to 45 is a diagram for explaining a method of manufacturing a semiconductor memory device according to some example embodiments. Figures 25 to 39 For reference, Fig.40 It is used to illustrate Fig.32 Figure 1 shows the manufacturing method that is then performed.

[0181] Reference Fig.40 and Fig.41 , a pre-channel structure AP_P may be formed along the sidewall and bottom surface of the channel trench CH_T. The pre-channel structure AP_P may be formed on the liner film 174. The pre-channel structure AP_P is not formed on the upper surface of the protruding insulating pattern 175.

[0182] A sacrificial film 30 may then be formed on the pre-channel structure AP_P. The sacrificial film 30 may fill the channel trench CH_T. The sacrificial film 30 may be, but is not limited to, one of an insulating material and a silicon oxide film formed using a SOG technique.

[0183] Reference Fig.42 and Fig.43 By patterning the pre-channel structure AP_P, a channel structure AP_ST extending along the sidewall and bottom surface of the channel trench CH_T may be formed.

[0184] For example, a trench separation mask (not shown) may be formed on the sacrificial film 30 and the protruding insulating pattern 175. A portion of the sacrificial film 30 may be removed using the trench separation mask. By removing a portion of the sacrificial film 30, a portion of the pre-channel structure AP_P may be exposed.

[0185] A portion of the exposed pre-channel structure AP_P may be removed using an etching process. Thus, a channel structure AP_ST may be formed in the channel trench CH_T.

[0186] The sacrificial film 30 may then be removed inside the channel trench CH_T.

[0187] Reference Fig.44 and Fig.45 , each of the pre-gate insulating film GOX_P and the pre-word line WL_P may be formed on the channel structure AP_ST and the protruding insulating pattern 175 .

[0188] For example, a pre-gate insulating film GOX_P may be formed on upper surfaces of the channel structure AP_ST and the protruding insulating pattern 175. Subsequently, a pre-word line WL_P may be formed along an outline of the pre-gate insulating film GOX_P.

[0189] Subsequently, an anisotropic etching process is performed on the pre-word line WL_P, and a Fig.38 The first word line WL1, the second word line WL2 and the gate insulating film GOX. The subsequent manufacturing method is the same as Fig.38 and Fig.39 The manufacturing method is the same as described in.

[0190] In summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the exemplary embodiments without departing substantially from the principles of the inventive concept. Therefore, the disclosed exemplary embodiments of the inventive concept are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A semiconductor memory device, comprising: a bit line comprising metal and extending in a first direction on the substrate; a channel structure on the bit line, the channel structure comprising a first channel pattern extending along a second direction, the channel structure comprising a second channel pattern spaced apart from the first channel pattern along the first direction and extending along the second direction; a liner film between the bit line and the channel structure, the liner film including the metal; a first word line, between the first channel pattern and the second channel pattern, the first word line extending along the second direction; a second word line between the first channel pattern and the second channel pattern, the second word line extending along the second direction, the second word line being spaced apart from the first word line in the first direction; as well as A first capacitor and a second capacitor are on the first channel pattern and the second channel pattern, respectively, and are connected to the first channel pattern and the second channel pattern, respectively.

2. The semiconductor memory device according to claim 1, The liner film extends along an upper surface of the bit line.

3. The semiconductor memory device according to claim 1, further comprising: a protruding insulating pattern on the bit line, The protruding insulating pattern and the liner film completely cover the upper surface of the bit line.

4. The semiconductor memory device according to claim 1, The liner film includes nitride.

5. The semiconductor memory device according to claim 1, further comprising: a protruding insulating pattern on the bit line, wherein the bit line includes a first portion overlapping the protruding insulating pattern along a third direction, and The liner film is not disposed on the first portion of the bit line.

6. The semiconductor memory device according to claim 1, further comprising: a protruding insulating pattern on the bit line, The first channel pattern includes a vertical portion extending along a sidewall of the protruding insulating pattern and a horizontal portion extending along an upper surface of the liner film.

7. The semiconductor memory device according to claim 1, further comprising: a gate separation pattern on the bit line and separating the first word line from the second word line, Wherein, the gate separation pattern contacts the liner film.

8. The semiconductor memory device according to claim 1, further comprising: a gate separation pattern on the bit line and separating the first word line from the second word line, Wherein, the gate separation pattern contacts the bit line.

9. The semiconductor memory device according to claim 1, further comprising: a gate separation pattern on the bit line and separating the first word line from the second word line; as well as a connecting channel pattern, connecting the first channel pattern and the second channel pattern, Wherein, the connection channel pattern is between the gate separation pattern and the liner film.

10. The semiconductor memory device according to claim 1, in, The channel structure includes indium gallium zinc oxide.

11. The semiconductor memory device according to claim 1, further comprising: A shielding structure extends in the first direction and is spaced apart from the bit line in the second direction.

12. The semiconductor memory device according to claim 1, in, The first channel pattern includes a first metal oxide pattern and a second metal oxide pattern sequentially on the liner film, The first metal oxide pattern and the second metal oxide pattern each include an amorphous metal oxide, and A composition of the first metal oxide pattern is different from a composition of the second metal oxide pattern.

13. A semiconductor memory device comprising: A bit line extending along a first direction on the substrate; a protruding insulating pattern on the substrate, the protruding insulating pattern including a channel trench exposing the bit line, the protruding insulating pattern extending in a second direction crossing the first direction; a liner film on the exposed upper surface of the bit line; a channel structure extending along a lower surface and a side surface of the channel groove, the channel structure comprising a first channel pattern and a second channel pattern spaced apart from the first channel pattern in the first direction; a first word line and a second word line on the channel structure, the first word line and the second word line being spaced apart from each other in the first direction and each extending in the second direction; a gate insulating film between the first channel pattern and the first word line, and between the second channel pattern and the second word line; as well as A first capacitor and a second capacitor are respectively on the first channel pattern and the second channel pattern, and the first capacitor and the second capacitor are respectively connected to the first channel pattern and the second channel pattern.

14. The semiconductor memory device according to claim 13, in, The bit line includes a first element, and The spacer film includes the first element and a second element different from the first element.

15. The semiconductor memory device according to claim 14, in, The second element includes nitrogen (N).

16. The semiconductor memory device according to claim 13, in, The channel structure includes indium gallium zinc oxide.

17. The semiconductor memory device according to claim 13, in, The channel structure includes a connecting channel pattern connecting the first channel pattern and the second channel pattern, and The liner film is between the connection channel pattern and the bit line.

18. The semiconductor memory device according to claim 13, further comprising: a gate separation pattern on the bit line and separating the first word line from the second word line, Wherein, the gate separation pattern contacts the bit line.

19. The semiconductor memory device according to claim 13, further comprising: a gate separation pattern on the bit line and separating the first word line from the second word line, The gate separation pattern overlaps the liner film in the third direction.

20. A semiconductor memory device, comprising: a peripheral gate structure on a substrate; a bit line on the peripheral gate structure and extending in a first direction; a protruding insulating pattern on the substrate, the protruding insulating pattern including a channel trench exposing the bit line, the protruding insulating pattern extending in a second direction crossing the first direction; a channel structure in the channel trench, the channel structure comprising a horizontal portion and a first vertical portion and a second vertical portion protruding from the horizontal portion; a liner film between the bit line and the horizontal portion of the channel structure, the liner film comprising a nitride; a first word line on the channel structure, the first word line extending in the second direction; a second word line on the channel structure, the second word line extending in the second direction, the second word line being spaced apart from the first word line in the first direction; a gate insulating film between the first vertical portion of the channel structure and the first word line and between the second vertical portion of the channel structure and the second word line; a gate separation pattern on the horizontal portion of the channel structure, the gate separation pattern separating the first word line and the second word line; as well as A first capacitor and a second capacitor on the channel structure, the first capacitor and the second capacitor being connected to the first vertical portion of the channel structure and the second vertical portion of the channel structure, respectively.

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