Method for preparing flash memory

Abstract

The present invention provides a flash memory and a method for preparing the same, comprising: providing a substrate; forming a hard mask layer, the hard mask layer at least covering the sidewall surface of an isolation layer; forming a first sidewall located on the sidewall surface of the hard mask layer; forming a stacked floating gate and a control gate located on both sides of each word line; forming a second sidewall oxide layer covering at least the side surfaces of the floating gate and the control gate and extending upward to cover the side surface of the first sidewall; and forming a second sidewall nitride layer covering the side surface of the second sidewall oxide layer. The steps of forming the floating gate and the control gate are provided after forming the first sidewall and before forming the second sidewall oxide layer. Because the hard mask layer and the first sidewall protect the interface between the control gate and the isolation layer, no step is formed at the interface. The first sidewall no longer needs to be formed on the step, and thus the first sidewall is no longer disconnected. The outer sidewall size of the flash memory cell is reduced. Simultaneously, the thinning of the sidewall reduces the aspect ratio of the interlayer dielectric layer and increases the fill window.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a method for preparing a flash memory. Background Art

[0002] Flash memory, with its advantages of low cost, low power consumption, and fast access speed, is gaining an increasingly important position in the non-volatile memory sector. With the advancement of technology, data storage media applications are shifting from traditional non-volatile memory to flash memory. Large-capacity solid-state storage devices using flash memory as the primary storage medium have become one of the mainstream data storage solutions today.

[0003] Figure 1 FIG. 1 is a schematic diagram of the structure of a flash memory, such as Figure 1 As shown, a flash memory device includes a substrate 100, a word line 103 located on the substrate 100, a floating gate layer 101 and a control gate layer 102 stacked on both sides of the word line 103, and an oxide layer 104 (made of polysilicon) covering the word line 103 and the control gate layer 102. During the etching process to form the control gate layer 102, due to the certain selectivity between polysilicon and the oxide layer 104 during both wet and dry etching, a step is generated at the interface between the control gate layer 102 and the oxide layer 104 on the side away from the word line 103. This step pushes up the first sidewall spacer 105 of the flash memory device. Subsequent dry etching causes the first sidewall spacer 105 to break at the point covered by the step (circled). As the outer second sidewall spacer 106 becomes thinner, the frequency of this situation increases significantly. As a result, acid, etching gas, charged substances, or other contaminants may enter the point where the first sidewall spacer 105 is broken, causing yield and even reliability issues, thereby affecting the performance of the flash memory device. Summary of the Invention

[0004] The present invention aims to provide a flash memory and a method for manufacturing the same, wherein the first sidewall is no longer disconnected, thereby improving the yield and quality of the flash memory. The outer sidewalls of the flash memory cell are reduced in size, and the thinning of the sidewalls reduces the aspect ratio of the interlayer dielectric layer and increases the fill window.

[0005] The present invention provides a method for preparing a flash memory, comprising:

[0006] Providing a substrate, on which a floating gate material layer, a control gate material layer, and a plurality of word lines penetrating the control gate material layer and the floating gate material layer are formed; an isolation layer is formed above each word line, the isolation layer covering the word line and the control gate material layer in adjacent areas on both sides of the word line;

[0007] forming a hard mask layer, wherein the hard mask layer at least covers a sidewall surface of the isolation layer that is perpendicular to the control gate material layer;

[0008] forming a first spacer, wherein the first spacer is located on a sidewall surface of the hard mask layer;

[0009] Etching the control gate material layer and the floating gate material layer exposed by the isolation layer to form stacked floating gates and control gates located on both sides of each word line;

[0010] forming a second spacer oxide layer, wherein the second spacer oxide layer at least covers the side surfaces of the floating gate and the control gate and extends upward to cover the side surface of the first spacer;

[0011] A second sidewall nitride layer is formed, where the second sidewall nitride layer covers a side surface of the second sidewall oxide layer.

[0012] Furthermore, forming the hard mask layer and the first sidewall spacer specifically includes:

[0013] forming a hard mask material layer, wherein the hard mask material layer covers the isolation layer and the control gate material layer;

[0014] forming a first spacer material layer, wherein the first spacer material layer covers the hard mask material layer;

[0015] The first spacer material layer and the hard mask material layer are etched without a mask, and the remaining first spacer material layer is etched to form the first spacer; and the remaining hard mask material layer is etched to form the hard mask layer.

[0016] Furthermore, the material of the second sidewall oxide layer is silicon oxide; the process for forming the second sidewall oxide layer is a thermal oxidation process; the process parameters of the thermal oxidation process include: O2 flow rate is 12sccm to 220sccm, and the reaction chamber temperature is 680℃ to 1000℃.

[0017] Furthermore, the formed flash memory includes a plurality of flash memory cells, each of which includes the word line, the stacked floating gate and the control gate on both sides of the word line, the isolation layer, and a spacer;

[0018] The spacer includes, from a side close to the word line to a side far from the word line, the hard mask layer, the first spacer, the second spacer oxide layer and the second spacer nitride layer.

[0019] Furthermore, after forming the second sidewall nitride layer, the preparation method further includes:

[0020] An interlayer dielectric layer is formed, where the interlayer dielectric layer fills the gaps between adjacent flash memory cells and covers the flash memory cells.

[0021] Furthermore, the thickness of the second sidewall oxide layer is 150 to 200 angstroms.

[0022] Furthermore, the thickness of the second sidewall nitride layer is 350 to 500 angstroms.

[0023] The present invention also provides a flash memory, comprising:

[0024] A substrate having a word line and a floating gate and a control gate stacked on both sides of the word line formed on the substrate; an isolation layer formed above the word line, the isolation layer covering the word line and the control gates on both sides of the word line;

[0025] a hard mask layer, wherein the hard mask layer at least covers a sidewall surface of the isolation layer that is perpendicular to the control gate;

[0026] a first spacer, wherein the first spacer is located on a sidewall surface of the hard mask layer;

[0027] a second spacer oxide layer, wherein the second spacer oxide layer at least covers side surfaces of the floating gate and the control gate and extends upward to cover side surfaces of the first spacer;

[0028] A second sidewall nitride layer covers a side surface of the second sidewall oxide layer.

[0029] Furthermore, the flash memory includes a plurality of flash memory cells, each of which includes the word line, the stacked floating gate and the control gate on both sides of the word line, the isolation layer, and a spacer;

[0030] The spacer includes, from a side close to the word line to a side far from the word line, the hard mask layer, the first spacer, the second spacer oxide layer and the second spacer nitride layer.

[0031] Furthermore, the flash memory further includes an interlayer dielectric layer, wherein the interlayer dielectric layer fills the gaps between adjacent flash memory cells and covers the flash memory cells.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] The present invention provides a flash memory and a preparation method thereof, the preparation method comprising: providing a substrate, on which a floating gate material layer, a control gate material layer and a plurality of word lines are formed; forming an isolation layer above each word line; forming a hard mask layer, the hard mask layer at least covering the side wall surface of the isolation layer perpendicular to the control gate material layer; forming a first sidewall, the first sidewall being located on the side wall surface of the hard mask layer; etching the control gate material layer and the floating gate material layer exposed by the isolation layer to form a stacked floating gate and a control gate located on both sides of each word line; forming a second sidewall oxide layer, the second sidewall oxide layer at least covering the side surfaces of the floating gate and the control gate and extending upward to cover the side surface of the first sidewall; and forming a second sidewall nitride layer, the second sidewall nitride layer covering the side surface of the second sidewall oxide layer. The steps of forming the floating gate and the control gate of the present invention are arranged after forming the first sidewall and before forming the second sidewall oxide layer. In this way, the junction between the control gate and the isolation layer away from the word line is protected by the first sidewall, and no step is formed at the junction. The first sidewall no longer needs to be formed on the step, so the first sidewall is no longer disconnected, the size of the sidewall outside the flash memory cell is reduced, and at the same time, the thinning of the sidewall reduces the aspect ratio of the interlayer dielectric layer and increases the filling window. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram of the structure of a flash memory.

[0035] Figures 2 to 6 Schematic diagram of the steps of the attempted improved flash memory formation method.

[0036] Figure 7 The figure is a flow chart of a method for preparing a flash memory according to an embodiment of the present invention.

[0037] Figures 8 to 14 Schematic diagram of each step of a method for preparing a flash memory according to an embodiment of the present invention.

[0038] Figure 15 for Figure 14 An enlarged schematic diagram of the middle side wall.

[0039] Figure 16 for Figure 6 An enlarged schematic diagram of the middle side wall.

[0040] The accompanying drawings are numerals as follows:

[0041] exist Figure 1 Middle: 100 - substrate; 101 - floating gate layer; 102 - control gate layer; 103 - word line; 104 - oxide layer; 105 - first spacer; 106 - second spacer;

[0042] exist Figures 2 to 6Middle: 200 - substrate; 201 - floating gate material layer; 210 - floating gate; 202 - control gate material layer; 220 - control gate; 203 - word line; 204 - isolation layer; 205 - hard mask layer; 206 - first spacer; 207 - second spacer oxide layer; 208 - second spacer nitride layer;

[0043] exist Figures 8 to 14 Middle: 300-substrate; 301-floating gate material layer; 310-floating gate; 302-control gate material layer; 320-control gate; 303-word line; 304-isolation layer; 350-hard mask material layer; 305-hard mask layer; 306-first spacer material layer; 360-first spacer; 307-second spacer oxide layer; 308-second spacer nitride material layer; 380-second spacer nitride layer. DETAILED DESCRIPTION

[0044] Aiming at the problem that the first sidewall of flash memory in the background art is easily disconnected at the step, an improved method for forming flash memory is developed. Figures 2 to 6 The steps of an improved method for forming a flash memory are introduced in detail.

[0045] like Figure 2 As shown, a substrate 200 is provided, on which a floating gate material layer 201, a control gate material layer 202 and a plurality of word lines 203 passing through the control gate material layer 202 and the floating gate material layer 201 are formed; an isolation layer 204 is formed above each word line 203, and the isolation layer 204 covers the word line 203 and the control gate material layer 202 in the adjacent areas on both sides of the word line 203.

[0046] like Figure 3 As shown, the control gate material layer 202 and the floating gate material layer 201 exposed by the isolation layer 204 are etched to form a stacked floating gate 210 and a control gate 220 located on both sides of each word line.

[0047] like Figure 4 As shown, a hard mask material layer is formed, and the hard mask material layer is etched to form a hard mask layer 205; the hard mask material layer covers the side surfaces of the isolation layer 204, the floating gate 210 and the control gate 220 and the upper surface of the substrate 200, and the remaining hard mask material layer is etched to form the hard mask layer 205; the hard mask layer 205 covers the side surfaces of the floating gate 210 and the control gate 220 and extends to cover the side wall surface of the isolation layer 204.

[0048] like Figure 5As shown, a first spacer material layer is formed, and the first spacer material layer is etched to form a first spacer 206; the first spacer material layer covers the isolation layer 204, the side surface of the hard mask layer 205 and the upper surface of the substrate 200, and the remaining first spacer material layer is etched to form the first spacer 206; the first spacer 206 covers the side surface of the hard mask layer 205.

[0049] like Figure 6 As shown, a second spacer oxide layer 207 is formed, covering the sidewall surfaces of the first spacer 206. A second spacer nitride layer 208 is formed, covering the sidewall surfaces of the second spacer oxide layer 207. The sidewalls of the flash memory cell, from the inner side to the outer side, include: a hard mask layer 205, a first spacer 206, a second spacer oxide layer 207, and a second spacer nitride layer 208.

[0050] In the improved flash memory formation method attempted, the control gate material layer 202 and the floating gate material layer 201 are first etched to form the floating gate 210 and the control gate 220. A hard mask layer 205 is then formed. The hard mask layer 205 covers the side surfaces of the floating gate 210 and the control gate 220 and extends upward to cover the sidewall surfaces of the isolation layer 204. The thicker hard mask layer 205 softens the step at the junction of the control gate 220 and the isolation layer 204 away from the word line 203. A first spacer 206 covers the side surfaces of the hard mask layer 205 and prevents disconnection at the junction of the control gate 220 and the isolation layer 204 away from the word line 203.

[0051] The improved flash memory formation method attempted has the following advantages: the hard mask layer 205 softens the step at the junction of the control gate 220 and the isolation layer 204, and the first sidewall 206 is no longer disconnected. Disadvantages: the outer sidewalls of the flash memory cell increase the thickness of the hard mask layer 205, occupying space for the floating gate, word line, and contact hole, which is not conducive to the reduction of the flash memory cell. In addition, the hard mask layer 205 is generally a PETEOS (plasma-enhanced tetraethyl orthosilicate) film, which is formed using TEOS (tetraethyl orthosilicate) and oxygen as raw materials and a PECVD (plasma-enhanced chemical vapor deposition) process. One advantage of using TEOS and oxygen as raw materials to grow PETEOS film is good step coverage. Due to the high mobility of the TEOS surface, the formation of low-density areas or voids can be avoided. However, another characteristic of the PETEOS formation process for the hard mask layer 205 is that it requires plasma activation. Plasma bombardment can cause physical damage to the gate oxide of the flash memory and charging effects.

[0052] In the improved flash memory fabrication method attempted, although the first sidewall spacer 206 is no longer disconnected, the hard mask layer 205 occupies space for the floating gate, word line, and contact hole, hindering the miniaturization of the flash memory cell. To address this issue, the inventors conducted further research and provided a flash memory fabrication method according to the present invention.

[0053] The following is a detailed description of a flash memory manufacturing method provided by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0054] For ease of description, some embodiments of the present application may use spatially relative terms such as "above," "below," "top," "below," etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that, in addition to the orientations described in the figures, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the figures is turned over, the elements or components described as being "below" or "beneath" other elements or components will subsequently be positioned as being "above" or "above" other elements or components. The terms "first," "second," etc., hereinafter, are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It is to be understood that, where appropriate, these terms used in this manner are interchangeable.

[0055] The embodiment of the present invention provides a method for preparing a flash memory, such as Figure 7 Shown, including:

[0056] Step S1: providing a substrate on which a floating gate material layer, a control gate material layer, and a plurality of word lines penetrating the control gate material layer and the floating gate material layer are formed; an isolation layer is formed above each word line, the isolation layer covering the word line and the control gate material layer in adjacent areas on both sides of the word line;

[0057] Step S2, forming a hard mask layer, wherein the hard mask layer at least covers the sidewall surface of the isolation layer perpendicular to the control gate material layer;

[0058] Step S3, forming a first sidewall spacer, the first sidewall spacer is located on the sidewall surface of the hard mask layer;

[0059] Step S4: etching the control gate material layer and the floating gate material layer exposed by the isolation layer to form stacked floating gates and control gates located on both sides of each word line;

[0060] Step S5, forming a second spacer oxide layer, wherein the second spacer oxide layer at least covers the side surfaces of the floating gate and the control gate and extends upward to cover the side surface of the first spacer;

[0061] Step S6: forming a second sidewall nitride layer, wherein the second sidewall nitride layer covers the side surface of the second sidewall oxide layer.

[0062] The following combination Figures 8 to 15 The accompanying drawings illustrate in detail the steps of the method for preparing the flash memory of the present invention.

[0063] like Figure 8 As shown, a substrate 300 is provided, which provides a process platform for forming a flash memory. The material of the substrate 300 can be silicon, germanium or silicon germanium. The substrate 300 can also be silicon on insulator (SOI), germanium on insulator (GeOI) or silicon germanium on insulator (SiGeOI). In this embodiment, the material of the substrate 300 is, for example, single crystal silicon. A floating gate material layer 301, a control gate material layer 302 and a plurality of word lines 303 passing through the control gate material layer 302 and the floating gate material layer 301 are formed on the substrate 300; an isolation layer 304 is formed above each word line 303, and the isolation layer 304 covers the word line 303 and the control gate material layer 302 in the adjacent areas on both sides of the word line 303. The material of the isolation layer 304 is, for example, an oxide layer.

[0064] like Figure 9 As shown, a hard mask material layer 350 is formed, and the hard mask material layer 350 covers the isolation layer 304 and the control gate material layer 302. The material of the hard mask material layer 350 can be silicon nitride.

[0065] like Figure 10 As shown, a first spacer material layer 306 is formed. The first spacer material layer 306 covers the hard mask material layer 350 . The material for forming the first spacer material layer 306 may be silicon nitride.

[0066] like Figure 11 As shown, the first spacer material layer 306 and the hard mask material layer 350 are etched without a mask. The remaining first spacer material layer 306 is etched to form a first spacer 360. The remaining hard mask material layer 350 is etched to form a hard mask layer 305. The hard mask layer 305 covers the sidewall surface of the isolation layer 304 perpendicular to the control gate material layer 302. The first spacer 360 is located on the sidewall surface of the hard mask layer 305. The maskless etching process can be a plasma dry etching process.

[0067] like Figure 12As shown, the control gate material layer 302 and floating gate material layer 301 exposed by the isolation layer 304 are etched to form stacked floating gates 310 and control gates 320 located on both sides of each wordline. The process for etching the floating gates 310 and control gates 320 can be a plasma dry etch process. Next, a second spacer oxide layer 307 is formed. The second spacer oxide layer 307 covers the isolation layer 304, the side surfaces of the first spacer 360, the side surfaces of the floating gates 310 and control gates 320, and the top surface of the substrate 300. The material of the second spacer oxide layer 307 can be silicon oxide, and the process for forming the second spacer oxide layer 307 can be a thermal oxidation process. In this embodiment, the process parameters of the thermal oxidation process include an O2 flow rate of 12 sccm to 220 sccm and a reaction chamber temperature of 680°C to 1000°C. The second spacer oxide layer 307 does not require a PETEOS process, thereby avoiding the gate oxide physical damage and charging effects caused by plasma bombardment on the flash memory.

[0068] like Figure 13 As shown, a second spacer nitride material layer 308 is formed, and the second spacer nitride material layer 308 covers the surface of the second spacer oxide layer 307 .

[0069] like Figure 14 As shown, the second sidewall nitride material layer 308 and the second sidewall oxide layer 307 are etched without a mask, and the remaining second sidewall oxide layer 307 is etched to cover the side surfaces of the floating gate 310 and the control gate 320 and the side surface of the first sidewall 360; the remaining second sidewall nitride material layer 308 is etched to form a second sidewall nitride layer 380, and the second sidewall nitride layer 380 covers the side surface of the remaining second sidewall oxide layer 307.

[0070] The formed flash memory includes several flash memory cells, each of which includes a word line 303, a stacked floating gate 310 and a control gate 320 on either side of the word line, an isolation layer 304, and spacers. The spacers, from the side closest to the word line 303 to the side further away from the word line 303, include: a hard mask layer 305, a first spacer 360, a second spacer oxide layer 307, and a second spacer nitride layer 380. A trench or gap is formed between adjacent flash memory cells for forming the flash memory lead-out structure. After forming the second spacer nitride layer, the preparation method further includes forming an interlayer dielectric layer (not shown), which fills the gap between adjacent flash memory cells and covers the flash memory cells.

[0071] Figure 15 for Figure 14 An enlarged schematic diagram of the middle side wall. Figure 16 for Figure 6 An enlarged schematic diagram of the middle side wall. Figure 16As shown, in this improved flash memory formation method, the hard mask layer 205 softens the step at the junction of the control gate 220 and the isolation layer 204, and the first sidewall spacer 206 is no longer disconnected. Disadvantage: The sidewall spacers on the outside of the flash memory cell increase the thickness of the hard mask layer 205, occupying space for the floating gate, word line, and contact hole, which is not conducive to the reduction of flash memory cell size. Figure 15 The width of the two dashed lines in Figure 16 The two dashed lines in are of equal width. Figure 16 The width of the two dotted lines in is the width of the side wall. Figure 15 As shown, the step of etching the control gate material layer 302 and the floating gate material layer 301 to form the floating gate 310 and the control gate 320 is arranged after forming the first sidewall spacer 360 and before forming the second sidewall spacer oxide layer 307. In this way, the junction between the control gate 320 and the isolation layer 304 away from the word line 303 is protected by the hard mask layer 305 and the first sidewall spacer 360, so no step is formed at the junction. The first sidewall spacer 360 does not need to be formed on the step, so the first sidewall spacer 360 is no longer disconnected, the size of the outer sidewall of the flash memory cell is reduced, and the thinning of the sidewall reduces the aspect ratio of the interlayer dielectric layer and increases the filling window. In addition, the second sidewall oxide layer 307 does not require the PETEOS process, thereby avoiding the gate oxide physical damage charging effect caused by plasma bombardment on the flash memory.

[0072] In summary, the present invention provides a flash memory and a preparation method thereof, the preparation method comprising: providing a substrate, on which a floating gate material layer, a control gate material layer and a plurality of word lines are formed; forming an isolation layer above each word line; forming a hard mask layer, the hard mask layer at least covering the side wall surface of the isolation layer perpendicular to the control gate material layer; forming a first side wall, the first side wall being located on the side wall surface of the hard mask layer; etching the control gate material layer and the floating gate material layer exposed by the isolation layer to form a stacked floating gate and a control gate located on both sides of each word line; forming a second side wall oxide layer, the second side wall oxide layer at least covering the side surfaces of the floating gate and the control gate and extending upward to cover the side surface of the first side wall; forming a second side wall nitride layer, the second side wall nitride layer covering the side surface of the second side wall oxide layer. The steps of forming the floating gate and the control gate of the present invention are arranged after forming the first sidewall and before forming the second sidewall oxide layer. In this way, the junction between the control gate and the isolation layer away from the word line is protected by the first sidewall, and no step is formed at the junction. The first sidewall no longer needs to be formed on the step, so the first sidewall is no longer disconnected, the size of the sidewall outside the flash memory cell is reduced, and at the same time, the thinning of the sidewall reduces the aspect ratio of the interlayer dielectric layer and increases the filling window.

[0073] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. The methods disclosed in the embodiments are described briefly because they correspond to the devices disclosed in the embodiments. For relevant details, refer to the method description.

[0074] The above description is only a description of the preferred embodiment of the present invention, and does not limit the scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing a flash memory, characterized in that: include: Providing a substrate, on which a floating gate material layer, a control gate material layer, and a plurality of word lines passing through the control gate material layer and the floating gate material layer are formed; An isolation layer is formed above each word line, and the isolation layer covers the word line and the control gate material layer in adjacent areas on both sides of the word line; forming a hard mask layer, wherein the hard mask layer at least covers a sidewall surface of the isolation layer that is perpendicular to the control gate material layer; forming a first spacer, wherein the first spacer is located on a sidewall surface of the hard mask layer; Etching the control gate material layer and the floating gate material layer exposed by the isolation layer to form stacked floating gates and control gates located on both sides of each word line; forming a second spacer oxide layer, wherein the second spacer oxide layer at least covers the side surfaces of the floating gate and the control gate and extends upward to cover the side surface of the first spacer; A second sidewall nitride layer is formed, where the second sidewall nitride layer covers a side surface of the second sidewall oxide layer.

2. The method for preparing a flash memory according to claim 1, wherein: Forming the hard mask layer and the first sidewall spacer specifically includes: forming a hard mask material layer, wherein the hard mask material layer covers the isolation layer and the control gate material layer; forming a first spacer material layer, wherein the first spacer material layer covers the hard mask material layer; The first spacer material layer and the hard mask material layer are etched without a mask, and the remaining first spacer material layer is etched to form the first spacer; and the remaining hard mask material layer is etched to form the hard mask layer.

3. The method for preparing a flash memory according to claim 1, wherein: The material of the second sidewall oxide layer is silicon oxide; The process for forming the second sidewall oxide layer is a thermal oxidation process; the parameters of the thermal oxidation process include: an O2 flow rate of 12 sccm to 220 sccm, and a reaction chamber temperature of 680° C. to 1000° C.

4. The method for preparing a flash memory according to claim 1, wherein: The formed flash memory includes a plurality of flash memory cells, each of which includes a word line, the stacked floating gate and the control gate on both sides of the word line, the isolation layer, and a spacer; The spacer includes, from a side close to the word line to a side far from the word line, the hard mask layer, the first spacer, the second spacer oxide layer and the second spacer nitride layer.

5. The method for preparing a flash memory according to claim 4, wherein: After forming the second sidewall nitride layer, the preparation method further includes: An interlayer dielectric layer is formed, where the interlayer dielectric layer fills the gaps between adjacent flash memory cells and covers the flash memory cells.

6. The method for preparing a flash memory according to claim 1, wherein: The thickness of the second sidewall oxide layer is 150 to 200 angstroms.

7. The method for preparing a flash memory according to claim 1, wherein: The thickness of the second sidewall nitride layer is 350 to 500 angstroms.

8. A flash memory, characterized in that: include: A substrate having a word line and a floating gate and a control gate stacked on both sides of the word line formed on the substrate; an isolation layer formed above the word line, the isolation layer covering the word line and the control gates on both sides of the word line; a hard mask layer, wherein the hard mask layer at least covers a sidewall surface of the isolation layer that is perpendicular to the control gate; a first spacer, wherein the first spacer is located on a sidewall surface of the hard mask layer; a second spacer oxide layer, wherein the second spacer oxide layer at least covers side surfaces of the floating gate and the control gate and extends upward to cover side surfaces of the first spacer; A second sidewall nitride layer covers a side surface of the second sidewall oxide layer.

9. The flash memory according to claim 8, wherein: The flash memory includes a plurality of flash memory cells, each of which includes a word line, the stacked floating gate and the control gate on both sides of the word line, the isolation layer, and a spacer; The spacer includes, from a side close to the word line to a side far from the word line, the hard mask layer, the first spacer, the second spacer oxide layer and the second spacer nitride layer.

10. The flash memory according to claim 9, wherein: The flash memory further includes an interlayer dielectric layer, which fills gaps between adjacent flash memory cells and covers the flash memory cells.

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