Chip test control circuit, test control method and related equipment

Abstract

The invention provides a chip test control circuit, a test control method and related equipment, and relates to the technical field of chip test. The chip test control circuit comprises a test voltage pin used for accessing a test voltage; and the control circuit is connected with the test voltage pin and is used for outputting a first control signal under the condition that the test voltage accessed by the test voltage pin meets a first voltage condition so as to enable the tested chip to start a test mode. According to the invention, the test voltage pin for accessing the test voltage is arranged on the chip, and the control signal for controlling the chip to start the test mode is output only when the voltage accessed by the test pin meets the preset voltage condition, so that the problem that the chip enters the test mode due to false triggering of the test command can be avoided, and a layer of protection is added for the chip.

Description

Technical Field

[0001] The present disclosure relates to the field of chip testing technology, and in particular to a chip testing control circuit, a testing control method and related equipment. Background Art

[0002] The test mode and user mode of a chip are different. The test mode is the working mode in which a tester debugs the chip, and the user mode is the working mode in which a user uses the chip.

[0003] At present, in the related technology, the test mode of the chip is turned on by sending a test command. However, when using the chip, the user may randomly send commands, which may cause the chip to enter the test mode. If used improperly, the performance of the chip may be damaged. Summary of the invention

[0004] The present disclosure provides a chip test control circuit, a test control method and related equipment, which are used to solve the technical problem that the chip may enter a test mode due to user misoperation during chip use, thereby causing the chip performance to be damaged.

[0005] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0006] According to one aspect of the present disclosure, a chip test control circuit is provided, which includes: a test voltage pin for connecting a test voltage; a control circuit connected to the test voltage pin, and used to output a first control signal to enable the chip under test to start a test mode when the test voltage connected to the test voltage pin meets a first voltage condition.

[0007] In some embodiments, the control circuit is further used to: when the test voltage connected to the test voltage pin meets a second voltage condition, output a second control signal to turn off the test mode of the chip under test.

[0008] In some embodiments, the control circuit includes: a test start module, used to input a test start signal or a test start command, and the test start signal or test command is used to turn on or off the test mode of the chip under test; a first logic circuit, connected to the test voltage pin and the test start module respectively, and used to output the first control signal or the second control signal according to the test voltage connected to the test voltage pin and the test start signal or test start command input by the test start module.

[0009] In some embodiments, the first logic circuit is an AND gate circuit, comprising: at least two input ports and one output port; wherein, one input port of the first logic circuit is connected to the test voltage pin, and another input port of the first logic circuit is connected to the test start module; the output port of the first logic circuit is used to output the first control signal or the second control signal.

[0010] In some embodiments, the first logic circuit is a transmission gate circuit, including: a control port, an input port and an output port; wherein the control port of the first logic circuit is connected to the test voltage pin, and the input port of the first logic circuit is connected to the test start module; the output port of the first logic circuit is used to output the first control signal or the second control signal.

[0011] In some embodiments, the chip test control circuit also includes: a test command port, used to input a test command for testing the chip under test; a second logic circuit, connected to the test command port and the output port of the first logic circuit, and used to output a third control signal based on the signal output by the first logic circuit and the test command input by the test command port, so that the chip under test enters a test mode.

[0012] In some embodiments, the second logic circuit is an AND gate circuit, comprising: at least two input ports and one output port; wherein, one input port of the second logic circuit is connected to the output port of the first logic circuit, and another input port of the second logic circuit is connected to the test command port; the output port of the second logic circuit is used to output the third control signal.

[0013] In some embodiments, the first logic circuit is a transmission gate circuit, including: a control port, an input port and an output port; wherein the control port of the second logic circuit is connected to the output port of the first logic circuit, and the input port of the second logic circuit is connected to the test command port; the output port of the second logic circuit is used to output the third control signal.

[0014] In some embodiments, the control circuit includes: a voltage monitoring unit connected to the test voltage pin, and configured to monitor whether the test voltage satisfies the first voltage condition.

[0015] In some embodiments, the voltage monitoring unit includes: at least one voltage comparator, each voltage comparator having two input ports and one output port; wherein one input port of the voltage comparator is connected to the test voltage pin; another input port of the voltage comparator is used to access a reference voltage; and the output port of the voltage comparator is used to output a comparison result between the test voltage and the reference voltage.

[0016] In some embodiments, the control circuit includes: a voltage cache unit, which is respectively connected to the test voltage pin and the test start module, and is used to cache the voltage connected to the test voltage pin, and output the first control signal or the second control signal after monitoring that the test start module inputs a test start signal or a test start command.

[0017] In some embodiments, the voltage cache unit includes: a latch, the latch including: a data input port, a clock signal input port, and an output port;

[0018] Among them, the data input port of the latch is connected to the test voltage pin for inputting the voltage connected to the test voltage pin; the clock signal input port of the latch is connected to the test start module for monitoring whether the test start module inputs the test start signal or the test start command; the output port output of the latch is used to output the first control signal or the second control signal.

[0019] According to another aspect of the present disclosure, a storage device is provided. The storage device includes: a memory and any one of the chip test control circuits described above.

[0020] In some embodiments, the memory includes: a memory chip and a substrate for packaging the memory chip; wherein the test voltage pin and the control circuit are coupled to the substrate; the input end of the control circuit is electrically connected to the test voltage pin, and the output end of the control circuit is electrically connected to the memory chip.

[0021] According to another aspect of the present disclosure, a chip test control method is also provided, the method comprising: monitoring a test voltage connected to a test voltage pin; in response to the test voltage connected to the test voltage pin satisfying a first voltage condition, outputting a first control signal to enable the chip to start a test mode.

[0022] In some embodiments, after monitoring the test voltage connected to the test voltage pin, the method further includes: in response to the test voltage connected to the test voltage pin satisfying a second voltage condition, outputting a second control signal to turn off the test mode of the chip.

[0023] In some embodiments, in response to the test voltage connected to the test voltage pin satisfying a first voltage condition, a first control signal is output to enable the chip to start a test mode, including: in response to the test voltage connected to the test voltage pin satisfying the first voltage condition, monitoring whether a test start signal or a test start command for starting the chip test mode is received; when the test voltage satisfies the first voltage condition and the test start signal or the test start command is received, outputting the first control signal to enable the chip to start a test mode.

[0024] In some embodiments, after outputting the first control signal to enable the chip to enter the test mode, the method further includes: monitoring whether a test command for testing the chip is received; and controlling the chip to enter the test mode according to the test command.

[0025] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the chip test control method described in any one of the above is implemented.

[0026] According to another aspect of the present disclosure, a computer program product is provided, including: a computer program or instructions, wherein when the computer program or instructions are executed by a processor, any one of the chip test control methods described above is implemented.

[0027] The chip test control circuit, test control method and related equipment provided in the embodiments of the present disclosure provide a test voltage pin for accessing the test voltage on the chip, and only output a control signal for controlling the chip to start the test mode when the voltage accessed by the test pin meets the preset voltage condition. Through the embodiments of the present disclosure, the problem of the chip entering the test mode due to the erroneous triggering of the test command can be avoided, and a layer of protection is added to the chip.

[0028] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0030] Figure 1 An exemplary chip test control circuit diagram including a test voltage pin and a control circuit in one embodiment of the present disclosure is shown;

[0031] Figure 2 An exemplary chip test control circuit diagram in one embodiment of the present disclosure is shown;

[0032] Figure 3 An exemplary chip test control circuit diagram in another embodiment of the present disclosure is shown;

[0033] Figure 4 An exemplary chip test control circuit diagram in another embodiment of the present disclosure is shown;

[0034] Figure 5 An exemplary chip test control circuit diagram in another embodiment of the present disclosure is shown;

[0035] Figure 6 A chip test control signal timing diagram in one embodiment of the present disclosure is shown;

[0036] Figure 7 A schematic diagram of an exemplary storage device including a memory chip and a chip test control circuit in one embodiment of the present disclosure is shown;

[0037] Figure 8 A schematic diagram of a memory in one embodiment of the present disclosure is shown;

[0038] Fig. 9 A flow chart of a chip test control method in one embodiment of the present disclosure is shown;

[0039] Fig.10 A flow chart of a chip test control method in another embodiment of the present disclosure is shown;

[0040] Fig.11 A flow chart of a chip test control method in another embodiment of the present disclosure is shown;

[0041] Fig.12 An exemplary chip test control circuit diagram for implementing multiple test mode activation in one embodiment of the present disclosure is shown;

[0042] Fig.13 An exemplary chip test control circuit diagram for implementing activation of multiple test modes in yet another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0043] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0044] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0045] For ease of understanding, before introducing the embodiments of the present disclosure, some terms or nouns involved in the embodiments of the present disclosure are explained as follows:

[0046] Test start signal: a start signal used to control the chip to start the test mode, which can be one bit or multiple bits. In the embodiment of the present disclosure, a two-bit signal combination is used as the test start signal.

[0047] Test start command: A start command used to control the chip to start the test mode.

[0048] Test command: A command used to control the chip to enter the corresponding test mode. Different test modes may correspond to different test commands.

[0049] The specific implementation of the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0050] Figure 1 An exemplary chip test control circuit including a test voltage pin and a control circuit in one embodiment of the present disclosure is shown, with reference to Figure 1 , the test voltage pin 10 is used to connect the test voltage; the control circuit 20 is connected to the test voltage pin 10, and is used to output a first control signal to enable the chip under test to start the test mode when the test voltage connected to the test voltage pin 10 meets the first voltage condition. It can be seen that if the test voltage connected to the test voltage pin 10 does not meet the first condition, the chip under test will not start the test mode, and there will be no problem of the chip entering the test mode due to the user's mistaken triggering of the test command.

[0051] In the specific implementation, for the test of the chip, the test engineer often determines the appropriate test voltage according to the test requirements and chip specifications. In some embodiments, the test voltage pin 10 in the embodiment of the present disclosure can be a high voltage pin (the voltage value is higher than a preset threshold, such as 100V). However, it is not ruled out that in some special scenarios, the chip needs to be tested at a low voltage (such as lower than a preset threshold, such as 5V), so in other embodiments, the test voltage pin 10 in the embodiment of the present disclosure is a low voltage pin (the voltage value is lower than a preset threshold). For some chip tests that require a specific voltage range, the test voltage pin 10 in the embodiment of the present disclosure may include a first pin and a second pin to access a test voltage in a certain voltage range (such as between 5V and 30V or between 30V and 100V) through the first pin and the second pin. For different test voltages, the test voltage pin added to the chip in the embodiment of the present disclosure may be one or more. When there is only one test voltage pin, it can be directly connected to a high voltage power supply, a low voltage power supply or ground, or it can be used with one or more voltage comparators to achieve access to different test voltages; when there are multiple test voltage pins, a test voltage within a certain voltage range can be directly accessed through two of the pins.

[0052] In the disclosed embodiment, by adding a pin (test voltage pin 10) for external voltage to the chip, the voltage connected to the pin is used to control whether the test mode of the chip is turned on, so as to avoid the user from accidentally triggering the test command and causing the chip to enter the test mode. The chip will only turn on the test mode when the voltage connected to the test voltage pin meets the test voltage condition. Taking the high-voltage pin as an example, when the voltage connected to the high-voltage pin is a high voltage, the test mode of the chip is turned on; when the voltage connected to the high-voltage pin is a low voltage or grounded, the test mode of the chip is disabled, and the chip will not enter the test mode even if the user inputs a test command.

[0053] In some embodiments, the control circuit 20 in the embodiment of the present disclosure is also used to: when the test voltage connected to the test voltage pin 10 meets the second voltage condition, output a second control signal to turn off the test mode of the chip under test. It should be noted that the second voltage condition in the embodiment of the present disclosure is a voltage condition corresponding to the non-test mode. The non-test mode here can be but is not limited to the user mode. When the test voltage pin is a high voltage pin, the first voltage condition is higher than a certain voltage threshold, and the second voltage condition is lower than the voltage threshold or grounded.

[0054] refer to Figure 2In some embodiments, the control circuit 20 in the embodiment of the present disclosure may specifically include: a test start module 201, used to input a test start signal or a test start command, the test start signal or the test command is used to turn on or off the test mode of the chip under test; a first logic circuit 202, connected to the test voltage pin 10 and the test start module 201 respectively, and used to output a first control signal or a second control signal according to the test voltage connected to the test voltage pin 10 and the test start signal or the test start command input by the test start module 201.

[0055] It should be noted that the test start signal in the above embodiment can be one bit or multiple bits. In one embodiment, a two-bit signal combination can be used as the test start signal. The above test start command is a start command used to control the chip to start the test mode.

[0056] Exemplarily, the first logic circuit 202 in the embodiment of the present disclosure can be any circuit that can implement logical operations, and the functions implemented by the circuit are: when the test voltage connected to the test voltage pin meets the first voltage condition and the test start module inputs a test start signal or a test start command, output a first control signal to control the chip to start the test mode; when the test voltage connected to the test voltage pin does not meet the first voltage condition, or the test start module does not input a test start signal or a test start command, output a second control signal to control the chip to turn off the test mode.

[0057] The chip test control circuit provided in the above embodiment can enable the chip to start the test mode only when the voltage connected to the test voltage pin meets the conditions and the correct test start signal or test start command is input, which can further protect the chip.

[0058] In one embodiment of the present disclosure, the first logic circuit 202 is an AND gate circuit, which includes: at least two input ports and one output port; wherein one input port of the first logic circuit 202 is connected to the test voltage pin 10, and the other input port of the first logic circuit 202 is connected to the test start module 201; the output port of the first logic circuit 202 is used to output the first control signal or the second control signal. The corresponding logic function of the first logic circuit 202 is realized by the AND gate circuit, and the circuit design is simple.

[0059] In another embodiment of the present disclosure, the first logic circuit 202 is a transmission gate circuit, including: a control port, an input port and an output port; wherein the control port of the first logic circuit 202 is connected to the test voltage pin 10, and the input port of the first logic circuit 202 is connected to the test start module 201; the output port of the first logic circuit 202 is used to output a first control signal or a second control signal. Under the action of the control signal, the transmission gate circuit can completely close the transmission path of the signal, thereby reducing power consumption when signal transmission is not required. In the embodiment of the present disclosure, the test voltage pin 10 is connected to the control port of the transmission gate circuit, and the signal transmission can be closed when the test voltage connected to the test voltage pin 10 does not meet the first voltage condition, so as to reduce the power consumption of signal transmission.

[0060] refer to Figure 3 In some embodiments, the chip test control circuit in the embodiment of the present disclosure also includes: a test command port 203, which is used to input a test command for testing the chip under test; a second logic circuit 204, which is connected to the test command port 203 and the output port of the first logic circuit 202, and is used to output a third control signal based on the signal output by the first logic circuit 202 and the test command input by the test command port 203, so that the chip under test enters the test mode.

[0061] In one embodiment of the present disclosure, the second logic circuit 204 is an AND gate circuit, including: at least two input ports and one output port; wherein one input port of the second logic circuit 204 is connected to the output port of the first logic circuit 202, and another input port of the second logic circuit 204 is connected to the test command port 203; the output port of the second logic circuit 204 is used to output the third control signal. Similarly, the corresponding logic function of the second logic circuit 204 is realized by the AND gate circuit, and the circuit design is simple.

[0062] In another embodiment of the present disclosure, the first logic circuit 202 is a transmission gate circuit, including: a control port, an input port, and an output port; wherein the control port of the second logic circuit 204 is connected to the output port of the first logic circuit 202, and the input port of the second logic circuit 204 is connected to the test command port 203; the output port of the second logic circuit 204 is used to output a third control signal. Similarly, in the embodiment of the present disclosure, the output port of the first logic circuit 202 is connected to the control port of the transmission gate circuit, so that the signal transmission can be turned off when the signal output by the first logic circuit 202 does not meet the condition, so as to reduce the power consumption of signal transmission.

[0063] refer to Figure 4 In some embodiments, the control circuit 20 includes: a voltage monitoring unit 205 connected to the test voltage pin 10, for monitoring whether the test voltage meets the first voltage condition.

[0064] In some embodiments, the voltage monitoring unit 205 includes: at least one voltage comparator 205a, each voltage comparator 205a has two input ports and one output port; wherein, one input port of the voltage comparator 205a is connected to the test voltage pin 10; another input port of the voltage comparator 205a is used to access the reference voltage 205b; the output port of the voltage comparator 205a is used to output the comparison result between the test voltage and the reference voltage 205b.

[0065] refer to Figure 5 In some embodiments, the control circuit 20 in the embodiment of the present disclosure may also include: a voltage cache unit 206, which is respectively connected to the test voltage pin 10 and the test start module 201, and is used to cache the voltage connected to the test voltage pin 10, and output a first control signal or a second control signal after monitoring that the test start module 201 inputs a test start signal or a test start command.

[0066] It should be noted that the voltage cache unit 206 in the embodiment of the present disclosure may be any circuit unit that can cache the voltage accessed by the test voltage pin 10. In some embodiments, the voltage cache unit 206 in the embodiment of the present disclosure may be implemented by a latch 206a, such as Figure 5 As shown, the latch 206a may specifically include: a data input port, a clock signal input port and an output port; wherein the data input port of the latch 206a is connected to the test voltage pin 10, and is used to input the voltage connected to the test voltage pin 10; the clock signal input port of the latch 206a is connected to the test start module 201, and is used to monitor whether the test start module 201 inputs a test start signal or a test start command; the output port output of the latch 206a is used to output a first control signal or a second control signal.

[0067] Take the test voltage pin as a high voltage pin as an example, Figure 6 FIG. 1 shows a timing diagram of a chip test control signal in an embodiment of the present disclosure. Figure 6 As shown, the limited value high voltage is a preset voltage threshold. When the test voltage pin (high voltage pin) of the chip is connected to a test voltage greater than or equal to the limited value high voltage, the test start signal (such as the two-bit signal combination 11) input through other pins turns on the test mode of the chip (that is, the test mode enable signal of the chip changes from a low level to a high level); when the test mode enable signal is at a high level, if the input test command is detected, the chip is controlled to enter the test mode. When the test voltage pin (high voltage pin) of the chip is connected to a test voltage less than the limited value high voltage or grounded, the test mode enable signal changes from a high level to a low level, and the chip cannot enter the test mode.

[0068] Figure 7 An exemplary storage device including a memory chip and a chip test control circuit in one embodiment of the present disclosure is shown. Figure 7 As shown, the storage device 70 includes: a memory 701 and a chip test control circuit 702, wherein the chip test control circuit can be any of the above-mentioned chip test control circuits.

[0069] like Figure 8 In one embodiment shown, the memory 701 may specifically include: a memory chip 701A and a substrate 701B for packaging the memory chip; wherein the test voltage pin 10 and the control circuit 20 are coupled to the substrate 701B; the input end of the control circuit 20 is electrically connected to the test voltage pin 10, and the output end of the control circuit 20 is electrically connected to the memory chip 701A.

[0070] Fig. 9 A flow chart of a chip test control method in one embodiment of the present disclosure is shown as follows: Fig. 9 As shown, the method specifically comprises the following steps:

[0071] S902, monitoring the test voltage connected to the test voltage pin;

[0072] S904 , in response to the test voltage connected to the test voltage pin satisfying a first voltage condition, output a first control signal to enable the chip to enter a test mode.

[0073] Exemplarily, the above-mentioned test voltage pin can be one or more pins added on the chip for accessing the test voltage. Only when the test voltage pin is connected to the test voltage that meets the first voltage condition, can the first control signal for controlling the chip to start the test mode be output. The first voltage condition in the embodiment of the present disclosure is a preset voltage condition for controlling the chip to start the test mode, and the first control signal is a control signal for the chip to start the test mode triggered after the test voltage pin is connected to the test voltage that meets the first voltage condition. In a specific implementation, there is a control circuit between the test voltage pin and the chip, and the control circuit can output a corresponding control signal according to the test voltage connected to the test voltage pin. If the test voltage connected to the test voltage pin meets the first voltage condition, the first control signal is output, and the control signal for controlling the chip to start the test mode is output; if the test voltage connected to the test voltage pin does not meet the first voltage condition, the control signal for controlling the chip to close the test mode is output.

[0074] In specific implementation, different packaging methods can be used for the test voltage pin for different application scenarios. For example, for scenarios where the chip may not be tested again after leaving the factory, the test pin can be completely packaged; but in order to facilitate the debugging work of the chip after leaving the factory or the testing work in some special scenarios, the test pin can be retained. When the chip needs to be tested, the test voltage pin is connected to a voltage that meets the first voltage condition; when the chip does not need to be tested, the test voltage pin is connected to a voltage that does not meet the first voltage condition or is directly grounded.

[0075] For a scenario where the test voltage pin needs to be connected to a voltage that does not meet the first voltage condition, in some embodiments, such as Fig.10 As shown, after monitoring the test voltage connected to the test voltage pin, the chip test control method provided in the embodiment of the present disclosure may further include the following steps:

[0076] S906 , in response to the test voltage connected to the test voltage pin satisfying a second voltage condition, output a second control signal to turn off the test mode of the chip.

[0077] Exemplarily, the second voltage condition may be a preset voltage condition that is different from the first voltage condition. In some embodiments, it may be the voltage condition required for the chip in a non-test mode (such as a user mode). When the test voltage connected to the test voltage pin meets the second voltage condition, a second control signal is output to control the chip to turn off the test mode.

[0078] In some embodiments, the above-mentioned S902 can be implemented through the following steps during specific implementation: in response to the test voltage connected to the test voltage pin satisfying a first voltage condition, monitoring whether a test start signal or a test start command for starting the chip test mode is received; when the test voltage satisfies the first voltage condition and a test start signal or a test start command is received, outputting a first control signal to enable the chip to start the test mode.

[0079] In the above embodiment, if the voltage connected to the test voltage pin meets the first voltage condition (such as the voltage condition corresponding to the high voltage test, the voltage value may be equal to 30V), it is further monitored whether a test start signal or a test start command for starting the chip test mode is received, and when a test start signal or a test start command for starting the chip test mode is received, a first control signal for controlling the chip to start the test mode is output. Specifically, the first control signal for controlling the chip to start the test mode can be output to the chip through the control circuit. Since the first control signal is output only when the test voltage meets the first voltage condition and the test start signal or the test start command is received, if the voltage connected to the test voltage pin does not meet the first voltage condition, even if a test start signal or a test start command for starting the chip test mode is received, the first control signal will not be output, thereby avoiding the problem that the user mistakenly triggers the test start command and causes the chip to start the test mode.

[0080] When the chip turns on the test mode, different tests are performed on the chip, and different test commands may need to be input. Therefore, in some embodiments, after outputting the first control signal to turn on the chip in the test mode, the chip test control method provided in the embodiment of the present disclosure may further include the following steps:

[0081] S908, monitoring whether a test command for testing the chip is received;

[0082] S910, controlling the chip to enter a test mode according to the test command.

[0083] Exemplarily, the above-mentioned test command refers to the command required for the chip to perform the test mode. Different test modes may correspond to different test commands, and the embodiments of the present disclosure do not specifically limit this. After the test mode of the chip is turned on by the first control signal, the chip can be controlled to enter the corresponding test mode by inputting the corresponding test command. For ordinary users, as long as it is ensured that the test voltage pin is not connected to a voltage that meets the first voltage condition, it is impossible to control the chip to open the entrance of the test mode through a test start signal or a test start command. This means that ordinary users cannot enter the test mode by inputting a test command when using the chip, which can prevent users from accidentally triggering the test command and causing the chip to enter the test mode.

[0084] It should be noted that the chip test includes but is not limited to: low voltage test (such as less than 5V), medium voltage test (such as between 5V and 30V), high voltage test (such as between 30V and 100V), and very high withstand voltage test (such as above 100V); it can be seen that different chip tests may have different corresponding test voltages. In order to enable the chip control method in the embodiment of the present disclosure to meet the tests within different test voltage ranges, the test voltage pin can be connected to multiple test voltages in different voltage ranges.

[0085] Fig.12 An exemplary chip test control circuit for implementing multiple test mode activation in one embodiment of the present disclosure is shown. Fig.12 For example, when the test voltage pin can be connected to N voltage ranges (such as the first voltage range, the second voltage range . . . the Nth voltage range), multiple control signals can be output through the control circuit to enable the chip to enter multiple test modes.

[0086] In a specific implementation, the test voltage pin may be implemented through multiple pins, or may be implemented through one pin and multiple voltage comparators. Fig.13 The present invention shows a chip test control circuit that controls the activation of multiple test modes by accessing test voltages of different voltage ranges through a test voltage pin and multiple voltage comparators (such as the first voltage comparator, the second voltage comparator ... the Nth voltage comparator).

[0087] The embodiment of the present disclosure provides a non-temporary computer-readable storage medium on which computer instructions are stored, wherein the computer instructions execute any of the above-mentioned chip test control methods when they are executed. The computer instructions are suitable for being loaded by the processor and executing the chip test control method provided by each step in any of the above-mentioned embodiments. For details, please refer to the implementation method provided by each step in any of the above-mentioned embodiments, which will not be repeated here. In addition, the description of the beneficial effects of adopting the same method will not be repeated. For technical details not disclosed in the computer-readable storage medium embodiment involved in the present disclosure, please refer to the description of the method embodiment of the present disclosure. As an example, the computer program can be deployed to be executed on a computer device, or on multiple computer devices located at one location, or on multiple computer devices distributed at multiple locations and interconnected by a communication network.

[0088] The present disclosure also provides a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method provided in any of the above-mentioned optional modes.

[0089] In summary, the chip test control circuit, test control method and related equipment provided in the embodiments of the present disclosure provide a test voltage pin for accessing the test voltage on the chip, and only output a control signal for controlling the chip to start the test mode when the voltage accessed by the test pin meets the preset voltage condition. Through the embodiments of the present disclosure, the problem of the chip entering the test mode due to the erroneous triggering of the test command can be avoided, and a layer of protection is added to the chip.

[0090] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in this description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this disclosure.

[0091] The method and related apparatus provided by the embodiments of the present disclosure are described with reference to the method flow chart and / or structural diagram provided by the embodiments of the present disclosure. Specifically, each process and / or box in the method flow chart and / or structural diagram, as well as the combination of the processes and / or boxes in the flow chart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable application display device to generate a machine, so that the instructions executed by the processor of the computer or other programmable application display device generate instructions for implementing the process in the process. Figure 1 Schematic diagram of one or more processes and / or structures Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable application display device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 Schematic diagram of one or more processes and / or structures Figure 1 These computer program instructions can also be loaded onto a computer or other programmable application display device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A flow or multiple flows and / or structures illustrate the steps of the functions specified in one block or multiple blocks.

[0092] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The description and examples are to be regarded as exemplary only, and the true scope of the present disclosure is indicated by the appended claims.

Claims

1. A chip test control circuit, characterized in that: include: Test voltage pin, used to connect the test voltage; The control circuit is connected to the test voltage pin and is used to output a first control signal to enable the chip under test to start the test mode when the test voltage connected to the test voltage pin meets the first voltage condition.

2. The chip test control circuit according to claim 1, characterized in that: The control circuit is further used for: when the test voltage connected to the test voltage pin meets the second voltage condition, outputting a second control signal to turn off the test mode of the chip under test.

3. The chip test control circuit according to claim 2, characterized in that: The control circuit comprises: A test start module, used for inputting a test start signal or a test start command, wherein the test start signal or the test command is used for turning on or off the test mode of the chip under test; The first logic circuit is connected to the test voltage pin and the test start module respectively, and is used to output the first control signal or the second control signal according to the test voltage connected to the test voltage pin and the test start signal or test start command input by the test start module.

4. The chip test control circuit according to claim 3, characterized in that: The first logic circuit is an AND gate circuit, comprising: at least two input ports and one output port; Among them, one input port of the first logic circuit is connected to the test voltage pin, and another input port of the first logic circuit is connected to the test start module; the output port of the first logic circuit is used to output the first control signal or the second control signal.

5. The chip test control circuit according to claim 3, characterized in that: The first logic circuit is a transmission gate circuit, including: a control port, an input port and an output port; Among them, the control port of the first logic circuit is connected to the test voltage pin, the input port of the first logic circuit is connected to the test start module; the output port of the first logic circuit is used to output the first control signal or the second control signal.

6. The chip test control circuit according to claim 3, characterized in that: The chip test control circuit also includes: A test command port, used to input a test command for testing the chip under test; The second logic circuit is connected to the test command port and the output port of the first logic circuit, and is used to output a third control signal according to the signal output by the first logic circuit and the test command input by the test command port to make the chip under test enter the test mode.

7. The chip test control circuit according to claim 6, characterized in that: The second logic circuit is an AND gate circuit, comprising: at least two input ports and one output port; Among them, one input port of the second logic circuit is connected to the output port of the first logic circuit, and another input port of the second logic circuit is connected to the test command port; the output port of the second logic circuit is used to output the third control signal.

8. The chip test control circuit according to claim 6, characterized in that: The first logic circuit is a transmission gate circuit, including: a control port, an input port and an output port; Among them, the control port of the second logic circuit is connected to the output port of the first logic circuit, the input port of the second logic circuit is connected to the test command port; and the output port of the second logic circuit is used to output the third control signal.

9. The chip test control circuit according to claim 1, characterized in that: The control circuit comprises: A voltage monitoring unit is connected to the test voltage pin and is used to monitor whether the test voltage meets the first voltage condition.

10. The chip test control circuit according to claim 9, characterized in that: The voltage monitoring unit comprises: at least one voltage comparator, each voltage comparator having two input ports and one output port; Among them, one input port of the voltage comparator is connected to the test voltage pin; another input port of the voltage comparator is used to access the reference voltage; and the output port of the voltage comparator is used to output the comparison result between the test voltage and the reference voltage.

11. The chip test control circuit according to claim 3, characterized in that: The control circuit comprises: A voltage cache unit is respectively connected to the test voltage pin and the test start module, and is used to cache the voltage connected to the test voltage pin, and output the first control signal or the second control signal after monitoring that the test start module inputs a test start signal or a test start command.

12. The chip test control circuit according to claim 11, characterized in that: The voltage cache unit includes: a latch, and the latch includes: a data input port, a clock signal input port and an output port; Among them, the data input port of the latch is connected to the test voltage pin for inputting the voltage connected to the test voltage pin; the clock signal input port of the latch is connected to the test start module for monitoring whether the test start module inputs the test start signal or the test start command; the output port output of the latch is used to output the first control signal or the second control signal.

13. A storage device, characterized in that: include: A memory and a chip test control circuit as claimed in any one of claims 1 to 11.

14. The storage device according to claim 13, characterized in that: The memory comprises: a memory chip and a substrate for packaging the memory chip; The test voltage pin and the control circuit are coupled to the substrate; the input end of the control circuit is electrically connected to the test voltage pin, and the output end of the control circuit is electrically connected to the memory chip.

15. A chip test control method, characterized in that: The method comprises: Monitor the test voltage connected to the test voltage pin; In response to the test voltage connected to the test voltage pin meeting a first voltage condition, a first control signal is output to enable the chip to start a test mode.

16. The chip test control method according to claim 15, characterized in that: After monitoring the test voltage connected to the test voltage pin, the method further includes: In response to the test voltage connected to the test voltage pin meeting a second voltage condition, a second control signal is output to turn off the test mode of the chip.

17. The chip test control method according to claim 15, characterized in that: In response to the test voltage connected to the test voltage pin meeting the first voltage condition, outputting a first control signal to enable the chip to start the test mode, including: In response to the test voltage connected to the test voltage pin satisfying a first voltage condition, monitoring whether a test start signal or a test start command for starting a chip test mode is received; When the test voltage satisfies a first voltage condition and the test start signal or the test start command is received, the first control signal is output to enable the chip to start a test mode.

18. The chip test control method according to claim 15, characterized in that: After outputting the first control signal to enable the chip to start a test mode, the method further includes: monitoring whether a test command for testing the chip is received; The chip is controlled to enter a test mode according to the test command.

19. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the chip test control method according to any one of claims 15 to 18 is implemented.

20. A computer program product comprising: A computer program or instruction, characterized in that when the computer program or instruction is executed by a processor, it implements the chip test control method described in any one of claims 15 to 18.

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