Data flashing method and device, electronic equipment and storage medium

Abstract

The invention relates to a data flashing method and device, electronic equipment and a storage medium. The method comprises the steps that in response to a data flashing instruction, a control unit is started; and in response to starting of the control unit, flashing the other starting address in the data flash memory and the corresponding program flash memory area based on starting of one starting address in the data flash memory and the corresponding program flash memory area. According to the data refreshing scheme, the backup starting address and the corresponding Bootloader are stored by means of the additional Dflash and the additional Pflash, self-updating of the Bootloader is achieved by refreshing the Dflash and the Pflash respectively, the situation that an ECU cannot operate due to the fact that the Bootloader fails to be refreshed is avoided, the refreshing sequence, redundancy and the like are designed, and the data refreshing stability and the refreshing speed are improved.

Description

Technical Field

[0001] The present disclosure generally relates to the field of computers, and in particular to a data flashing method, device, electronic device and storage medium. Background Art

[0002] With the rapid development of automobile electrification and intelligence, the development requirements of automobile software are increasing and becoming more complex. Automakers need to continuously upgrade and iterate ECU software to meet the increasingly diversified needs of the market, which also brings considerable challenges to ECU software flashing. Automakers have the need to upgrade software during the development and mass production stages of ECU. Usually, automakers define a set of specifications for flashing application software based on the industry standard UDS (Unified Diagnostic Services) diagnostic communication protocol, which is usually called Bootloader in the automotive industry.

[0003] The first user program executed after the ECU starts is the Bootloader. In the Bootloader, it will determine whether the Application program is valid to decide whether to jump to the Application program or stay in the Bootloader to run. The Bootloader is mainly used to flash the Application program, but in the development stage of the ECU or when there is a bug in the Bootloader, such as being unable to flash the application program, the Bootloader also needs to be updated. Since the Bootloader is the first user program executed after the chip starts, once the Bootloader fails to update and is damaged, it will cause the ECU to fail to start and the software cannot run.

[0004] In order to avoid the ECU from being unable to run due to a failure in flashing the Bootloader, there are two main Bootloader self-update flashing methods in the prior art according to different functional chips: (1) Enable the chip that supports the A / B partition function to implement flashing: Specifically, after enabling the A / B SWAP function, the chip's hardware Pflash is divided into two partitions of equal size, A and B, namely A-Bank and B-Bank. At the same time, only one Bank can be mapped to the CPU's executable space, which is called the active partition (Active Bank), and the other Bank is called the inactive partition (Inactive Bank). Executing the Bootloader software flashing is to flash the inactive partition in the currently running active partition. If the flashing is successful, the active and inactive partitions are switched to each other. After the ECU is restarted, the software starts running from the Bootloader of the new active partition. If the flashing fails, the partition switching is not performed, and the Bootloader of the current active partition is not damaged. The program is still executed in the current active partition, thereby ensuring that the Bootloader of the current active partition is complete at any time, and the ECU will not be unable to run due to a failure in flashing the Bootloader. (2) Use additional Pflash space to store the backup Bootloader for flashing: Since the chip needs to find the Bootloader entry address to run the Bootloader after power-on, the Bootloader entry address needs to be stored in the area where the chip stores the user program startup address. At the same time, the Bootloader also needs to include this area for storing the startup address. This ensures that after the Bootloader is flashed and restarted, the chip can find the Bootloader entry address at the location where the user program startup address is stored, and then jump to the Bootloader for execution; create two Bootloaders 0 and Bootloader 1 that back up each other. These two Bootloaders have the same functions but are stored in different Pflash locations.The entry address of Bootloader0 is stored in the first user startup address specified by the chip, and the entry address of Bootloader1 is stored in the second user startup address specified by the chip. Only one Bootloader can be executed at the same time, so it is necessary to ensure that at least one Bootloader exists. If both Bootloader0 and Bootloader1 exist, Bootloader0 is executed first; flashing Bootloader is to flash Bootloader to the backup area. Only when both Bootloaders exist can the currently executed Bootloader be flashed. This also ensures that whenever a flash failure occurs, there is a complete Bootloader, and the ECU will not be unable to run due to a failure to flash Bootloader. The flashing method of Bootloader update is implemented by flashing Bootloader and its entry address to the backup Pflash area. The area where the chip stores the Bootloader entry address is fixed on Pflash. Bootloader needs to include the Pflash area that stores the Bootloader entry address. In this way, after a Pflash flash, the chip can find the Bootloader startup address in the Pflash area that stores the Bootloader entry address, and then execute the updated Bootloader.

[0005] The flashing method of the first prior art requires the chip to support the A / B partition function, which is currently only supported by a few chips. In addition, this method sacrifices Pflash resources to achieve the A / B partition function, so this method is not applicable to projects that do not support the A / B partition function or occupy a large amount of Pflash resources. The flashing method of the second prior art is no longer applicable to chips whose user program startup address is not stored on Pflash. In addition, the refresh method of the prior art also has problems such as unstable data refresh and slow refresh speed, and cannot meet the update needs of autonomous driving vehicles. Summary of the invention

[0006] According to the example embodiments of the present disclosure, a flashing solution is provided to at least partially solve the problems existing in the prior art; in particular, for an ECU whose user program startup address is stored on Dflash and has large requirements for Pflash resources and cannot enable the A / B partition function, the technical problem of Bootloader self-update flashing is solved.

[0007] In a first aspect of the present disclosure, a data flashing method is provided, comprising: in response to a data flashing indication, a control unit starts; in response to the control unit starting, based on a startup address and a corresponding program flash memory area in a data flash memory, another startup address and a corresponding program flash memory area in the data flash memory are started and written.

[0008] In some embodiments, the method may also include: starting based on a startup address and a corresponding program flash area in the data flash memory, and flashing another startup address and a corresponding program flash area in the data flash memory, specifically: entering the first Bootloader in the program flash memory based on the first startup address in the data flash memory; erasing the program flash area storing the second Bootloader; erasing the data flash area storing the second Bootloader startup address; writing the new second Bootloader to the corresponding program flash area; writing the new second Bootloader startup address to the corresponding data flash area; erasing the data flash area storing the first Bootloader startup address.

[0009] In some embodiments, the method may also include: starting based on a startup address and a corresponding program flash area in the data flash memory, and flashing another startup address and a corresponding program flash area in the data flash memory, specifically: entering the second Bootloader in the program flash memory based on the second startup address in the data flash memory; erasing the program flash area storing the first Bootloader; erasing the data flash area storing the startup address of the first Bootloader; writing the new first Bootloader to the corresponding program flash area; writing the new first Bootloader startup address to the corresponding data flash area; erasing the data flash area storing the startup address of the second Bootloader.

[0010] In some embodiments, the method may further include: the data flash memory has a data flash memory area with two or more boot addresses, and the program flash memory has a program flash memory area with two or more bootloaders corresponding one-to-one to the two or more boot addresses.

[0011] In some embodiments, the method may also include: in response to the control unit being started, checking whether one of the two or more startup addresses to be executed is valid, if valid, starting from the corresponding program flash memory area, if invalid, checking whether the next startup address to be executed is valid, until normal startup or all addresses are invalid.

[0012] In some embodiments, the method may further include: when multiple booting and flashing are performed based on two or more boot addresses and corresponding program flash memory areas, booting and flashing are performed in a uniform order.

[0013] In some embodiments, the method may further include: when performing multiple boots and flashing based on multiple boot addresses and corresponding program flash memory areas, reserving an initial boot address and corresponding program flash memory area as redundancy, without flashing and performing the final boot.

[0014] In some embodiments, the method may further include: when performing multiple boots and flashing based on multiple boot addresses and corresponding program flash memory areas, reserving an initial boot address and a corresponding program flash memory area as redundancy, not flashing and performing the final boot; other boot addresses and corresponding program flash memory areas are booted and flashed in a uniform order.

[0015] In the second aspect of the present disclosure, a flashing device is provided, characterized in that it includes: an instruction acquisition module, which controls the control unit to start in response to a data flashing instruction; a flashing execution module, which starts based on a startup address and a corresponding program flash area in the data flash memory in response to the control unit starting, and flashes another startup address and a corresponding program flash area in the data flash memory; the flashing device is used to execute the parking method described in any embodiment of the first aspect of the present disclosure.

[0016] In a third aspect of the present disclosure, an electronic device is provided, comprising: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the method according to the first aspect of the present disclosure.

[0017] In a fourth aspect of the present disclosure, a computer-readable storage medium is provided, wherein a computer program is stored on the medium, and when the program is executed by a processor, the method according to the first aspect of the present disclosure is implemented.

[0018] In a fifth aspect of the present disclosure, a computer program product is provided, which includes a computer program / instructions, and when the computer program / instructions are executed by a processor, the method according to the first aspect of the present disclosure is implemented.

[0019] It should be understood that the contents described in the summary of the invention are not intended to limit the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements. The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure, wherein:

[0021] Figure 1 A schematic diagram illustrating an example environment in which various embodiments of the present disclosure can be implemented;

[0022] Figure 2 A schematic block diagram of a data flushing method according to multiple embodiments of the present disclosure is shown;

[0023] Figure 3 A schematic block diagram of a controller Bootloader memory according to multiple embodiments of the present disclosure is shown;

[0024] Figure 4 A schematic block diagram of a flashing process for updating a bootloader when an ECU runs on Bootloader0 according to multiple embodiments of the present disclosure is shown.

[0025] Figure 5 A schematic block diagram of a flashing process of updating a bootloader when an ECU runs on Bootloader1 according to multiple embodiments of the present disclosure is shown;

[0026] Figure 6 A schematic block diagram of controller software startup capable of implementing multiple embodiments of the present disclosure is shown.

[0027] Figure 7 A schematic block diagram of a data flushing device according to multiple embodiments of the present disclosure is shown;

[0028] Figure 8 A schematic block diagram of an electronic device capable of implementing various embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0029] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0030] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0031] ECU (Electronic Control Unit) is an electronic device used to control automobiles, machines and other equipment. ECU can monitor and control various parameters of the equipment, such as engine speed, vehicle speed, temperature, etc., and adjust these parameters according to preset programs and algorithms to ensure the normal operation of the equipment. ECU is usually composed of a microprocessor, memory, input / output interface and other related circuits. It can collect equipment status information through sensors and use this information to control the operation of actuators to achieve precise control of the equipment. With the continuous development of technology, the functions and performance of ECU are also constantly improving, providing stronger support for the intelligence and automation of equipment.

[0032] Distributed ECU means that each electronic control function of the car is controlled by multiple independent ECUs. These ECUs can be connected through a bus system and work together to realize the control function of the whole vehicle. The distributed ECU architecture can flexibly select suitable ECUs according to specific control function requirements and optimize the design. At the same time, it can improve the reliability of the system because each ECU can work independently. Even if an ECU fails, it will not affect the normal operation of other ECUs.

[0033] It should be understood that ECUs need to be flashed and upgraded because the upgrade can bring many benefits. For example, the upgrade can improve functions, fix vulnerabilities, and enhance vehicle performance and safety. Data flash upgrades can also add new functions to vehicles, optimize performance, solve compatibility issues, meet user needs, and enhance product competitiveness.

[0034] At present, the main chip of BMS is MCU (Microcontroller Unit) chip, that is, micro control unit chip. MCU chip is a chip-level computer that appropriately reduces the frequency and specifications of the central processing unit (CPU) and integrates peripheral interfaces such as counters, USB, A / D conversion, UART and driving circuits into a single chip.

[0035] Programs in MCU chips are usually stored in FLASH, which usually has multiple storage areas, and different areas are used to store different program data. Figure 1 The FLASH flash memory shown is allocated with "Bootloader area", "Running area" and "Backup area". The Bootloader area is used to verify the backup program. If the preset verification conditions are met, the backup program will replace the original application program to achieve the upgrade of the application program. The Running area is used to run the application program, and the Backup area is used to receive the upgrade data of the application program.

[0036] Pflash (program flash), also known as program flash in Chinese, is used to store code or data, which is the main flash.

[0037] Dflash (Data flash), Chinese name is data flash, usually FlexNVM, can be divided into EEPROM backup and Dataflash. If it is dataflash, it can coexist with the main flash and can be erased and written when the main program memory is running. It can be used to store bootloader code, address or large data blocks. Dflash and Pflash must be operated according to the flash command and erased according to the sector.

[0038] As mentioned above, the flashing in the prior art requires the chip to support the A / B partition function, which is currently only supported by a few chips, and this method sacrifices Pflash resources to achieve the A / B partition function, so this method of flashing is no longer applicable to projects that do not support the A / B partition function or occupy a large amount of Pflash resources; and the Bootloader flashing that uses additional Pflash space to store backups is no longer applicable to chips where the user program startup address is not stored on Pflash. In addition, the refresh method of the prior art also has problems such as unstable data refresh and slow refresh speed, which cannot meet the update needs of autonomous driving vehicles; therefore, in order to solve the above problems, it is urgent to provide an ECU that stores the user program startup address of the chip on Dflash, and has large requirements for Pflash resources and cannot enable the A / B partition function, to solve the technical problems of Bootloader self-update flashing, and to have a technical solution with stable data refresh and fast refresh speed.

[0039] The various embodiments of the present disclosure use additional Dflash and Pflash to store the backup startup address and the corresponding Bootloader, and implement Bootloader self-update by flashing Dflash and Pflash respectively, so as to avoid the ECU from being unable to operate due to the failure of flashing the Bootloader, and design the flashing order and redundancy, so as to improve the data refresh stability and refresh speed.

[0040] The following will combine Figures 1 to 8 Exemplary embodiments of the present disclosure are schematically introduced.

[0041] Figure 1 FIG. 1 shows a schematic diagram of a data flashing environment 100 according to an embodiment of the present disclosure. Figure 1As shown, in the environment 100 , an OTA cloud 102 is disposed on a vehicle 101 , the OTA cloud 102 can wirelessly communicate with an onboard computing device 103 , and the vehicle can include a plurality of ECUs or be communicatively coupled with a plurality of ECUs.

[0042] As mentioned above, the multiple ECUs may be various electronic control units on the vehicle 101, such as an engine control unit (ECU), a transmission control unit (TCU), a brake control unit (BCU), a body control unit (BCM), an in-vehicle entertainment system control unit (ECU), etc. The multiple ECUs may communicate with the in-vehicle computing device 103 via wired or wireless means. In a preferred embodiment, the multiple ECUs communicate with the in-vehicle computing device 103 via Ethernet.

[0043] In some embodiments, vehicle 101 may be any type of vehicle that can carry people and / or objects and move through a power system such as an engine, including but not limited to cars, trucks, buses, electric vehicles, motorcycles, RVs, trains, etc. In some embodiments, one or more vehicles in environment 100 may be vehicles with certain autonomous driving capabilities, which are also referred to as unmanned vehicles. In some embodiments, a vehicle may also be a vehicle without autonomous driving capabilities.

[0044] In one embodiment, the data flashing may be a data file used to update the software, firmware or parameters of multiple ECUs on the vehicle 101. After the OTA upgrade file is downloaded, it may be distributed to multiple ECUs on the vehicle 101 for flashing.

[0045] In one embodiment, OTA cloud 102 may be a cloud computing platform for storing and managing OTA upgrade files and wirelessly communicating with computing devices. OTA cloud 102 may provide a user interface for users to upload OTA upgrade files and distribute them to computing devices for upgrading.

[0046] In one embodiment, the computing device is a mobile device such as a smartphone, a personal digital assistant, a tablet computer, a wearable device, an in-vehicle electronic device, an edge computing device, etc., but the present disclosure is not limited to this.

[0047] like Figure 1 As shown, the computing device 103 can interact and control the OTA cloud 102 to download OTA upgrade files from the OTA cloud 102 and upgrade multiple ECUs.

[0048] In some embodiments, continue to refer to Figure 1, the vehicle 101 can be communicatively coupled to the computing device 103. Although shown as a separate entity, the computing device 103 can be embedded in the vehicle 101. The computing device 103 can also be an entity external to the vehicle 101 and can communicate with the vehicle 101 via a wireless network. The computing device 103 can be any device with computing capabilities. As a non-limiting example, the computing device 103 can be any type of fixed computing device, mobile computing device, or portable computing device, including but not limited to a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet computer, a multimedia computer, a mobile phone, etc.; all or part of the components of the computing device 103 can be distributed in the cloud. The computing device 103 includes at least a processor, a memory, and other components that are typically present in a general-purpose computer to implement computing, storage, communication, control, and the like. The computing device 103 can perform all or part of the operations according to the various embodiments of the present disclosure, which will be described in detail below.

[0049] It should be noted that the above environment 100 is merely exemplary and does not constitute a limitation to the present disclosure. The above vehicle 101 is also merely exemplary and may not be limited to vehicles. The vehicle 101 may also be any device that requires data flashing, such as a ship, an airplane, etc., or a processing device, such as various CNC machine tools, CNC machines, etc. In short, the vehicle 101 can be broadly interpreted as a device or apparatus, specifically a device that requires data flashing, especially a device or apparatus that has an electronic control unit (ECU) and requires data flashing.

[0050] Figure 2 FIG. 2 shows a schematic block diagram of a data flashing method 200 according to an embodiment of the present disclosure. For example, the method 200 may be performed as follows: Figure 1 The method 200 is executed by the computing device 103 shown. It should be understood that the method 200 may also include additional blocks not shown and / or may omit the blocks shown, and the scope of the present disclosure is not limited in this respect.

[0051] exist Figure 2 In the illustrated embodiment, a data flashing method is provided, including: in box 201, in response to a data flashing indication, a control unit (ECU) starts; in box 202, in response to the control unit (ECU) starting, based on a startup address in a data flash memory (Dflash) and a corresponding program flash memory (Pflash) area, another startup address in the data flash memory and a corresponding program flash memory area are started, and flashed.

[0052] In some embodiments, the method may also include: starting based on a startup address and a corresponding program flash area in the data flash memory, and flashing another startup address and a corresponding program flash area in the data flash memory, specifically: entering the first Bootloader (Bootloader0) in the program flash memory based on the first startup address in the data flash memory; erasing the program flash area storing the second Bootloader; erasing the data flash area storing the startup address of the second Bootloader (Bootloader1); writing the new second Bootloader to the corresponding program flash area; writing the new second Bootloader startup address to the corresponding data flash area; erasing the data flash area storing the startup address of the first Bootloader.

[0053] Figure 4 A schematic block diagram of the flashing process of updating the bootloader when the ECU runs on Bootloader0 according to an embodiment of the present disclosure is shown. The system working process is schematically described in combination with the schematic block diagram. The process is not intended to limit the implementation of the present disclosure described and / or required in other embodiments, and is only a schematic description of the execution method.

[0054] Combination Figure 4 , schematically describes the flashing process of updating the bootloader when the ECU is running on Bootloader0. (0) After the ECU is started, it enters bootloader0 from the startup address 1; (1) Then erase the Pflash area of ​​Bootloader1; (2) Then erase the Dflash area that stores the startup address of Bootloader1; (3) Then write the new Bootloader1 to the corresponding Pflash area; (4) Then write the new startup address of Bootloader1 to the corresponding Dflash area; (5) Then erase the Dflash area that stores the startup address of Bootloader0. Among them, steps (1) to (4) are to flash bootloader1 and its startup address to the corresponding Pflash and Dflash, and step (6) is to destroy the startup address of Bootloader0 so that after the software is started, it can enter Bootloader1 and run through the startup address 2 in Dflash. No matter which step of the above flashing fails, the software has at least one Bootloader and startup address that are valid, so there will be no problem of flashing failure and software startup failure and inability to run.

[0055] In some embodiments, the method may also include: starting based on a startup address and a corresponding program flash area in the data flash memory, and flashing another startup address and a corresponding program flash area in the data flash memory, specifically: entering the second Bootloader in the program flash memory based on the second startup address in the data flash memory; erasing the program flash area storing the first Bootloader; erasing the data flash area storing the first Bootloader startup address; writing the new first Bootloader to the corresponding program flash area; writing the new first Bootloader startup address to the corresponding data flash area; erasing the data flash area storing the second Bootloader startup address.

[0056] Figure 5 A schematic block diagram of the flashing process of updating the bootloader when the ECU runs on Bootloader1 according to an embodiment of the present disclosure is shown. The system working process is schematically described in combination with the schematic block diagram. The process is not intended to limit the implementation of the present disclosure described and / or required in other embodiments, and is only a schematic description of the execution method.

[0057] Combination Figure 5 , schematically describes the flashing process of updating the bootloader when the ECU is running on Bootloader1. (0) After the ECU is started, it enters bootloader1 from the startup address 1; (1) Then erase the Pflash area of ​​Bootloader0; (2) Then erase the Dflash area that stores the startup address of Bootloader0; (3) Then write the new Bootloader0 to the corresponding Pflash area; (4) Then write the new startup address of Bootloader0 to the corresponding Dflash area. Among them, steps (1) to (4) are to flash bootloader0 and its startup address to the corresponding Pflash and Dflash. After the ECU is restarted, it will enter Bootloader0 to run through the startup address 1 in Dflash. The flashing of Bootloader1 lacks the step of erasing the current startup address of Dflash compared to the flashing of Bootloader0, because when the chip starts, it defaults to executing the user program at the startup address 1 of Dflash first, such as Figure 4 As shown. Similarly, no matter which step of the above fails to flash, at least one Bootloader and startup address of the software is valid, so there will be no problem of flash failure and software startup failure and inability to run.

[0058] In some embodiments, the method may further include: the data flash memory has a data flash memory area with two or more boot addresses, and the program flash memory has a program flash memory area with two or more bootloaders corresponding to the two or more boot addresses.

[0059] Figure 3 A schematic block diagram of a controller Bootloader memory according to an embodiment of the present disclosure is shown, and the system working process is schematically described in combination with the schematic block diagram. The process is not intended to limit the implementation of the present disclosure described and / or required in other embodiments, and is only a schematic description of the execution method.

[0060] Combination Figure 3 , schematically describes the memory layout of the ECU Bootloader software. Before flashing, Bootloader0 (the first Bootloader) and Bootloader1 (the second Bootloader) have the same functions, but the storage Pflash area is different. The entry addresses of Bootloader0 and Bootloader1 are stored in the corresponding Dflash area respectively. After the ECU is started, the corresponding Bootloader software can be executed according to the startup address stored in the Dflash area.

[0061] In some embodiments, the method may also include: in response to the control unit starting, checking whether one of the two or more startup addresses to be executed is valid, if valid, starting from the corresponding program flash area, if invalid, checking whether the next startup address to be executed is valid, until normal startup or all addresses are invalid.

[0062] Figure 6 A schematic block diagram of controller software startup according to an embodiment of the present disclosure is shown, and the system working process is schematically described in combination with the schematic block diagram. The process is not intended to limit the implementation of the present disclosure described and / or required in other embodiments, and is only a schematic description of the execution method.

[0063] Combination Figure 6 , schematically describes the schematic process of controller software startup. After the ECU is started, it first searches for the startup address 1 in the Dflash area. If the startup address 1 is invalid, it continues to search for the startup address 2 in the Dflash area. As long as a valid startup address is found, it jumps to the address to execute the corresponding Bootloader program. If there is no valid startup address, the ECU startup fails and the software cannot run.

[0064] In some embodiments, the method may further include: when multiple booting and flashing are performed based on two or more boot addresses and corresponding program flash memory areas, booting and flashing are performed in a uniform order. That is, in this embodiment, booting and flashing are no longer performed in a default manner, but in a compiled or compilable manner.

[0065] In some embodiments, the method may further include: when performing multiple boots and flashing based on multiple boot addresses and corresponding program flash memory areas, reserving an initial boot address and corresponding program flash memory area as redundancy, without flashing and performing the final boot.

[0066] In some embodiments, the method may further include: when multiple boots and flashes are performed based on multiple boot addresses and corresponding program flash memory areas, an initial boot address and a corresponding program flash memory area are reserved as redundancy, and are not flashed and used as the final boot; other boot addresses and corresponding program flash memory areas are booted and flashed in a uniform order. For example, the first boot is from boot address 1 and the corresponding program flash memory area, and boot address 2 (3, 4...) and the corresponding program flash memory area are flashed; the next time the flash is performed, boot from boot address 2 (3, 4...) and the corresponding program flash memory area, and boot address 1 and the corresponding program flash memory area are flashed, and so on, booting and flashing are performed in a uniform order.

[0067] In some embodiments, the method may further include: when multiple boots and flashes are performed based on multiple boot addresses and corresponding program flash memory areas, the number of boots and flashes for each boot address and the corresponding program flash memory area is counted, and boot and flash allocation is performed based on the counting result. A counting threshold may also be set, and an alarm is issued when the threshold is exceeded.

[0068] By using additional Dflash and Pflash, which are used to store the Bootloader and its startup address respectively, and using Bootloader0 and Bootloader1, which back up each other, to flash each other, the Bootloader self-update is realized. For the ECU whose user program startup address is stored in Dflash and has high requirements for Pflash resources and cannot enable the A / B partition function, this flashing method can not only realize the Bootloader self-update but also avoid the problem of ECU software startup failure and inability to run due to failure to flash the Bootloader.

[0069] In order to improve the efficiency and security of data transmission, compression flashing technology can be used. Through data compression transmission, bandwidth utilization can be effectively increased, and the amount of data transmission between the flashing tool and the ECU can be reduced, thereby significantly shortening the ECU upgrade time. In addition, in order to enhance the security and confidentiality of data, data transmission can also be encrypted. The request download service (SID = 0x34) and the request file transfer service (0x38) define that data can be transmitted based on compression and encryption.

[0070] The download request service (0x34) allows data to be transmitted in a compressed and encrypted manner. In the request message format of this service, "dataFormatIdentifier" is a key parameter with a size of 1 byte, of which the upper four bits (bit4-bit7) are the parameter "compressionMethod", which defines whether the data needs to be compressed, and the lower four bits (bit0-bit3) are the parameter "encryptingMethod", which defines whether the data needs to be encrypted. If the downloaded data does not need to be compressed or encrypted, the parameter value is 0x00. If a non-0x00 value is used, it means that the downloaded data needs to be compressed, encrypted, or both. If the value of "dataFormatIdentifier" is 0x10, it means that the downloaded data needs to be compressed but not encrypted. If the value of "dataFormatIdentifier" is 0x11, it means that the downloaded data needs to be compressed and encrypted.

[0071] The download request service (0x34) allows data to be transmitted in a compressed and encrypted manner. In the request message format of this service, "dataFormatIdentifier" is a key parameter with a size of 1 byte, of which the upper four bits (bit4-bit7) are the parameter "compressionMethod", which defines whether the data needs to be compressed, and the lower four bits (bit0-bit3) are the parameter "encryptingMethod", which defines whether the data needs to be encrypted. If the downloaded data does not need to be compressed or encrypted, the parameter value is 0x00. If a non-0x00 value is used, it means that the downloaded data needs to be compressed, encrypted, or both. If the value of "dataFormatIdentifier" is 0x10, it means that the downloaded data needs to be compressed but not encrypted. If the value of "dataFormatIdentifier" is 0x11, it means that the downloaded data needs to be compressed and encrypted.

[0072] Software flashing can choose to burn the software program or transfer it to a specific address segment of the ECU chip memory through UDS flashing, and then the ECU will run the software program to realize its unique functions. Common ECU flashing file formats are: .hex, .s19 and .bin, etc. Compressed flashing files are made through a specific compression algorithm.

[0073] Flashing can be done with compression or without compression. Compression is done for each logical block independently, and there is also a "compression as a whole" method. The number of logical blocks in the flash file does not change before and after compression, the starting address does not change, the data length of each logical block becomes smaller, and the corresponding end address also changes.

[0074] In some embodiments, a TSMaster-based UDS diagnostic flash may be selected.

[0075] The present invention may not be limited to automatic flashing or manual flashing, that is, it also has another independent embodiment, a data flashing method, comprising: starting based on a startup address and a corresponding program flash (Pflash) area in a data flash memory (Dflash), and flashing another startup address and a corresponding program flash area in the data flash memory.

[0076] Figure 7 FIG. 7 is a schematic block diagram of a data flushing device 700 according to an embodiment of the present disclosure. Figure 7 As shown, the device 700 includes: an instruction acquisition module 701, which controls the start-up of a control unit in response to a data flash instruction; a flash execution module 702, which starts based on a startup address and a corresponding program flash area in the data flash memory in response to the start-up of the control unit, and flashes another startup address and a corresponding program flash area in the data flash memory; the flash device is used to execute the method of any of the aforementioned embodiments.

[0077] In some embodiments, the device 700 is also configured to: enter the first Bootloader in the program flash memory based on the first boot address in the data flash memory; erase the program flash memory area storing the second Bootloader; erase the data flash memory area storing the second Bootloader boot address; write the new second Bootloader to the corresponding program flash memory area; write the new second Bootloader boot address to the corresponding data flash memory area; erase the data flash memory area storing the first Bootloader boot address.

[0078] In some embodiments, the device 700 is also configured to: enter the second Bootloader in the program flash memory based on the second boot address in the data flash memory; erase the program flash memory area storing the first Bootloader; erase the data flash memory area storing the first Bootloader boot address; write the new first Bootloader to the corresponding program flash memory area; write the new first Bootloader boot address to the corresponding data flash memory area; erase the data flash memory area storing the second Bootloader boot address.

[0079] In some embodiments, the apparatus 700 is further configured as follows: the data flash memory has a data flash memory area with two or more boot addresses, and the program flash memory has a program flash memory area with two or more bootloaders corresponding one-to-one to the two or more boot addresses.

[0080] In some embodiments, the device 700 is also configured to: in response to the control unit being started, check whether one of the two or more startup addresses to be executed is valid; if so, start from the corresponding program flash memory area; if not, check whether the next startup address to be executed is valid, until normal startup or all addresses are invalid.

[0081] In some embodiments, the apparatus 700 is further configured to: when multiple booting and flashing are performed based on two or more booting addresses and corresponding program flash memory areas, booting and flashing are performed in a uniform order.

[0082] In some embodiments, the device 700 is also configured to: when multiple boots and flashes are performed based on multiple boot addresses and corresponding program flash memory areas, an initial boot address and a corresponding program flash memory area are reserved as redundancy, and are not flashed and used as the final boot; other boot addresses and corresponding program flash memory areas are booted and flashed in a uniform order.

[0083] Combination Figure 3 , may be in an independent embodiment, a device comprising: a data flash memory having a data flash memory area with two or more boot addresses; a program flash memory having a program flash memory area with two or more bootloaders corresponding one-to-one to the two or more boot addresses. Figure 3The memory layout of the ECU Bootloader software in this independent embodiment is schematically described. Before flashing, Bootloader0 (the first Bootloader) and Bootloader1 (the second Bootloader) have the same functions, but the storage Pflash areas are different. The entry addresses of Bootloader0 and Bootloader1 are respectively stored in the corresponding Dflash areas. After the ECU is started, the corresponding Bootloader software can be executed according to the startup address stored in the Dflash area.

[0084] In another embodiment of the present disclosure, an electronic device is provided, which includes: one or more processors; and a storage device for storing one or more programs, and when the one or more programs are executed by the one or more processors, the one or more processors implement the method according to the first aspect of the present disclosure.

[0085] In another embodiment of the present disclosure, a computer-readable storage medium is provided, wherein a computer program is stored on the medium, and when the program is executed by a processor, the method according to the first aspect of the present disclosure is implemented.

[0086] Figure 8 800 is a schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present disclosure. The electronic device 800 can be used to implement Figure 2 The operations in the method 200 shown may be used to at least partially implement Figure 1 103 shown in . Electronic device 800 is intended to represent various forms of digital computers, such as car computers, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0087] like Figure 8 As shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0088] A number of components in the device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0089] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as method 200. For example, in some embodiments, the method 200 may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of the method 200 described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform the method 200 in any other appropriate manner (e.g., by means of firmware).

[0090] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0091] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0092] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0093] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0094] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0095] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship between the client and the server is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services ("Virtual Private Server", or "VPS" for short). The server may also be a server of a distributed system, or a server combined with a blockchain.

[0096] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable image scaling device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, the instruction device being implemented in the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0097] It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can also be loaded onto a computer or other programmable image scaling device, so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0098] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0099] The technical effects of the present disclosure should not be limited to the description in this article, but should also cover what can be reasonably judged by those skilled in the art based on the scheme of the present disclosure, which is not elaborated in this article.

[0100] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A data flashing method, comprising: In response to the data flushing instruction, the control unit is started; as well as In response to the control unit starting up, based on a start-up address in the data flash memory and a corresponding program flash memory area, another start-up address in the data flash memory and a corresponding program flash memory area are flashed.

2. The method according to claim 1, characterized in that In response to the control unit starting up, based on a start-up address and a corresponding program flash memory area in the data flash memory, flashing another start-up address and a corresponding program flash memory area in the data flash memory comprises: Enter the first Bootloader in the program flash memory based on the first boot address in the data flash memory; erase the program flash memory area storing the second Bootloader; erase the data flash memory area storing the second Bootloader startup address; write the new second Bootloader to the corresponding program flash memory area; write the new second Bootloader startup address to the corresponding data flash memory area; erase the data flash memory area storing the first Bootloader startup address.

3. The method according to claim 1, characterized in that In response to the control unit starting up, based on a start-up address and a corresponding program flash memory area in the data flash memory, flashing another start-up address and a corresponding program flash memory area in the data flash memory comprises: Enter the second Bootloader in the program flash memory based on the second boot address in the data flash memory; erase the program flash memory area storing the first Bootloader; erase the data flash memory area storing the first Bootloader boot address; write the new first Bootloader to the corresponding program flash memory area; write the new first Bootloader boot address to the corresponding data flash memory area; erase the data flash memory area storing the second Bootloader boot address.

4. The method according to any one of claims 1 to 3, characterized in that: The data flash memory has data flash memory areas with two or more startup addresses, and the program flash memory has two or more Bootloader program flash memory areas corresponding to the two or more startup addresses one by one.

5. The method according to any one of claims 1 to 3, characterized in that: In response to the data flushing instruction, the control unit starts and further includes: In response to the control unit being started, checking whether one of the two or more start addresses to be executed is valid; If valid, boot from the corresponding program flash area; If it is invalid, check whether the next startup address to be executed is valid until it starts normally or all addresses are invalid.

6. The method according to any one of claims 1 to 3, characterized in that: Also includes: When multiple boot and flash are performed based on two or more boot addresses and corresponding program flash memory areas, the boot and flash are performed in an even order.

7. The method according to any one of claims 1 to 3, characterized in that: Also includes: When multiple boots and flashes are performed based on multiple boot addresses and corresponding program flash memory areas, an initial boot address and a corresponding program flash memory area are reserved as redundancy, and are not flashed or used as the final boot; The other boot addresses and corresponding program flash memory areas are booted and flashed in an even order.

8. A parking device, characterized in that: include: The instruction acquisition module is configured to control the start-up of the control unit in response to the data flashing instruction; A flash execution module, in response to the control unit starting up, starts based on a startup address and a corresponding program flash memory area in the data flash memory, and flashes another startup address and a corresponding program flash memory area in the data flash memory; the flash execution module is used to execute the method described in any one of claims 1 to 7.

9. An electronic device, comprising: one or more processors; as well as A storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, enables the one or more processors to implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, wherein the program, when executed by a processor, implements the method according to any one of claims 1 to 7.

Images