Method, device, computer device and system for implementing memory sharing control

Abstract

A method, device, computer device and system for realizing memory sharing control to improve utilization of memory resources. The computer device is provided with a memory sharing control device between a processor and a memory pool, and the processor accesses the memory pool through the memory sharing control device. Different processing units, such as processors or cores in the processors, access at least one memory in the memory pool at different time periods, so that the memory is shared by multiple processing units, thereby improving the utilization of memory resources.

Description

[0001] This application is a divisional application, the original application number is 202110351637.5, the original application date is March 31, 2021, and the entire contents of the original application are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of information technology, and in particular to a method, device and system for controlling shared memory. BACKGROUND

[0003] With the popularization of big data technology, the demand for computing resources in various fields is increasing day by day. Large-scale computing represented by applications such as graph computing and deep learning represents the latest development direction of applications. At the same time, with the slowing down of semiconductor process development, applications have been unable to continuously obtain scalable performance improvement from processor upgrades, and multi-core-based processors have gradually become mainstream.

[0004] Multi-core processor systems have increasing demands for memory capacity. As an indispensable important component in servers, the cost of memory accounts for about 30-40% of the total system cost of servers. Improving the utilization of memory is an important means to reduce the total cost of operations (TCO). SUMMARY

[0005] The present application provides a method for implementing memory sharing control, a device, a computer device and a system for implementing memory sharing control to improve the utilization of memory resources.

[0006] In a first aspect, the present application provides a computer device, comprising at least two processing units, a memory sharing control device and a memory pool, the processing units being processors, cores in processors or combinations of cores in processors, and the memory pool comprising one or more memories;

[0007] The at least two processing units are coupled to the memory sharing control device;

[0008] The memory sharing control device is configured to allocate memories from the memory pool to the at least two processing units respectively, and at least one memory in the memory pool can be accessed by different processing units at different time periods;

[0009] The at least two processing units are configured to access the allocated memories through the memory sharing control device.

[0010] The at least two processing units in the computer device can access at least one memory in the memory pool at different time periods through the memory sharing control device, and the sharing of memories by multiple processing units can be achieved, thereby improving the utilization of memory resources.

[0011] Optionally, the at least one memory in the memory pool can be accessed by different processing units in different time periods, which means that any two processing units in the at least two processing units can access the at least one memory in the memory pool in different time periods, respectively. For example, the at least two processing units include a first processing unit and a second processing unit. In a first time period, a first memory in the memory pool is accessed by the first processing unit, and the second processing unit cannot access the first memory. In a second time period, the first memory in the memory pool is accessed by the second processing unit, and the first processing unit cannot access the first memory. Optionally, the processor can be a central processing unit (CPU), and one CPU can include two or more cores.

[0012] Optionally, one processing unit in the at least two processing units can be one processor, a core in one processor, a combination of multiple cores in one processor, or a combination of multiple cores in different processors. Taking the combination of multiple cores in one processor as one processing unit or taking the combination of multiple cores in different processors as one processing unit can meet the access of the same memory by multiple different cores when the multiple different cores perform tasks in parallel in a parallel computing scenario, and can improve the efficiency of the multiple different cores when performing parallel computing.

[0013] Optionally, the memory sharing control device can allocate memories in the memory pool to the at least two processing units according to a control instruction received from an operating system in the computer device. Specifically, a driver in the operating system can send a control instruction for allocating memories in the memory pool to the at least two processing units to the memory sharing control device through a dedicated channel. The operating system is implemented by a CPU in the computer device by executing relevant codes. The CPU running the operating system has a privilege mode, in which the driver in the operating system can send a control instruction to the memory sharing control device through a dedicated or specific channel.

[0014] Optionally, the memory sharing control device can be implemented by a field programmable gate array (FPGA) chip, an application-specific integrated circuit (ASIC), or other similar chips. An ASIC chip has a circuit function defined at the initial design, and has the characteristics of high chip integration, easy implementation of mass production, low single-chip cost, small size, and the like.

[0015] In some possible implementation manners, the at least two processing units and the memory sharing control device are connected through a serial bus;

[0016] The first processing unit of the at least two processing units is configured to send a first memory access request in the form of a serial signal to the memory sharing device through the serial bus, and the first memory access request is used to access a first memory allocated to the first processing unit.

[0017] The serial bus has the characteristics of high bandwidth and low latency, and the at least two processing units and the memory sharing control device are connected through the serial bus, which can ensure the efficiency of data transmission between the processing units and the memory sharing control device.

[0018] Optionally, the serial bus is a memory semantic bus. The memory semantic bus includes but is not limited to a bus based on a quick path interconnect (QPI), a peripheral component interconnect express (PCIe), a Huawei Cache Coherence System (HCCS), or a compute express link (CXL) protocol interconnection.

[0019] Optionally, the first processing unit generates a memory access request in the form of a parallel signal. The first processing unit can convert the memory access request in the form of a parallel signal into a first memory access request in the form of a serial signal through an interface capable of realizing conversion between a parallel signal and a serial signal, for example, a Serdes interface, and send the first memory access request to the memory sharing device through the serial bus.

[0020] In some possible implementation manners, the memory sharing control device includes a processor interface, and the processor interface is configured to:

[0021] receive the first memory access request;

[0022] convert the first memory access request into a second memory access request in the form of a parallel signal.

[0023] The processor interface converts the first memory access request into a second memory access request in the form of a parallel signal, which can enable the memory sharing control device to access the first memory and realize memory sharing without changing the framework of an existing memory access architecture.

[0024] Optionally, the processor interface is an interface capable of realizing parallel signal and serial signal conversion, for example, can be a Serdes interface.

[0025] In some possible implementation manners, the memory sharing control device comprises a control unit, and the control unit is configured to:

[0026] establish a correspondence between the memory address of the first memory and a first processing unit in the at least two processing units, so as to allocate the first memory to the first processing unit from the memory pool.

[0027] Optionally, the correspondence between the memory address of the first memory and the first processing unit can be dynamically adjusted. For example, the correspondence between the memory address of the first memory and the first processing unit can be dynamically adjusted on demand.

[0028] Optionally, the memory address of the first memory can be a continuous physical memory address in the memory pool. The continuous physical memory address in the memory pool can simplify the management of the first memory. Of course, the memory address of the first memory can also be several discontinuous physical memory addresses in the memory pool.

[0029] Optionally, the memory address information of the first memory comprises a start address of the first memory and a size of the first memory. The first processing unit has an identifier, and the establishment of the correspondence between the memory address of the first memory and the first processing unit can be the establishment of the correspondence between the unique identifier of the first processing unit and the memory address information of the first memory.

[0030] In some possible implementation manners, the memory sharing control device comprises a control unit, and the control unit is configured to:

[0031] virtually create a plurality of virtual memory devices from the memory pool, wherein a first virtual memory device in the plurality of virtual memory devices corresponds to the first memory;

[0032] allocate the first virtual memory device to the first processing unit. Optionally, the virtual memory device corresponds to a continuous physical memory address in the memory pool. The virtual memory device corresponding to the continuous physical memory address in the memory pool can simplify the management of the virtual memory device. Of course, the virtual memory device can also correspond to several discontinuous physical memory addresses in the memory pool.

[0033] Optionally, the first virtual memory device can be assigned to the first processing unit by establishing an access control table. For example, the access control table can include the identification of the first processing unit, the identification of the first virtual memory device, the start address and size of the memory corresponding to the first virtual memory device, and the like. The access control table can also include the permission information of the first processing unit accessing the first virtual memory device, the attribute information of the memory to be accessed (including but not limited to information whether it is a persistent memory), and the like.

[0034] In some possible implementation manners, the control unit is further configured to:

[0035] when the preset condition is met, cancel the correspondence between the first virtual memory device and the first processing unit;

[0036] establish the correspondence between the first virtual memory device and a second processing unit of the at least two processing units.

[0037] Optionally, the correspondence between the virtual memory device and the processing unit can be dynamically adjusted according to the demand of the at least two processing units for the memory resource.

[0038] By dynamically adjusting the correspondence between the virtual memory device and the processing unit, the demand of different processing units for the memory resource in different service scenarios can be flexibly adapted, and the utilization rate of the memory resource can be improved.

[0039] Optionally, the preset condition can be that the demand of the first processing unit for accessing the memory decreases, and the demand of the second processing unit for accessing the memory increases.

[0040] Optionally, the control unit is further configured to:

[0041] when the preset condition is met, cancel the correspondence between the first memory and the first virtual memory device; establish the correspondence between the first memory and a second virtual memory device of the plurality of virtual memory devices; and assign the second virtual memory device to a second processing unit of the at least two processing units. In this case, the correspondence between the virtual memory device and the physical memory address in the memory pool does not need to be changed, and only the correspondence between the virtual memory device and different processing units needs to be changed, so that the same physical memory can be accessed by different processing units at different time periods.

[0042] In some possible implementation manners, the memory sharing control device further includes a cache unit, which is configured to cache the data read by any one of the at least two processing units from the memory pool, or cache the data discarded by any one of the at least two processing units.

[0043] Through the cache unit, the efficiency of the processing unit accessing the memory data can be further improved.

[0044] Optionally, the cache unit can include a first-level cache and a second-level cache. The first-level cache can have a small capacity but a higher read-write speed than the second-level cache. For example, the first-level cache can be a cache with a size of 100 million bytes (MB) and a speed of nanoseconds. The second-level cache can have a large capacity but a lower read-write speed than the first-level cache. For example, the second-level cache can be a dynamic random access memory (DRAM) with a size of 1 gigabyte (GB). Through the first-level cache and the second-level cache, the space of the cache can be increased while the speed of the processor accessing the data through the cache is improved, and the range of the processor quickly accessing the memory through the cache is expanded, so that the rate of the processor resource pool accessing the memory is further improved as a whole.

[0045] Optionally, the data in the memory can be first cached in the second-level cache, and then the data in the second-level cache can be cached in the first-level cache according to the needs of the processing unit for the memory data. The data that is discarded or temporarily not needed for processing in the processing unit can also be cached in the first-level cache. To ensure that the first-level cache has enough space for other processing units to cache data, the data discarded by the processing unit in part of the first-level cache can be cached in the second-level cache unit.

[0046] In some possible implementation manners, the memory sharing control device further includes a prefetch engine configured to prefetch data required to be read by any one of the at least two processing units from the memory pool and cache the data in the cache unit.

[0047] Optionally, the prefetch engine can use a specific algorithm or an artificial intelligence (AI) algorithm to realize intelligent data prefetching, so as to further improve the efficiency of the processing unit accessing the memory data.

[0048] In some possible implementation manners, the memory sharing control device further comprises a quality of service (Qos) engine, which is configured to implement optimized storage of data required to be cached by any one of the at least two processing units in the cache unit. Through the Qos engine, different processing units can have different caching capabilities for accessing data in the memory in the cache unit 304. For example, a memory access request initiated by a processing unit with high priority has exclusive caching space in the cache unit 304, so that the data accessed by the processing unit can be cached in time, thereby ensuring the quality of service processing of the processing unit.

[0049] In some possible implementation manners, the memory sharing control device further comprises a compression / decompression engine, which is configured to implement compression or decompression of the data related to memory access.

[0050] Optionally, the function of the compression / decompression engine can be turned off.

[0051] The compression / decompression engine can compress data written into the memory by the processing unit by a compression ratio algorithm with a granularity of 4 kilobit (KB) per page, and then write the compressed data into the memory; or when the processing unit reads compressed data in the memory, the data to be read is decompressed and then sent to the processor. In this way, the data transmission rate can be improved, and the efficiency of the processing unit accessing data in the memory can be further improved. Optionally, the compression / decompression engine can be turned off.

[0052] Optionally, the memory sharing control device further comprises a storage unit, which comprises software codes of at least one of the Qos engine, the prefetch engine, and the compression / decompression engine. The memory sharing control device can read the codes in the storage unit to implement corresponding functions.

[0053] Optionally, at least one of the Qos engine, the prefetch engine, and the compression / decompression engine can be implemented through control logic of the memory sharing control device.

[0054] In some possible implementation manners, the first processing unit further has a local memory, which is configured to be accessed by the first processing unit. Optionally, the first processing unit can preferentially access the local memory. The first processing unit can access the local memory at a faster speed, so that the speed of the first processing unit accessing the memory can be further improved.

[0055] In some possible implementations, the plurality of memories included in the memory pool belong to different media types. For example, at least one of the following memory media can be included in the memory pool: DRAM, phase change memory (PCM), storage class memory (SCM), static random access memory (SRAM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), NAND FLASH Memory, spin-torque transfer read only memory (STT-RAM), or resistor read only memory (RRAM). A dual in-line memory module (DIMM) or a solid state disk (SSD) can also be included in the memory pool.

[0056] Different memory media can be used to meet the memory resource requirements of different processing units for different services. For example, DRAM has the characteristics of fast read-write speed and volatility, and the memory of DRAM can be allocated to a processing unit that initiates hot data access; and PCM has the characteristic of non-volatility, and the memory of PCM can be allocated to a processing unit that accesses data that needs to be saved for a long time. In this way, the flexibility of memory access control can be improved while sharing memory resources.

[0057] For example, the memory pool includes volatile DRAM storage medium and non-volatile PCM storage medium, the DRAM and the PCM in the memory pool can be a parallel architecture, and the DRAM and the PCM have no seniority; or the memory pool can be a non-parallel architecture in which the DRAM is used as a cache and the PCM is used as a main memory, the DRAM can be used as a first-level storage medium, and the PCM can be used as a second-level storage medium. For the parallel architecture of the DRAM and the PCM, the control unit can store hot data with a high access frequency on the DRAM, that is, the control unit can establish a corresponding relationship between a processing unit that initiates access to the hot data with the high access frequency and a virtual memory device corresponding to the memory of the DRAM, so that the read / write speed of the memory data and the service life of the main memory system can be improved. The control unit can also establish a corresponding relationship between a processing unit that initiates access to cold data with a low access frequency and a virtual memory device corresponding to the memory of the PCM, and store the cold data with the low access frequency on the PCM, so that the safety of important data can be ensured by using the non-volatile feature of the PCM. For the non-parallel architecture of the DRAM and the PCM, the control unit can use the PCM as a main memory to store various data and use the DRAM as a cache, so that the efficiency and performance of memory access can be further improved by using the high integration of the PCM and the low read / write delay of the DRAM.

[0058] In a second aspect, the present application provides a system including at least two computer devices of the first aspect, and the at least two computer devices are connected through a network.

[0059] The computer device of the system can not only access the memory pool of the computer device through the memory sharing control device, so as to improve the utilization rate of the memory, but also access the memory pool of other computer devices through the network. Expanding the range of the memory pool can further improve the utilization rate of the memory resources.

[0060] Optionally, the memory sharing control device in the computer device of the system can also have the function of a network adapter, and can send the access request of the processing unit to other computer devices in the system through the network to access the memory in the other computer devices.

[0061] Optionally, the computer device of the system can also include a network adapter with a serial-parallel conversion interface (such as a Serdes interface), and the memory sharing control device in the computer device can send the memory access request of the processing unit to other computer devices in the system through the network adapter through the network to access the memory in the other computer devices.

[0062] Optionally, the computer device of the system can be connected through an Ethernet-based network or a unit-bus (U-bus) based network.

[0063] In a third aspect, the present application provides a memory sharing control device, comprising a control unit, a processor interface and a memory interface;

[0064] The processor interface is configured to receive memory access requests sent by at least two processing units; wherein the processing units are processors, cores in the processors, or combinations of cores in the processors;

[0065] The control unit is configured to allocate memories in a memory pool to the at least two processing units respectively, and at least one memory in the memory pool can be accessed by different processing units at different time periods;

[0066] The control unit is further configured to enable the at least two processing units to access the allocated memories through the memory interface.

[0067] Through the memory sharing control device, different processing units can access at least one memory in the memory pool at different time periods, the demand of the processing units for memory resources can be met, and the utilization rate of the memory resources is improved.

[0068] Optionally, the at least one memory in the memory pool can be accessed by different processing units at different time periods, which means that any two processing units of the at least two processing units can access the at least one memory in the memory pool at different time periods respectively. For example, the at least two processing units comprise a first processing unit and a second processing unit, in a first time period, a first memory in the memory pool is accessed by the first processing unit, and the second processing unit cannot access the first memory; in a second time period, the first memory in the memory pool is accessed by the second processing unit, and the first processing unit cannot access the first memory.

[0069] Optionally, the memory interface can be a double data rate (DDR) controller, or the memory interface can be a memory controller with PCM control function.

[0070] Optionally, the memory sharing control device can allocate memory from the memory pool to the at least two processing units according to a control instruction received from an operating system in the computer device. Specifically, a driver in the operating system can send a control instruction for allocating memory in the memory pool to the at least two processing units to the memory sharing control device through a dedicated channel. The operating system is implemented by a CPU in the computer device by executing relevant code. The CPU running the operating system has a privilege mode in which a driver in the operating system can send a control instruction to the memory sharing control device through a dedicated or specific channel.

[0071] Optionally, the memory sharing control device can be an FPGA chip, an ASIC, or other similar chip.

[0072] In some possible implementation manners, the processor interface is further configured to receive, through a serial bus, a first memory access request sent by a first processing unit of the at least two processing units in a serial signal form, where the first memory access request is used to access a first memory allocated to the first processing unit.

[0073] The serial bus has the characteristics of high bandwidth and low latency. Receiving the first memory access request sent by the first processing unit of the at least two processing units in a serial signal form through the serial bus can ensure the efficiency of data transmission between the processing unit and the memory sharing control device.

[0074] Optionally, the serial bus is a memory semantic bus. The memory semantic bus includes but is not limited to a bus interconnected by a QPI, a PCIe, an HCCS, or a CXL protocol.

[0075] In some possible implementation manners, the processor interface is further configured to convert the first memory access request into a second memory access request in a parallel signal form, and send the second memory access request to the control unit.

[0076] The control unit is further configured to implement access of the first memory by the second memory access request through the memory interface.

[0077] Optionally, the processor interface is an interface capable of converting a parallel signal and a serial signal, for example, a Serdes interface.

[0078] In some possible implementation manners, the control unit is further configured to establish a correspondence between a memory address of the first memory in the memory pool and the first processing unit, to allocate the first memory to the first processing unit from the memory pool.

[0079] Optionally, the correspondence between the memory addresses of the first memory and the first processing unit is dynamically adjustable. For example, the correspondence between the memory addresses of the first memory and the first processing unit is dynamically adjustable on demand.

[0080] Optionally, the memory addresses of the first memory can be a continuous physical memory address in the memory pool. The continuous physical memory address in the memory pool can simplify the management of the first memory. Of course, the memory addresses of the first memory can also be discontinuous physical memory addresses in the memory pool.

[0081] Optionally, the memory address information of the first memory includes a starting address of the first memory and a size of the first memory. The first processing unit has an identifier, and the establishment of the correspondence between the memory addresses of the first memory and the first processing unit can be the establishment of the correspondence between the unique identifier of the first processing unit and the memory address information of the first memory. In some possible implementation manners, the control unit is further configured to virtually output a plurality of virtual memory devices from the memory pool, wherein a first virtual memory device in the plurality of virtual memory devices corresponds to the first memory.

[0082] The first virtual memory device is allocated to the first processing unit.

[0083] Optionally, the virtual memory device corresponds to a continuous physical memory address in the memory pool. The virtual memory device corresponding to the continuous physical memory address in the memory pool can simplify the management of the virtual memory device. Of course, the virtual memory device can also correspond to discontinuous physical memory addresses in the memory pool.

[0084] Optionally, the first virtual memory device can be allocated to the first processing unit by establishing an access control table. For example, the access control table can include the identifier of the first processing unit, the identifier of the first virtual memory device, the starting address and size of the memory corresponding to the first virtual memory device, and the like. The access control table can also include the permission information of the first processing unit accessing the first virtual memory device, the attribute information of the memory to be accessed (including but not limited to the information whether it is a persistent memory), and the like.

[0085] In some possible implementation manners, the control unit is further configured to: when a preset condition is met, cancel the correspondence between the first virtual memory device and the first processing unit, and establish the correspondence between the first virtual memory device and a second processing unit in the at least two processing units.

[0086] Optionally, the correspondence between the virtual memory device and the processing unit can be dynamically adjusted according to the demand of the at least two processing units for the memory resource.

[0087] By dynamically adjusting the correspondence between the virtual memory device and the processing unit, the demand of different processing units for the memory resource in different service scenarios can be flexibly adapted, and the utilization rate of the memory resource can be improved.

[0088] Optionally, the control unit is further configured to:

[0089] When the preset condition is met, the correspondence between the first memory and the first virtual memory device is released, the correspondence between the first memory and a second virtual memory device in the plurality of virtual memory devices is established, and the second virtual memory device is allocated to a second processing unit in the at least two processing units. In this case, the correspondence between the virtual memory device and the physical memory address in the memory pool does not need to be changed, and only the correspondence between the virtual memory device and the different processing units needs to be changed, so that the access of different processing units to the same physical memory in different time periods can be realized. In some possible implementation manners, the memory sharing control device further includes a cache unit.

[0090] The cache unit is configured to cache data read by any one of the at least two processing units from the memory pool, or cache data discarded by any one of the at least two processing units.

[0091] Through the cache unit, the efficiency of the processing unit in accessing the memory data can be further improved.

[0092] Optionally, the cache unit can include a first-level cache and a second-level cache. The first-level cache can have a smaller capacity but a higher read-write speed than the second-level cache. For example, the first-level cache can be a cache with a capacity of 100 MB and a speed of nanoseconds. The second-level cache can have a larger capacity but a lower read-write speed than the first-level cache. For example, the second-level cache can be a DRAM with a capacity of 1 GB. Through the first-level cache and the second-level cache, the space of the cache can be increased while the speed of the processor in accessing the data through the cache is improved, the range of the processor in accessing the memory through the cache is expanded, and the rate of the processor resource pool in accessing the memory is further improved as a whole.

[0093] In some possible implementation manners, the memory sharing control device further includes a prefetch engine configured to prefetch data required to be read by any one of the at least two processing units from the memory pool and cache the data in the cache unit.

[0094] Optionally, the prefetch engine can achieve intelligent data prediction through specific algorithms or AI algorithms to further improve the efficiency of the processing unit accessing memory data.

[0095] In some possible implementations, the memory sharing control device also includes a Quality of Service (QoS) engine;

[0096] The QoS engine is used to control the optimized storage of data that needs to be cached by any one of the at least two processing units in the cache unit. Through the QoS engine, different processing units can have different caching capabilities for data accessed in memory within the cache unit 304. For example, memory access requests initiated by higher-priority processing units have dedicated cache space in the cache unit 304, ensuring that the data accessed by that processing unit is cached in a timely manner, thereby guaranteeing the quality of business processing for that type of processor.

[0097] In some possible implementations, the memory sharing control device may further include a compression / decompression engine;

[0098] The compression / decompression engine is used to compress or decompress data related to memory access.

[0099] Optionally, the compression / decompression engine can be disabled.

[0100] Optionally, the compression / decompression engine can compress the data to be written to memory by the processing unit in 4KB granularity using a compression ratio algorithm before writing it to memory; or, when the processing unit reads compressed data from memory, the data to be read is decompressed before being sent to the processor. This can improve the data transfer rate and further enhance the efficiency of the processing unit accessing memory data. Optionally, the compression / decompression engine can be disabled.

[0101] Optionally, the memory sharing control device may further include a storage unit, which includes software code for at least one of the QoS engine, the prefetch engine, and the compression / decompression engine. The memory sharing control device can read the code in the storage unit to implement corresponding functions.

[0102] Optionally, at least one of the QoS engine, the prefetch engine, and the compression / decompression engine can be implemented through the control logic of the memory sharing control device.

[0103] Fourthly, this application provides a method for memory sharing control, the method being applied in a computer device, the computer device including at least two processing units, a memory sharing control device, and a memory pool, the memory pool including one or more memory units, the method comprising:

[0104] The memory sharing control device receives a first memory access request sent by a first processing unit of the at least two processing units; wherein the processing unit is a processor, a core in the processor, or a combination of cores in the processor;

[0105] The memory sharing control device allocates a first memory for the first processing unit from a memory pool, and the first memory can be accessed by a second processing unit of the at least two processing units at other time periods;

[0106] The first processing unit accesses the first memory through the memory sharing control device.

[0107] By the method, different processing units access at least one memory in the memory pool at different time periods, the demand of the processing units for memory resources can be met, and the utilization rate of the memory resources is improved.

[0108] In some possible implementation manners, the method further includes:

[0109] The memory sharing control device receives, through a serial bus, a first memory access request sent by a first processing unit of the at least two processing units in a serial signal form, and the first memory access request is used to access a first memory allocated to the first processing unit.

[0110] In some possible implementation manners, the method further includes:

[0111] The memory sharing control device converts the first memory access request into a second memory access request in a parallel signal form, and implements access to the first memory according to the second memory access request.

[0112] In some possible implementation manners, the method further includes:

[0113] The memory sharing control device establishes a correspondence between a memory address of the first memory in the memory pool and a first processing unit of the at least two processing units.

[0114] In some possible implementation manners, the method further includes:

[0115] The memory sharing control device virtually outputs a plurality of virtual memory devices from the memory pool, wherein a first virtual memory device of the plurality of virtual memory devices corresponds to the first memory;

[0116] The memory sharing control device is further configured to allocate the first virtual memory device to the first processing unit.

[0117] In some possible implementation manners, the method further includes:

[0118] When the preset condition is met, the memory sharing control device releases the correspondence between the first virtual memory device and the first processing unit, and establishes the correspondence between the first virtual memory device and a second processing unit of the at least two processing units.

[0119] In some possible implementation manners, the method further includes:

[0120] The memory sharing control device caches data read by any one of the at least two processing units from the memory pool, or caches data evicted by any one of the at least two processing units.

[0121] In some possible implementation manners, the method further includes:

[0122] The memory sharing control device pre-fetches data required to be read by any one of the at least two processing units from the memory pool and caches the data.

[0123] In some possible implementation manners, the method further includes:

[0124] The memory sharing control device controls optimized storage of data required to be cached by any one of the at least two processing units in the cache storage medium.

[0125] In some possible implementation manners, the method further includes:

[0126] Compressing or decompressing data related to memory access.

[0127] In a fifth aspect, an embodiment of the present application further provides a chip, which is used to implement functions of the memory sharing control device in the third aspect.

[0128] In a sixth aspect, an embodiment of the present application further provides a computer readable storage medium, including program codes, the program codes including instructions for executing part or all steps of any method provided in the fourth aspect.

[0129] In a seventh aspect, an embodiment of the present application further provides a computer program product, which, when running on a computer, causes any method provided in the fourth aspect to be executed.

[0130] It can be understood that any memory sharing control device, computer readable storage medium or computer program product provided above is used to execute the corresponding method provided above, and thus the beneficial effects achieved by the memory sharing control device, the computer readable storage medium or the computer program product can refer to the beneficial effects in the corresponding method, which will not be described herein again. BRIEF DESCRIPTION OF DRAWINGS

[0131] The drawings needed to be used in the following embodiment description will be briefly introduced, obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained according to the drawings without creative labor for the ordinary skilled in the art.

[0132] Figure 1A It is a schematic diagram of a centralized shared memory system architecture;

[0133] Figure 1B It is a schematic diagram of a distributed shared memory system architecture;

[0134] Figure 2A It is a schematic diagram of a memory sharing control device 200 provided by the embodiment of the present application;

[0135] Figure 2B It is a schematic diagram of the connection relationship between the memory sharing control device 200 and the processor and the memory;

[0136] Figure 3 It is a schematic diagram of an internal structure of an SRAM type FPGA provided by the embodiment of the present application;

[0137] Figure 4 It is a schematic diagram of a specific structure of a Serdes interface provided by the embodiment of the present application;

[0138] Figure 5 It is a schematic diagram of an internal structure of a memory controller 500 provided by the embodiment of the present application;

[0139] Figure 6 It is a schematic diagram of a structure of a processor 210 provided by the embodiment of the present application;

[0140] Figure 7A It is a schematic diagram of a structure of a memory sharing control device 300 provided by the embodiment of the present application;

[0141] Figure 7B It is a schematic diagram of a structure of another memory sharing control device 300 provided by the embodiment of the present application;

[0142] Figure 7C It is a schematic diagram of a structure of a memory sharing control device 300 provided by the embodiment of the present application, which includes a cache unit;

[0143] Figure 7D It is a schematic diagram of a structure of a memory sharing control device 300 provided by the embodiment of the present application, which includes a storage unit;

[0144] Figure 7E It is a schematic diagram of a connection relationship structure of a memory sharing control device 300 provided by the embodiment of the present application and a memory pool;

[0145] Figure 7F Another connection relationship structure diagram of the memory sharing control device 300 and the memory pool provided by the embodiment of the present application is shown in FIG. 3;

[0146] Figure 8A-1 A structure diagram of a computer device 80a provided by the embodiment of the present application is shown in FIG. 4;

[0147] Figure 8A-2 A structure diagram of another computer device 80a provided by the embodiment of the present application is shown in FIG. 5;

[0148] Figure 8B-1 A structure diagram of a computer device 80b provided by the embodiment of the present application is shown in FIG. 6;

[0149] Figure 8B-2 A structure diagram of another computer device 80b provided by the embodiment of the present application is shown in FIG. 7;

[0150] Figure 9A A structure diagram of a system 901 provided by the embodiment of the present application is shown in FIG. 8;

[0151] Figure 9B A structure diagram of a system 902 provided by the embodiment of the present application is shown in FIG. 9;

[0152] Figure 9C A structure diagram of a system 903 provided by the embodiment of the present application is shown in FIG. 10;

[0153] Figure 10 A logic diagram when the memory sharing is implemented provided by the embodiment of the present application is shown in FIG. 11;

[0154] Figure 11 A structure diagram of a computer device 1100 provided by the embodiment of the present application is shown in FIG. 12;

[0155] Figure 12 A flow diagram of a memory sharing control method provided by the embodiment of the present application is shown in FIG. 13. DETAILED DESCRIPTION

[0156] The embodiments of the present application are described below in conjunction with the accompanying drawings.

[0157] The terms "first", "second", and the like, in the description and in the claims of the present application and above-described drawings, are used to distinguish similar objects and are not necessarily used to describe a specific sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments described herein are capable of functioning in other sequences than the one(s) explicitly described or illustrated. Furthermore, the terms "first", "second", etc. are used herein solely for the purpose of description and are not intended to refer to or imply relative importance or to imply that it is intended to limit the indicated technical features to a number of steps or components.

[0158] In the present application specification and claims, the terms "comprising" and "having" and any variations thereof, are intended to cover a non-exclusive inclusion, for example, a process, method, system, product or apparatus that includes a list of steps or modules as non- limiting to those steps or modules clearly listed, but can include other steps or modules not clearly listed or inherent to such processes, methods, products or apparatus. The naming or numbering of steps in the present application does not mean that the steps in the method flow must be executed in the time / logical order indicated by the naming or numbering, and the named or numbered flow steps can change the execution order according to the technical purpose to be achieved, as long as the same or similar technical effects can be achieved. The division of units in the present application is a logical division, and in actual application, it can have another division manner, for example, multiple units can be combined or integrated in another system, or some features can be ignored or not executed, in addition, the coupling or direct coupling or communication connection between the units shown or discussed can be through some interface, the indirect coupling or communication connection between the units can be electrical or other similar forms, which are not limited in the present application. And, the units or sub-units described as separate components can or can not be physically separate, can or can not be physical units, or can be distributed into multiple circuit units, and part or all of the units can be selected according to actual needs to achieve the purpose of the present application scheme.

[0159] It is to be understood that the terms used in the description and claims of the present application describing various described examples are intended to describe specific examples, and are not intended to be limiting. As used in the description of various described examples and the appended claims, the singular forms "a", "an" and "the" are intended to include plural forms as well, unless the context clearly indicates otherwise.

[0160] It should also be understood that, in the claims, any means-plus-function clause is intended to cover the structures described herein as performing the recited functionality and also cover structures yet to be invented. It should also be understood that, in the claims, a structure, limitation, or means for performing a function does not, by itself, teach the manner of operation for the claimed application. The functions claimed are intended to be incorporated as functions of a manufacturing and / or processing facility independently of structural support, material or other support important for operation of the functions. Those skilled in the art will recognize that missing specification can be found implanting by standard engineering practices from the function remaining in the claim.

[0161] It should be understood that determining B based on A does not mean that B is determined only based on A, but B can also be determined based on A and / or other information.

[0162] It should be understood that the term "comprising" (also "includes," "including," "comprises," and / or "comprising"), when used in this specification, specifies the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0163] It should be understood that the term "if' can be construed to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [a stated condition or event] is detected" can be construed to mean "upon determining" or "in response to determining" or "upon detecting [the stated condition or event]" or "in response to detecting [the stated condition or event]," depending on the context.

[0164] It should be understood that the term "one embodiment," "an embodiment," "a possible implementation," and the like, as used in the specification, means that a particular feature, structure, or characteristic described in connection with the embodiment or implementation is included in at least one implementation of the application. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" or "a possible implementation" in various places in the specification are not necessarily referring to the same embodiment or implementation. Further, the particular features, structures, or characteristics can be combined in any suitable manner in one or more implementations.

[0165] First, some terms and related technologies involved in the present application are explained to facilitate understanding:

[0166] Memory controller: is an important component of computer system to control memory and exchange data between memory and processor, and is a bridge between central processing unit and memory. The main function of memory controller is to read and write operation of memory, which can be divided into two kinds of traditional and integrated. In the traditional computer system, the location of memory controller is in the north bridge chip of motherboard chipset. In this structure, any CPU and memory data transmission through the path of "CPU-north bridge-memory-north bridge-CPU". Since the CPU read and write data from memory, all through the multi-stage data transmission, the delay is large. Integrated memory controller is located in the CPU, any CPU and memory data transmission through the path of "CPU-memory-CPU", compared to the traditional, the data transmission delay is greatly reduced.

[0167] DRAM: is a widely used memory medium. Unlike sequential access of disk medium, DRAM allows central processing unit to directly random access any byte in it. The storage structure of DRAM is relatively simple, each storage structure mainly contains a capacitor and a transistor. When the capacitor is charged, it represents the stored data "1". The state after discharge represents data "0".

[0168] PCM: is a kind of non-volatile memory based on phase change storage material to store information. Each storage unit in PCM is composed of phase change material (such as chalcogenide glass) and two electrodes. By changing the voltage size and power time of electrode, the phase change material can be transformed between crystalline and amorphous state. The medium is in crystalline state, the resistance is low; when in amorphous state, the resistance is high. Therefore, the data can be stored by changing the state of phase change material. The most typical feature of PCM is non-volatile.

[0169] Serializer / deserializer (Serdes): converting parallel data into serial data at the sending end, and then transmitting it to the receiving end through the transmission line; converting serial data into parallel data at the receiving end, which can reduce the number of transmission lines and reduce system cost. Serdes is a time division multiplexing (TDM) and point-to-point communication technology, that is, converting multiple low-speed parallel signals (i.e. parallel data) at the sending end into high-speed serial signals (i.e. serial data), and finally converting the high-speed serial signals into low-speed parallel signals at the receiving end. Serdes uses differential signal transmission, which makes the interference noise loaded on the two transmission lines cancel each other out, not only improving the transmission speed, but also improving the signal transmission quality. Since the parallel interface technology refers to the parallel transmission of multiple-bit data, and the synchronous clock is transmitted at the same time to divide the data bytes, this method is simple and easy to implement, but the number of signal lines is large, and it is generally used for short-distance data transmission. The serial interface technology transmits byte data bit by bit, and is widely used in long-distance data communication.

[0170] With the continuous improvement of integrated circuit technology level, especially the continuous progress in the design of processor architecture, the performance of the processor is gradually improved. Compared with the processor, the performance of the memory improves much slower. With the cumulative growth of the gap, the cumulative growth of this imbalance leads to the consequence that the memory access speed lags far behind the computing speed of the processor, and the bottleneck formed by the memory will make it difficult to play the advantages of high-performance processors. For example, for the growing high-performance computing (HPC), the memory access speed constitutes a great constraint.

[0171] At the same time, multi-core processors gradually replace single-core processors, and the number of parallel executions of multiple cores in the processor also increases significantly. This leads to an increase in the bandwidth demand between the processor and the memory.

[0172] To improve the access speed and bandwidth between the processor and the memory, a shared memory resource is usually used.

[0173] According to whether there is a difference in the access of the processor to the memory, the multi-processor shared memory architecture can be divided into centralized shared memory system and distributed shared memory system. The centralized shared memory system has the characteristics of small number of processors and single interconnection mode, and the memory is connected to all processors through a crossbar switch or a shared bus. Figure 1Ais a typical centralized shared memory system architecture. Because access to memory is equal or symmetric for all processors, this type of architecture is also called unified memory architecture (UMA) or symmetric multiprocessing (SMP).

[0174] The centralized shared memory system faces the problem that the processor number cannot provide the required memory bandwidth after reaching a certain scale, which becomes a bottleneck of performance. The distributed shared memory system effectively solves this problem. Figure 1B is a schematic diagram of the structure of a distributed shared memory system. As shown in Figure 1B , in the system, the memory is globally shared and uniformly addressed and distributed on each processor. The address space of the memory is divided into several parts, which are managed by the processors respectively. For example, if processor 1 accesses the memory address space managed by the processor itself, it does not need to cross the processor or the interconnection bus. If processor 1 accesses the memory space managed by other processors, for example, the memory address space managed by processor N, it needs to pass through the interconnection bus. The distributed shared memory system is also called a non-uniform memory access (NUMA) system.

[0175] In the NUMA system, the address space of the shared memory is managed by the processors respectively. Due to the lack of unified memory management mechanism, the sharing of memory resources is not flexible when a processor needs to use the memory space managed by other processors, and there is a problem of low utilization of memory resources. Moreover, when a processor accesses the memory address space managed by other processors, the delay is often large because of the interconnection bus.

[0176] Embodiments of the present application provide a device, a chip, a computer device, a system and a method for implementing memory sharing control, and provide a brand new memory access architecture. A bridge between the processor and the shared memory pool (which can also be referred to as a memory pool in the embodiments) is established by the memory sharing control device, and the utilization of memory resources is improved.

[0177] Figure 2A is a schematic diagram of the structure of a memory sharing control device 200 provided by the embodiments of the present application. As shown in Figure 2A , the memory sharing control device 200 includes a control unit 201, a processor interface 202 and a memory interface 203.

[0178] The memory sharing control device 200 can be a chip between the processor (CPU or core in the CPU) and the memory (also called main memory) in the computer device, for example, it can be an FPGA chip.

[0179] Figure 2B This is a schematic diagram showing the connection relationship between the memory sharing control device 200 and the processor and memory. (See diagram below.) Figure 2B The processor 210 is connected to the memory sharing control device 200 via a processor interface 202, and the memory 220 is connected to the memory sharing control device 200 via a memory interface 203. The processor 210 can be a CPU or a CPU with multiple cores; the memory 220 includes, but is not limited to, DRAM, PCM, flash memory, SCM, SRAM, PROM, EPROM, STT-RAM, or RRAM. SCM is a composite storage technology that combines the characteristics of traditional storage devices and memory. Storage-class memory can provide faster read and write speeds than hard drives, but its processing speed is slower than DRAM, and it is also cheaper than DRAM. In this embodiment, the memory 220 may also include DIMMs or SSDs.

[0180] Processor interface 202 is the interface connecting memory sharing control device 200 and processor 210. This interface can receive serial signals sent by the processor and convert them into parallel signals. Based on processor interface 202, memory sharing control device 200 and processor 210 can be connected via a serial bus. The serial bus has the characteristics of high bandwidth and low latency, which can ensure the efficiency of data transmission between processor 210 and memory sharing control device 200. For example, processor interface 202 can be a low-latency SerDes interface. The SerDes interface, as processor interface 202, is connected to the processor via a serial bus and can realize the conversion between serial signals and parallel signals based on serial-to-parallel conversion logic. The serial bus can be a memory-semantic bus. The memory-semantic bus includes, but is not limited to, buses interconnected based on QPI, PCIe, HCCS, or CXL protocols.

[0181] In a specific implementation, the processor 210 can be connected to the processor interface 202 (for example, a Serdes interface) of the memory sharing control device 200 through a serial bus and a Serdes interface. The processor 210 initiates a memory access request in the form of a parallel signal, converts the memory access request in the form of a parallel signal into a memory access request in the form of a serial signal through the Serdes interface in the processor 210, and sends the memory access request in the form of a serial signal through the serial bus. After the processor interface 202 receives the memory access request in the form of a serial signal from the processor 210 through the serial bus, the processor interface 202 converts the memory access request in the form of a serial signal into a memory access request in the form of a parallel signal, and sends the converted memory access request to the control unit 301. The control unit 301 can access the corresponding memory based on the memory access request in the form of a parallel signal. For example, the corresponding memory can be accessed in a parallel manner. In the embodiments of the present application, a parallel signal can refer to a signal that transmits multiple bits at a time, and a serial signal can refer to a signal that transmits one bit at a time.

[0182] Similarly, when the memory sharing control device 200 returns a response message of a memory access request to the processor 210, the processor interface 202 (for example, a Serdes interface) converts the response message in the form of a parallel signal into a response message in the form of a serial signal, and sends the response message in the form of a serial signal to the processor 210 through the serial bus. After the processor 210 receives the response message in the form of a serial signal, the processor 210 converts the response message in the form of a serial signal into a response message in the form of a parallel signal and performs subsequent processing.

[0183] The memory sharing control device 200 can access the corresponding memory in the memory 220 through the memory interface 203 as a memory controller. For example, when the memory 220 is a shared memory pool composed of DRAM, the memory interface 203 is a DDR controller for DRAM control functions, used to implement interface control of a DRAM storage medium; when the memory 220 is a shared memory pool composed of PCM, the memory interface 203 is a memory controller for PCM control functions, used to implement interface control of a PCM storage medium.

[0184] It should be noted that, Figure 2BThe processor 210 shown in the figure is only an example. The processor connected with the memory sharing control device 200 can also be a multi-core processor, and can also be a processor resource pool. The processor resource pool includes at least two processing units, and each processing unit can be a processor, a core in the processor, or a combination of cores in the processor. The processing units in the processor resource pool can be a combination of different cores in the same processor, or a combination of different cores in different processors. When the processor needs to perform a computing task in parallel by using multiple cores, or needs to perform a computing task in parallel by using cores in different processors, the combination of the cores can be used as a processing unit to access the same block of memory in the shared memory pool.

[0185] Figure 2B The memory 220 shown in the figure is only an example. The memory 220 connected with the memory sharing control device 200 can also be a shared memory pool composed of multiple memories. At least one memory in the shared memory pool can be accessed by different processing units at different time periods. The memory in the shared memory pool includes but is not limited to DRAM, PCM, flash memory, STT-RAM, or RRAM. Similarly, the memory in the shared memory pool can be a memory on a computer device, or a memory on different computer devices. It can be understood that the computer device can be a computer (desktop computer or portable computer) or a server, and the like, which needs a processor to access a memory, and can also include a terminal device such as a mobile phone terminal. The embodiments of the present application do not limit the form of the specific device.

[0186] The control unit 201 is configured to control memory access according to a memory access request, including but not limited to dividing the memory resources in the shared memory pool into multiple independent memory resources, and respectively allocating (for example, on-demand allocation) the memory resources to each processing unit in the processor resource pool. The independent memory resources divided by the control unit 201 can be a memory storage space corresponding to a physical address in the shared memory pool. The physical address of the memory resource can be continuous or discontinuous. For example, the memory sharing control device 200 can virtually create multiple virtual memory devices based on the shared memory pool, and each virtual memory device corresponds to or manages a part of the memory resources. The control unit 201 respectively allocates the multiple independent memory resources divided in the shared memory pool to each processing unit in the processor resource pool by establishing a corresponding relationship between different virtual memory devices and the processing units.

[0187] However, the correspondence between the processing units and the memory resources is not fixed and can be adjusted when certain conditions are met. That is, the correspondence between the processing units and the memory resources can be dynamically adjusted. The control unit 201 adjusts the correspondence between the processing units and the memory resources by receiving a control instruction sent by a driver in an operating system and adjusting the correspondence according to the control instruction. The control instruction includes information for deleting, changing, or adding the correspondence.

[0188] For example, the computer device 20 (not shown in the figure) includes Figure 2B The processor 210, the memory sharing device 200, and the memory 220 are shown. The processor 210 runs an operating system required by the computer device 20 to implement control of the computer device 20. Assuming that the computer device 20 is a server providing cloud services, and the processor 210 has 8 cores, core A provides cloud service for user A, and core B provides cloud service for user B. The operating system of the computer device allocates memory resource A in the memory 220 as a memory access resource for core A and allocates memory resource B in the memory 220 as a memory access resource for core B based on the service needs of user A and user B. The operating system can send a control instruction for establishing the correspondence between core A and memory resource A and the correspondence between core B and memory resource B to the memory sharing control device 200. The memory sharing control device 200 establishes the correspondence between core A and memory resource A and the correspondence between core B and memory resource B according to the control instruction of the operating system. In this way, when core A initiates a memory access request, the memory sharing control device 200 can determine the memory resource (i.e., memory resource A) that core A can access according to the information carried in the access request, and implement access of core A to memory resource A. When user A needs to rest and no longer uses cloud services due to service needs or time zone reasons, resulting in a decrease in the demand for memory resources, and user B needs to use more cloud services due to service needs or time zone reasons, resulting in a need for more memory resources, the operating system of the computer device 20 can send a control instruction for removing the correspondence between core A and memory resource A and allocating memory resource A for use by core B based on changes in the service needs of user A and user B. The operating system, specifically a driver in the operating system, can send a control instruction for deleting the correspondence between core A and memory resource A and establishing the correspondence between core B and memory resource A, and the memory sharing control device 200 reconfigures the correspondence of memory resource A based on the control instruction sent by the driver in the operating system, deletes the correspondence between core A and memory resource A, and establishes the correspondence between core B and memory resource A. In this way, memory resource A can be used as the memory of core A and core B at different time periods, can meet the needs of different cores for different services, and improves the utilization rate of memory resources.

[0189] The driver of the operating system sends a control instruction to the memory sharing control device 200, which can be sent through a dedicated or specific channel. Specifically, the processor running the operating system is in a privileged mode, and the driver in the operating system can send a control instruction to the memory sharing control device 200 through a dedicated or specific channel. In this way, the driver in the operating system can send a control instruction to delete, change or add the corresponding relationship through a dedicated channel.

[0190] The memory sharing control device 200 described above can be connected to the processor 210 through an interface supporting serial-parallel conversion (for example, a Serdes interface), and the processor 210 can communicate with the memory sharing control device 200 through a serial bus. Based on the high-bandwidth and low-latency characteristics of the serial bus, even if the communication distance between the processor 210 and the memory sharing control device 200 is far, the access rate of the processor 210 accessing the shared memory pool can be guaranteed.

[0191] In addition, the control unit 201 can also be used to realize cache control, compression control, priority control and the like of data, thereby further improving the efficiency and quality of processor access to memory.

[0192] The following takes an FPGA as an example of a chip implementing the memory sharing control device 200 to exemplarily describe the implementation mode of the memory sharing control device 200 provided by the embodiment of the application.

[0193] As a programmable logic device, an FPGA can be divided into three categories according to different programmable principles: SRAM type, anti-fuse type and FLASH type based on static random access memory (SRAM). Thanks to the erasability and volatility of SRAM, the FPGA based on SRAM can be repeatedly programmed, but the configuration data will be lost after power failure. The FPGA of the anti-fuse type can only be programmed once, and the circuit function is fixed after programming and cannot be modified again, so even in the state of no power supply, the circuit function will not change.

[0194] The following takes an FPGA based on SRAM as an example to exemplarily describe the internal structure of the FPGA. Figure 3 An internal structure diagram of an SRAM type FPGA. As shown in Figure 3 The FPGA internally includes at least the following parts:

[0195] Configurable Logic Block (CLB): mainly includes lookup table (LUT), multiplexer, carry chain, D flip-flop and other programmable resources inside, which are used to realize different logic functions and are the core of the whole FPGA chip.

[0196] Input / Output Block (IOB): provides the interface between the FPGA and the external circuit, and provides appropriate driving of the input / output signal to achieve matching when the electrical characteristics inside and outside the FPGA are different. Through electronic design automation (EDA) development software, different electrical standards and physical information can be configured according to the needs, such as adjusting the size of the driving current, changing the resistance value of the pull-up resistor and the pull-down resistor. Generally, several IOBs are divided into a bank. The number of IOBs contained in each bank is different in different series of FPGA chips.

[0197] Block Random Access Memory (BRAM): used to store data with large data volume, in order to meet different data read / write requirements, it can be configured as a single-port RAM, a dual-port RAM, a content addressable memory (CAM) and a first in first out (FIFO) storage structure, and the storage bit width and depth can be changed according to the design requirements. BRAM can expand the application range of FPGA and improve its flexibility.

[0198] Switch Matrix (SM): is an important part of the interconnect resource (IR) inside the FPGA, which is mainly distributed on the left end of each resource module. The switch matrix on the left end of different modules is very similar but also different, which plays a role in connecting the resources of each module. Another part of the interconnection resource inside the FPGA is the interconnection metal line (Wire Segment), which is used in cooperation with the SM to connect the resources of the whole chip.

[0199] Figure 3 Only several main components related to the memory sharing control device 200 in the embodiments of the present application in the FPGA chip are shown. In the specific implementation, in addition to the above-mentioned components, other components in the FPGA chip can also be used in the implementation of the memory sharing control device 200. Figure 3In addition to the illustrated components, the FPGA can also include other components or embedded functional units, such as a digital signal processor (DSP), a phase locked loop (PLL), or a multiplier (MUL), etc.

[0200] The control unit 201 in the above Figure 2A or Figure 2B may be implemented by a CLB in the above Figure 3 . That is, the control unit 201 is implemented by a CLB to control the shared memory pool connected to the memory sharing control device 200, such as dividing the memory resources in the shared memory pool into multiple blocks, allocating one or more blocks of memory resources to a processing unit, or virtually creating multiple virtual memory devices based on the memory resources in the shared memory pool, each virtual memory device corresponding to a physical address space in the shared memory pool, and allocating one or more virtual memory devices to a processing unit, and establishing a correspondence table between the allocated virtual memory device and the corresponding processing unit, etc.

[0201] The processor interface 202 in the above Figure 2A or Figure 2B may be implemented by an IOB in the above Figure 3 , that is, the processor interface 202 can be implemented by an IOB having a serial-parallel conversion function, such as a Serdes interface implemented by an IOB.

[0202] Figure 4 is a specific structure diagram of a Serdes interface. As shown in Figure 4 , the Serdes interface mainly consists of a transmitting channel and a receiving channel. In the transmitting channel, the input parallel data is encoded by an encoder, and then converted into a serial signal by a parallel-to-serial module, and then the serial data is driven and output by a transmitter (Tx). In the receiving channel, the receiver and the clock recovery circuit recover the sampling clock and the data, and then the byte boundary is found by a serial-to-parallel module to convert the parallel data, and finally the original parallel data is recovered by a decoder.

[0203] The encoder and the decoder complete the encoding and decoding functions of the data, and ensure the direct current balance of the serial data stream and as many data jumps as possible. For example, an 8b / 10b and irregular encoding / decoding (Scrambling / Descrambling) encoding / decoding scheme can be used. The parallel-to-serial module and the serial-to-parallel module are used to complete the conversion between the parallel form and the serial form of the data. The clock generation circuit generates a conversion clock for the parallel-to-serial circuit, which is generally implemented by a phase locked loop. The clock generation circuit and the clock recovery circuit provide conversion control signals for the serial-to-parallel circuit, which are also generally implemented by a phase locked loop, but can also be implemented by a phase interpolator, etc.

[0204] The above is only an example of a Serdes interface implementation, i.e., the Serdes interface can be implemented based on Figure 3 IOB in Figure 4 The Serdes interface shown in FIG. 8. Of course, the Serdes interface can also be implemented based on other hardware components, such as other specialized hardware components in the FPGA, and the embodiments of the present application do not limit the specific implementation of the Serdes interface.

[0205] The above Figure 2A or Figure 2B The memory interface 203 can be implemented based on the above-mentioned IOB or other specialized circuits. For example, when the memory interface 203 is implemented by a DDR controller, the logic structure thereof can be as shown in FIG. 9. Figure 5

[0206] Figure 5 is a schematic diagram of an internal structure of a memory controller 500. Referring to Figure 5 , the memory controller 500 includes:

[0207] The receiving module 501 is used to record information of an access request. An access request mainly includes a request type and a request address. According to the two pieces of information, it can be known that the access request is to perform what operation on which memory address. The information of the access request recorded by the receiving module 501 can include the request type and the request address. In addition, the information recorded by the receiving module 501 can also include some auxiliary information used to estimate system performance, such as the arrival time and completion time of the access request.

[0208] The control module 502 is used to control the initialization and power-off of the memory. At the same time, the control module 502 can also control the depth of the memory queue used to implement the memory access control, judge the empty and full of the memory queue, judge whether the memory request is completed, decide which arbitration scheme to use, and decide which scheduling mode to use, etc.

[0209] The address mapping module 503 is used to implement the conversion between the address of the access request and the address recognizable by the memory. For example, for a DDR4 memory system, the memory address is divided into six parts, i.e., Channel, Rank, Bankgroup, Bank, Row, and Column. Different address mapping modes have different access efficiencies.

[0210] ​The refresh module 504 is configured to implement the timing refresh of the memory. The DRAM is internally composed of a plurality of repeated cells, each of which is composed of a transistor (Mosfet) and a capacitor. The capacitor is used to store electric charge and determines whether the logical state of the DRAM unit is 1 or 0. However, due to the leakage phenomenon of the capacitor, the electric charge will be lost after a period of time, thereby causing the loss of data, and therefore the timing refresh needs to be implemented by the refresh module 504.

[0211] The scheduling module 505 is configured to schedule the access request to different queues based on the type of the access request sent by the address mapping module 503. For example, an access request can be scheduled to a queue with high priority, and a request with the highest priority is selected from the queue with the highest priority according to a preset scheduling strategy, to complete a scheduling. The queue is a queue for implementing the memory access control, and the scheduling strategy can be determined according to the time sequence of the request arrival, or the scheduling strategy can be determined according to which request is prepared first.

[0212] It should be noted that, Figure 5 Only the components or functional modules of the memory controller 500 are shown, and the memory controller 500 can further include other components or functional modules in actual implementation. For example, the memory controller 500 can further include a VLIW engine for multi-threaded computing or a direct memory access (DMA) module for memory direct access, and the like, which will not be described herein.

[0213] The above describes one implementation manner of the memory sharing control device 200 taking the FPGA as an example. In actual implementation, the memory sharing control device 200 can also be implemented by other chips or other devices capable of implementing similar chip functions. For example, the memory sharing control device 200 can also be implemented by an ASIC. The ASIC chip is a chip whose circuit function is defined at the beginning of design, and has the characteristics of high chip integration, easy implementation of mass production, low single-chip cost, small size, and the like. The embodiments of the present application do not limit the specific hardware implementation manner of the memory sharing control device 200.

[0214] In the embodiments of the present application, the processor connected with the memory sharing control device 200 can be any processor capable of implementing the function of the processor. Figure 6 A structure schematic diagram of the processor 210 provided by the embodiments of the present application is shown in FIG. 6. As shown in FIG. 6, the processor 210 includes a core 601, a memory 602, and a peripheral and interface 603, and the like. The core 601 can include one or more than one core, and is configured to implement the function of the processor 600. Figure 6 Figure 6 ​The example uses two cores (core 1 and core 2), but this is not a limitation on the number of cores in processor 600; processor 600 can also include 4, 8, or 16 cores, etc. Memory 602 includes cache or SRAM, used to cache data read and write operations for core 1 or core 2. Peripherals and interfaces 603 include a SerDes interface 6031, a memory controller 6032, input / output interfaces, power supply, and clock, etc. The SerDes interface 6031 is the interface connecting processor 210 to the serial bus. Memory access requests initiated by processor 210 in the form of parallel signals are converted into serial signals by the SerDes interface 6031 and then sent to the memory sharing control device 200 via the serial bus. The memory controller 6032 can be... Figure 5 A memory controller with similar function to the memory controller shown is used when the processor 210 has its own local memory. The processor 210 can control access to the local memory through the memory controller 6031.

[0215] Understandable. Figure 6 This is merely an exemplary structural diagram of one implementation of the processor. The embodiments of this application do not limit the specific structure or form of the processor connected to the memory sharing control device 200. Any processor capable of performing certain calculation or control functions is within the scope of the disclosure in the embodiments of this application.

[0216] The specific implementation of the memory sharing control device provided in the embodiments of this application will be further described below.

[0217] Figure 7A This is a schematic diagram of the structure of the memory sharing control device 300 provided in an embodiment of this application. Figure 7A As shown, the memory sharing control device 300 includes a control unit 301, a processor interface 302, and a memory interface 303. The specific implementation of the memory sharing control device 300 shown in Figure 7 can be found above. Figure 2A or Figure 2B The implementation method of the shared memory controller 200 can also be referenced. Figure 3 The FPGA shown is used for implementation. Specifically, the control unit 301 can be referred to the above. Figure 2A or Figure 2B The implementation method of the control unit 201 can be achieved through... Figure 3 The CLB shown is used for implementation. The processor interface 302 can be referenced above. Figure 4 The SerDes interface shown is used for implementation; memory interface 303 can be referenced above. Figure 5 The memory controller shown is used for implementation, and will not be described in detail further.

[0218] Specifically, Figure 7AThe control unit 301 in the memory sharing control device 300 can realize the following functions by configuration:

[0219] 1. Based on the memory resources connected to the memory sharing control device 300, a plurality of virtual memory devices are virtually created.

[0220] The memory resources connected to the memory sharing control device 300 form a shared memory pool. The control unit 301 can uniformly address the memory resources in the shared memory pool, and divide the uniformly addressed memory physical address space into a plurality of address segments, each address segment corresponding to a virtual memory device. The sizes of the address segments corresponding to the divided address spaces can be the same or different. That is, the sizes of each virtual memory device can be the same or different.

[0221] A virtual memory device is not an actually existing device, but a segment of memory address space in the shared memory pool identified by the control unit 301, which is allocated to a processing unit (which can be a processor, a core in a processor, a combination of different cores in the same processor, or a combination of cores in different processors) for memory access (such as reading and writing data), hence the name virtual memory device. For example, each virtual memory device corresponds to a segment of physically contiguous memory region. Alternatively, a virtual memory device can also correspond to a non-contiguous physical address space.

[0222] The control unit 301 can assign an identifier to each virtual memory device for identifying different virtual memory devices. Figure 7A Two virtual memory devices are exemplarily shown: virtual memory device a and virtual memory device b. Virtual memory device a and virtual memory device b respectively correspond to different memory address spaces in the shared memory pool. 2. The plurality of virtually created virtual memory devices are allocated to the processing units connected to the memory sharing control device 300.

[0223] The control unit 301 can assign one virtual memory device to one processing unit. To avoid possible complex logic or possible traffic storm, the control unit 301 avoids assigning one virtual memory device to multiple processors, or assigning one virtual memory device to multiple cores in a processor when assigning virtual memory devices. However, for some services that require different cores in the same processor to perform computing tasks in parallel, or require different cores in different processors to perform computing tasks in parallel, the efficiency of service processing during parallel computing can be improved by assigning the memory corresponding to one virtual memory device to a combination of cores through complex logic.

[0224] The control unit 301 can assign the virtual memory device in a manner of establishing a correspondence between the identity of the virtual memory device and the identity of the processing unit. For example, the control unit 301 can establish a correspondence between the virtual memory device and different processing units based on the number of processing units connected to the memory sharing control device 300. Alternatively, the control unit 301 can also establish a correspondence between the processing unit and the virtual memory device, and a correspondence between the virtual memory device and different memory resources, thereby establishing a correspondence between the processing unit and the different memory resources.

[0225] 3. Record the correspondence between the virtual memory device and the assigned processing unit;

[0226] In a specific implementation, the control unit 301 can maintain an access control table (also referred to as a mapping table) for recording the correspondence between the virtual memory device and the processing unit. One implementation of the access control table can be as shown in Table 1:

[0227]

[0228] Table 1

[0229] In Table 1, Device_ID represents the identity of the virtual memory device, Address represents the start address of the physical memory address managed or accessible by the virtual memory device, Size represents the size of the memory managed or accessible by the virtual memory device, Access Attribute represents the access mode, which is a read operation or a write operation; and Resource ID represents the identity of the processing unit.

[0230] The Resource ID in Table 1 usually corresponds to one processing unit. Since one processing unit can be one processor, one core in a processor, a combination of multiple cores in a processor, or a combination of multiple cores in different processors, the control unit 301 can also maintain a correspondence table between the Resource ID and the combination of cores to clearly indicate the information of the corresponding core or processor of each processing unit. For example, Table 2 exemplarily shows the correspondence between the Resource ID and the core:

[0231]

[0232]

[0233] Table 2

[0234] Since the cores in different processors have unified identification in a computer device, the ID of the core in Table 2 can distinguish different cores in different processors. It can be understood that Table 2 only exemplarily shows the correspondence between the Resource ID of the processing unit and the corresponding core or the corresponding processor. The embodiments of the present application do not limit the manner in which the memory sharing control device 300 determines the correspondence between the Resource ID and the corresponding core or the corresponding processor.

[0235] In another implementation manner, if the memory connected by the memory sharing control device 300 includes DRAM and PCM, since the DRAM storage medium has the non-persistent characteristic and the PCM storage medium has the persistent characteristic, the access control table maintained by the control unit 301 can further include whether each virtual memory device is a persistent virtual memory device or a non-persistent virtual memory device.

[0236] Table 3 is another implementation manner of the access control table provided by the embodiments of the present application:

[0237]

[0238] Table 3

[0239] In Table 3, the Persistent Attribute represents the persistent attribute of the virtual memory device, that is, represents whether the memory address space corresponding to the virtual memory device is persistent or non-persistent.

[0240] Optionally, the access control table maintained by the control unit 301 can further include other information for implementing further memory access control. Exemplarily, the access control table can further include permission information of the processing unit accessing the virtual memory device, and the permission information includes but is not limited to read-only access or write-only access and the like.

[0241] 4. When receiving the memory access request sent by the processing unit, based on the correspondence between the virtual memory device and the processing unit recorded in the access control table, the virtual memory device corresponding to the processing unit sending the memory access request is determined, and the corresponding memory is accessed based on the determined virtual memory device;

[0242] For example, a memory access request includes the RESOURCE_ID of the processing unit, address information and access attribute and the like. The RESOURCE_ID is the ID of the combination of the cores, the address information indicates the address information of the memory to be accessed, and the access attribute indicates whether the memory access request is a read request or a write request. The control unit 301 can determine at least one virtual memory device corresponding to the RESOURCE_ID according to the RESOURCE_ID and the access control table (for example, Table 1). For example, the determined virtual memory device isFigure 7A According to Table 2, it can be determined that the core corresponding to the RESOURCE_ID is able to access the memory resource that the virtual memory device a is able to manage access to. The control unit 301 controls the memory access request to implement access control of the memory on the memory address space that the virtual memory device a is able to manage or access, in combination with the address information and the access attribute in the access request. Optionally, when the permission information is recorded in the access control table, the control unit 301 can also control the access of the corresponding processing unit to the memory based on the permission information recorded in the access control table.

[0243] It should be noted that the access control of the virtual memory device by the control unit 301 is to implement access control of the memory on the physical address space of the memory resource corresponding to the virtual memory device.

[0244] 5. Dynamically adjusting the correspondence between the virtual memory device and the processing unit.

[0245] The control unit 301 can dynamically adjust the virtual memory device by changing the correspondence between the processing unit and the virtual memory device in the access control table based on a preset condition (for example, different needs of different processing units for the memory resource). For example, deleting the correspondence between a virtual memory device and a processing unit, that is, releasing the memory resource corresponding to the virtual memory device, the released memory resource can be allocated to other processing units for access to the memory. Specifically, the way of dynamically adjusting the correspondence by the control unit 201 described in Figure 2B may be implemented.

[0246] In an optional implementation, the modulation of the correspondence between the processing unit and the memory resource in the shared memory pool can also be achieved by changing the memory resource corresponding to each virtual memory device. For example, when the service handled by a processing unit is in a dormant state and does not need to occupy too much memory, the memory resource managed by the virtual memory device corresponding to the processing unit can be allocated to the virtual memory device corresponding to another processing unit, so as to achieve the purpose that the same memory resource is accessed by different processing units at different time periods.

[0247] For example, when the memory sharing control device 300 is implemented by the FPGA chip as shown in Figure 3 , the CLB in Figure 3 may be configured to implement the function of the control unit 301 described above.

[0248] It should be noted that the control unit 301 virtually creates multiple virtual memory devices, allocates the virtually created multiple virtual memory devices to the processing units connected to the memory sharing control device 300, and dynamically adjusts the correspondence relationship between the virtual memory devices and the processing units, which can be realized according to the control instructions received by the driver of the operating system transmitted through the dedicated channel. That is, the driver in the operating system of the computer device where the memory sharing control device 300 is located sends instructions for virtually creating multiple virtual memory devices, allocating virtual memory devices to processing units, and dynamically adjusting the correspondence relationship between virtual memory devices and processing units to the memory sharing control device 300 through a dedicated channel, and the control unit 301 realizes the corresponding functions according to the received control instructions.

[0249] The memory sharing control device 300 described above is connected with the processor through a serial bus based on a serial-parallel conversion interface (for example, a Serdes interface), which can realize long-distance transmission between the memory sharing control device 300 and the processor while ensuring the speed of the processor accessing the memory, so that the processor can quickly access the memory resources in the shared memory pool. Since the memory resources in the shared memory pool can be allocated to different processing units for memory access at different times, the utilization rate of the memory resources is improved.

[0250] For example, the control unit 301 in the memory sharing control device 300 can dynamically adjust the correspondence relationship between the virtual memory devices and the processing units. When the demand for memory space of a certain processing unit increases, the unoccupied virtual memory device or the virtual memory device that has been allocated to other processing units but is temporarily idle is adjusted to the processing unit with increased demand for memory, that is, the correspondence relationship between these idle virtual memory devices and the processing unit with increased demand is established. In this way, the existing memory resources can be effectively utilized to meet the different business demands of the processing units, not only ensuring the demand for memory space of the processing units in different business scenarios, but also improving the utilization rate of the memory resources.

[0251] Figure 7B Another structural schematic diagram of the memory sharing control device 300 provided by the embodiment of the present application is provided. Figure 7B The memory sharing control device 300 shown in Figure 7A further includes a cache unit 304.

[0252] The cache unit 304, which can be a random access memory (RAM), is used to cache data that the processing unit needs to access when accessing the memory. For example, data that the processing unit needs to read is read from the shared memory pool in advance and cached in the cache unit 304, so as to achieve the purpose of fast access of the processing unit to the data, and further improve the speed of reading data of the processing unit. The cache unit 304 can also cache data evicted by the processing unit, such as Cacheline data evicted by the processing unit. Through the cache unit 304, the speed of accessing memory data of the processing unit can be further improved.

[0253] In an optional implementation, the cache unit 304 can include a first-level cache and a second-level cache. As shown in FIG. 3, the cache unit 304 in the memory sharing control device 300 further includes a first-level cache 3041 and a second-level cache 3042, wherein: Figure 7C

[0254] The first-level cache 3041 can be a small-capacity (for example, a capacity of 100 MB) cache, and can be a nanosecond-level SRAM medium. The first-level cache 3041 caches Cacheline data evicted from the processing unit.

[0255] The second-level cache 3042 can be a large-capacity (for example, a capacity of 1 GB) cache, and can be a DRAM medium. The second-level cache 3042 can cache Cacheline data evicted from the first-level cache and data prefetched from the memory 220 (for example, a DDR or PCM medium) at a granularity of 4 KB per page. The Cacheline data is data in the cache. For example, the cache in the cache unit 304 is composed of three parts of valid bits, tag bits and data bits, each row contains the three kinds of data, and one row of data constitutes a Cacheline. When the processing unit initiates a memory access request, the Cacheline data in the cache is read or the data is written into the cache by matching the data in the memory access request with the corresponding bits of the cache.

[0256] For example, when the memory sharing control device 300 is implemented by an FPGA chip as shown in FIG. 4, the functions of the above-mentioned cache unit 304 can be implemented by configuring the BRAM in the FPGA chip 400, or the functions of the above-mentioned first-level cache 3041 and second-level cache 3042 can be implemented by configuring the BRAM in the FPGA chip 400. Figure 3 Figure 3 Figure 3

[0257] ​​​​The cache unit 304 further comprises a first cache 3041 and a second cache 3042, which can increase the space of the cache, expand the range of the fast access of the processing unit to the memory through the cache, and further improve the speed of the processor resource pool in accessing the memory.

[0258] Figure 7D is another structure diagram of the memory sharing control device 300 provided by the embodiment of the present application. As shown in Figure 7D the memory sharing control device 300 further comprises a storage unit 305. The storage unit 305 can be a volatile memory such as RAM, and can also comprise a non-volatile memory such as a read-only memory (ROM), a flash memory, etc. The storage unit 305 stores programs or instructions readable by the control unit 301, such as program codes of at least one process or program codes of at least one thread. The control unit 301 realizes corresponding control by executing the program codes in the storage unit 202.

[0259] The program codes stored in the storage unit 305 can comprise at least one of a Qos engine 306, a prefetch engine 307, and a compression / decompression engine 308. Figure 7D In order to conveniently display the functions of the Qos engine 306, the prefetch engine 307, and the compression / decompression engine 308, these engines are displayed outside the control unit 301 and the storage unit 305, which does not mean that these engines are located outside the control unit 301 and the storage unit 305. In the specific implementation, these engines realize corresponding functions by the control unit 301 executing corresponding codes stored in the storage unit 305.

[0260] The Qos engine 306 is configured to control the storage area of the data to be accessed by the processing unit in the cache unit 304 (the first cache 3041 or the second cache 3042) according to the RESOURCE_ID in the memory access request, so as to realize different cache capabilities of the data accessed by different processing units in the cache unit 304. For example, the memory access request initiated by the processing unit with high priority has exclusive cache space in the cache unit 304, so that the data accessed by the processing unit can be cached in time, thereby guaranteeing the quality of the service processing of the processing unit.

[0261] The prefetch engine 307 is used to prefetch data in memory based on a specific algorithm, enabling the processing unit to prefetch the data it needs to read. Different prefetching methods affect the accuracy of prefetching and the efficiency of memory access. By using the prefetch engine 307 to achieve higher precision prefetching based on a specific algorithm, the hit rate when the processing unit accesses memory data can be further improved. For example, the prefetching implemented by the prefetch engine 307 includes, but is not limited to: prefetching cacheline data from L2 cache to L1 cache, or prefetching data from external DRAM or PCM to cache.

[0262] The compression / decompression engine 308 is used to compress or decompress data accessed in memory. For example, it can compress data written to memory by the processing unit at a granularity of 4KB per page using a compression ratio algorithm before writing it back to memory; or, when the processing unit reads compressed data from memory, it can decompress the data to be read before sending it to the processing unit. Optionally, the compression / decompression engine can be disabled. In this way, the compression / decompression engine 308 is deenabled, and the processing unit no longer performs compression or decompression when accessing data in memory.

[0263] The above describes the QoS engine 306, prefetch engine 307, and compression / decompression engine 308 as software modules stored in storage unit 305. Control unit 301 reads the corresponding code from the storage unit to implement the corresponding functions. As an optional implementation, at least one of the QoS engine 306, prefetch engine 307, and compression / decompression engine 308 can also be directly configured in control unit 301 and implemented through the control logic of control unit 301. In this way, control unit 301 can implement the relevant functions by executing the relevant control logic without needing to read the code from storage unit 305. For example, when memory sharing control device 300... Figure 3 When implementing the FPGA chip shown, it can be configured... Figure 3 The CLB in the code implements the functions related to the QoS engine 306, the prefetch engine 307, and the compression / decompression engine 308.

[0264] It is understandable that parts of the QoS engine 306, prefetch engine 307, and compression / decompression engine 308 can be directly implemented by the control unit 301, while others are stored in the storage unit 305. The control unit 301 executes the corresponding functions by reading the software code in the storage unit 305. For example, the QoS engine 306 and prefetch engine 307 are directly implemented through the control logic of the control unit 301, while the compression / decompression engine 308 is software code stored in the storage unit 305. The control unit 301 reads the software code of the compression / decompression engine 308 from the storage unit 305 to implement the functions of the compression / decompression engine 308.

[0265] For example, when the memory sharing control device 300 passes through Figure 3 When implementing the FPGA chip shown, it can be configured... Figure 3 The BRAM in the memory is used to implement the function of the aforementioned storage unit 305.

[0266] The following example illustrates how the memory sharing control device 300 accesses memory, using DRAM and PCM as examples of memory resources connected to it.

[0267] Figure 7E and Figure 7F Two implementations are shown, one using DRAM and the other using PCM as the storage medium for a shared memory pool. Figure 7E In the implementation shown, DRAM and PCM are different types of memory contained in the shared memory pool, without any hierarchical distinction. Data is... Figure 7E The shared memory pool shown does not distinguish between different types of memory when storing data. Additionally, in Figure 7E In this configuration, the DDR controller 3031 controls the DRAM storage medium, and the PCM controller 3032 controls the PCM storage medium. The control unit 301 can access the DRAM through the DDR controller 3031 and the PCM through the PCM controller 3032. Figure 7F In the implementation shown, since DRAM is faster and has higher performance than PCM, DRAM can be used as the first-level memory, where frequently accessed data can be stored preferentially. PCM is used as the second-level memory to store infrequently accessed data or data that has been evicted from DRAM. Figure 7F In this system, the memory controller 303 comprises two parts: PCM control logic and DDR control logic. Memory access requests received by the control unit 301 are routed to the PCM storage medium via the PCM control logic. Based on a preset algorithm or strategy, when an upcoming access is predicted, the data can be pre-cached in DRAM. Subsequent access requests from the control unit 301 can then retrieve the corresponding data from DRAM via the DDR control logic, thereby further improving memory access efficiency.

[0268] As an optional implementation method, in Figure 7EIn the horizontal architecture shown, DRAM and PCM correspond to different memory spaces. For this architecture, the control unit 301 can store frequently accessed (hot) data in DRAM, establishing a mapping between the processing unit initiating the access to frequently accessed hot data and the virtual memory device corresponding to the DRAM memory. This improves memory data read / write speed and extends the lifespan of the main memory system. The control unit 301 can also establish a mapping between the processing unit initiating the access to frequently accessed (cold) data and the virtual memory device corresponding to the PCM memory, storing frequently accessed (cold) data in the PCM. This leverages the non-volatile nature of PCM to ensure the security of important data. Figure 7F The vertical architecture shown leverages the high integration of PCM and the low read / write latency of DRAM. On one hand, larger-capacity PCM main memory can be used to store various types of data, reducing the number of disk accesses. On the other hand, using DRAM as a cache further improves memory access efficiency and performance.

[0269] It should be noted that, although Figure 7E or Figure 7F It includes caching (Level 1 cache 3041 or Level 2 cache 3042), QoS engine 306, prefetch engine 307, and compression / decompression engine 308, but these components are optional implementations. Figure 7E or Figure 7F These components may be excluded, or at least one of these components may be included.

[0270] based on Figure 7E and Figure 7F Based on the characteristics of different architectures, the control unit 301 in the memory sharing control device 300 can create virtual memory devices with different characteristics under different architectures and allocate them to processing units with different business needs. This can more flexibly meet the needs of processing units to access memory resources and further improve the efficiency of processing units when accessing memory.

[0271] Figure 8A-1 This is a schematic diagram of the structure of a computer device 80a provided in an embodiment of this application. Figure 8A-1 As shown, the computer device 80a includes multiple processors (processors 810a to 810a+N), a memory sharing control device 800a, a shared memory pool consisting of N memory units 820a, and a bus 840a. The memory sharing control device 800a is connected to the processors (processors 810a to 810a+N) via the bus 840a, and the shared memory pool (memory units 820a to 820a+N) is connected to the bus 840a. In this embodiment, N is a positive integer greater than or equal to 1.

[0272] Figure 8A-1In this architecture, each processor 810a has its own local memory, for example, processor 810a has local memory 1. Each processor 810a can access its local memory. When it needs to expand the memory resources it needs to access, it can access the shared memory pool through the memory sharing control device 800a. By providing a unified shared memory pool for any processor from processor 810a to processor 810a+N to share, not only can the utilization of memory resources be improved, but the problem of excessive latency caused by cross-processor access when processor 810a accesses the local memory controlled by other processors can also be avoided.

[0273] Optional, Figure 8A-1 The memory sharing control device 800a may also include the logical function of a network adapter, enabling the memory sharing control device 800a to access memory resources in other computer devices via the network, thereby further expanding the scope of shared memory resources and improving the utilization rate of memory resources.

[0274] Figure 8A-2 This is a schematic diagram of the structure of another computer device 80a provided in an embodiment of this application. (See attached diagram.) Figure 8A-2 As shown, computer device 80a also includes network adapter 830a, which is connected to bus 840a via a SerDes interface. Memory sharing control device 800a can access memory resources in other computer devices through network adapter 830a. Figure 8A-2 In the computer device 80a shown, the memory sharing control device 800a may not have the function of a network adapter.

[0275] Figure 8B-1 This is a schematic diagram of the structure of a computer device 80b provided in an embodiment of this application. Figure 8B-1 As shown, computer device 80b includes a processor resource pool consisting of multiple processors 810b (processors 810b to 810b+N), a memory sharing control device 800b, a shared memory pool consisting of multiple memory units 820b (memory units 820b to 820b+N), and a bus 840b. The processor resource pool is connected to the bus 840b via the memory sharing control device 800b, and the shared memory pool is also connected to the bus 840b. Figure 8A-1 or Figure 8A-2 different, Figure 8B-1 or Figure 8B-2 Each processor (any one of processors 810b to 810b+N) does not have its own local memory. Memory access requests from the processors are made through the memory sharing control device 800b in a shared memory pool consisting of memory 820b (memory 820b to memory 820b+N).

[0276] Optional, Figure 8B-1The memory sharing control device 800a in the computer device 80a can also include the logical function of the network adapter, so that the memory sharing control device 800b can also access the memory resources in other computer devices through the network, which can further expand the range of shared memory resources and improve the utilization of memory resources.

[0277] Figure 8B-2 Another structural schematic diagram of a computer device 80b is provided in an embodiment of the present application. As shown in Figure 8B-2 , the computer device 80b also includes a network adapter 830b, which is connected to the bus 840b through a Serdes interface. The memory sharing control device 800b can access the memory resources in other computer devices through the network adapter 830b. In the computer device 80b shown in Figure 8B-2 , the memory sharing control device 800b can not have the function of the network adapter.

[0278] Figure 8A-1 and Figure 8A-2 , and Figure 8B-1 and Figure 8B-2 , the memory sharing control device 80a and the memory sharing control device 80b can be implemented by referring to the implementation of the memory sharing control device 200 in the above Figure 2A or Figure 2B , or the implementation of the memory sharing control device 300 in the above Figures 7A-7F . The processor 810a or the processor 810b can be implemented by referring to the implementation of the processor in the above Figure 6 , and the memory 820a or the memory 820b can be a memory resource such as DRAM or PCM. The network adapter 830a is connected to the bus 840a through a serial interface such as a Serdes interface, and the network adapter 830b is connected to the bus 840b through a serial interface such as a Serdes interface. The bus 840a or the bus 840b can be a PCI e bus.

[0279] In the computer device 80a or the computer device 80b, multiple processors can access the shared memory pool quickly through the memory sharing control device, and the utilization of the memory resources in the shared memory pool can be improved. At the same time, since the network adapter 830 is connected to the bus through a serial interface, the time delay of data transmission between the processor and the network adapter will not be significantly increased with the increase of distance. The computer device 80a or the computer device 80b can expand the memory resources accessible by the processor to other devices connected to the computer device 80a or the computer device 80b through the memory sharing control device and the network adapter, so as to further expand the range of memory resources that can be shared by the processor, and realize the sharing of memory resources in a larger range and further improve the utilization of memory resources.

[0280] It is understood that computer device 80a may also include processors without local memory, which access the shared memory pool through memory sharing control device 800a to achieve memory access. Computer device 80b may also include processors with local memory, which can access both local memory and memory in the shared memory pool through memory sharing control device 800b. Optionally, when some processors in computer device 80b have local memory, most memory accesses by these processors are performed in local memory.

[0281] Figure 9A This is a schematic diagram of the structure of a system 901 provided in an embodiment of this application. For example... Figure 9A As shown, system 901 includes M computer devices, such as computer device 80a, computer device 81a, computer device 82a, etc. In this embodiment, M is a positive integer greater than or equal to 3. The M computer devices are connected through network 910a, which can be an Ethernet-based network or a U-bus-based network. Computer device 81a has a similar structure to computer device 80a, including a processor resource pool consisting of multiple processors (processors 8012a to 8012a+N), a memory sharing control device 8011a, a shared memory pool consisting of multiple memory units (memory units 8013a to 8013a+N), a network adapter 8014a, and a bus 8015a. In computer device 81a, the processor resource pool, memory sharing control device 8011a, and network adapter 8014a are connected to bus 8015a, and the shared memory pool (memory units 8013a to 8013a+N) is connected to memory sharing control device 8011a. Memory access requests initiated by processors in the processor resource pool access the shared memory pool through the memory sharing control device 8011a. The memory sharing control device 8011a can be referenced as described above. Figure 2A or Figure 2B The memory sharing control device 200, or the above Figures 7A-7F The implementation method of the memory sharing control device 300 in the above is as follows. The processor 8012a can refer to the above. Figure 6 The processor is implemented in a specific manner, and the memory 8013a can be DRAM or PCM memory resources. The network adapter 8014a is connected to the bus 8015a via a serial interface, such as a SerDes interface. The bus 8015a can be a PCIe bus.

[0282] Figure 9AEach processor has its own local memory, which is the main memory resource for the processor to access. Take the processor 8012a as an example. The processor 8012a can directly access its local memory 1, and most of the memory access requests of the processor 8012a can be implemented in its memory 1. When the processor 8012a needs more memory for processing burst traffic, it can access the memory resource in the shared memory pool through the memory sharing control device 8011a to meet the demand of the processor 8012a for memory resource. Optionally, the processor 8012a can also access the local memory of other processors, for example, it can access the local memory (memory N) of the processor N, that is, the processor 8012a can also access the local memory of other processors in the manner of memory sharing in the NUMA system.

[0283] The structure of the computer device 82a and other computer devices M can be similar to that of the computer device 80a, and will not be described in detail.

[0284] In the system 901, the processor 80a can access the shared memory pool composed of the memory 8013a through the memory sharing control device 800a, the network adapter 830a, the network 910a, the network adapter 8014a and the memory sharing control device 8011a. That is, the memory resources accessible by the processor 810a include the memory resources in the computer device 80a and the memory resources in the computer device 81a. In a similar manner, the processor 810a can also access the memory resources in all computer devices in the system 901. In this way, when the processor 8012a running on the computer device 81a has low traffic load and has more memory 8013a in the idle state, while the processor 810a in the computer device 80a needs a large amount of memory resource for executing HPC and the like, the memory resources of the computer device 81a can be allocated to the processor 810a in the computer device 80a through the memory sharing control device 800a. In this way, the memory resources in the system 901 are effectively utilized, not only meeting the demand of different computer devices for memory when processing traffic, but also improving the utilization rate of the memory resources of the whole system, which is more obvious in the effect of improving the utilization rate of the memory resources to reduce TCO.

[0285] It should be noted that, Figure 9AIn the system 901 shown, computer device 80a includes a network adapter 830a. In a specific implementation, computer device 80a may also exclude the network adapter 830a, and memory sharing control device 800a may include the control logic for the network adapter. In this case, processor 810a can access other memory resources in the network through memory sharing control device 8011a. For example, processor 80a can access a shared memory pool composed of memory 8013a through memory sharing control device 800a, network 910a, network adapter 8014a, and memory sharing control device 8011a. When computer device 81a also excludes the network adapter 8014a and the function of the network adapter is implemented by memory sharing control device 8011a, processor 80a can access the shared memory pool composed of memory 8013a through memory sharing control device 800a, network 910a, and memory sharing control device 8011a.

[0286] Figure 9B This is a schematic diagram of the structure of a system 902 provided in an embodiment of this application. For example... Figure 9B As shown, system 902 includes M computer devices, such as computer device 80b, computer device 81b, computer device 82b, etc., where M is a positive integer greater than or equal to 3. The M computer devices are connected via network 910b, which can be an Ethernet-based network or a U-bus-based network. Computer device 81b has a similar structure to computer device 80b, including a processor resource pool consisting of multiple processors (processors 8012b to 8012b+N), a memory sharing control device 8011b, a shared memory pool consisting of multiple memory units (memory units 8013b to 8013b+N), a network adapter 8014b, and a bus 8015b. The processor resource pool is connected to bus 8015b via memory sharing control device 8011b, and the shared memory pool and network adapter 8014b are also connected to bus 8015b. Memory sharing control device 8011b can be referenced as described above. Figure 2A or Figure 2B The memory sharing control device 200, or the above Figures 7A-7F The implementation method of the memory sharing control device 300 in the above is as follows. The processor 8012b can refer to the above. Figure 6 The processor is implemented in a specific manner, and memory 8013b can be DRAM or PCM memory resources. Network adapter 8014b connects to bus 8015b via a serial interface, such as a SerDes interface. Bus 8015b can be a PCIe bus.

[0287] The structure of computer device 82b and other computer devices M can be similar to that of computer device 80b, and will not be described in detail here.

[0288] In the system 902, the processor 810b can access the shared memory pool composed of the memory 8013b through the memory sharing control device 800b, the network adapter 830b, the network 910b and the network adapter 8014b. That is, the memory resources accessible by the processor 810b include the memory resources in the computer device 80b and the memory resources in the computer device 81b. In a similar way, the processor 810b can also access the memory resources in all the computer devices in the system 902, so as to regard the memory resources in the system 902 as shared memory resources. In this way, when the processor 8012 running on the computer device 81b has a low service load and has more memory 8013b in an idle state, while the processor 810b in the computer device 80b needs a large amount of memory resources for executing an HPC application, the memory sharing control device 800b can allocate the memory resources of the computer device 81b to the processor 810b in the computer device 80b. In this way, the memory resources in the system 902 are effectively utilized to meet the memory requirements of different computer devices in processing services, and the utilization of the memory resources in the system 902 is improved, which will be more obvious in terms of reducing the TCO by improving the utilization of the memory resources.

[0289] It should be noted that, Figure 9B In the system 902 shown, the computer device 80b includes the network adapter 830b. In a specific implementation, the computer device 80b can also not include the network adapter 830b, and the memory sharing control device 800b can include the control logic of the network adapter, so that the processor 810b can access other memory resources in the network through the memory sharing control device 8011b. For example, the processor 80b can access the shared memory pool composed of the memory 8013b through the memory sharing control device 800b, the network 910b, the network adapter 8014b and the memory sharing control device 8011b. When the computer device 81b also does not include the network adapter 8014b and the function of the network adapter is implemented by the memory sharing control device 8011b, the processor 80b can access the shared memory pool composed of the memory 8013b through the memory sharing control device 800b, the network 910b and the memory sharing control device 8011b.

[0290] Figure 9C A structural schematic diagram of a system 903 provided by an embodiment of the present application is shown in FIG. 9. As shown in FIG. 9, the system 903 includes a plurality of computer devices 80b, 81b, 82b and 83b. The computer device 80b includes a processor 810b, a memory 8011b and a memory sharing control device 800b. The memory sharing control device 800b is connected to the processor 810b and the memory 8011b. The memory sharing control device 800b is configured to control the processor 810b to access the memory resources in the computer devices 81b, 82b and 83b through the memory sharing control device 800b. Figure 9CAs shown, system 903 includes computer devices 80a, 81b, 82c to M. 80a in system 903 is implemented in the same way as 80a in system 901, and 81b in system 903 is implemented in the same way as 81b in system 902. Computer devices 82c to M can be computer devices similar to computer device 80a or similar to computer device 81b. System 903 integrates computer device 80a in system 910 and computer device 81b in system 920, and can also improve the utilization of memory resources in the system through memory sharing.

[0291] It should be noted that in Systems 901-903, computer devices need to transmit memory access requests over the network. Since the network adapter 830b connects to the memory sharing control device via a serial bus through a SerDes interface, the transmission rate and bandwidth of the serial bus can guarantee the data transmission rate. Therefore, although network transmission will have some impact on the data transmission rate, from the perspective of improving memory resource utilization, this method can improve memory resource utilization while maintaining the processor's memory access speed.

[0292] Figure 10 for Figure 8A-1 or Figure 8A-2 The computer device 80a shown, or is Figure 8B-1 or Figure 8B-2 The logic diagram of the computer device 80b implementing memory sharing can also be... Figures 9A-9C The diagram shown illustrates the logic of system 900 implementing memory sharing.

[0293] by Figure 8A-1 Taking the logic diagram of computer device 80a implementing memory sharing as an example, processors 1-4 represent any four processors (or cores within processors) in the processor resource pool composed of processors 810a, memory sharing control device 1000 represents memory sharing control device 800a, and memory 1-4 represent any four memory units in the shared memory pool composed of memory units 820a. Memory sharing control device 1000 virtualizes four virtual memory devices based on memory 1-4 (i.e., Figure 10 The virtual memory devices 1-4 are shown in the diagram. Access control table 1001 records the correspondence between virtual memory devices and processors. When memory sharing control device 1000 receives a memory access request from any of the processors 1-4, it obtains the information of the virtual memory device corresponding to the processor that sent the memory access request based on access control table 1001, and accesses the corresponding memory through memory controller 1002 according to the obtained information of the virtual memory device.

[0294] by Figure 9B Taking the logic diagram of system 902 implementing memory sharing as an example, processors 1-4 represent four processors (or cores within processors) in any one or more computer devices in system 902, memory sharing control device 1000 represents a memory sharing control device in any one computer device, and memory 1-4 represent four memory units in any one or more computer devices in system 900. Memory sharing control device 1000 virtualizes four virtual memory devices (i.e., memory units) based on memory 1-4. Figure 10 The virtual memory devices 1-4 are shown in the diagram. Access control table 1001 records the correspondence between virtual memory devices and processors. When memory sharing control device 1000 receives a memory access request from any of the processors 1-4, it obtains the information of the virtual memory device corresponding to the processor that sent the memory access request based on access control table 1001, and accesses the corresponding memory through memory controller 1002 according to the obtained information of the virtual memory device.

[0295] Figure 11 This is a schematic diagram of the structure of a computer device 1100 provided in an embodiment of this application. Figure 11 As shown, the computer device 1100 includes at least two processing units 1102, a memory sharing control device 1101, and a memory pool. The processing unit is a processor, a core in a processor, or a combination of cores in a processor. The memory pool includes one or more memory modules 1103.

[0296] The at least two processing units 1102 are coupled to the memory sharing control device 1101;

[0297] The memory sharing control device 1101 is used to allocate memory from the memory pool to the at least two processing units 1102 respectively, and at least one memory in the memory pool can be accessed by different processing units at different time periods;

[0298] The at least two processing units 1102 are used to access allocated memory through the memory sharing control device 1101.

[0299] The coupling of the at least two processing units 1102 with the memory sharing control device 1101 means that the at least two processing units 1102 are respectively connected to the memory sharing control device 1101. Any one of the at least two processing units 1102 can be directly connected to the memory sharing control device 1101, or it can be connected through other hardware components (such as other chips).

[0300] Figure 11The specific implementation of the computer device 1100 shown can be implemented with reference to the implementation of the computer device (e.g., the computer device 80a or the computer device 80b, etc.) in the above Figure 8A-1 、 Figure 8A-2 、 Figure 8B-1 and Figure 8B-2 , and can also be implemented with reference to the implementation of the computer device (e.g., the computer device 80a or the computer device 80b, etc.) in the above Figures 9A-9C , and can also be implemented with reference to the implementation shown in the above Figure 10 ; the memory sharing control device 1101 in the computer device 1100 can also be implemented with reference to the implementation of the memory sharing control device 200 in the above Figure 2A or Figure 2B , or the implementation of the memory sharing control device 300 in the above Figures 7A-7F , and will not be described here.

[0301] Figure 11 At least two processing units 1102 in the computer device 1100 shown can access at least one memory in the memory pool at different time periods through the memory sharing control device 1101, so as to meet the demand of the processing units for memory resources and improve the utilization rate of memory resources

[0302] Figure 12 A flowchart of a memory sharing control method provided by an embodiment of the present application is shown. The method can be applied to the computer device shown in the above Figure 8A-1 、 Figure 8A-2 、 Figure 8B-1 or Figure 8B-2 , or can be applied to the computer device (e.g., the computer device 80a or the computer device 80b, etc.) in the above Figures 9A-9C , which includes at least two processing units, a memory sharing control device and a memory pool, and the memory pool includes one or more memories, as shown in the above Figure 12 , the method includes the following steps.

[0303] Step 1200: The memory sharing control device receives a first memory access request sent by a first processing unit in the at least two processing units; wherein the processing unit is a processor, a core in the processor or a combination of cores in the processor.

[0304] Step 1202: The memory sharing control device allocates a first memory for the first processing unit from the memory pool, and the first memory can be accessed by a second processing unit in the at least two processing units at other time periods.

[0305] Step 1204: The first processing unit accesses the first memory through the memory sharing control device.

[0306] Based on Figure 12The method shown allows different processing units to access at least one memory in the memory pool at different times, which can meet the memory resource requirements of the processing units and improve the utilization of memory resources.

[0307] Specifically, Figure 12 The method shown can be referred to the above. Figure 2A or Figure 2B The memory sharing control device 200, or the above Figures 7A-7F The implementation method of the memory sharing control device 300 is not described in detail here.

[0308] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0309] In the embodiments provided in this application, the described device embodiments are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, or may be electrical, mechanical or other forms of connection.

[0310] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments of the present invention, depending on actual needs.

[0311] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A computer device, characterized in that, It includes at least two processing units, a memory sharing control device, and a memory pool, wherein the processing unit is a processor, a core in a processor, or a combination of cores in a processor, and the memory pool includes one or more memory modules; The at least two processing units are coupled to the memory sharing control device, and the at least two processing units are connected to the memory sharing control device via a serial bus; The memory sharing control device is used to allocate memory from the memory pool to the at least two processing units respectively, wherein at least one memory in the memory pool can be accessed by different processing units at different time periods; The at least two processing units are configured to access allocated memory via the memory sharing control device; The memory sharing control device includes a control unit, which is used for: Multiple virtual memory devices are generated from the memory pool, wherein the physical memory corresponding to the first virtual memory device among the multiple virtual memory devices is the first memory allocated to the first processing unit among the at least two processing units; The first virtual memory device is allocated to the first processing unit; The correspondence between the first virtual memory device and the first processing unit is recorded in an access control table. The access control table is maintained by the control unit and includes: the identifier of the first virtual memory device, the starting address of the physical memory address corresponding to the first virtual memory device, the memory size corresponding to the first virtual memory device, the access method, and the identifier of the first processing unit. When preset conditions are met, the access control table is adjusted. The preset conditions are related to the amount of memory access required by the first processing unit.

2. The computer device according to claim 1, characterized in that, The first processing unit of the at least two processing units is configured to send a first memory access request in the form of a serial signal to the memory sharing device via the serial bus, the first memory access request being used to access the first memory allocated to the first processing unit.

3. The computer device according to claim 2, characterized in that, The memory sharing control device includes a processor interface, which is used for: Receive the first memory access request; The first memory access request is converted into a second memory access request in the form of parallel signals.

4. The computer device according to claim 2 or 3, characterized in that, The memory sharing control device includes a control unit, which is used for: Establish a correspondence between the memory address of the first memory in the memory pool and the first processing unit among the at least two processing units, so as to allocate the first memory from the memory pool to the first processing unit.

5. The computer device according to claim 1, characterized in that, The control unit is also used for: When the preset conditions are met, the correspondence between the first virtual memory device and the first processing unit is terminated; Establish a correspondence between the first virtual memory device and the second processing unit among the at least two processing units.

6. The computer device according to any one of claims 1-5, characterized in that, The memory sharing control device further includes a cache unit, which is used to cache data read from the memory pool by any one of the at least two processing units, or to cache data evicted by any one of the at least two processing units.

7. The computer device according to claim 6, characterized in that, The memory sharing control device further includes a prefetch engine, which is used to prefetch data that any one of the at least two processing units needs to read from the memory pool and cache it in the cache unit.

8. The computer device according to claim 6 or 7, characterized in that, The memory sharing control device also includes a Quality of Service (QoS) engine, which is used to optimize the storage of data that any one of the at least two processing units needs to cache in the cache unit.

9. The computer device according to any one of claims 1-8, characterized in that, The memory sharing control device also includes a compression / decompression engine, which is used to compress or decompress data related to memory access.

10. The computer device according to any one of claims 1-9, characterized in that, The first processing unit also has local memory for memory access by the first processing unit.

11. The computer device according to any one of claims 1-10, characterized in that, The memory pool contains multiple memory modules of different media types.

12. A system comprising at least two computer devices as described in claims 1-11, wherein the at least two computer devices as described in claims 1-11 are connected via a network.

13. A memory sharing control device, characterized in that, The memory sharing control device includes a control unit, a processor interface, and a memory interface; The processor interface is used to receive memory access requests sent by at least two processing units; wherein, the processing unit is a processor, a core in a processor, or a combination of cores in a processor, and the memory sharing control device is connected to the at least two processing units via a serial bus; The control unit is configured to allocate memory from a memory pool to the at least two processing units respectively, wherein at least one memory in the memory pool can be accessed by different processing units at different time periods; The control unit is also configured to enable the at least two processing units to access the allocated memory through the memory interface; The control unit is further configured to virtualize multiple virtual memory devices from the memory pool, wherein the physical memory corresponding to the first virtual memory device among the multiple virtual memory devices is the first memory allocated to the first processing unit among the at least two processing units; allocate the first virtual memory device to the first processing unit; record the correspondence between the first virtual memory device and the first processing unit in an access control table, the access control table being maintained by the control unit, the access control table including: the identifier of the first virtual memory device, the starting address of the physical memory address corresponding to the first virtual memory device, the memory size corresponding to the first virtual memory device, the access method, and the identifier of the first processing unit; and adjust the access control table when a preset condition is met, the preset condition being related to the memory access requirements of the first processing unit.

14. The memory sharing control device according to claim 13, characterized in that: The processor interface is further configured to receive, via a serial bus, a first memory access request sent in the form of a serial signal by a first processing unit among the at least two processing units, the first memory access request being used to access first memory allocated to the first processing unit.

15. The memory sharing control device according to claim 14, characterized in that: The processor interface is further configured to convert the first memory access request into a second memory access request in the form of parallel signals, and send the second memory access request to the control unit; The control unit is further configured to implement the second memory access request to access the first memory through the memory interface.

16. The memory sharing control device according to claim 14 or 15, characterized in that: The control unit is further configured to establish a correspondence between the memory address of the first memory in the memory pool and the first processing unit, so as to allocate the first memory from the memory pool to the first processing unit.

17. The memory sharing control device according to claim 13, characterized in that: The control unit is further configured to: when a preset condition is met, release the correspondence between the first virtual memory device and the first processing unit, and establish a correspondence between the first virtual memory device and the second processing unit among the at least two processing units.

18. The memory sharing control device according to any one of claims 13-17, characterized in that, The memory sharing control device also includes a cache unit; The cache unit is used to cache data read from the memory pool by any one of the at least two processing units, or to cache data evicted by any one of the at least two processing units.

19. The memory sharing control device according to claim 18, characterized in that, The memory sharing control device further includes a prefetch engine, which is used to prefetch data that any one of the at least two processing units needs to read from the memory pool and cache it in the cache unit.

20. The memory sharing control device according to claim 18 or 19, characterized in that, The memory sharing control device also includes a Quality of Service (QoS) engine; The QoS engine is used to optimize the storage of data that needs to be cached by any one of the at least two processing units in the cache unit.

21. The memory sharing control device according to any one of claims 13-20, characterized in that, The memory sharing control device also includes a compression / decompression engine; The compression / decompression engine is used to compress or decompress data related to memory access.

22. A method for memory sharing control, characterized in that, The method is applied to a computer device, the computer device including at least two processing units, a memory sharing control device, and a memory pool, the memory pool including one or more memory units, the method comprising: The memory sharing control device receives a first memory access request sent by a first processing unit among at least two processing units; wherein, the processing unit is a processor, a core in a processor, or a combination of cores in a processor, and the memory sharing control device is connected to the at least two processing units via a serial bus; The memory sharing control device allocates first memory to the first processing unit from the memory pool, and the first memory can be accessed by the second processing unit of the at least two processing units at other times. The first processing unit accesses the first memory through the memory sharing control device; The method further includes: The memory sharing control device virtualizes multiple virtual memory devices from the memory pool, wherein the physical memory corresponding to the first virtual memory device among the multiple virtual memory devices is the first memory; The memory sharing control device is further configured to allocate the first virtual memory device to the first processing unit; The memory sharing control device is further configured to record the correspondence between the first virtual memory device and the first processing unit in an access control table. The access control table is maintained by the memory sharing control device and includes: the identifier of the first virtual memory device, the starting address of the physical memory address corresponding to the first virtual memory device, the memory size corresponding to the first virtual memory device, the access method, and the identifier of the first processing unit. The memory sharing control device is also used to adjust the access control table when preset conditions are met, the preset conditions being related to the amount of memory access required by the first processing unit.

23. The method according to claim 22, characterized in that, The method further includes: The memory sharing control device receives a first memory access request sent in the form of a serial signal by the first processing unit of the at least two processing units via a serial bus. The first memory access request is used to access the first memory allocated to the first processing unit.

24. The method according to claim 23, characterized in that, The method further includes: The memory sharing control device converts the first memory access request into a second memory access request in the form of parallel signals, and accesses the first memory according to the second memory access request.

25. The method according to claim 23 or 24, characterized in that, The method further includes: The memory sharing control device establishes a correspondence between the memory address of the first memory in the memory pool and the first processing unit among the at least two processing units.

26. The method according to claim 22, characterized in that, The method further includes: When the preset conditions are met, the memory sharing control device removes the correspondence between the first virtual memory device and the first processing unit, and establishes a correspondence between the first virtual memory device and the second processing unit among the at least two processing units.

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