Port switching circuit, controller, solid-state drive, storage product and server

Abstract

The present invention relates to the technical field of solid-state drives, and discloses a port switching circuit, a controller, a solid-state drive, a storage product, and a server. The port switching circuit includes a mode recognition circuit and a gating circuit. Among them, when the mode recognition circuit recognizes that multiple external devices are connected, the mode recognition circuit outputs a multi-port signal to the gating circuit, and the multi-port signal is used to control the gating circuit to transmit the control signal and data between one external device and one corresponding storage device. According to the number of externally connected devices, the present invention determines the bus interface connected to the gating circuit. That is, when one external device is connected, only one bus interface is used, and the storage device is in a single-port mode. When multiple external devices are connected, each external device uses one bus interface, and the storage device is in a multi-port mode. Thus, on a set of hardware single boards, a single-port / multi-port SSD design is realized, making up for the product specifications of multi-port SSDs.

Description

Technical Field

[0001] The present invention relates to the technical field of solid state drives, and particularly to a port switching circuit, a controller, a solid state drive, a storage product, and a server. Background Art

[0002] A solid state disk (SSD), also known as a solid state drive, is a hard disk made of an array of solid state electronic storage chips. Compared with a hard disk drive (HDD), an SSD has significant advantages in terms of speed, power consumption, capacity, noise, reliability, etc. SSDs include SCSI SSDs, SATA SSDs, and PCIe SSDs. Among them, PCIe SSDs have significant advantages in terms of bandwidth, latency, etc., so the market share of PCIe SSDs is increasing.

[0003] PCIe SSDs are generally used in server products and storage products. PCIe SSDs work in single-port mode in server products and in dual-port mode in storage products. However, when designing the main controller for an SSD controller, due to factors such as the area within the chip die and product cost, the SSD main controller cannot support the dual-port working mode. At this time, hardware developers need to flexibly utilize the peripheral hardware circuits and designs to implement the dual-port working mode of the SSD main controller, thereby realizing the product design of dual-port SSDs. Summary of the Invention

[0004] In view of this, the present invention provides a port switching circuit, a controller, a solid state drive, a storage product, and a server to solve the problem of how to enable an SSD to support both single-port and dual-port simultaneously.

[0005] In a first aspect, the present invention provides a port switching circuit for implementing signal and data transmission between an external device and a storage device. The port switching circuit includes: a mode recognition circuit and a gating circuit. The first end of the mode recognition circuit is connected to the bus interface of the external device, and the second end of the mode recognition circuit is connected to the first end of the gating circuit. The second end of the gating circuit is connected to each bus interface of the storage device. When the mode recognition circuit recognizes that only one external device is connected, the mode recognition circuit outputs a single-port signal to the gating circuit. The single-port signal is used to control the gating circuit to send the control signal sent by the external device to each bus interface, and to control the gating circuit to establish a data transmission connection between the external device and any one or a specified bus interface. When the mode recognition circuit recognizes that multiple external devices are connected, the mode recognition circuit outputs a multi-port signal to the gating circuit. The multi-port signal is used to control the gating circuit to perform control signal and data transmission between one external device and a corresponding one bus interface.

[0006] According to the number of externally connected devices accessed by the present invention, the bus interface connected to the gating circuit is determined. That is, when one externally connected device is accessed, only one bus interface is used, and the storage device is in a single-port mode. When multiple externally connected devices are accessed, each externally connected device uses one bus interface, and the storage device is in a multi-port mode. Thus, on a set of hardware single boards, a single-port / multi-port SSD design is implemented, making up for the product specifications of multi-port SSDs and improving the comprehensive competitiveness of SSD products.

[0007] In an optional implementation manner, the control signals include: a reset signal and a clock signal. Among them, the gating circuit sends the reset signal and the clock signal sent by the externally connected device to each bus interface based on the single-port signal, and each bus interface multiplexes the reset signal and the clock signal; the gating circuit sends the reset signal and the clock signal sent by each externally connected device to a corresponding bus interface based on the multi-port signal.

[0008] In an optional implementation manner, the storage device is a controller of a solid-state drive. The controller of the solid-state drive includes a first bus interface and a second bus interface. The first bus interface includes 4 data interfaces, a clock signal interface, and a reset signal interface. The second bus interface includes 2 data interfaces, a clock signal interface, and a reset signal interface. The mode recognition circuit includes: a U.2 interface connector. Among them, the U.2 interface connector includes a first clock signal interface, a second clock signal interface, a first reset signal interface, a second reset signal interface, an enable output interface, and 4 data interfaces; the first end of the first clock signal interface and the first end of the first reset signal interface are respectively connected to the clock signal interface and the reset clock signal interface of the first externally connected device, and the second end of the first clock signal interface and the second end of the first reset signal interface are connected to the first end of the gating circuit; the first end of the second clock signal interface and the first end of the second reset signal interface are respectively used to be connected to the clock signal interface and the reset clock signal interface of the second externally connected device, and the second end of the second clock signal interface and the second end of the second reset signal interface are connected to the first end of the gating circuit.

[0009] The present invention utilizes the single / double-port SSD recognition signal of the U.2 interface to identify the number of peripheral devices, thereby realizing single-port and multi-port switching control.

[0010] In an alternative embodiment, the gating circuit includes a signal line switching circuit and a data line switching circuit. Among them, the first end of the signal line switching circuit is connected to each clock signal interface, each reset signal interface, and the enable output interface of the U.2 interface connector. The second end of the signal line switching circuit is connected to each bus interface. The signal line switching circuit sends the clock signal and the reset signal to each bus interface based on a single-port signal. The signal line switching circuit transmits the clock signal and the reset signal sent by the first external device to the first bus interface and transmits the clock signal and the reset signal sent by the second external device to the second bus interface based on a multi-port signal. The first end of the data line switching circuit is connected to each data interface and the enable output interface of the U.2 interface connector. The second end of the data line switching circuit is connected to each data interface of each bus interface. When receiving a single-port signal, the data line switching circuit realizes data transmission between the external device and the first bus interface. When receiving a multi-port signal, the data line switching circuit realizes data transmission between the first external device and the first bus interface and data transmission between the second external device and the second bus interface.

[0011] In an alternative embodiment, the signal line switching circuit includes a clock signal switching circuit and a reset signal switching circuit. Among them, the first end of the clock signal switching circuit is connected to each clock signal interface of the U.2 interface connector. The second end of the clock signal switching circuit is connected to the enable output terminal of the U.2 interface connector. The third end of the clock signal switching circuit is connected to the clock signal interface of each bus interface. When receiving a single-port signal, the clock signal switching circuit delivers the clock signal to each bus interface. When receiving a multi-port signal, the clock signal switching circuit delivers the clock signal of the first external device to the first bus interface and delivers the clock signal of the second external device to the second bus interface. The first end of the reset signal switching circuit is connected to each reset signal interface of the U.2 interface connector. The second end of the reset signal switching circuit is connected to the enable output terminal of the U.2 interface connector. The third end of the reset signal switching circuit is connected to the reset signal interface of each bus interface. When receiving a single-port signal, the reset signal switching circuit delivers the reset signal to each bus interface. When receiving a multi-port signal, the reset signal switching circuit delivers the reset signal of the first external device to the first bus interface and transmits the reset signal of the second external device to the second bus interface.

[0012] In an alternative embodiment, the clock signal switching circuit includes: one clock buffer and one 1-bit multiplexer for clock signals. Among them, the first end of the clock buffer is connected to the first clock signal interface of the U.2 interface connector, and the second end of the clock buffer is connected to the third end of the 1-bit multiplexer for clock signals; the first end of the 1-bit multiplexer for clock signals is connected to the second clock signal interface of the U.2 interface connector, the second end of the 1-bit multiplexer for clock signals is connected to the enable output interface of the U.2 interface connector, and the fourth end of the 1-bit multiplexer for clock signals is connected to the clock signal interface of the second bus interface.

[0013] In an alternative embodiment, the clock signal switching circuit includes: one signal direct-through line and one 1-bit multiplexer for clock signals. Among them, the first end of the signal direct-through line is connected to the first clock signal interface of the U.2 interface connector, and the second end of the signal direct-through line is connected to the third end of the 1-bit multiplexer for clock signals and the clock signal interface of the first bus interface; the first end of the 1-bit multiplexer for clock signals is connected to the second clock signal interface of the U.2 interface connector, the second end of the 1-bit multiplexer for clock signals is connected to the enable output interface of the U.2 interface connector, and the fourth end of the 1-bit multiplexer for clock signals is connected to the clock signal interface of the second bus interface.

[0014] In an alternative embodiment, the clock signal switching circuit includes: a first clock buffer, a second clock buffer, a first 2-to-1 clock multiplexer, and a second 2-to-1 clock multiplexer. Among them, the first end of the first clock buffer is connected to the first clock signal interface of the U.2 interface connector, the second end of the first clock buffer is connected to the clock signal interface of the first bus interface, and the second end of the first clock buffer is connected to the third end of the second 2-to-1 clock multiplexer; the first end of the first 2-to-1 clock multiplexer is connected to the first clock signal interface of the U.2 interface connector, the second end of the first 2-to-1 clock multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the first 2-to-1 clock multiplexer is connected to the clock signal interface of the first bus interface; the first end of the second clock buffer is connected to the second clock signal interface of the U.2 interface connector, the second end of the second clock buffer is connected to the clock signal interface of the second bus interface, and the second end of the second clock buffer is connected to the third end of the first 2-to-1 clock multiplexer; the first end of the second 2-to-1 clock multiplexer is connected to the second clock signal interface of the U.2 interface connector, the second end of the second 2-to-1 clock multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the second 2-to-1 clock multiplexer is connected to the clock signal interface of the second bus interface; when the clock signal interface of the external device is connected to the first clock signal interface of the U.2 interface connector and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first clock buffer outputs a homologous clock signal to the first bus interface and the second 2-to-1 clock multiplexer, and the second 2-to-1 clock multiplexer outputs the homologous clock signal to the second bus interface, and the first 2-to-1 clock multiplexer is locked; when the clock signal interface of the external device is connected to the second clock signal interface of the U.2 interface connector and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the second clock buffer outputs a homologous clock signal to the second bus interface and the first 2-to-1 clock multiplexer, and the first 2-to-1 clock multiplexer outputs the homologous clock signal to the first bus interface, and the second 2-to-1 clock multiplexer is locked; when the clock signal interfaces of the first external device and the second external device are respectively connected to the first clock signal interface and the second clock signal interface of the U.2 interface connection and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a multi-port signal, the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer are locked, the first clock buffer outputs a homologous clock signal of the clock signal of the first external device to the first bus interface, and the second clock buffer outputs a homologous clock signal of the clock signal of the second external device to the second bus interface.

[0015] In an alternative embodiment, the clock signal switching circuit includes: a first 2-to-1 clock multiplexer and a second 2-to-1 clock multiplexer. Among them, the first end of the first 2-to-1 clock multiplexer is connected to the first clock signal interface connected to the U.2 interface, the second end of the first 2-to-1 clock multiplexer is connected to the enable output interface connected to the U.2 interface, the third end of the first 2-to-1 clock multiplexer is connected to the second clock signal interface connected to the U.2 interface, and the fourth end of the first 2-to-1 clock multiplexer is connected to the clock signal interface of the first bus interface; the first end of the second 2-to-1 clock multiplexer is connected to the second clock signal interface connected to the U.2 interface, the second end of the second 2-to-1 clock multiplexer is connected to the enable output interface connected to the U.2 interface, the third end of the second 2-to-1 clock multiplexer is connected to the first clock signal interface connected to the U.2 interface, and the fourth end of the second 2-to-1 clock multiplexer is connected to the clock signal interface of the second bus interface; when the clock signal interface of an external device is connected to the first clock signal interface of the U.2 interface connector and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the external device to the second bus interface; when the clock signal interface of an external device is connected to the second clock signal interface of the U.2 interface connector and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the external device to the second bus interface; when the clock signal interfaces of a first external device and a second external device are respectively connected to the first clock signal interface and the second clock signal interface connected to the U.2 interface and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a multi-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the first external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the second external device to the second bus interface.

[0016] In an alternative embodiment, the reset signal switching circuit includes: one signal through-line and one reset signal multiplexer. The first end of the signal through-line is connected to the first reset signal interface of the U.2 interface connector, and the second end of the signal through-line is connected to the reset signal interface of the first bus interface. The first end of the reset signal multiplexer is connected to the second reset signal interface of the U.2 interface connector, the second end of the reset signal multiplexer is connected to the first end of the signal through-line, the third end of the reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the reset signal multiplexer is connected to the reset signal interface of the second bus interface.

[0017] In an alternative embodiment, the reset signal switching circuit includes: a first reset signal multiplexer and a reset signal multiplexer. The first end and the second end of the first reset signal multiplexer are connected to the first reset signal interface and the second reset signal interface of the U.2 interface connector respectively. The third end of the first reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the first reset signal multiplexer is connected to the reset signal interface of the first bus interface. The first end and the second end of the second reset signal multiplexer are connected to the second reset signal interface and the first reset signal interface of the U.2 interface connector respectively. The third end of the second reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the second reset signal multiplexer is connected to the reset signal interface of the second bus interface. When the reset signal interface of an external device is connected to the first reset signal interface of the U.2 interface connector and the first reset signal multiplexer and the second reset signal multiplexer receive a single-port signal, the first reset signal multiplexer outputs the clock signal of the external device to the first bus interface, and the second reset signal multiplexer outputs the clock signal of the external device to the second bus interface. When the reset signal interface of an external device is connected to the second reset signal interface of the U.2 interface connector and the first reset signal multiplexer and the second reset signal multiplexer receive a single-port signal, the first reset signal multiplexer outputs the clock signal of the external device to the first bus interface, and the second reset signal multiplexer outputs the clock signal of the external device to the second bus interface. When the reset signal interfaces of a first external device and a second external device are connected to the first reset signal interface and the second reset signal interface of the U.2 interface connector respectively and the first reset signal multiplexer and the second reset signal multiplexer receive a multi-port signal, the first reset signal multiplexer outputs the reset signal of the first external device to the first bus interface, and the second reset signal multiplexer outputs the reset signal of the second external device to the second bus interface.

[0018] In an alternative embodiment, the data line switching circuit includes: a first data direct line, a second data direct line, a first data line switching sub-circuit, and a second data line switching sub-circuit. Among them, the first data direct line connects the first data interface of the U.2 interface connector to the first data interface of the first bus interface; the second data direct line connects the second data interface of the U.2 interface connector to the second data interface of the first bus interface; the first end of the first data line switching sub-circuit is connected to the third data interface of the U.2 interface connector, the second end of the first data line switching sub-circuit is connected to the enable output port of the U.2 interface connector, and the third end of the first data line switching sub-circuit is connected to the third data interface of the first bus interface and the first data interface of the second bus interface; the first end of the second data line switching sub-circuit is connected to the fourth data interface of the U.2 interface connector, the second end of the second data line switching sub-circuit is connected to the enable output port of the U.2 interface connector, and the third end of the second data line switching sub-circuit is connected to the fourth data interface of the first bus interface and the second data interface of the second bus interface.

[0019] In an alternative embodiment, the first data line switching sub-circuit includes: a first transmit switching circuit and a first receive switching circuit. Among them, the first end of the first transmit switching circuit is connected to the third data interface of the first bus interface, the second end of the first transmit switching circuit is connected to the first data interface of the second bus interface, the third end of the first transmit switching circuit is connected to the third data interface of the U.2 interface connector, and the fourth end of the first transmit switching circuit is connected to the enable output port of the U.2 interface connector; the first end of the first receive switching circuit is connected to the third data interface of the U.2 interface connector, the second end of the first receive switching circuit is connected to the enable output port of the U.2 interface connector, the third end of the first receive switching circuit is connected to the third data interface of the first bus interface, and the fourth end of the first receive switching circuit is connected to the first data interface of the second bus interface.

[0020] In an alternative embodiment, each of the second data line switching sub-circuits includes: a second transmission switching circuit and a second reception switching circuit. Among them, the first end of the second transmission switching circuit is connected to the fourth data interface of the first bus interface, the second end of the second transmission switching circuit is connected to the second data interface of the second bus interface, the third end of the second transmission switching circuit is connected to the fourth data interface of the U.2 interface connector, and the fourth end of the second transmission switching circuit is connected to the enable output port of the U.2 interface connector; the first end of the second reception switching circuit is connected to the fourth data interface of the U.2 interface connector, the second end of the second reception switching circuit is connected to the enable output port of the U.2 interface connector, the third end of the second reception switching circuit is connected to the fourth data interface of the first bus interface, and the fourth end of the second reception switching circuit is connected to the second data interface of the second bus interface; when the second transmission switching circuit receives a single-port signal, the second transmission switching circuit connects the fourth data interface of the first bus interface to the fourth data interface of the U.2 interface connector; when the second transmission switching circuit receives a multi-port signal, the second transmission switching circuit connects the second data interface of the second bus interface to the fourth data interface of the U.2 interface connector; when the second reception switching circuit receives a single-port signal, the second reception switching circuit connects the fourth data interface of the second bus interface to the second data interface of the U.2 interface connector; when the second reception switching circuit receives a multi-port signal, the second reception switching circuit connects the second data interface of the second bus interface to the fourth data interface of the U.2 interface connector.

[0021] In an alternative embodiment, each of the first transmission switching circuit and the second transmission switching circuit includes: a 2:1 signal multiplexer; each of the first reception switching circuit and the second reception switching circuit includes: a 1:2 signal demultiplexer.

[0022] In an alternative embodiment, the port switching circuit further includes: a plurality of signal connectors, wherein the first end of the mode recognition circuit is connected to the bus interface of an external device through a signal connector.

[0023] In an alternative embodiment, the port switching circuit further includes: a backplane, wherein the mode recognition circuit and the signal connectors are both fixed to the backplane.

[0024] In an alternative embodiment, the external device clock signal, reset signal, received and transmitted data are all differential interfaces and differential data.

[0025] In a second aspect, the present invention provides a controller which is applied to a solid-state drive. The controller includes a port switching circuit and a controller body as described in the first aspect and any of its optional embodiments. The controller body includes a first bus interface and a second bus interface, and the first bus interface and the second bus interface are connected to an external device through the port switching circuit.

[0026] The controller of the present invention has a built-in port switching circuit. The port switching circuit identifies the number of external devices connected, and determines the bus interface to which the gating circuit is connected. That is, when one external device is connected, only one bus interface is used, and the storage device is in a single-port mode. When multiple external devices are connected, each external device uses one bus interface, and the storage device is in a multi-port mode. Thus, on a single hardware board, a single-port / multi-port SSD design is realized, the product specifications of multi-port SSDs are supplemented, and the comprehensive competitiveness of SSD products is improved.

[0027] In a third aspect, the present invention provides a solid-state drive, including the controller of the solid-state drive according to the second aspect and a solid-state drive body.

[0028] In a fourth aspect, the present invention provides a storage product, including the solid-state drive according to the third aspect and multiple central processing units. The first end of the mode recognition circuit is connected to the bus interface of the CPU, and the second end of the mode recognition circuit is connected to the first end of the gating circuit. The second end of the gating circuit is connected to each bus interface of the storage device. When the mode recognition circuit recognizes that only one central processing unit is connected, the mode recognition circuit outputs a single-port signal to the gating circuit. The single-port signal is used to control the gating circuit to send the control signal sent by the central processing unit to each bus interface, and to control the gating circuit to realize the data transmission connection between the central processing unit and any one or a designated bus interface. When the mode recognition circuit recognizes that multiple central processing units are connected, the mode recognition circuit outputs a multi-port signal to the gating circuit. The multi-port signal is used to control the gating circuit to perform control signal and data transmission between one central processing unit and a corresponding one bus interface.

[0029] The present invention combines the port switching circuit with the storage product. When the CPU of the storage product operates in the PCIe x2 mode, two ports are output through the gating circuit, and each port performs information transmission with one bus interface of the storage device, thereby improving the flexibility of the storage product to be applicable to various types of hard disk devices.

[0030] In a fifth aspect, the present invention provides a server, including the solid-state drive according to the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0032] Figure 1 It is a schematic diagram of the related art PCIe SSD working in single - port mode in a server product;

[0033] Figure 2 It is a schematic diagram of the related art PCIe SSD working in multi - port mode in a storage product;

[0034] Figure 3 It is a composition diagram of the port switching circuit according to an embodiment of the present invention;

[0035] Figure 4 It is a schematic diagram of the single - port mode of the port switching circuit according to an embodiment of the present invention;

[0036] Figure 5 It is a schematic diagram of the dual - port mode of the port switching circuit according to an embodiment of the present invention;

[0037] Figure 6 It is a composition diagram of the gating circuit according to an embodiment of the present invention;

[0038] Figure 7 It is a composition diagram of the signal line switching circuit according to an embodiment of the present invention;

[0039] Figure 8 It is a composition diagram of the clock signal switching circuit according to an embodiment of the present invention;

[0040] Figure 9 It is a composition diagram of another clock signal switching circuit according to an embodiment of the present invention;

[0041] Figure 10 It is a composition diagram of another clock signal switching circuit according to an embodiment of the present invention;

[0042] Figure 11 It is a composition diagram of another clock signal switching circuit according to an embodiment of the present invention;

[0043] Figure 12 It is a composition diagram of the reset signal switching circuit according to an embodiment of the present invention;

[0044] Figure 13 It is a composition diagram of another reset signal switching circuit according to an embodiment of the present invention;

[0045] Figure 14 It is a composition diagram of another port switching circuit according to an embodiment of the present invention;

[0046] Figure 15 It is a specific circuit structure diagram of a clock signal switching circuit according to an embodiment of the present invention;

[0047] Figure 16 It is a specific circuit structure diagram of a reset signal switching circuit according to an embodiment of the present invention;

[0048] Figure 17 It is a composition diagram of a data line switching circuit according to an embodiment of the present invention;

[0049] Figure 18 It is a composition diagram of another data line switching circuit according to an embodiment of the present invention;

[0050] Figure 19 It is a specific circuit structure diagram of a first receiving switching circuit and a second receiving switching circuit according to an embodiment of the present invention;

[0051] Figure 20 It is a specific circuit structure diagram of a first transmitting switching circuit and a second transmitting switching circuit according to an embodiment of the present invention. Specific Embodiments

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0053] In this embodiment, a port switching circuit is provided. The port switching circuit is used to implement signal and data transmission between an external device and a storage device. The external device can be a server or a storage product, and the storage device can be a PCIe SSD. The PCIe SSD operates in a single-port mode in a server product, that is, the 4 lanes of the SSD PCIe link are connected to one CPU; it operates in a dual-port mode in a storage product, that is, the 4 lanes of the SSD PCIe link are divided into 2 groups, 2 lanes are connected to CPU0, and the other 2 lanes are connected to another 2 CPUs1. The relevant application block diagrams are as Figure 1 and Figure 2 shown.

[0054] Generally speaking, the SSD controller supports the single-port working mode, and its implementation on the hardware circuit is relatively simple. That is, the 4-Lane PCIe TX / RX differential signals, 1 pair of PCIe Clock differential signals, and 1 PCIe Reset signal are directly connected to the corresponding signals of the single-port SSD respectively. However, when designing the main controller of the SSD controller, due to factors such as the area within the chip die and product cost, the SSD main controller cannot support the dual-port working mode. At this time, hardware developers need to flexibly utilize the peripheral hardware circuits and designs to implement the dual-port working mode of the SSD main controller, and then realize the product design of the dual-port SSD.

[0055] Based on the above problems, as Figure 3 shown, the port switching circuit includes: a mode recognition circuit and a gating circuit.

[0056] As Figure 3 shown, the first end of the mode recognition circuit is connected to the bus interface of the external device, and the second end of the mode recognition circuit is connected to the first end of the gating circuit; the second end of the gating circuit is connected to each bus interface of the storage device.

[0057] Specifically, the mode recognition circuit can recognize the number of external devices connected, and make the gating circuit form a single port or multiple ports according to the number of external devices, as follows:

[0058] (1) When the mode recognition circuit recognizes that only one external device is connected, the mode recognition circuit outputs a single-port signal to the gating circuit. The single-port signal is used to control the gating circuit to send the control signal sent by the external device to each bus interface, and to control the gating circuit to realize the data transmission connection between the external device and any one or a specified bus interface;

[0059] (2) When the mode recognition circuit recognizes that multiple external devices are connected, the mode recognition circuit outputs a multi-port signal to the gating circuit. The multi-port signal is used to control the gating circuit to perform the control signal and data transmission between one external device and the corresponding one bus interface.

[0060] Exemplarily, taking the storage device as a PCIe SSD and the external device as a server product as an example, the PCIe SSD includes two bus interfaces, PHY0 and PHY1. The PHY0 bus interface includes 4 data interfaces, and the PHY1 bus interface includes one data interface. The server product has a built-in Central Processing Unit (CPU for short). The CPU operates in the PCIe x4 mode, that is, the CPU has 4 data lines. After the mode recognition circuit recognizes the access of the CPU, the mode recognition circuit sends a single-port signal to the gating circuit. The gating circuit connects the 4 data lines of the CPU to the data interfaces of PHY0, and at the same time, the gating circuit sends all the control signals sent by the CPU to both PHY0 and PHY1 for synchronization of the two bus interfaces.

[0061] Exemplarily, taking the storage device as a PCIe SSD and the external device as a storage product as an example, the storage product includes two CPUs, CPU0 and CPU1. Each CPU operates in the PCIe x2 mode, that is, each CPU has 2 data lines. After the mode recognition circuit recognizes the access of CPU0 and CPU1, the mode recognition circuit sends a multi-port signal to the gating circuit. The gating circuit connects the 2 data lines of CPU0 to the data interfaces of PHY0, and the gating circuit connects the 2 data lines of CPU1 to the data interfaces of PHY1. At the same time, the gating circuit sends all the control signals sent by CPU0 to PHY0, and the gating circuit sends all the control signals sent by CPU1 to PHY1.

[0062] In some alternative embodiments, the bus interface of the external device includes: a clock signal interface, a reset signal interface, and multiple data interfaces. Among them, the control signals include: a reset signal and a clock signal. The clock signal interface, the reset signal interface, and each data interface of the external device are connected to the first end of the mode recognition circuit; the external device outputs the clock signal of the bus interface to the mode recognition circuit through its clock signal interface, the external device outputs the reset signal of the bus interface to the mode recognition circuit through its reset signal interface, and the external device receives or sends data through its data interfaces.

[0063] Specifically, the gating circuit sends the reset signal and the clock signal to each bus interface based on the single-port signal, and realizes data transmission between one corresponding bus interface and the external device; the gating circuit sends the reset signal and the clock signal output by each external device to the corresponding bus interface based on the multi-port signal, and realizes data transmission between each external device and the corresponding bus interface.

[0064] Exemplarily, taking the storage device as a PCIe SSD and the external device as a server product as an example, the gating circuit sends the reset signal and clock signal sent by the CPU to PHY0 and PHY1 based on a single-port signal, that is, PHY1 multiplexes the reset signal and clock signal sent by the CPU.

[0065] Exemplarily, taking the storage device as a PCIe SSD and the external device as a storage product as an example, the gating circuit sends the reset signal and clock signal sent by CPU0 to PHY0 based on a multi-port signal, and the gating circuit sends the reset signal and clock signal sent by CPU1 to PHY1 based on a multi-port signal.

[0066] In some alternative embodiments, the storage device is a controller of a solid-state drive, and the controller of the solid-state drive includes a first bus interface (i.e., PHY0) and a second bus interface (i.e., PHY1). The first bus interface includes 4 data interfaces, a clock signal interface, and a reset signal interface. The second bus interface includes 2 data interfaces, a clock signal interface, and a reset signal interface. The mode recognition circuit includes: a U.2 interface connector, where the U.2 interface connector includes a first clock signal interface, a second clock signal interface, a first reset signal interface, a second reset signal interface, an enable output interface, and 4 data interfaces.

[0067] Specifically, as Figure 4 、 Figure 5 shown, Figure 4 、 Figure 5 In, the 1st pin of the U.2 interface connector is connected to its 9th pin to form a first clock signal interface, the 2nd pin of the U.2 interface connector is connected to its 10th pin to form a first reset signal interface, the 3rd pin of the U.2 interface connector is connected to its 11th pin to form a second clock signal interface, the 4th pin of the U.2 interface connector is connected to its 12th pin to form a second reset signal interface, the 5th pin of the U.2 interface connector is connected to its 14th pin, the 6th pin is connected to the 15th pin, the 7th pin is connected to the 16th pin, and the 8th pin is connected to the 17th pin to form 4 data interfaces. The 13th pin of the U.2 interface connector is an enable output interface.

[0068] Specifically, Figure 4 、 Figure 5 In, the 1st pin and 2nd pin of PHY0 are a clock signal interface and a reset signal interface respectively, and the 3rd to 6th pins of PHY0 are all data interfaces; the 1st pin and 2nd pin of PHY1 are a clock signal interface and a reset signal interface respectively, and the 3rd and 4th pins of PHY1 are all data interfaces.

[0069] Specifically, Figure 4 、 Figure 5Among them, after the 1st pin of the strobe circuit is connected to its 9th pin, it forms its first clock signal interface; after the 2nd pin of the strobe circuit is connected to its 10th pin, it forms its first reset signal interface; after the 3rd pin of the strobe circuit is connected to its 11th pin, it forms its second clock signal interface; after the 4th pin of the strobe circuit is connected to its 12th pin, it forms its second reset signal interface; after the 5th pin of the strobe circuit is connected to its 14th pin, the 6th pin to the 15th pin, the 7th pin to the 16th pin, and the 8th pin to the 17th pin, 4 data interfaces are formed; the 13th pin of the strobe circuit is the enable input interface.

[0070] Specifically, if the external device operates in a 4-data-bus mode, when the 4 data interfaces of the external device are connected to the 4 data interfaces of the U.2 interface connector, the first clock signal interface and the first reset signal interface of the U.2 interface connector respectively receive the clock signal and the reset signal sent by the external device, and the enable output interface outputs a single-port signal. The single-port signal is used to control the strobe circuit to send the clock signal and the reset signal sent by the external device to each bus interface. The strobe circuit also connects the data interface of the external device to the data interface of the first bus interface through the data interface of the U.2 interface connector.

[0071] Exemplarily, taking the storage device as a PCIe SSD and the external device as a server product as an example, as Figure 4 shown, the 1st pin and the 2nd pin of the CPU of the server product are the clock signal interface and the reset signal interface respectively, and the 5th to 8th pins of the CPU of the server product are 4 data interfaces. When the CPU of the server product is connected, the 1st pin and the 2nd pin of the strobe circuit are correspondingly connected to the 1st pin and the 2nd pin of the CPU through the U.2 interface connector, the 5th to 8th pins of the strobe circuit are correspondingly connected to the 5th to 8th pins of the CPU through the U.2 interface connector, the 11th and 12th pins of the strobe circuit are actually also correspondingly connected to the 1st pin and the 2nd pin of the CPU, and the 14th to 17th pins of the strobe circuit are correspondingly connected to the 3rd to 6th pins of PHY0.

[0072] Specifically, when the first external device and the second external device operate in a two-data-bus mode, and the four data interfaces of the two external devices are connected to the four data interfaces of the U.2 interface connector, the first clock signal interface and the first reset signal interface respectively receive the clock signal and the reset signal sent by the first external device, the second clock signal interface and the second reset signal interface respectively receive the clock signal and the reset signal sent by the second external device, and the gating circuit sends the clock signal and the reset signal sent by the first external device to the first bus interface. The gating circuit connects the data interface of the first external device to the data interface of the first bus interface through the data interface of the U.2 interface connector. The gating circuit sends the clock signal and the reset signal sent by the second external device to the second bus interface. The gating circuit connects the data interface of the second external device to the data interface of the second bus interface through the data interface of the U.2 interface connector.

[0073] Exemplarily, taking the storage device as a PCIe SSD and the external device as a storage product as an example, as Figure 5 shown, pin 1 and pin 2 of CPU0 of the server product are the clock signal interface and the reset signal interface respectively, pins 3 and 4 of CPU0 of the server product are two data interfaces, pin 1 and pin 2 of CPU1 are the clock signal interface and the reset signal interface respectively, and pins 3 and 4 of CPU1 of the server product are two data interfaces. When the CPU0 and CPU1 of the storage product are connected, pin 1 and pin 2 of the gating circuit are connected to pin 1 and pin 2 of CPU0 through the U.2 interface connector, pin 3 and pin 4 of the gating circuit are connected to pin 1 and pin 2 of CPU0 through the U.2 interface connector, pin 5 and pin 6 of the gating circuit are connected to pins 3 and 4 of CPU1 through the U.2 interface connector, pin 7 and pin 8 of the gating circuit are connected to pins 3 and 4 of CPU0 through the U.2 interface connector, pin 9 and pin 10 of the gating circuit are respectively connected to pin 1 and pin 2 of PHY0, pin 11 and pin 12 of the gating circuit are respectively connected to pin 1 and pin 2 of PHY1, pin 16 and pin 17 of the gating circuit are respectively connected to pin 3 and pin 4 of PHY0, and pin 14 and pin 15 of the gating circuit are respectively connected to pin 3 and pin 4 of PHY1.

[0074] In some alternative embodiments, as Figure 6 shown, the gating circuit includes: a signal line switching circuit and a data line switching circuit. Figure 6 Taking two bus interfaces as an example.

[0075] As Figure 6 shown, the first end of the signal line switching circuit is connected to each clock signal interface, each reset signal interface, and the enable output interface of the U.2 interface connector, and the second end of the signal line switching circuit is connected to each bus interface. Pins 1 to 4 of the signal line switching circuit respectively correspond to Figure 4 ,Figure 5 Pins 1 to 4 of the strobe circuit and pins 5 to 8 of the signal line switching circuit respectively correspond to Figure 4 , Figure 5 Pins 9 to 12 of the strobe circuit and pin 9 of the signal line switching circuit in Figure 4 , Figure 5 respectively correspond to pin 13 of the strobe circuit in

[0076] Specifically, when the signal line switching circuit receives a single-port signal, the signal line switching circuit sends the clock signal and the reset signal to each bus interface; when the signal line switching circuit receives a multi-port signal, the signal line switching circuit transmits the clock signal and the reset signal sent by the first external device to the first bus interface and transmits the clock signal and the reset signal sent by the second external device to the second bus interface.

[0077] Exemplarily, Figure 6 in, taking the storage device as a PCIe SSD and the external device as a server product as an example, when the server product is connected, pin 9 of the signal line switching circuit receives a single-port signal, pin 1 of the signal line switching circuit receives the clock signal of pin 1 from the CPU through the U.2 interface connector, pin 2 of the signal line switching circuit receives the reset signal of pin 2 from the CPU through the U.2 interface connector, both PHY0 and PHY1 receive the clock signal from pin 5 of the signal line switching circuit and the reset signal from pin 7 of the signal line switching circuit, that is, PHY0 and PHY1 multiplex the clock signal and the reset signal of the CPU.

[0078] Exemplarily, Figure 6 in, taking the storage device as a PCIe SSD and the external device as a storage product as an example, when the storage product is connected, pin 9 of the signal line switching circuit receives a multi-port signal, pins 1 and 2 of the signal line switching circuit receive the clock signal and the reset signal of pins 1 and 2 from CPU0 through the U.2 interface connector, pins 3 and 4 of the signal line switching circuit receive the clock signal and the reset signal of pins 1 and 2 from CPU1 through the U.2 interface connector, PHY0 receives the clock signal and the reset signal from pins 5 and 6 of the signal line switching circuit, and PHY1 receives the clock signal and the reset signal from pins 7 and 8 of the signal line switching circuit.

[0079] As Figure 6 shown, the first end of the data line switching circuit is connected to each data interface and the enable output interface of the U.2 interface connector, and the second end of the data line switching circuit is connected to each data interface of each bus interface. Pins 1 to 4 of the data line switching circuit respectively correspond to Figure 4 , Figure 5Pins 5 to 8 of the strobe circuit and pins 5 to 8 of the data line switching circuit respectively correspond to Figure 4 , Figure 5 Pins 14 to 17 of the strobe circuit in and pin 9 of the data line switching circuit respectively correspond to Figure 4 , Figure 5 Pin 13 of the strobe circuit in.

[0080] Specifically, when the data line switching circuit receives a single-port signal, the data line switching circuit connects the 4 data interfaces of the external device to the data interface of the first bus interface through the data interface of the U.2 interface connector; when the data line switching circuit receives a multi-port signal, the data line switching circuit connects the data interface of the first external device to the data interface of the first bus interface through the data interface of the U.2 interface connector, and the data line switching circuit connects the data interface of the second external device to the data interface of the second bus interface through the data interface of the U.2 interface connector.

[0081] Exemplarily, Figure 6 In, taking the storage device as a PCIe SSD and the external device as a storage product as an example, when the server product is connected, pin 9 of the data line switching circuit receives a multi-port signal, pins 1 to 4 of the data line switching circuit respectively receive data from pins 1 to 4 of the CPU through the U.2 interface connector, pins 3 to 6 of PHY0 receive data from pins 5 to 8 of the data line switching circuit, and at the same time, pins 3 to 6 of PHY0 send data to pins 5 to 8 of the data line switching circuit, and pins 1 to 4 of the data line switching circuit send data to pins 1 to 4 of the CPU.

[0082] Exemplarily, Figure 6 In, taking the storage device as a PCIe SSD and the external device as a storage product as an example, when the server product is connected, pin 9 of the data line switching circuit receives a multi-port signal, pins 1 and 2 of the data line switching circuit respectively receive data from pins 3 and 4 of CPU1 through the U.2 interface connector, pins 3 and 4 of the data line switching circuit respectively receive data from pins 3 and 4 of CPU0 through the U.2 interface connector, pins 3 and 4 of PHY0 receive data from pins 7 and 8 of the data line switching circuit, pins 3 and 4 of PHY1 receive data from pins 5 and 6 of the data line switching circuit, and at the same time, pins 3 and 4 of PHY0 send data to pins 7 and 8 of the data line switching circuit, pins 3 and 4 of PHY1 send data to pins 5 and 6 of the data line switching circuit, pins 1 and 2 of the data line switching circuit send data to pins 3 and 4 of CPU1, and pins 3 and 4 of the data line switching circuit send data to pins 3 and 4 of CPU1.

[0083] In some alternative embodiments, such as Figure 7 shown, the signal line switching circuit includes: a clock signal switching circuit and a reset signal switching circuit.

[0084] Such as Figure 7 shown, the first end of the clock signal switching circuit is connected to each clock signal interface of the U.2 interface connector, the second end of the clock signal switching circuit is connected to the enable output end of the U.2 interface connector, and the third end of the clock signal switching circuit is connected to the clock signal interface of each bus interface. Figure 7 Among them, pin 1 and pin 2 of the clock signal switching circuit are equivalent to pin 1 and pin 3 of the gating circuit, pin 3 and pin 4 of the clock signal switching circuit are equivalent to pin 9 and pin 11 of the gating circuit, and pin 5 of the clock signal switching circuit is equivalent to pin 13 of the gating circuit.

[0085] Specifically, when a single-port signal is received, the clock signal switching circuit delivers the clock signal to each bus interface; when a multi-port signal is received, the clock signal switching circuit delivers the clock signal of the first external device to the first bus interface and the clock signal of the second external device to the second bus interface.

[0086] Such as Figure 7 shown, the first end of the reset signal switching circuit is connected to each reset signal interface of the U.2 interface connector, the second end of the reset signal switching circuit is connected to the enable output end of the U.2 interface connector, and the third end of the reset signal switching circuit is connected to the reset signal interface of each bus interface. Pin 1 and pin 2 of the reset signal switching circuit are equivalent to pin 2 and pin 4 of the gating circuit, pin 3 and pin 4 of the clock signal switching circuit are equivalent to pin 10 and pin 12 of the gating circuit, and pin 5 of the clock signal switching circuit is equivalent to pin 13 of the gating circuit.

[0087] Specifically, when a single-port signal is received, the reset signal switching circuit delivers the reset signal to each bus interface; when a multi-port signal is received, the reset signal switching circuit delivers the reset signal of the first external device to the first bus interface and transmits the reset signal of the second external device to the second bus interface.

[0088] Exemplarily, Figure 7In this case, taking the storage device as a PCIe SSD and the external device as a server product as an example, when the server product is connected, the 5th pin of the clock signal switching circuit and the 5th pin of the reset signal switching circuit receive a single-port signal. The 1st pin of the clock signal switching circuit receives the clock signal from the 1st pin of the CPU through the U.2 interface connector, and the 1st pin of the reset signal switching circuit receives the reset signal from the 2nd pin of the CPU through the U.2 interface connector. Both PHY0 and PHY1 receive the clock signal from the 3rd pin of the clock signal switching circuit and the reset signal from the 3rd pin of the reset signal switching circuit, that is, PHY0 and PHY1 multiplex the clock signal and the reset signal of the CPU.

[0089] Exemplarily, Figure 7 In this case, taking the storage device as a PCIe SSD and the external device as a storage product as an example, when the storage product is connected, the 5th pin of the clock signal switching circuit and the 5th pin of the reset signal switching circuit receive a multi-port signal. The 1st pin and the 2nd pin of the clock signal switching circuit receive the reset signals from the 1st pin of CPU0 and the 1st pin of CPU1 respectively through the U.2 interface connector, and the 1st pin and the 2nd pin of the reset signal switching circuit receive the reset signals from the 2nd pin of CPU0 and the 2nd pin of CPU1 respectively through the U.2 interface connector. PHY0 receives the clock signal from the 3rd pin of the clock signal switching circuit and the reset signal from the 3rd pin of the reset signal switching circuit, and PHY1 receives the clock signal and the reset signal from the 4th pin of the clock signal switching circuit and the 4th pin of the reset signal switching circuit.

[0090] In some alternative embodiments, such as Figure 8 shown, the clock signal switching circuit includes: 1 clock buffer and 1 1-to-2 clock signal multiplexer.

[0091] As Figure 8 shown, the first end of the clock buffer is connected to the first clock signal interface of the U.2 interface connector, and the second end of the clock buffer is connected to the third end of the 1-to-2 clock signal multiplexer.

[0092] As Figure 8 shown, the first end of the 1-to-2 clock signal multiplexer is connected to the second clock signal interface of the U.2 interface connector, the second end of the 1-to-2 clock signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the 1-to-2 clock signal multiplexer is connected to the clock signal interface of the second bus interface.

[0093] Specifically, Figure 8Among them, pin 1 of the clock buffer is equivalent to pin 1 of the gating circuit, pin 2 of the clock buffer is equivalent to pin 9 of the gating circuit, pin 1 of the 2-to-1 clock signal multiplexer is equivalent to pin 3 of the gating circuit, pin 2 of the 2-to-1 clock signal multiplexer is equivalent to pin 13 of the gating circuit, and pin 4 of the 2-to-1 clock signal multiplexer is equivalent to pin 11 of the gating circuit.

[0094] Specifically, when only the clock buffer receives the clock signal and the 2-to-1 clock signal multiplexer receives the single-port signal, the clock buffer buffers the received clock signal and outputs the same-source clock signal. The clock buffer outputs the same-source clock signal to the first bus interface and the 2-to-1 clock signal multiplexer, and the 2-to-1 clock signal multiplexer sends the same-source clock signal to the second bus interface.

[0095] Exemplarily, Figure 8 Among them, taking the storage device as a PCIe SSD and the external device as a server product as an example, when the server product is connected, PHY0 receives the same-source clock signal from pin 2 of the clock buffer, pin 2 of the 2-to-1 clock signal multiplexer receives the single-port signal, and pin 4 of the 2-to-1 clock signal multiplexer outputs the same-source clock signal from pin 2 of the clock buffer, that is, PHY1 receives the same-source clock signal from pin 2 of the clock buffer.

[0096] Specifically, when the clock buffer receives the clock signal of the first external device, the 2-to-1 clock signal multiplexer receives the clock signal of the second external device, and the 2-to-1 clock signal multiplexer receives the multi-port signal, the clock buffer buffers the received clock signal and outputs the same-source clock signal. The clock buffer outputs the same-source clock signal to the first bus interface and the 2-to-1 clock signal multiplexer, and the 2-to-1 clock signal multiplexer sends the received clock signal of the second external device to the second bus interface.

[0097] Exemplarily, Figure 8 Among them, taking the storage device as a PCIe SSD and the external device as a storage product as an example, when the storage product is connected, PHY0 receives the same-source clock signal from pin 2 of the clock buffer, that is, PHY1 receives the clock signal from CPU0. Pin 2 of the 2-to-1 clock signal multiplexer receives the multi-port signal, and pin 4 of the 2-to-1 clock signal multiplexer outputs the same-source clock signal from pin 11 of the U.2 interface connector of the clock buffer, that is, PHY1 receives the clock signal from CPU1.

[0098] It should be noted that Figure 8 Among them, for the server product, when the server product is connected, since the position of the clock buffer is fixed, pin 1 of the CPU of the server product needs to be connected to pin 1 of the U.2 interface connector.

[0099] In some alternative embodiments, such asFigure 9 As shown, the clock signal switching circuit includes: one signal direct-through line and one 2-to-1 clock signal multiplexer. Among them,

[0100] The first end of the signal direct-through line is connected to the first clock signal interface of the U.2 interface connector, and the second end of the signal direct-through line is connected to the third end of the 2-to-1 clock signal multiplexer and the clock signal interface of the first bus interface;

[0101] The first end of the 2-to-1 clock signal multiplexer is connected to the second clock signal interface of the U.2 interface connector, the second end of the 2-to-1 clock signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the 2-to-1 clock signal multiplexer is connected to the clock signal interface of the second bus interface.

[0102] Specifically, when the signal direct-through line receives the clock signal of the external device and the 2-to-1 clock signal multiplexer receives the single-port signal, the signal direct-through line transmits the clock signal to PHY0 and the 2-to-1 clock signal multiplexer, and the 2-to-1 clock signal multiplexer transmits the clock signal to PYH1; specifically, when both the signal direct-through line and the 2-to-1 clock signal multiplexer receive the clock signal, and the 2-to-1 clock signal multiplexer receives the multi-port signal, that is, the first external device is connected to the first clock signal interface of the U.2 interface connector, and the second external device is connected to the second clock signal interface of the U.2 interface connector, the signal direct-through line transmits the clock signal of the first external device to PHY0, and the 2-to-1 clock signal multiplexer transmits the clock signal of the second external device to PHY1.

[0103] In some alternative embodiments, such as Figure 10 As shown, the clock signal switching circuit includes: a first clock buffer, a second clock buffer, a first 2-to-1 clock multiplexer, and a second 2-to-1 clock multiplexer.

[0104] Such as Figure 10 As shown, the first end of the first clock buffer is connected to the first clock signal interface of the U.2 interface connector, the second end of the first clock buffer is connected to the clock signal interface of the first bus interface, and the second end of the first clock buffer is connected to the third end of the second 2-to-1 clock multiplexer;

[0105] Such as Figure 10 As shown, the first end of the first 2-to-1 clock multiplexer is connected to the first clock signal interface of the U.2 interface connector, the second end of the first 2-to-1 clock multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the first 2-to-1 clock multiplexer is connected to the clock signal interface of the first bus interface;

[0106] Such as Figure 10As shown, the first end of the second clock buffer is connected to the second clock signal interface of the U.2 interface connector, the second end of the second clock buffer is connected to the clock signal interface of the second bus interface, and the second end of the second clock buffer is connected to the third end of the first 2-to-1 clock multiplexer;

[0107] As Figure 10 shown, the first end of the second 2-to-1 clock multiplexer is connected to the second clock signal interface of the U.2 interface connector, the second end of the second 2-to-1 clock multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the second 2-to-1 clock multiplexer is connected to the clock signal interface of the second bus interface;

[0108] Specifically, when the clock signal interface of the external device is only connected to the first clock signal interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive single-port signals, the first clock buffer buffers the received clock signal and outputs a homologous clock signal. The first clock buffer sends the homologous clock signal to the second 2-to-1 clock multiplexer and the first bus interface, and the second 2-to-1 clock multiplexer sends the homologous clock signal to the second bus interface.

[0109] Exemplarily, Figure 10 in the case where the storage device is a PCIe SSD and the external device is a server product, when pins 1 and 2 of the CPU are connected to pins 1 and 2 of the U.2 interface connector, that is, when the first clock buffer receives the clock signal from the CPU and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive single-port signals, the first clock buffer outputs a homologous clock signal to PHY0 and the second 2-to-1 clock multiplexer. The single-port signal locks the first 2-to-1 clock multiplexer and unlocks the second 2-to-1 clock multiplexer, and the second 2-to-1 clock multiplexer sends the homologous clock signal to PHY1.

[0110] Specifically, when the clock signal interface of the external device is only connected to the second clock signal interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive single-port signals, the second clock buffer buffers the received clock signal and outputs a homologous clock signal. The second clock buffer sends the homologous clock signal to the first 2-to-1 clock multiplexer and the second bus interface, the first 2-to-1 clock multiplexer sends the homologous clock signal to the first bus interface, and the single-port signal locks the second 2-to-1 clock multiplexer and unlocks the first 2-to-1 clock multiplexer.

[0111] Exemplarily, Figure 10In this case, taking the storage device as a PCIe SSD and the external device as a server product as an example, when pin 1 and pin 2 of the CPU are connected to pin 3 and pin 4 of the U.2 interface connector, that is, when the second clock buffer receives the clock signal from the CPU and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive the single-port signal, the second clock buffer outputs the same-source clock signal to PHY1 and the first 2-to-1 clock multiplexer. This single-port signal locks the second 2-to-1 clock multiplexer and unlocks the first 2-to-1 clock multiplexer, and the first 2-to-1 clock multiplexer sends the same-source clock signal to PHY0.

[0112] Specifically, when the clock signal interface of the first external device is connected to the first clock signal interface of the U.2 interface connector, the clock signal interface of the second external device is connected to the second clock signal interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive the multi-port signal, the first clock buffer outputs the same-source clock signal of the clock signal of the first external device to the first bus interface, and the second clock buffer outputs the same-source clock signal of the clock signal of the second external device to the second bus interface.

[0113] Exemplarily, Figure 10 In this case, taking the storage device as a PCIe SSD and the external device as a storage product as an example, when pin 1 and pin 2 of CPU0 are connected to pin 1 and pin 2 of the U.2 interface connection, and pin 1 and pin 2 of CPU1 are connected to pin 3 and pin 4 of the U.2 interface connection, that is, when the first clock buffer receives the clock signal of CPU0 and at the same time the second clock buffer receives the clock signal of CPU1, the multi-port signal locks the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer. The first clock buffer sends the same-source clock signal of the clock signal of CPU0 to PHY0, and the second clock buffer sends the same-source clock signal of the clock signal of CPU1 to PHY1.

[0114] It should be noted that Figure 10 In this case, when pin 1 and pin 2 of the CPU of the server product are connected to either pin 1 and pin 2 of the U.2 interface connector or pin 3 and pin 4 of the U.2 interface connector, the U.2 interface connector can recognize that only one CPU is connected.

[0115] In some alternative embodiments, such as Figure 11 shown, the clock signal switching circuit includes: a first 2-to-1 clock multiplexer and a second 2-to-1 clock multiplexer.

[0116] Such as Figure 11As shown, the first end of the first 2-to-1 clock multiplexer is connected to the first clock signal interface connected to the U.2 interface, the second end of the first 2-to-1 clock multiplexer is connected to the enable output interface connected to the U.2 interface, the third end of the first 2-to-1 clock multiplexer is connected to the second clock signal interface connected to the U.2 interface, and the fourth end of the first 2-to-1 clock multiplexer is connected to the clock signal interface of the first bus interface.

[0117] As Figure 11 shown, the first end of the second 2-to-1 clock multiplexer is connected to the second clock signal interface connected to the U.2 interface, the second end of the second 2-to-1 clock multiplexer is connected to the enable output interface connected to the U.2 interface, the third end of the second 2-to-1 clock multiplexer is connected to the first clock signal interface connected to the U.2 interface, and the fourth end of the second 2-to-1 clock multiplexer is connected to the clock signal interface of the second bus interface.

[0118] When the clock signal interface of the external device is connected to the first clock signal interface of the U.2 interface connector and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the external device to the second bus interface.

[0119] Specifically, when the clock signal interface of the external device is connected to the first clock signal interface of the U.2 interface connector and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the external device to the second bus interface.

[0120] Exemplarily, Figure 11 in, when the clock signal interface of the CPU is connected to pin 9 of the U.2 interface connector, at this time, the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, and both the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive the clock signal of the CPU, then the first 2-to-1 clock multiplexer sends the clock signal to CPU0, and the second 2-to-1 clock multiplexer sends the clock signal to CPU1.

[0121] Specifically, when the clock signal interface of the external device is connected to the second clock signal interface of the U.2 interface connector and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the external device to the second bus interface.

[0122] Exemplarily, Figure 11In the case where the clock signal interface of the CPU is connected to pin 11 of the U.2 interface connector, at this time, the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal. Since both the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive the clock signal of the CPU, the first 2-to-1 clock multiplexer sends the clock signal to CPU0, and the second 2-to-1 clock multiplexer sends the clock signal to CPU1.

[0123] Specifically, when the clock signal interfaces of the first external device and the second external device are respectively connected to the first clock signal interface and the second clock signal interface of the U.2 interface, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a multi-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the first external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the second external device to the second bus interface.

[0124] Exemplarily, Figure 11 In the case where the clock signal interface of CPU0 is connected to pin 9 of the U.2 interface connector and the clock signal interface of CPU1 is connected to pin 11 of the U.2 interface connector, at this time, the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal. Since the first 2-to-1 clock multiplexer receives the clock signal of CPU0 and the second 2-to-1 clock multiplexer receives the clock signal of CPU1, the first 2-to-1 clock multiplexer sends the clock signal of CPU0 to CPU0, and the second 2-to-1 clock multiplexer sends the clock signal of CPU1 to CPU1.

[0125] It should be noted that for Figure 10 、 Figure 11 the structure shown, generally, when only one CPU is connected, due to the U.2 interface specification and the relevant protocols in the solid-state drive, this CPU can only be connected to pin 9 of the U.2 interface connector. However, for the case where the CPU is connected to pin 11 of the U.2 interface connector, it can also be achieved under the condition of adaptively modifying the relevant protocols, etc.

[0126] In some alternative embodiments, as Figure 12 shown, the reset signal switching circuit includes: 1 signal direct-through line and 1 reset signal multiplexer.

[0127] As Figure 12As shown, the first end of the signal direct-through line is connected to the first reset signal interface of the U.2 interface connector, and the second end of the signal direct-through line is connected to the reset signal interface of the first bus interface; the first end of the reset signal multiplexer is connected to the second reset signal interface of the U.2 interface connector, the second end of the reset signal multiplexer is connected to the first end of the signal direct-through line, the third end of the reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the reset signal multiplexer is connected to the reset signal interface of the second bus interface.

[0128] Specifically, when the signal direct-through line receives a reset signal and the reset signal multiplexer receives a single-port signal, the signal direct-through line transmits the reset signal to the first bus interface and the reset signal multiplexer, and each reset signal multiplexer transmits the reset signal transmitted by the signal direct-through line to the second bus interface.

[0129] Exemplarily, Figure 12 In, taking the storage device as a PCIe SSD and the external device as a server product as an example, when pin 1 and pin 2 of the CPU are connected to pin 1 and pin 2 of the U.2 interface connector, that is, the signal direct-through line receives the reset signal of the CPU and the reset signal multiplexer receives a single-port signal, then the reset signal multiplexer multiplexes the reset signal of the CPU to PHY1.

[0130] Specifically, when the signal direct-through line receives the reset signal of the first external device and the reset signal multiplexer receives the reset signal and multi-port signal of the second external device, the signal direct-through line transmits the reset signal to the first bus interface and the reset signal multiplexer, and the reset signal multiplexer transmits the reset signal of the second external device to the second bus interface.

[0131] Exemplarily, Figure 12 In, taking the storage device as a PCIe SSD and the external device as a server product as an example, when pin 1 and pin 2 of CPU0 are connected to pin 1 and pin 2 of the U.2 interface connector, and pin 1 and pin 2 of CPU1 are connected to pin 3 and pin 4 of the U.2 interface connector, that is, the signal direct-through line receives the reset signal of CPU0, the reset signal multiplexer receives a single-port signal, the reset signal multiplexer receives a single-port signal, the reset signal multiplexer receives a single-port signal, and the reset signal of CPU1, then the reset signal multiplexer multiplexes the reset signal of CPU1 to PHY1.

[0132] In some alternative embodiments, as Figure 13 shown, the reset signal switching circuit includes: a first reset signal multiplexer and a second reset signal multiplexer.

[0133] As Figure 13As shown, the first end and the second end of the first reset signal multiplexer are connected to the first reset signal interface and the second reset signal interface of the U.2 interface connector, the third end of the first reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the first reset signal multiplexer is connected to the reset signal interface of the first bus interface.

[0134] As Figure 13 shown, the first end and the second end of the second reset signal multiplexer are connected to the second reset signal interface and the first reset signal interface of the U.2 interface connector, the third end of the second reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the second reset signal multiplexer is connected to the reset signal interface of the second bus interface.

[0135] Specifically, when the reset signal interface of the external device is connected to the first reset signal interface of the U.2 interface connector, and the first reset signal multiplexer and the second reset signal multiplexer receive a single-port signal, the first reset signal multiplexer outputs the clock signal of the external device to the first bus interface, and the second reset signal multiplexer outputs the clock signal of the external device to the second bus interface.

[0136] Exemplarily, Figure 13 in, taking the storage device as a PCIe SSD and the external device as a server product as an example, when pin 1 and pin 2 of the CPU are connected to pin 1 and pin 2 of the U.2 interface connector, that is, the first reset signal multiplexer and the second reset signal multiplexer receive a single-port signal and the reset signal of the CPU, the first reset signal multiplexer sends the reset signal of the CPU to PHY0, and the second reset signal multiplexer sends the reset signal of the CPU to PHY1.

[0137] Specifically, when the reset signal interface of the external device is connected to the second reset signal interface of the U.2 interface connector, and the first reset signal multiplexer and the second reset signal multiplexer receive a single-port signal, the first reset signal multiplexer outputs the clock signal of the external device to the first bus interface, and the second reset signal multiplexer outputs the clock signal of the external device to the second bus interface.

[0138] Exemplarily, Figure 13 in, taking the storage device as a PCIe SSD and the external device as a server product as an example, when pin 1 and pin 2 of the CPU are connected to pin 3 and pin 4 of the U.2 interface connector, that is, the first reset signal multiplexer and the second reset signal multiplexer receive a single-port signal and the reset signal of the CPU, the first reset signal multiplexer sends the reset signal of the CPU to PHY0, and the second reset signal multiplexer sends the reset signal of the CPU to PHY1.

[0139] Specifically, when the reset signal interfaces of the first external device and the second external device are respectively connected to the first reset signal interface and the second reset signal interface connected by the U.2 interface, and when the first reset signal multiplexer and the second reset signal multiplexer receive the multi-port signal, the first reset signal multiplexer outputs the reset signal of the first external device to the first bus interface, and the second reset signal multiplexer outputs the reset signal of the second external device to the second bus interface.

[0140] Exemplarily, Figure 13 In, taking the storage device as a PCIe SSD and the external device as a server product as an example, when pin 1 and pin 2 of CPU0 are connected to pin 1 and pin 2 of the U.2 interface connector, and pin 1 and pin 2 of CPU1 are connected to pin 3 and pin 4 of the U.2 interface connector, that is, the first reset signal multiplexer receives the single-port signal and the reset signal of CPU0, and the second reset signal multiplexer receives the single-port signal and the reset signal of CPU1, then the first reset signal multiplexer sends the reset signal of CPU0 to PHY0, and the second reset signal multiplexer sends the reset signal of CPU1 to PHY1.

[0141] It should be noted that, Figure 13 In, when only one CPU is connected, no matter whether pin 1 and pin 2 of the CPU are connected to pin 1 and pin 2 of the U.2 interface connector, or pin 1 and pin 2 of the CPU are connected to pin 3 and pin 4 of the U.2 interface connector, the U.2 interface connector can recognize them.

[0142] It should be noted that for Figure 13 the structure shown, generally, when only one CPU is connected, due to the U.2 interface specification and the relevant protocols in the solid-state drive, this CPU can only be connected to pin 10 of the U.2 interface connector. However, for the case where the CPU is connected to pin 12 of the U.2 interface connector, it can also be realized under the condition of adaptively modifying the relevant protocols, etc.

[0143] Based on Figure 8 、 Figure 11 , the structure of the port switching circuit is as Figure 14 shown, Figure 14 In, the single / double port enable output signal DUALPORTEN_n of the U.2 interface connector is used to output high and low levels respectively, where the high level corresponds to the single-port signal and the low level corresponds to the multi-port signal. For the access of different types of products, there are the following two situations:

[0144] (1) When the DUALPORTEN_n signal outputs a high level in the server system, one CPU in the server system operates in the PCIe x4 mode. At this time, the communication signals passing through the U.2 interface connector are one differential PCIe clock signal PCIe_CLK0_P / N, one PCIe reset signal PCIe_RST0_n, one single-port output enable signal DUALPORTEN_n, and four PCIe communication signals PCIe0 to PCIe3. Since the single / double-port enable output signal DUALPORTEN_n is at a high level, the 1:2 PCIe Clock Buffer outputs a homologous clock signal. After passing through the 2:1 PCIe Clock Muxer, the differential clock signals of the SSD controller PHY0 and PHY1 share the PCIe_CLK0_P / N signal from the server side. At the same time, the single-channel PCIe_RST0_n signal from the server side, after passing through the 2:1 Single Muxer, the reset signals of the SSD controller PHY0 and PHY1 share this signal. At this time, the two groups of PCIe2 and PCIe3 signals at the U.2 interface connector end are connected to the two groups of Lane2 and Lane3 end PCIe signals of the SSD controller on-chip PHY0 through the 1:2 PCIe SingleDemuxer, 2:1 PCIe Single Muxer, and the single-port output enable signal. In summary, in the single-port mode, the server system realizes the connection and communication with the internal PCIe signal link of the SSD controller PHY0.

[0145] (2) In the storage system, the single / double-port enable output signal DUALPORTEN_n outputs a low level, and the two CPUs in the storage system work in the PCIe x2 mode respectively. At this time, the relevant communication signals passing through the U.2 interface connector are two differential PCIe clock signals PCIe_CLK0_P / N and PCIe_CLK1_P / N, two PCIe reset signals PCIe_RST0_n and PCIe_RST1_n, one double-port output enable signal DUALPORTEN_n, and four PCIe communication signals PCIe0 to PCIe3. Since the DUALPORTEN_n signal is at a low level, the 1:2 PCIe Clock Buffer outputs a homologous clock signal. After passing through the 2:1 PCIe Clock Muxer, the differential clock signals of the SSD controller PHY0 and PHY1 are respectively from the PCIe_CLK0_P / N signal and PCIe_CLK1_P / N of the two CPUs in the storage system. At the same time, the single-channel PCIe_RST0_n signal from the storage system end passes through the 2:1 Single Muxer, and the reset signals of the SSD controller PHY0 and PHY1 are respectively from the PCIe_RST0_n and PCIe_RST1_n of the two CPUs in the storage system. At this time, the two groups of PCIe2 and PCIe3 signals at the U.2 connector end are connected to the two groups of Lane0 and Lane1 end PCIe signals of the SSD controller on-chip PHY1 through the 1:2 PCIe Single Demuxer, 2:1 PCIe Single Muxer, and the double-port output enable signal. In short, in the dual-port mode, the PCIe0 to PCIe3 of the two CPUs in the storage system are respectively connected and communicate with the internal PCIe signal links of the SSD controller PHY0 (Lane0 to Lane1) and PHY1 (Lane2 to Lane3).

[0146] Figure 14 Among them, the clock buffer and the 2-to-1 clock signal multiplexer respectively select the PCIe3.0 Clock Buffer device 9DBV0231 and the Clock Muxer device 9DMV0141 of the IDT manufacturer, as Figure 15 shown.

[0147] The CLK_IN input pin of the Clock Buffer device 9DBV0231 is connected to the clock signal PCIe_CLK0_P / N at the U.2 interface connector end, and is correctly configured at the peripheral control pins (for example: attached Figure 15The vOE(1:0) in it represents the enable signal of the 2-channel clock signal, which is default pulled down by a 10K resistor, namely the R1 and R2 resistors are pulled down to the ground. The SMbus branch of this chip is not processed by default, so the peripheral circuits of SDATA_3.3 and SCLK_3.3 are not processed. CKPWRGD_PD# indicates that enabling the low level will put this chip into the low-power consumption mode, and this pin is pulled up to the 1.8V power supply level through R3. vHIBW_BYPM_LOBW# represents the default PLL operation. In this application circuit, this pin is divided by two 10K resistors R4 and R5, and this chip is set in the bypass operation mode). Under the condition of power supply to the power pins, 2-channel differential clock signals DIF1 and DIF0 are output. Among them, DIF1 is connected to the 1-channel differential clock signal PCIe0_CLK_P / N of the SSD controller PHY0, and DIF0 is connected to the 1-channel differential clock input signal DIF_INA of the Clock Muxer device. Of course, the hardware connection relationship between DIF1 and DIF0 can be adjusted according to the PCB layout and wiring convenience.

[0148] The other 1-channel differential clock input signal DIF_INB of the Clock Muxer device is connected to the clock signal PCIe_CLK1_P / N at the U.2 interface connector end, and the differential clock output signal DIF0 is connected to the differential clock signal PCIe1_CLK_P / N of the SSD controller PHY1. With the correct configuration of the peripheral control pins (for example: Figure 15OE0# represents the output enable signal, and this pin is default pulled low to ground through the R7 10K resistor; vSW_MODE represents the switch mode signal, and this pin is default pulled low to ground through the R6 10K resistor, indicating the asynchronous working mode). In the case of being powered by the power supply pin, the SEL_A_B# pin is connected to the single / double port signal DUALPORTEN_n at the U.2 connector end: when DUALPORTEN_n outputs a high level, that is, the single port mode, at this time, the differential output clock signal DIF0 of the ClockMuxer device selects the signal at the DIF_INA end, that is, the PCIe_CLK0_P / N signal of the U.2 interface connector; when DUALPORTEN_n outputs a low level, that is, the double port mode, at this time, the differential output clock signal DIF0 of the Clock Muxer device selects the signal at the DIF_INB end, that is, the PCIe_CLK1_P / N signal of the U.2 port. In summary, when the SSD disk works in the single port mode (when DUALPORTEN_n outputs a high level), the differential clock signals PCIe0_CLK_P / N and PCIe1_CLK_P / N of the PHY0 and PHY1 of the SSD controller come from the same source clock signal PCIe_CLK0_P / N; when the SSD disk works in the double port mode (when DUALPORTEN_n outputs a low level), the differential clock signals PCIe0_CLK_P / N and PCIe1_CLK_P / N of the PHY0 and PHY1 of the SSD controller come from non - same - source clock signals PCIe_CLK0_P / N and PCIe_CLK1_P / N respectively.

[0149] For the reset switching circuit working in single and double ports, the detailed circuit is as Figure 16 shown. Figure 16 Select the 2:1 Signal Muxer device TMUX154E of TI manufacturer, connect the A0 input terminal to the PCIe_RST1_n signal of the U.2 interface connector, connect the A1 input terminal to the PCIe_RST0_n signal of the U.2 connector and the PCIe reset signal PCIe0_RSTn input at the PHY0 end of the SSD controller, and connect the A output terminal to the PCIe reset signal PCIe1_RSTn input at the PHY1 end of the SSD controller. With the correct configuration of the peripheral control pins (for example: attach Figure 16EN_n represents the output enable signal, which is default pulled low to ground through the R8 10K resistor) and powered by the power supply pin. When the SEL pin is connected to the single / double port signal DUALPORTEN_n at the U.2 connector end: when DUALPORTEN_n outputs a high level, i.e., the single port mode, the output signal A of the Signal Muxer device selects the signal at the A1 end, i.e., the PCIe_RST0_n signal of the U.2 interface connector; when DUALPORTEN_n outputs a low level, i.e., the double port mode, the output signal A of the Signal Muxer device selects the signal at the A0 end, i.e., the PCIe_RST1_n signal of the U.2 interface connector. In summary, when the SSD operates in the single port mode (when DUALPORTEN_n outputs a high level), the PCIe reset signals PCIe0_RSTn and PCIe1_RSTn of the PHY0 and PHY1 of the SSD controller come from the same reset signal PCIe_RST0_n; when the SSD operates in the double port mode (when DUALPORTEN_n outputs a low level), the PCIe reset signals PCIe0_RSTn and PCIe1_RSTn of the PHY0 and PHY1 of the SSD controller come from non - homologous reset signals PCIe_RST0_n and PCIe_RST1_n respectively.

[0150] In some alternative embodiments, the data interfaces of the U.2 interface connector are the first data interface, the second data interface, the third data interface, and the fourth data interface. The data interfaces of the first bus interface include: the first data interface, the second data interface, the third data interface, and the fourth data interface. The data interfaces of the second bus interface include: the first data interface and the second data interface, as Figure 17 shown, the data line switching circuit includes: a first data direct line, a second data direct line, a first data line switching sub - circuit, and a second data line switching sub - circuit.

[0151] Specifically, the first data direct line connects the first data interface of the U.2 interface connector to the first data interface of the first bus interface; the second data direct line connects the second data interface of the U.2 interface connector to the second data interface of the first bus interface.

[0152] Specifically, the first end of the first data line switching sub-circuit is connected to the third data interface of the U.2 interface connector, the second end of the first data line switching sub-circuit is connected to the enable output port of the U.2 interface connector, and the third end of the first data line switching sub-circuit is connected to the third data interface of the first bus interface and the first data interface of the second bus interface; the first end of the second data line switching sub-circuit is connected to the fourth data interface of the U.2 interface connector, the second end of the second data line switching sub-circuit is connected to the enable output port of the U.2 interface connector, and the third end of the second data line switching sub-circuit is connected to the fourth data interface of the first bus interface and the second data interface of the second bus interface.

[0153] Specifically, if the external device operates in a 4-data bus mode, when the 4 data interfaces of the external device are connected to the 4 data interfaces of the U.2 interface connector, the first data line switching sub-circuit connects the third data interface of the U.2 interface connector to the third data interface of the first bus interface and connects the fourth data interface of the U.2 interface connector to the fourth data interface of the first bus interface.

[0154] Exemplarily, taking the storage device as a PCIe SSD and the external device as a server product, when the CPU is connected, the data interfaces of PHY0 are connected to pins 16, 17 of the U.2 interface connector, the first data line switching sub-circuit, and the second data switching sub-circuit, that is, data is transmitted between PHY0 and the CPU.

[0155] Specifically, when the first external device and the second external device operate in a 2-data bus mode, and the 2 data interfaces of the first external device are connected to the first data interface and the second data interface of the U.2 interface connector, and the 2 data interfaces of the second external device are connected to the third data interface and the fourth data interface of the U.2 interface connector, the first data line switching sub-circuit connects the third data interface of the U.2 interface connector to the first data interface of the second bus interface and connects the fourth data interface of the U.2 interface connector to the second data interface of the second bus interface.

[0156] Exemplarily, taking the storage device as a PCIe SSD and the external device as a storage product, when CPU0 and CPU1 are connected, the data interfaces of PHY0 are connected to pins 16, 17 of the U.2 interface connector, and the data interfaces of PHY1 are connected to the first data line switching sub-circuit and the second data switching sub-circuit, that is, data is transmitted between CPU0 and PHY0, and data is transmitted between CPU1 and PHY1.

[0157] In some alternative embodiments, each of the first data line switching sub-circuits includes: a first transmit switching circuit and a first receive switching circuit.

[0158] The first end of the first transmission switching circuit is connected to the third data interface of the first bus interface, the second end of the first transmission switching circuit is connected to the first data interface of the second bus interface, the third end of the first transmission switching circuit is connected to the third data interface of the U.2 interface connector, and the fourth end of the first transmission switching circuit is connected to the enable output port of the U.2 interface connector;

[0159] The first end of the first reception switching circuit is connected to the third data interface of the U.2 interface connector, the second end of the first reception switching circuit is connected to the enable output port of the U.2 interface connector, the third end of the first reception switching circuit is connected to the third data interface of the first bus interface, and the fourth end of the first reception switching circuit is connected to the first data interface of the second bus interface;

[0160] When the first transmission switching circuit receives a single-port signal, the first transmission switching circuit connects the third data interface of the first bus interface to the third data interface of the U.2 interface connector; when the first transmission switching circuit receives a multi-port signal, the first transmission switching circuit connects the first data interface of the second bus interface to the third data interface of the U.2 interface connector;

[0161] When the first reception switching circuit receives a single-port signal, the first reception switching circuit connects the third data interface of the first bus interface to the third data interface of the U.2 interface connector; when the first reception switching circuit receives a multi-port signal, the first reception switching circuit connects the first data interface of the second bus interface to the third data interface of the U.2 interface connector.

[0162] In some alternative embodiments, each of the second data line switching sub-circuits includes: a second transmission switching circuit and a second reception switching circuit.

[0163] The first end of the second transmission switching circuit is connected to the fourth data interface of the first bus interface, the second end of the second transmission switching circuit is connected to the second data interface of the second bus interface, the third end of the second transmission switching circuit is connected to the fourth data interface of the U.2 interface connector, and the fourth end of the second transmission switching circuit is connected to the enable output port of the U.2 interface connector;

[0164] The first end of the second reception switching circuit is connected to the fourth data interface of the U.2 interface connector, the second end of the second reception switching circuit is connected to the enable output port of the U.2 interface connector, the third end of the second reception switching circuit is connected to the fourth data interface of the first bus interface, and the fourth end of the second reception switching circuit is connected to the second data interface of the second bus interface;

[0165] When the second transmission switching circuit receives a single-port signal, the second transmission switching circuit connects the fourth data interface of the first bus interface to the fourth data interface of the U.2 interface connector; when the second transmission switching circuit receives a multi-port signal, the second transmission switching circuit connects the second data interface of the second bus interface to the fourth data interface of the U.2 interface connector.

[0166] When the second reception switching circuit receives a single-port signal, the second reception switching circuit connects the fourth data interface of the second bus interface to the second data interface of the U.2 interface connector; when the second reception switching circuit receives a multi-port signal, the second reception switching circuit connects the second data interface of the second bus interface to the fourth data interface of the U.2 interface connector.

[0167] Optionally, referring to Figure 18 , both the first transmission switching circuit and the second transmission switching circuit include: a 2:1 signal multiplexer; both the first reception switching circuit and the second reception switching circuit include: a 1:2 signal demultiplexer.

[0168] Figure 18Among them, the PCIe signals such as PCIe0_Tp / Tn, PCIe0_Rp / Rn; PCIe1_Tp / Tn, PCIe1_Rp / Rn of the U.2 interface connector are respectively connected to the PCIe signals such as Lane0_Rp / Rn, Lane0_Tp / Tn; Lane1_Rp / Rn, Lane1_Tp / Tn of the SSD controller PHY0. The PCIe2_Tp / Tn and PCIe3_Tp / Tn of the U.2 interface connector are respectively connected to the PCIe signals such as Lane2_Rp / Rn of the SSD controller PHY0 and Lane0_Rp / Rn of PHY1, and the PCIe signals such as Lane3_Rp / Rn of the SSD controller PHY0 and Lane1_Rp / Rn of PHY1 one by one through the 2-way PCIe signals output by the 1:2 PCIe signal Demuxer device. The 2-way PCIe signals such as Lane2_Tp / Tn of the SSD controller PHY0 and Lane0_Tp / Tn of PHY1 and the 2-way PCIe signals such as Lane3_Tp / Tn of PHY0 and Lane3_Tp / Tn of PHY1 are respectively connected to the PCIe2_Rp / Rn and PCIe3_Rp / Rn signals at the U.2 connector end one by one through the 1-way PCIe signal output by the 2:1 PCIe signal Muxer device. DUALPORTEN_n controls the channel selection of the 1:2 PCIe signal Demuxer device and the 2:1 PCIe signal Muxer device as the switch enable signal. When DUALPORTEN_n outputs a high level, the PCIe2_Tp / Tn and PCIe3_Tp / Tn of the U.2 interface connector are connected to the Lane2_Rp / Rn and Lane3_Rp / Rn signals of the SSD controller PHY0, and the PCIe2_Rp / Rn and PCIe3_Rp / Rn of the U.2 interface connector are connected to the Lane2_Tp / Tn and Lane3_Tp / Tn signals of the SSD controller PHY0; that is, the 4-way PCIe signals on the server side communicate with the 4 groups of PCIe signals inside the SSD controller PHY0. When DUALPORTEN_n outputs a low level, the PCIe2_Tp / Tn and PCIe3_Tp / Tn of the U.2 interface connector are connected to the Lane0_Rp / Rn and Lane1_Rp / Rn signals of PHY1 of the SSD controller PHY1, and the PCIe2_Rp / Rn and PCIe3_Rp / Rn of the U.2 interface connector are connected to the Lane0_Tp / Tn and Lane1_Tp / Tn signals of PHY1 of the SSD controller PHY1; that is, the 2-way PCIe signals of the 2 CPUs of the storage device respectively communicate with the 2 groups of PCIe signals of the SSD controllers PHY0 and PHY1.

[0169] Optionally, as Figure 19As shown in the figure, the 1:2 signal demultiplexer selects the integrated 1:2 4-channel signal separator DS160PR412 from TI, and 2 channels of this application circuit are used. Among them, the two PCIe transmit signals PCIe2_Tp, PCIe2_Tn and PCIe3_Tp, PCIe3_Tn of the U.2 connector are respectively connected one-to-one with the two PCIe transmit signals RX0P, RX0N and RX1P, RX1N of this chip; the A ports TXA0P, TXA0N and B ports TXB0P, TXB0N of the two PCIe TX signals of channel 0 of this chip are respectively connected one-to-one with Lane0_Rp, Lane0_Rn of SSD controller PHY1 and Lane2_Rp, Lane2_Rn of PHY0; the A ports TXA1P, TXA1N and B ports TXB1P, TXB1N of the two PCIe TX signals of channel 1 of this chip are respectively connected one-to-one with Lane1_Rp, Lane1_Rn of SSD controller PHY1 and Lane3_Rp, Lane3_Rn of PHY0.

[0170] The other pins of this chip are for power supply and configuration functions. Among them, the VCC power supply is powered by P3V3 power supply, and power supply filtering is carried out through C1 1uF and C2 0.1uF. VREG1 and VREG2 represent the voltage outputs inside this chip, and these pins are decoupled through C3 0.22uF and C4 0.22uF respectively. The PD pin is pulled down to GND through the R9 10K resistor, indicating the power-on working mode of this chip, not the power-off mode; the MODE pin is for mode configuration function. In this embodiment, this pin is pulled down to GND through the R10 1K resistor. At this time, the other EQ0, EQ1, GAIN, RX_EXT are used as power-on configuration pins to control the functions of this chip; the RX_EXT pin is configured in a floating state, indicating the normal PCIe working mode processed by this chip; the GAIN pin is configured in a floating state, indicating the flat gain set for the entire data path; the EQ0 and EQ1 pins are respectively pulled down to GND through the R11 and R12 resistors. R11 and R12 can select resistance values such as 1K, 13K, 59K or floating processing methods. In actual tests, the internal equalization parameters of this chip can be adjusted by selecting different resistance values, and high-frequency boost is applied to equalize the frequency-dependent insertion loss effect of the passive channel.

[0171] In addition, the DUALPORTEN_n signals at the U.2 connector end are respectively connected one-to-one with the port selection signal SEL of the chip and the GPIO signal at the SSD controller end. When the DUALPORTEN_n signal outputs a high level, the PCIe receive signals RX0P and RX0N of channel 0 of the chip select and conduct the PCIe transmit signals TXB0P and TXB0N of port B, and the PCIe receive signals RX1P and RX1N of channel 1 of the chip select and conduct the PCIe transmit signals TXB1P and TXB1N of port B. That is, the PCIe2 signal and PCIe3 signal from the server end respectively communicate with Lan2 and Lane3 of the SSD controller PHY0. At this time, the SSD controller works in the single-port mode. When the DUALPORTEN_n signal outputs a low level, the PCIe receive signals RX0P and RX0N of channel 0 of the chip select and conduct the PCIe transmit signals TXA0P and TXA0N of port A, and the PCIe receive signals RX1P and RX1N of channel 1 of the chip select and conduct the PCIe transmit signals TXA1P and TXA1N of port A. That is, the PCIe2 signal and PCIe3 signal from the storage device end respectively communicate with Lan0 and Lane1 of the SSD controller PHY1. At this time, the SSD controller works in the dual-port mode.

[0172] Optionally, as Figure 20 shown, the 2:1 signal multiplexer uses the integrated 2:1 4-channel signal multiplexer DS160PR421 from TI, and 2 channels of it are used for the first transmit switching circuit and the second transmit switching circuit. Among them, the TX0P, TX0N of channel 0 of the 2-channel PCIe transmit signal of the chip and the RX1P, RX1N signals of channel 1 are respectively connected one-to-one with the 2-channel PCIe receive signals PCIe2_Rp, PCIe2_Rn and PCIe3_Rp, PCIe3_Rn of the U.2 connector; the RXA0P, RXA0N of port A and the RXB0P, RXB0N of port B in the 2-channel PCIe receive signals of channel 0 of the chip are respectively connected one-to-one with the PCIe transmit signals Lane0_Tp, Lane0_Tn of the SSD controller PHY1 and the PCIe transmit signals Lane2_Tp, Lane2_Tn of PHY0; the RXA1P, RXA1N of port A and the RXB1P, RXB1N of port B in the 2-channel PCIe receive signals of channel 1 of the chip are respectively connected one-to-one with the PCIe transmit signals Lane1_Tp, Lane1_Tn of the SSD controller PHY1 and the PCIe transmit signals Lane3_Tp, Lane3_Tn of PHY0.

[0173] The other pins of the chip are for power supply and configuration functions. Among them, the VCC pin supplies power to the P3V3 power supply, and power filtering is performed through C5 1uF and C6 0.1uF. VREG1 and VREG2 represent the voltage outputs inside the chip, and these pins are decoupled through C7 0.22uF and C8 0.22uF respectively. The PD pin is pulled down to GND through the R16 10K resistor, indicating the power-on working mode of the chip, not the power-off mode; the MODE pin is for mode configuration function. In the patent embodiment, this pin is pulled down to GND through the R13 1K resistor. At this time, other pins such as EQ0, EQ1, GAIN, and RX_EXT are used as power-on configuration pins to control the functions of the chip; the RX_EXT pin is configured in a floating state, representing that the chip processes the normal PCIe working mode; the GAIN pin is configured in a floating state, representing setting the flat gain of the entire data path; the EQ0 and EQ1 pins are pulled down to GND through the R14 and R15 resistors respectively. R14 and R15 can be selected with resistance values such as 1K, 13K, 59K or floating treatment methods. In actual tests, by selecting different resistance values, the internal equalization parameters of the chip can be adjusted, and high-frequency boost is applied to equalize the frequency-dependent insertion loss effect of the passive channel.

[0174] In addition, the DUALPORTEN_n signals at the U.2 connector end are respectively connected one-to-one with the port selection signal SEL of the chip and the GPIO signal of the SSD controller end. When the DUALPORTEN_n signal outputs a high level, the PCIe transmit signals RX0P and RX0N of channel 0 of the chip select to conduct the PCIe transmit signals RXB0P and RXB0N of port B, and the PCIe transmit signals TX1P and TX1N of channel 1 of the chip select to conduct the PCIe transmit signals RXB1P and RXB1N of port B. That is, the PCIe2 signal and PCIe3 signal from the server end communicate with Lan2 and Lane3 of the SSD controller PHY0 respectively. At this time, the SSD controller works in the single-port mode. When the DUALPORTEN_n signal outputs a low level, the PCIe transmit signals TX0P and TX0N of channel 0 of the chip select to conduct the PCIe receive signals RXA0P and RXA0N of port A, and the PCIe transmit signals TX1P and TX1N of channel 1 of the chip select to conduct the PCIe receive signals RXA1P and RXA1N of port A. That is, the PCIe2 signal and PCIe3 signal from the storage device end communicate with Lan0 and Lane1 of the SSD controller PHY1 respectively. At this time, the SSD controller works in the dual-port mode.

[0175] This embodiment starts from an actual SSD controller, utilizes the signal characteristics of the PCIe interface of the SSD controller, and uses the single / double-port SSD signals on the U.2 interface to identify signals. Through the PCIe Clock Buffer, 2:1 PCIe Clock Muxer, and 2:1 Single Muxer in the peripheral hardware circuit, the on-chip PCIe PHY0 and PCIe PHY1 of the SSD controller can automatically switch the clock signals and reset signals in the single-port and double-port modes. Through the 1:2 PCIe SingleDemuxer and 2:1 PCIe Single Muxer in the peripheral hardware circuit, the 4 internal lanes of PCIe PHY0 and the 2 internal lanes of PCIe PHY1 in the SSD controller can automatically switch in the single-port and double-port modes, that is, 4 internal lanes of PCIe PHY0 are used in the single-port mode to form 1 port; in the double-port mode, 2 internal lanes of PCIe PHY0 and 2 internal lanes of PCIe PHY1 are used respectively to form 2 ports. Through the hardware circuit and device proposed in this embodiment, the adaptive design of single-port and double-port SSDs can be realized.

[0176] In some alternative embodiments, the port switching circuit further includes: a plurality of signal connectors and a backplane, wherein the first end of the mode recognition circuit is connected to the bus interface of an external device through a signal connector, and both the mode recognition circuit and the signal connector are fixed to the backplane.

[0177] This embodiment provides a controller for a solid-state drive, including: the port switching circuit and the controller body in the above embodiment and any of its alternative embodiments, wherein the controller body includes a first bus interface and a second bus interface, and the first bus interface and the second bus interface are connected to an external device through the port switching circuit.

[0178] This embodiment provides a solid-state drive, including: the controller of the solid-state drive in the above embodiment and the solid-state drive body.

[0179] This embodiment provides a storage product, including: the solid-state drive in the above embodiment and a plurality of central processing units, wherein

[0180] the first end of the mode recognition circuit is connected to the bus interface of the CPU, and the second end of the mode recognition circuit is connected to the first end of the gating circuit; the second end of the gating circuit is connected to each bus interface of the storage device;

[0181] When the pattern recognition circuit recognizes that only one central processing unit is connected, the pattern recognition circuit outputs a single-port signal to the gating circuit. The single-port signal is used to control the gating circuit to send the control signal sent by the central processing unit to each bus interface, and to control the gating circuit to implement the data transmission connection between the central processing unit and any one or a designated bus interface;

[0182] When the pattern recognition circuit recognizes that multiple central processing units are connected, the pattern recognition circuit outputs a multi-port signal to the gating circuit. The multi-port signal is used to control the gating circuit to perform the control signal and data transmission between one central processing unit and a corresponding one bus interface.

[0183] In this embodiment, a server is provided, including: the solid-state drive of the above embodiment.

[0184] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A port switching circuit, characterized in that: The port switching circuit is used to realize signal and data transmission between the external device and the storage device. The port switching circuit includes: a mode recognition circuit and a gating circuit, wherein: The first end of the mode recognition circuit is connected to the bus interface of the external device, and the second end of the mode recognition circuit is connected to the first end of the gating circuit; The second end of the gating circuit is connected to each bus interface of the storage device; When the mode recognition circuit recognizes that only one external device is connected, the mode recognition circuit outputs a single-port signal to the gating circuit, and the single-port signal is used to control the gating circuit to send the control signal sent by the external device to each bus interface, and control the gating circuit to realize the data transmission connection between the external device and any one or designated bus interface; When the mode recognition circuit recognizes that multiple external devices are connected, the mode recognition circuit outputs a multi-port signal to the selection circuit, and the multi-port signal is used to control the selection circuit to transmit control signals and data between an external device and a corresponding bus interface.

2. The port switching circuit according to claim 1, characterized in that: The control signal includes: a reset signal and a clock signal, wherein: The gating circuit sends the reset signal and the clock signal sent by the external device to each of the bus interfaces based on the single port signal, and each of the bus interfaces multiplexes the reset signal and the clock signal; The gating circuit sends the reset signal and the clock signal sent by each external device to a corresponding bus interface based on the multi-port signal.

3. The port switching circuit according to claim 2, characterized in that: The storage device is a controller of a solid-state hard disk, the controller of the solid-state hard disk includes a first bus interface and a second bus interface, the bus interface of the first bus interface includes four data interfaces, a clock signal interface, and a reset signal interface, the bus interface of the second bus interface includes two data interfaces, a clock signal interface, and a reset signal interface, the mode recognition circuit includes: a U.2 interface connector, wherein, The U.2 interface connector includes a first clock signal interface, a second clock signal interface, a first reset signal interface, a second reset signal interface, an enable output interface, and four data interfaces; The first end of the first clock signal interface and the first end of the first reset signal interface are connected to the clock signal interface and the reset clock signal interface of the first external device respectively, and the second end of the first clock signal interface and the second end of the first reset signal interface are connected to the first end of the gating circuit; The first end of the second clock signal interface and the first end of the second reset signal interface are respectively used to connect to the clock signal interface and the reset clock signal interface of the second external device, and the second end of the second clock signal interface and the second end of the second reset signal interface are connected to the first end of the selection circuit.

4. The port switching circuit according to claim 3, characterized in that: The gating circuit includes: a signal line switching circuit and a data line switching circuit, wherein: The first end of the signal line switching circuit is connected to each clock signal interface, each reset signal interface, and enable output interface of the U.2 interface connector, and the second end of the signal line switching circuit is connected to each bus interface; the signal line switching circuit sends the clock signal and the reset signal to each bus interface based on the single-port signal; the signal line switching circuit transmits the clock signal and the reset signal sent by the first external device to the first bus interface, and transmits the clock signal and the reset signal sent by the second external device to the second bus interface based on the multi-port signal; The first end of the data circuit switching circuit is connected to each data interface and enable output interface of the U.2 interface connector, and the second end of the data circuit switching circuit is connected to each data interface of each bus interface; when the single-port signal is received, the data circuit switching circuit realizes data transmission between the external device and the first bus interface; when the multi-port signal is received, the data circuit switching circuit realizes data transmission between the first external device and the first bus interface, and data transmission between the second external device and the second bus interface.

5. The port switching circuit according to claim 4, characterized in that: The signal line switching circuit includes: a clock signal switching circuit and a reset signal switching circuit, wherein: A first end of the clock signal switching circuit is connected to each clock signal interface of the U.2 interface connector, a second end of the clock signal switching circuit is connected to an enable output end of the U.2 interface connector, and a third end of the clock signal switching circuit is connected to a clock signal interface of each bus interface; When a single-port signal is received, the clock signal switching circuit transmits the clock signal to each bus interface; when a multi-port signal is received, the clock signal switching circuit transmits the clock signal of the first external device to the first bus interface and transmits the clock signal of the second external device to the second bus interface; A first end of the reset signal switching circuit is connected to each reset signal interface of the U.2 interface connector, a second end of the reset signal switching circuit is connected to an enable output end of the U.2 interface connector, and a third end of the reset signal switching circuit is connected to a reset signal interface of each bus interface; When a single-port signal is received, the reset signal switching circuit transmits the reset signal to each bus interface; when a multi-port signal is received, the reset signal switching circuit transmits the reset signal of the first external device to the first bus interface and transmits the reset signal of the second external device to the second bus interface.

6. The port switching circuit according to claim 5, characterized in that: The clock signal switching circuit includes: a clock buffer and a 2-to-1 clock signal multiplexer, wherein: The first end of the clock buffer is connected to the first clock signal interface of the U.2 interface connector, and the second end of the clock buffer is connected to the third end of the 2-to-1 clock signal multiplexer; The first end of the 2-to-1 clock signal multiplexer is connected to the second clock signal interface of the U.2 interface connector, the second end of the 2-to-1 clock signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the 2-to-1 clock signal multiplexer is connected to the clock signal interface of the second bus interface.

7. The port switching circuit according to claim 5, characterized in that: The clock signal switching circuit includes: a signal through line and a 2-to-1 clock signal multiplexer, wherein: The first end of the signal direct line is connected to the first clock signal interface of the U.2 interface connector, and the second end of the signal direct line is connected to the third end of the 2-to-1 clock signal multiplexer and the clock signal interface of the first bus interface; The first end of the 2-to-1 clock signal multiplexer is connected to the second clock signal interface of the U.2 interface connector, the second end of the 2-to-1 clock signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the 2-to-1 clock signal multiplexer is connected to the clock signal interface of the second bus interface.

8. The port switching circuit according to claim 5, characterized in that: The clock signal switching circuit includes: a first clock buffer, a second clock buffer, a first 2-to-1 clock multiplexer, and a second 2-to-1 clock multiplexer, wherein: A first end of the first clock buffer is connected to a first clock signal interface of the U.2 interface connector, a second end of the first clock buffer is connected to a clock signal interface of the first bus interface, and a second end of the first clock buffer is connected to a third end of the second 2-to-1 clock multiplexer; A first end of the first 2-to-1 clock multiplexer is connected to a first clock signal interface of the U.2 interface connector, a second end of the first 2-to-1 clock multiplexer is connected to an enable output interface of the U.2 interface connector, and a fourth end of the first 2-to-1 clock multiplexer is connected to a clock signal interface of the first bus interface; A first end of the second clock buffer is connected to the second clock signal interface of the U.2 interface connector, a second end of the second clock buffer is connected to the clock signal interface of the second bus interface, and a second end of the second clock buffer is connected to a third end of the first 2-to-1 clock multiplexer; A first end of the second 2-to-1 clock multiplexer is connected to the second clock signal interface of the U.2 interface connector, a second end of the second 2-to-1 clock multiplexer is connected to the enable output interface of the U.2 interface connector, and a fourth end of the second 2-to-1 clock multiplexer is connected to the clock signal interface of the second bus interface; When the clock signal interface of the external device is connected to the first clock signal interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first clock buffer outputs a homologous clock signal to the first bus interface and the second 2-to-1 clock multiplexer, and the second 2-to-1 clock multiplexer outputs the homologous clock signal to the second bus interface, and the first 2-to-1 clock multiplexer is locked; When the clock signal interface of the external device is connected to the second clock signal interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the second clock buffer outputs a homologous clock signal to the second bus interface and the first 2-to-1 clock multiplexer, the first 2-to-1 clock multiplexer outputs the homologous clock signal to the first bus interface, and the second 2-to-1 clock multiplexer is locked; When the clock signal interface of the first external device and the clock signal interface of the second external device are respectively connected to the first clock signal interface and the second clock signal interface connected to the U.2 interface, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a multi-port signal, the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer are locked, and the first clock buffer outputs the same source clock signal of the clock signal of the first external device to the first bus interface, and the second clock buffer outputs the same source clock signal of the clock signal of the second external device to the second bus interface.

9. The port switching circuit according to claim 5, characterized in that: The clock signal switching circuit includes: a first 2-to-1 clock multiplexer and a second 2-to-1 clock multiplexer, wherein: A first end of the first 2-to-1 clock multiplexer is connected to a first clock signal interface connected to the U.2 interface, a second end of the first 2-to-1 clock multiplexer is connected to an enable output interface connected to the U.2 interface, a third end of the first 2-to-1 clock multiplexer is connected to a second clock signal interface connected to the U.2 interface, and a fourth end of the first 2-to-1 clock multiplexer is connected to a clock signal interface of the first bus interface; A first end of the second 2-to-1 clock multiplexer is connected to a second clock signal interface connected to the U.2 interface, a second end of the second 2-to-1 clock multiplexer is connected to an enable output interface connected to the U.2 interface, a third end of the second 2-to-1 clock multiplexer is connected to a first clock signal interface connected to the U.2 interface, and a fourth end of the second 2-to-1 clock multiplexer is connected to a clock signal interface of a second bus interface; When the clock signal interface of the external device is connected to the first clock signal interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the external device to the second bus interface; When the clock signal interface of the external device is connected to the second clock signal interface of the U.2 interface connector, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a single-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the external device to the second bus interface; When the clock signal interface of the first external device and the clock signal interface of the second external device are respectively connected to the first clock signal interface and the second clock signal interface connected to the U.2 interface, and the first 2-to-1 clock multiplexer and the second 2-to-1 clock multiplexer receive a multi-port signal, the first 2-to-1 clock multiplexer outputs the clock signal of the first external device to the first bus interface, and the second 2-to-1 clock multiplexer outputs the clock signal of the second external device to the second bus interface.

10. The port switching circuit according to claim 6, characterized in that: The reset signal switching circuit includes: a signal through line and a reset signal multiplexer, wherein: The first end of the signal through line is connected to the first reset signal interface of the U.2 interface connector, and the second end of the signal through line is connected to the reset signal interface of the first bus interface; The first end of the reset signal multiplexer is connected to the second reset signal interface of the U.2 interface connector, the second end of the reset signal multiplexer is connected to the first end of the signal pass-through line, the third end of the reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the reset signal multiplexer is connected to the reset signal interface of the second bus interface.

11. The port switching circuit according to claim 6, characterized in that: The reset signal switching circuit comprises: a first reset signal multiplexer and a second reset signal multiplexer, wherein: The first end and the second end of the first reset signal multiplexer are connected to the first reset signal interface and the second reset signal interface of the U.2 interface connector, the third end of the first reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the first reset signal multiplexer is connected to the reset signal interface of the first bus interface; The first end and the second end of the second reset signal multiplexer are connected to the second reset signal interface and the first reset signal interface of the U.2 interface connector, the third end of the second reset signal multiplexer is connected to the enable output interface of the U.2 interface connector, and the fourth end of the second reset signal multiplexer is connected to the reset signal interface of the second bus interface; When the reset signal interface of the external device is connected to the first reset signal interface of the U.2 interface connector, and the first reset signal multiplexer and the second reset signal multiplexer receive a single-port signal, the first reset signal multiplexer outputs the clock signal of the external device to the first bus interface, and the second reset signal multiplexer outputs the clock signal of the external device to the second bus interface; When the reset signal interface of the external device is connected to the second reset signal interface of the U.2 interface connector, and the first reset signal multiplexer and the second reset signal multiplexer receive a single-port signal, the first reset signal multiplexer outputs the clock signal of the external device to the first bus interface, and the second reset signal multiplexer outputs the clock signal of the external device to the second bus interface; When the reset signal interface of the first external device and the reset signal interface of the second external device are respectively connected to the first reset signal interface and the second reset signal interface connected to the U.2 interface, and the first reset signal multiplexer and the second reset signal multiplexer receive a multi-port signal, the first reset signal multiplexer outputs the reset signal of the first external device to the first bus interface, and the second reset signal multiplexer outputs the reset signal of the second external device to the second bus interface.

12. The port switching circuit according to claim 4, characterized in that: The data line switching circuit comprises: a first data direct line, a second data direct line, a first data line switching sub-circuit, and a second data line switching sub-circuit, wherein: The first data through line connects the first data interface of the U.2 interface connector to the first data interface of the first bus interface; The second data through line connects the second data interface of the U.2 interface connector to the second data interface of the first bus interface; A first end of the first data line switching subcircuit is connected to the third data interface of the U.2 interface connector, a second end of the first data line switching subcircuit is connected to the enable output port of the U.2 interface connector, and a third end of the first data line switching subcircuit is connected to the third data interface of the first bus interface and the first data interface of the second bus interface; The first end of the second data line switching subcircuit is connected to the fourth data interface of the U.2 interface connector, the second end of the second data line switching subcircuit is connected to the enable output port of the U.2 interface connector, and the third end of the second data line switching subcircuit is connected to the fourth data interface of the first bus interface and the second data interface of the second bus interface.

13. The port switching circuit according to claim 12, characterized in that: The first data line switching sub-circuit includes: a first sending switching circuit and a first receiving switching circuit, wherein: A first end of the first transmission switching circuit is connected to the third data interface of the first bus interface, a second end of the first transmission switching circuit is connected to the first data interface of the second bus interface, a third end of the first transmission switching circuit is connected to the third data interface of the U.2 interface connector, and a fourth end of the first transmission switching circuit is connected to the enable output port of the U.2 interface connector; The first end of the first receiving switching circuit is connected to the third data interface of the U.2 interface connector, the second end of the first receiving switching circuit is connected to the enable output port of the U.2 interface connector, the third end of the first receiving switching circuit is connected to the third data interface of the first bus interface, and the fourth end of the first receiving switching circuit is connected to the first data interface of the second bus interface.

14. The port switching circuit according to claim 13, characterized in that: The second data line switching sub-circuit includes: a second sending switching circuit and a second receiving switching circuit, wherein: A first end of the second sending switching circuit is connected to the fourth data interface of the first bus interface, a second end of the second sending switching circuit is connected to the second data interface of the second bus interface, a third end of the second sending switching circuit is connected to the fourth data interface of the U.2 interface connector, and a fourth end of the second sending switching circuit is connected to the enable output port of the U.2 interface connector; A first end of the second receiving switching circuit is connected to the fourth data interface of the U.2 interface connector, a second end of the second receiving switching circuit is connected to the enable output port of the U.2 interface connector, a third end of the second receiving switching circuit is connected to the fourth data interface of the first bus interface, and a fourth end of the second receiving switching circuit is connected to the second data interface of the second bus interface; When the second transmission switching circuit receives a single-port signal, the second transmission switching circuit connects the fourth data interface of the first bus interface to the fourth data interface of the U.2 interface connector; when the second transmission switching circuit receives a multi-port signal, the second transmission switching circuit connects the second data interface of the second bus interface to the fourth data interface of the U.2 interface connector; When the second receiving switching circuit receives a single-port signal, the second receiving switching circuit connects the fourth data interface of the second bus interface to the second data interface of the U.2 interface connector; when the second receiving switching circuit receives a multi-port signal, the second receiving switching circuit connects the second data interface of the second bus interface to the fourth data interface of the U.2 interface connector.

15. The port switching circuit according to claim 14, characterized in that: The first transmission switching circuit and the second transmission switching circuit both include: a 2:1 signal multiplexer; The first receiving switching circuit and the second receiving switching circuit both include: a 1:2 signal demultiplexer.

16. The port switching circuit according to claim 1, characterized in that: Also includes: A plurality of signal connectors, wherein the first end of the pattern recognition circuit is connected to a bus interface of an external device through a signal connector.

17. The port switching circuit according to claim 16, characterized in that: Also includes: A backplane, wherein the mode recognition circuit and the signal connector are both fixed to the backplane.

18. The port switching circuit according to claim 1, characterized in that: The clock signal, reset signal, received and sent data of the external device are all differential interfaces and differential data.

19. A controller, characterized in that: The controller is applied to a solid state drive, and the controller includes: a port switching circuit and a controller body as described in any one of claims 1 to 17, wherein the controller body includes a first bus interface and a second bus interface, and the first bus interface and the second bus interface are connected to an external device through the port switching circuit.

20. A solid state hard disk, characterized in that: include: The solid state drive controller and solid state drive body as described in claim 19.

21. A storage product, characterized in that: include: The solid state drive and multiple central processing units as claimed in claim 20, wherein: A first end of the pattern recognition circuit is connected to a bus interface of the CPU, a second end of the pattern recognition circuit is connected to a first end of the gating circuit; a second end of the gating circuit is connected to each bus interface of the storage device; When the mode recognition circuit recognizes that only one central processor is connected, the mode recognition circuit outputs a single-port signal to the gating circuit, and the single-port signal is used to control the gating circuit to send the control signal sent by the central processor to each bus interface, and control the gating circuit to realize the data transmission connection between the central processor and any one or designated bus interface; When the pattern recognition circuit recognizes that multiple central processing units are connected, the pattern recognition circuit outputs a multi-port signal to the selection circuit, and the multi-port signal is used to control the selection circuit to transmit control signals and data between a central processing unit and a corresponding bus interface.

22. A server, characterized in that: include: The solid state drive of claim 20.

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