Method for generating circuit simulation model, electronic device and storage medium

Abstract

Embodiments of the present disclosure relate to a method for generating a circuit simulation model, an electronic device, and a storage medium. The generation method includes: simulating and optimizing predetermined model parameters of respective initial models of a plurality of semiconductor process devices to determine simulation values ​​of target parameters related to the predetermined model parameters, wherein the plurality of semiconductor process devices have different sizes; in response to the simulation values ​​of the target parameters satisfying predetermined standards, respectively determining the models corresponding to the simulation values ​​satisfying the predetermined standards as corresponding optimization models; arranging the grid points representing the respective optimization models into a matrix based on the size of each semiconductor process device; and determining the circuit simulation model for simulating semiconductor process devices of various sizes based on the relationship between the model parameters of the optimization models represented by each grid point in the matrix and the size of the corresponding semiconductor process device. The technical solution disclosed in the present disclosure can efficiently generate circuit simulation models of semiconductor process devices of various sizes.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to integrated circuits, and more particularly, to a method for generating a circuit simulation model, an electronic device, and a storage medium. Background Art

[0002] Design Technology Co-Optimization (DTCO) is gaining increasing attention in the industry during new process development. Typically, when developing new processes, semiconductor process device simulation (Technology Computer Aided Design, TCAD) is used to simulate processes and devices to obtain the device's electrical characteristics.

[0003] The finite element method used in TCAD requires the generation of a large number of meshes to solve discrete equations, making it impractical for simulating large-scale circuits. Therefore, it is essential to fit TCAD electrical simulation results to a Simulation Program with Integrated Circuit Emphasis (SPICE) model. This SPICE model can then be used for PPA (performance, process, area) simulation verification, or even circuit-level simulation verification. In other words, TCAD is used for early-stage process simulation to determine device characteristics, while later SPICE-level circuit simulation is required. Securing this transition from TCAD to SPICE has become a challenge plaguing the industry. Summary of the Invention

[0004] According to example embodiments of the present disclosure, a circuit simulation model generation solution is provided to at least partially overcome the above or other potential drawbacks.

[0005] According to one aspect of the present disclosure, a method for generating a circuit simulation model is provided, the method comprising: simulating and optimizing predetermined model parameters of respective initial models of a plurality of semiconductor process devices to determine simulation values ​​of target parameters related to the predetermined model parameters, the plurality of semiconductor process devices respectively having different sizes; in response to the simulation values ​​of the target parameters satisfying predetermined standards, determining the models corresponding to the simulation values ​​satisfying the predetermined standards as corresponding optimization models; arranging the grid points representing the respective optimization models into a matrix based on the sizes of the respective semiconductor process devices; and determining the circuit simulation model for simulating semiconductor process devices of respective sizes based on the relationship between the model parameters of the optimization models represented by the respective grid points in the matrix and the sizes of the corresponding semiconductor process devices.

[0006] In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor; and a memory coupled to the processor, the memory having instructions stored therein, which, when executed by the processor, cause the device to perform actions, the actions comprising: performing simulation optimization on predetermined model parameters of respective initial models of a plurality of semiconductor process devices to determine simulation values ​​of target parameters related to the predetermined model parameters, the plurality of semiconductor process devices having different sizes; in response to the simulation values ​​of the target parameters satisfying predetermined criteria, determining the models corresponding to the simulation values ​​satisfying the predetermined criteria as corresponding optimization models; arranging grid points representing the respective optimization models into a matrix based on the sizes of the respective semiconductor process devices; and determining, based on the relationship between the model parameters of the optimization models represented by the respective grid points in the matrix and the sizes of the corresponding semiconductor process devices, a circuit simulation model for simulating semiconductor process devices of respective sizes.

[0007] In some embodiments, simulation optimization of predetermined model parameters of respective initial models of multiple semiconductor process devices includes: taking a curve representing the electrical characteristics of the semiconductor process device obtained from semiconductor process device simulation TCAD or from wafer acceptance test WAT measurement as an optimization target; and simulation optimization of predetermined model parameters related to the target parameters corresponding to the points on the curve, so that the difference between the simulation value corresponding to the target parameter and the target value represented by the point on the curve becomes smaller during the iterative simulation process.

[0008] In some embodiments, simulation optimization of predetermined model parameters of respective initial models of a plurality of semiconductor process devices includes: taking a given value of a predetermined electrical parameter of the semiconductor process device as an optimization target; and simulation optimization of predetermined model parameters related to the predetermined electrical parameter so that the difference between the simulation value and the given value of the predetermined electrical parameter becomes smaller during the iterative simulation process.

[0009] In some embodiments, simulation optimization of predetermined model parameters of respective initial models of multiple semiconductor process devices includes: constructing a Jacobian matrix of each predetermined model parameter, wherein each predetermined model parameter serves as an input variable of a loss function in the Jacobian matrix, and the loss function is a function representing the difference between a simulation value of a target parameter and a target value represented by a point on a curve, or a function representing the difference between a simulation value of a predetermined electrical parameter and a given value; and iteratively optimizing the predetermined model parameters in response to changes in the value of the loss function to obtain optimized model parameters.

[0010] In some embodiments, the simulation value of the target parameter is determined to meet a predetermined criterion based on any one of the following: the value of the loss function during the simulation process is less than a predetermined threshold; the ratio of the simulation values ​​of two iterations before and after the simulation process is less than a predetermined threshold; and the number of iterations or the iteration time during the simulation process reaches a predetermined threshold.

[0011] In some embodiments, arranging the grid points representing each optimization model into a matrix based on the size of each semiconductor process device includes: arranging rows of grid points along a first direction based on a first size parameter of each semiconductor process device; and arranging columns of grid points along a second direction based on a second size parameter of each semiconductor process device.

[0012] In some embodiments, based on the relationship between the model parameters of the optimization model represented by each grid point in the matrix and the size of the corresponding semiconductor process device, determining the circuit simulation model for simulating semiconductor process devices of various sizes includes: determining any model corresponding to a point at any position within the range corresponding to the matrix based on the grid points of each square in the matrix; and determining the combination of each arbitrary model and each optimization model corresponding to each grid point as the circuit simulation model.

[0013] In some embodiments, determining any model corresponding to a point at any position within the range corresponding to the matrix based on the grid points of each square in the matrix includes: performing interpolation processing between the grid points in the matrix to determine the model corresponding to any position within the range corresponding to the matrix except for the grid points.

[0014] In some embodiments, interpolation processing is performed between each grid point in the matrix to determine the model corresponding to any position within the range corresponding to the matrix except for each grid point, including: constructing a set of equations based on a predetermined number of adjacent grid points within a predetermined range in the matrix, wherein each equation in the set of equations respectively represents the relationship between parameters related to the size characteristics of each semiconductor process device and the model parameters of the model represented by each grid point; solving the common characteristic parameters characterizing the optimized models represented by each grid point in the matrix based on the set of equations; and determining the model corresponding to the point at any position in the matrix based on the characteristic parameters and the coordinates of the point at any position within the predetermined range.

[0015] In some embodiments, the parameters related to the characteristics of each semiconductor process device include at least the following: a base parameter, which is a common parameter of each equation in the set of equations; a first size parameter; and a second size parameter.

[0016] In some embodiments, the semiconductor process device is a fin field effect transistor, the first size parameter is the length of the fin field effect transistor, the second size parameter is the number of fins of the fin field effect transistor, and wherein the parameters related to the characteristics of the semiconductor process device also include a third parameter, which is the product of the length and the number of fins.

[0017] In some embodiments, determining any model corresponding to a point at any position within the range corresponding to the matrix based on the grid points of each square in the matrix includes: selecting a square corresponding to the size of the semiconductor process device from the matrix based on the first size parameter, the second size parameter, and the third size parameter of the semiconductor process device corresponding to any position; and constructing a set of equations based on the model parameters and size parameters of the optimized model corresponding to the grid points of the selected square; and solving the set of equations to determine the model parameters of the model corresponding to any point, so as to determine any model corresponding to the point at any position.

[0018] In some embodiments, before simulating and optimizing predetermined model parameters of respective initial models of a plurality of semiconductor process devices, the method further includes: configuring a strategy for optimizing the model parameters and / or a strategy for secondary optimization of key target parameters in a target file; and selecting model parameters to be optimized based on the strategy for optimizing the model parameters.

[0019] In some embodiments, after the simulation value of the predetermined model parameter meets the predetermined standard, the method further includes: determining to perform secondary optimization on the key target parameters based on the optimization flag indication to generate a further optimized model.

[0020] In a third aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the program is executed by a processor, the method according to the first aspect of the present disclosure is implemented.

[0021] It will be understood from the following description that the technical solution of the present disclosure can efficiently generate circuit simulation models of semiconductor process devices of various sizes.

[0022] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the disclosure, nor is it intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Shown is a schematic diagram of the DTCO process;

[0024] Figure 2 A schematic diagram illustrating an example environment in which embodiments of the present disclosure can be implemented;

[0025] Figure 3 A flow chart illustrating a method for generating a circuit simulation model according to some embodiments of the present disclosure is shown;

[0026] Figure 4 shows a schematic diagram of a fitting curve according to some embodiments of the present disclosure;

[0027] Figure 5 shows a schematic diagram of a fitting curve according to some embodiments of the present disclosure;

[0028] Figure 6 shows a schematic diagram of a fitting curve according to some embodiments of the present disclosure;

[0029] Figure 7 shows a schematic diagram of a fitting curve according to some embodiments of the present disclosure;

[0030] Figure 8 A schematic diagram illustrating the difference between a simulated value and a target value of a target parameter according to some embodiments of the present disclosure;

[0031] Figure 9 A schematic structural diagram of a fin field effect transistor according to some embodiments of the present disclosure is shown;

[0032] Figure 10 shows a schematic diagram of a grid matrix according to some embodiments of the present disclosure;

[0033] Figure 11 A schematic diagram showing a grid point according to some embodiments of the present disclosure is shown;

[0034] Figure 12 A schematic diagram showing a data structure of a target file according to some embodiments of the present disclosure;

[0035] Figure 13 A block diagram is shown of a computing device capable of implementing various embodiments of the present disclosure.

[0036] In the various drawings, the same or corresponding reference numerals denote the same or corresponding parts. DETAILED DESCRIPTION

[0037] The principles of the present disclosure will be described below with reference to the various exemplary embodiments shown in the accompanying drawings. It should be understood that the description of these embodiments is only to enable those skilled in the art to better understand and further implement the present disclosure, and is not intended to limit the scope of the present disclosure in any way. It should be noted that similar or identical reference numerals can be used in the figures where possible, and similar or identical reference numerals can represent similar or identical functions. Those skilled in the art will readily recognize, from the description below, that alternative embodiments of the structures and methods described herein can be adopted without departing from the principles of the present invention described herein.

[0038] As used herein, the term "including" and its variations represent open inclusion, i.e., "including but not limited to." Unless otherwise stated, the term "or" means "and / or." The term "based on" means "based at least in part on." The terms "one example embodiment" and "an embodiment" mean "at least one example embodiment." The term "another embodiment" means "at least one additional embodiment." The terms "first," "second," etc. may refer to different or identical objects.

[0039] SPICE is a language simulator software used for circuit description and simulation. It is used to test the integrity of circuit connections and functionality, as well as to predict circuit behavior. To perform SPICE simulation, a device-level SPICE model must first be established, such as a SPICE model for a MOS device. This allows the simulation program to use a specific mathematical model to describe the corresponding component. The SPICE model of a component is closely related to the semiconductor manufacturing process, and the corresponding device characteristics can be simulated using the SPICE model of the component.

[0040] SPICE models typically consist of two parts: model equations and model parameters. Modeling typically requires SPICE engineers to manually change the values ​​of the model parameters in the model equations and then compare test data with simulation data until they find the model parameter values ​​that most closely match the test and simulation data. This approach requires repeated changes to model parameter values, and each change requires comparing test data with simulation data. This is time-consuming and labor-intensive, requiring significant manpower for modeling and preventing rapid response to adjustments to device process parameters.

[0041] Taking a MOS transistor as an example, the initial SPICE model of the MOS transistor includes model equations for characterizing the DC characteristics of the MOS device, model equations for characterizing the AC characteristics of the MOS transistor, and model equations for characterizing other characteristics of the MOS transistor (such as temperature characteristics, noise characteristics, and layout characteristics). Each model equation may include at least one equation, and each equation may include at least one model parameter. The model parameters in the initial SPICE model can be used to characterize the electrical characteristics of the target device, such as model parameters for characterizing the MOS transistor's saturation current Idsat, linear current Idlin, off-state current Idoff, linear threshold voltage Vtlin, and saturation threshold voltage Vtsat. Correspondingly, the model parameters in the initial SPICE model can also be used to characterize the physical characteristics of the target device, such as model parameters for characterizing the MOS transistor's channel length, channel width, and gate oxide thickness, etc.

[0042] Typically, the process design kit (PDK) provided by a designer is a process simulation package provided by the wafer foundry to a design company. Designers use the process device package within the PDK to perform simulations and circuit design. SPICE models are a key component of the DK. Design companies use simulation software (HSPICE) to call model cards and add stimulus conditions to simulate and design devices under various scenarios. Models are generally abstract mathematical formulas, and model cards record the coefficients of these abstract formulas in a text file, for example, to form a model card.

[0043] Currently, SPICE models used in the manufacturing industry are all based on the Berkeley BSIM model. Planar models primarily use BSIM3 and BSIM4, while the model for FinFETs is the Berkeley Short-channel IGFET Model – CommonMulti-Gate (BSIMCMG). The BSIM model uses a series of mathematical and physical formulas to accurately and analytically describe the device's electrical characteristics at various voltages and temperatures. Due to the numerous parameters and complex formulas involved in these models, the current industry practice is for EDA companies to incorporate these complex mathematical models into simulation software. Wafer foundries only require a card containing the model coefficients, known as a model card, which users can then use with SPICE simulation software to perform circuit simulations. Model cards can be categorized into: single-size point models, multi-size global models, and bin models. As the process window of advanced processes narrows, designers are demanding very high accuracy in FinFET SPICE models. Typically, these models must meet target accuracy requirements, such as vt <1mV and id <1% (the gate voltage corresponding to a fixed current on the IV (current-voltage) curve, and the gate and drain currents corresponding to fixed current values). Traditional global models are no longer able to meet these accuracy requirements.

[0044] For point models, one model card corresponds to a device of fixed size. For global models, one model card can cover devices of varying sizes. BIN models integrate many point model cards into a single model card. Electrical characteristics are typically integrated into the simulator, and the parameter coefficients that require adjustment are stored in a text file on the model card. The adjusted model card is then generated through parameter adjustment and TCAD curve fitting.

[0045] The FINFET industry currently uses BIN model cards. BIN models are a type of SPICE model. Model cards contain information such as model parameters and simulated device IV / CV characteristics. Currently, wafer foundries typically extract SPICE models based on existing silicon data or TCAD simulation data. Alternatively, they retarget (modify key performance parameters) VT and ID based on the previous generation technology node to create a model for the new node. However, for early-stage wafer foundries, they often use TCAD to create a virtual FAB to obtain preliminary simulation data. Whether retargeting an existing model or extracting a completely new model, parameters must be continuously adjusted to ensure that the simulation results match the target. Extracting SPICE models requires engineers with relevant experience and familiarity with the response direction of each parameter. Even experienced SPICE mode engineers can spend considerable time iterating to achieve satisfactory results, which is a significant factor in the DTCO development cycle.

[0046] From the perspective of advanced process R&D, the entire process from TCAD to SPICE has become a critical component of DTCO for every wafer foundry. Domestic model extraction software, such as BSIMPro Plus, still relies heavily on manual parameter adjustment and lacks a data interface with TCAD. Manual parameter adjustment involves manually adjusting parameters based on a curve or target values ​​for vt_lin, vt_sat, idlin, and idsat. Each time a parameter is manually adjusted, a new set of data is simulated. By comparing the simulation results with the curve and vt_lin, vt_sat, idlin, and idsat, the direction of parameter adjustment is manually determined, gradually achieving optimal results. Parameters to be optimized are selected from a model card. For example, if a model card has 100 parameters, 10 can be selected for manual adjustment.

[0047] The targets or sweep curves for different technology nodes may vary significantly (a sweep curve refers to a series of continuous curves, such as voltage, current, or capacitance-voltage curves). Often, a single strategy cannot address all process scenarios. Therefore, it is usually necessary to modify the optimization strategy for a specific process or project to achieve better optimization results.

[0048] In view of this, the present disclosure provides an improved solution.

[0049] An embodiment of the present disclosure provides an improved method for generating a circuit simulation model. The method includes: performing simulation optimization on predetermined model parameters of respective initial models of semiconductor process devices to determine simulation values ​​of target parameters related to the predetermined model parameters, wherein the plurality of semiconductor process devices have different sizes; in response to the simulation values ​​of the target parameters satisfying predetermined criteria, determining the models corresponding to the simulation values ​​satisfying the predetermined criteria as corresponding optimization models; arranging grid points representing the respective optimization models into a matrix based on the sizes of the respective semiconductor process devices; and determining a circuit simulation model for simulating semiconductor process devices of respective sizes based on the relationship between the model parameters of the optimization models represented by the respective grid points in the matrix and the sizes of the corresponding semiconductor process devices.

[0050] Some embodiments of the present disclosure obtain simulation models of devices of different sizes (eg, representative sizes) and quickly construct a model covering devices of all sizes based on the association between models of various sizes.

[0051] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0052] Figure 1 The basic process of DTCO is well known in the industry and is briefly described below.

[0053] At block 102, a new technical standard is provided.

[0054] At block 104 , a TCAD simulation is performed, which includes simulation of transistors and interconnects or connection relationships, and can output, for example, a curve of device characteristics.

[0055] At block 106 , a PDK is shown, which includes DR (design rules), standard cells, and models. The models include compact models and RC (resistance and capacitance).

[0056] At block 108 , a SPICE simulation of the circuit is shown.

[0057] At block 110 , the output from the circuit simulation of block 108 is fed back to block 102 for co-optimization.

[0058] Figure 2 1 shows a schematic diagram of an example environment 200 in which embodiments according to the present disclosure can be implemented. Figure 2 As shown, the example environment 200 includes a computing device 210 and a client 220 .

[0059] In some embodiments, computing device 210 can interact with client 220. For example, computing device 210 can receive input messages from client 220 and output feedback messages to client 220. In some embodiments, the input messages from client 220 can be data of semiconductor process devices. Computing device 210 can perform corresponding mathematical operations on the data of the semiconductor process devices and output the corresponding operation results to client 220.

[0060] In some embodiments, computing device 210 may include, but is not limited to, a personal computer, a server computer, a handheld or laptop device, a mobile device (such as a mobile phone, a personal digital assistant (PDA), a media player, etc.), consumer electronics, a minicomputer, a mainframe computer, cloud computing resources, etc.

[0061] It should be understood that the structure and functionality of the example environment 200 are described for illustrative purposes only and are not intended to limit the scope of the subject matter described herein. The subject matter described herein can be implemented in different structures and / or functions. This environment is merely illustrative and is not intended to limit the application environment of the embodiments of the present disclosure.

[0062] In order to explain the principle of the present disclosure more clearly, the following will refer to Figure 4 Let's describe it in more detail.

[0063] Figure 3 A flow chart of a method 300 for generating a simulation model (eg, a SPICE model) according to some embodiments of the present disclosure is shown.

[0064] At block 302 , simulation optimization is performed on predetermined model parameters of respective initial models of a plurality of semiconductor process devices to determine simulation values ​​of target parameters related to the predetermined model parameters, wherein the plurality of semiconductor process devices have different sizes.

[0065] In some embodiments, models of semiconductor process devices of different sizes may be obtained, and models of devices of these different sizes (for example, devices of representative sizes may be selected as needed) may be used to construct a model covering devices of various sizes.

[0066] In some embodiments, before simulation, a strategy for optimizing model parameters is configured in a target file. A strategy for secondary optimization of key target parameters may also be configured. Model parameters to be optimized may be selected based on the strategy for optimizing model parameters. The target file is described in detail below.

[0067] In some embodiments of the present disclosure, a data structure based on the JSON data format is designed. This data structure can be used in target files. This data structure simplifies the process of reading data interfaces. This data structure offers advantages such as easy definition, a simple format, and ease of subsequent code maintenance and upgrades.

[0068] Sweep curves are named according to the sweep_curve_x.json file, where "x" is an integer greater than or equal to 0. They are read and parsed through the TCAD TO SPICE Pro (ttspro) load interface, forming a tree structure on the GUI. By clicking the curve name in the tree, you can access the information of each curve and display it in the drawing area of ​​the Graphical User Interface (GUI).

[0069] The data structure of the object file consists of the following parts (called part 1):

[0070]

[0071] The target file's data structure first defines parameters, which represent the policy information that needs to be filled in. These parameters include columns, regions, parameters, value (initial value), scale (data scaling factor), factor (parameter sensitivity coefficient), and format.

[0072] Columns includes region1 to region5. Regions includes the column of arrays after region1 to region5, for example, [0, 0.25].

[0073] It should be understood that the various parameters included in the data structure shown in the embodiment of the present disclosure are illustrative and are not intended to limit the scope of the present disclosure. Various changes can be made to the various parameters therein according to actual needs, such as addition, deletion, modification, etc.

[0074] In some embodiments, the target file can be used to configure optimization strategies. Specifically, the target file can be used to configure simulation conditions and optimization strategies. The target file can also define settings for manual parameter adjustment and plotting. The target file can be imported into the simulation model using the load target interface on the GUI.

[0075] The second parameter in the data structure (part 1) above represents the model parameters that need to be optimized, such as phig, cdsc, Uθ, ua, etc. Regions represents the x-axis range of the IV (current-voltage) curve and the CV (capacitance-voltage) curve.

[0076] For Step 1 shown in the data structure, the first step is to optimize the drain current curve of id_vg1.

[0077] The meaning of each parameter is as follows:

[0078] Phig: Gate work function, which has a linear relationship with vt_lin. As phig increases, vt_lin increases, and as phig decreases, vt_lin decreases.

[0079] Cdsc: coupling capacitance between S / D and channel (coupling capacitance between S / D and channel);

[0080] Uθ: low field mobility;

[0081] Ua: phonon / surface roughness scattering parameter (phonon / surface roughness scattering parameter);

[0082] Eu: phonon / surface roughness scattering parameter;

[0083] Etamob: effective field parameter;

[0084] In some embodiments, the target file also configures a strategy for performing secondary optimization on key target parameters. Based on this strategy, the model parameters can be secondary optimized to obtain a further optimized model. See the following data structure (referred to as Part 2):

[0085]

[0086] The data structure shown here shows the settings for secondary optimization of key indicators (key target parameters).

[0087] att_flag: indicates whether to enable attribute (performance) optimization;

[0088] att_mod: mode;

[0089] att_param: parameter;

[0090] attribute: optimized parameter;

[0091] att_scale: data scaling factor;

[0092] att_target: target;

[0093] vt_lin: linear threshold voltage;

[0094] vt_sat: saturation threshold voltage

[0095] Idlin: linear current;

[0096] idsat: saturation current;

[0097] para_bounds: bounds of the optimization parameters.

[0098] For example, you can select specific parameters to modify (optimize) specific vt_lin, vt_sast, idlin, idsat. For example:

[0099] ; That is, use Phig to correct vt_lin;

[0100] ; That is, use U0 to correct idlin;

[0101] ; That is, use Dvtp0 to correct vt_sat.

[0102] In addition, it should be understood that if the electrical parameters shown in this disclosure are not introduced in detail or their Chinese names are not given, they can be understood according to the common understanding in the electrical field.

[0103] In some embodiments, the information to be optimized can be imported as text into a newly created project in the software. Clicking the corresponding "Run" button automatically calibrates the parameters and saves the calibration results to a folder. Automatic calibration automatically optimizes the parameters to be optimized. For example, if the target value of vt_sat is 100mV, the vt_sat of the model before optimization is 50mV, and after optimization, it is 99mV.

[0104] The information that needs to be optimized refers to which curve (id_vg1, id_vg2, id_vd, etc.) and which attribute target (vt_lin, vt_sat, idlin, idsat, etc.) needs to be optimized. For the data structure (part 1), the information that needs to be optimized is the content after the step character, which can be defined by the operator.

[0105] To optimize a device with a sweep curve, you can first optimize the curve according to the settings in the target file. For example, you can optimize the current and voltage of each curve, and automatically optimize according to the bias conditions set in the target file.

[0106] In some embodiments, after the simulated values ​​of predetermined model parameters meet predetermined criteria, a determination can be made based on an optimization flag to determine whether to perform secondary optimization on key target parameters to generate a further optimized model. For example, after a curve fit meets the expected criteria, a user-set optimization flag can be used to determine whether to perform secondary optimization on key targets (key target parameters) such as vt_lin, vt_sat, idlin, idsat, and swing_lin.

[0107] In some embodiments, the curve is a TCAD simulation curve or a wafer acceptance test (WAT) curve. If the scan curve is used as the optimization target value, the point on the curve represents the target.

[0108] In some embodiments, whether the curve fits the expected standard can be determined by calculating the RMS. Specifically, whether the expected standard is met can be determined based on the size of the RMS.

[0109]

[0110] where y mi is the value of the i-th point of the model, y ti is the simulation value of the i-th point of the target, n and N are positive integers, and they are equal in this formula, both representing the number of points.

[0111] A model card is typically a text file ending in "xx_yy.mod," where "xx" is an arbitrary string and "yy" is an integer greater than or equal to 0. The model to be optimized is imported into the project through the GUI's load mode (load mod) interface. The GUI analyzes the model parameters, displaying them in the parameter adjustment area. Parameters can also be adjusted manually.

[0112] In some embodiments, a Trust Region Reflective Curve Fitting (TRF) algorithm can be employed. In some embodiments, since the optimized parameters have bounds (which can be set in the target file), if the parameters are outside a reasonable range, the optimization results may differ significantly from the target, making subsequent optimization impossible and leading to optimization failure. This algorithm can effectively address the parameter boundary issue. For example, once a range is set, parameters can only be adjusted within the set range during optimization and cannot exceed it.

[0113] In addition to the trust region reflection curve fitting algorithm mentioned above, in some embodiments of the present disclosure, the Levenberg-Marquardt (LM) algorithm can also be used. The LM algorithm is a type of optimization algorithm. Optimization is to find the parameter vector that minimizes the function value. Specifically, the algorithm is an estimation method for least squares estimation of regression parameters in nonlinear regression. This method is a method that combines the steepest descent method and the linearization method (Taylor series). Because the steepest descent method is applicable to the situation where the parameter estimate is far from the optimal value at the beginning of the iteration, and the linearization method, that is, the Gauss-Newton method, is applicable to the later stage of the iteration, when the parameter estimate is close to the optimal value. Combining the two methods can find the optimal value more quickly.

[0114] In some embodiments, a sweep curve or an attribute value set in a target file may be used as an optimization target value, and parameters to be optimized may be selected as input values.

[0115] In some embodiments, a curve representing the electrical characteristics of a semiconductor process device obtained from semiconductor process device simulation TCAD or wafer acceptance test WAT measurement can be used as an optimization target; predetermined model parameters related to the target parameters corresponding to the points on the curve are simulated and optimized so that the difference between the simulation value corresponding to the target parameter and the target value represented by the point on the curve becomes smaller during the iterative simulation process.

[0116] In some embodiments, a given value of a predetermined electrical parameter of a semiconductor process device can be used as an optimization target; and predetermined model parameters related to the predetermined electrical parameter can be simulated and optimized so that the difference between the simulated value and the given value of the predetermined electrical parameter becomes smaller during the iterative simulation process.

[0117] The implementation of the optimization algorithm is described in detail below.

[0118] In some embodiments, simulation optimization of predetermined model parameters of respective initial models of a plurality of semiconductor process devices may include: constructing a Jacobian matrix of each predetermined model parameter, wherein each predetermined model parameter serves as an input variable of a cost function in the Jacobian matrix, and the cost function is a function representing the difference between a simulation value of a target parameter and a target value represented by a point on a curve, or a function representing the difference between a simulation value of a predetermined electrical parameter and a given value; and iteratively optimizing the predetermined model parameters based on changes in the value of the loss function to obtain optimized model parameters.

[0119] In some embodiments, a simulation is performed using a simulator to construct a Jacobian matrix J(x). The target value and the simulation result are subtracted, and the sum of the squares of the differences is used as the right-hand term f(x) of equation (1). The final optimization result is obtained by setting the number of iterations.

[0120]

[0121] Where x is the parameter in the model to be optimized as the input value mentioned above (also called model parameter), for example, Phig; Indicates the amount of parameter change required for optimization each time, that is, the difference between the two fitting x values. If the input parameter is Phig, then represents the change of Phig each time during the optimization process; f(x) is the defined loss function, which is used to indicate the difference between the target value and the simulation value. Specifically, it is to calculate the square sum of the difference between the target value and the simulation value of each point.

[0122] where the Jacobian matrix can take the following form:

[0123]

[0124]

[0125] Where x1 to x n They represent the first parameter to be optimized to the nth parameter to be optimized; f m Represents the mth point on a curve; y1 to y m The specific calculation method of the Jacobian matrix itself is well known and will not be described here.

[0126] At block 304 , in response to the simulated values ​​of the target parameters satisfying predetermined criteria, models corresponding to the simulated values ​​satisfying the predetermined criteria are respectively determined as corresponding optimization models.

[0127] In some embodiments, it can be determined that the simulation value of the target parameter meets the predetermined criteria based on any one of the following: the value of the loss function during the simulation process is less than a predetermined threshold; the ratio of the simulation values ​​of the two previous iterations during the simulation process is less than a predetermined threshold; the number of iterations or the iteration time during the simulation process reaches a predetermined threshold.

[0128] The final optimization results obtained through simulation optimization can be used for SPICE simulation. After optimization, optimized models of devices of various sizes can be generated. By further processing these models, SPICE models for circuit-level simulation can be realized.

[0129] During the optimization process, the completion of optimization of model parameters (e.g., Phig) is determined by comparing the target value of the target parameter (e.g., vt_lin) with the simulated value. For example, if the difference between the two is less than a predetermined threshold, the curve fit is considered to meet the expected requirements. Therefore, the optimization of the parameter to be optimized, Phig, is measured by whether the simulated value of another quantity related to Phig, vt_lin, meets the expected requirements. As mentioned earlier, Phig and vt_lin have a linear relationship: as phig increases, vt_lin increases, and as phig decreases, vt_lin decreases. Therefore, by comparing the target value of the target parameter (vt_lin) with the simulated value, model parameters (e.g., Phig) can be optimized.

[0130] Refer to the following Figure 4 Provide a description. Figure 4 Schematic diagram showing a fitting curve according to some embodiments of the present disclosure. Figure 4 The figure shows a curve for fitting Vt_lin as the target parameter. vt_lin is usually the x-coordinate value corresponding to a point on the curve, which is used to measure whether the fitting at this point is accurate. Figure 4 As shown, find the point with a value of 1e-7*w / L from the curve, and then find the corresponding x-coordinate value, which can indirectly measure whether the curve fitting is accurate.

[0131] Figure 5 Schematic diagram of a fitting curve according to some embodiments of the present disclosure is shown. Specifically, Figure 5 Figure 2 shows a schematic diagram of the ID-VG fitting curve. The horizontal axis is vgs, and the vertical axis is id. The id_vg fitting result at vd of 0.05V was obtained through optimization. Here, vd represents the drain voltage, and id represents the drain current.

[0132] Figure 6 Schematic diagram showing a fitting curve according to some embodiments of the present disclosure. Specifically, Figure 6Figure 2 shows a schematic diagram of the ID-VG fitting curve. The horizontal axis is vgs, and the vertical axis is log(id). The fitting results of id_vg at vd of 0.05V were obtained through optimization.

[0133] Figure 7 Schematic diagram showing a fitting curve according to some embodiments of the present disclosure. Figure 7 Figure 2 shows a schematic diagram of the ID-VG fitting curve. The horizontal axis is vgs, and the vertical axis is the derivative of ID and Vgs. The ID-VG fitting result at vd of 0.05V was obtained through optimization.

[0134] pass Figures 5 to 7 The three forms in the table can be used to view fitting results in multiple dimensions. When the data is small, it is necessary to take the logarithm. Checking the fit of the derivative curves provides further insight into the fitting results. W and L represent the width and length of the MOS transistor, respectively, and T represents the temperature. The exponents -09 and -08 are shown in the upper right corner of e, representing the scientific representation of the numbers.

[0135] Figure 8 Schematic diagram showing the difference between the simulated value and the target value of the target parameter according to some embodiments of the present disclosure. Figure 8 The error between the simulation results and the target is shown in Figure 2. The target here refers to key parameters such as vt_lin, vt_sat, idling, idat, etc. The error can be used to determine the fitting accuracy and, therefore, whether the model has been optimized to meet expectations.

[0136] Figure 9 FIG2 shows a schematic structural diagram of a fin field-effect transistor 900 according to some embodiments of the present disclosure. The fin field-effect transistor (FinFET) 900 is a complementary metal oxide semiconductor transistor, which includes a substrate 902, a gate 906, and silicon dioxide (which is a shallow trench isolation region) 904. Figure 9 As can be seen in FIG, the FinFET 900 has three fins. This disclosure is not limited to this, and the embodiments of this disclosure are applicable to FinFETs having any number of fins. In some embodiments of this disclosure, the method for determining a circuit simulation model will be described using a FinFET as an example.

[0137] Back to Figure 3 At block 306 , the grid points representing the respective optimization models are arranged into a matrix based on the size of the respective semiconductor process devices.

[0138] In some embodiments, rows of grid points may be arranged along a first direction based on a first dimensional parameter of each semiconductor process device, and columns of grid points may be arranged along a second direction based on a second dimensional parameter of each semiconductor process device. The first dimensional parameter may be the length of the device, the second dimensional parameter may be the width of the device, or, for example, for a fin FET, nfin, i.e., the number of fins.

[0139] SPICE models usually need to cover different sizes. It is usually unrealistic to establish multiple sets of corresponding model cards through curves or target information of many sizes. Therefore, many parameters in the BSIM model are related to length (length), number of fins (nfin), and length*nfin. For two-dimensional devices, the length and width are generally continuous, and the electrical characteristics are monotonic or smooth in the length and width directions, so the global model can achieve a better fitting effect. For three-dimensional devices, such as FINFET, the length and NFIN are discrete and the electrical characteristics vary greatly. In addition, the accuracy requirements of the SPICE model are high, so the global model cannot meet the fitting results of all FINFET size information. Therefore, the BIN model is particularly important.

[0140] In some embodiments of the present disclosure, the BIN model is to first fit the M*N grid size one by one, and then fit the obtained model card according to Figure 10 In other words, each model card is arranged as a grid point. This forms a binning-like structure, where M*N corresponds to L and NFIN respectively.

[0141] In some embodiments of the present disclosure, model cards for each size can be automatically extracted and then automatically merged into a bin model. For each small unit BIN in the bin model, the corresponding model parameters, such as vsat, are solved using equations (2)-(5) below to determine the coefficients. This establishes the relationship between the parameters within each bin and the size within the bin. A single model card can accurately represent the information of models of all sizes. This is described in detail below.

[0142] Typically, SPICE models are extracted for multiple devices together. For example, a complete SPICE model for a 6T static random-access memory (SRAM) structure requires extracting six devices to form a model card. Due to the inherent symmetry of SRAM, only three devices (PD, PG, and PU) need to be extracted. For logic devices, the target number of devices is usually large, and interpolation simulation is often performed, that is, dimensions not present in the target are interpolated. Therefore, it is often impractical to obtain model cards for all matrices using point models. Furthermore, due to the discrete nature of FINFET length and NIFN, traditional global models cannot meet accuracy requirements. However, precisely because of the discrete nature of FINFET dimensions, it is possible to first obtain models of some representative dimensions, and then use BIN models to solve the problem of internal FINFET interpolation (for example, length and NIFN).

[0143] In some embodiments, the number of point models that need to be established in the BIN model needs to be a matrix distribution of M*N, where M and N are both integers greater than or equal to 2. M can be the number of Fins or the number of Lengths. In some embodiments, the defined BIN Map (which can be called a grid map) can be based on Figure 10 Defined in the manner shown.

[0144] See also Figure 10 , Figure 10 A schematic diagram of a grid matrix according to some embodiments of the present disclosure is shown. Figure 10 In the grid matrix shown, there are 9 bins, which can be called grids in this article, and the grids are numbered from 1 to 9. In addition, there are 16 grid points in the matrix. Each grid point corresponds to a model of a device of a certain size. In other words, the devices corresponding to the 16 grid points have different sizes. The horizontal axis LG represents the length of the device, and the lengths of the devices corresponding to the grid points are 0.009um, 0.016um, 0.032um, and 0.072um respectively. The vertical axis NFIN represents the number of fins. Figure 10 As shown, 2, 3, 4, 6 are shown, that is, the number of fins is 2, 3, 4, 6 respectively. Figure 2 The matrix is ​​arranged and numbered 1, 2, 3, 4, 5, 6, 7, 8, 9. In this way, each grid point corresponds to a model, or corresponds to a model card of a model, where the model card records the model parameters and other information of the model.

[0145] The following uses the position of the first bin (i.e., bin numbered 1) as an example: the coordinates of the four vertices of this bin are (0.009, 2), (0.009, 3), (0.016, 2), and (0.016, 3). Subsequent bins follow this order from right to left. It should be understood that the arrangement of the grid points shown here is illustrative and is not intended to be limiting. The arrangement can be modified as needed.

[0146] Figure 11 A schematic diagram of a grid point according to some embodiments of the present disclosure is shown. The P parameter for bin 1 in the smallest unit of the BIN, i.e., points P1, P2, P3, and P4, is shown, which are the values ​​of a parameter in the model corresponding to each grid point. For a given model, its parameters are known.

[0147] Back to Figure 3 At block 308 , based on the relationship between the model parameters of the optimization model represented by each grid point in the matrix and the size of the corresponding semiconductor process device, a circuit simulation model for simulating semiconductor process devices of various sizes is determined.

[0148] In some embodiments, determining a circuit simulation model for simulating semiconductor process devices of various sizes based on the relationship between the model parameters of the optimized models represented by each grid point in the matrix and the size of the corresponding semiconductor process device may include: determining, based on the grid points of each square in the matrix, any model corresponding to a point at any position within the range corresponding to the matrix; and determining the circuit simulation model as a combination of each of the arbitrary models and the optimized models corresponding to each grid point. In other words, by determining the model corresponding to a point at any position between each grid point and combining it with the known models of each grid point, a circuit simulation model for devices of various sizes can be obtained.

[0149] In some embodiments, determining any model corresponding to a point at any position within the range corresponding to the matrix based on the grid points of each square in the matrix may include: performing interpolation processing between the grid points in the matrix; and determining the model corresponding to any position within the range corresponding to the matrix except for the grid points through interpolation processing.

[0150] In some embodiments, performing interpolation between grid points in a matrix to determine the model corresponding to any position within the range corresponding to the matrix other than the grid points may include: constructing a set of equations based on a predetermined number of adjacent grid points within a predetermined range in the matrix, wherein each equation in the set of equations represents a relationship between a parameter related to a dimensional feature of each semiconductor process device and a model parameter of the model represented by each grid point; solving characteristic parameters representing the common characteristics of the optimized models represented by each grid point in the matrix based on the set of equations; and determining the model corresponding to any point in the matrix based on the characteristic parameters, parameters related to the dimensional features corresponding to adjacent grid points, and the coordinates of a point at any position within the predetermined range. For example, the model parameters of the model corresponding to any position in a square grid may be solved based on the dimensional parameters of the model corresponding to the position and the parameter information of the models corresponding to the grid points in the square grid.

[0151] In some embodiments, parameters related to the characteristics of each semiconductor process device may include at least the following: a base parameter (a common parameter for each equation in the system of equations); a first dimension parameter; and a second dimension parameter. For example, if the semiconductor process device is a MOS transistor, the first dimension parameter is its length L, and the second dimension parameter is its width W. It should be understood that the present disclosure is not limited to this; depending on the device type, the characteristic-related parameters may also be other parameters.

[0152] In some embodiments, the semiconductor device is a fin field-effect transistor. In this case, the first dimension parameter is the length of the fin field-effect transistor, the second dimension parameter is the number of fins of the fin field-effect transistor, and the parameters related to the characteristics of the semiconductor device further include a third parameter, which is the product of the length and the number of fins.

[0153] In some embodiments, determining any model corresponding to a point at any position within the range corresponding to the matrix based on the grid points of each grid in the matrix may include: selecting a grid corresponding to the size of the semiconductor process device from the matrix based on the first size parameter, the second size parameter, and the third size parameter of the semiconductor process device corresponding to the any position; constructing a set of equations based on the model parameters and size parameters of the optimized model corresponding to the grid points of the selected grid; and solving the set of equations to determine the model parameters of the model corresponding to any point, thereby determining any model corresponding to the any position. In short, the model parameters of the model to be determined are determined by selecting a grid containing a model with similar size characteristics to the model to be determined.

[0154] Please refer to the attached Figure 10 This is further described. Figure 10 The grid matrix shown in , the parameters on the four grid points of each BIN satisfy the following relationship:

[0155]

[0156]

[0157]

[0158]

[0159] Base has no physical meaning, only mathematical. A Bin has four grid points, and four unknown parameters are required to determine a unique solution. X, Y, and Z represent the three dimensions, namely the parameters in the X / L direction, the Y / NFIN direction, and the Z / (L*NFIN) direction. L1 represents the length in the LG direction. Par1 is the value corresponding to a parameter in the model card corresponding to grid point 1. For example, if phig = 0.5, then par1 = 0.5; par2, par3, and par4 are the values ​​corresponding to the phig parameter in the model cards for the other three grid points. All binnable parameters in the model card (phig, u0, vsat, etc.) must satisfy the above relationship.

[0160] As is known in the industry, MOS has only two dimensions: length and width. Specifically, consider two MOS devices with Lg*NFIN values ​​of 5*5 and 6*8, respectively. Therefore, substituting these into the above formula, the dimensions of L1 and L2 are 5 and 6, respectively. Solving the equations for the four MOS parameters (par1, par2, par3, par4) and dimensions (L1*NFIN1, L2*NFIN2, L3*NFIN3, L4*NFIN4) yields Base, X, Y, and Z. X and Y correspond to the coordinates of a point within a bin (Z is not shown in the bin diagram). Substituting these equations, or any other equation in the system, for any point (X, Y) within a bin yields the corresponding parameter Par, which represents the model parameters in the model card. This means that for any device size, the corresponding parameters in the model card can be obtained. In other words, this method allows the model of a device of a corresponding size to be derived for any point at any location. In the embodiment of the present disclosure, by adjusting the coefficients of the weight functions of these parameters (such as Base, X, Y, Z), the extracted SPICE model can be completed with one model card at various sizes.

[0161] Regarding the calculation of Base, X, Y, and Z, take the first BIN as an example: Substitute the parameters and size information (length, nfin) of the model card corresponding to the four grid points of the BIN into (2)-(5), and you can get a set of four linear equations. Solving them can get a BIN model card, and the parameter values ​​of the four grid points at the vertex are consistent with the parameter values ​​corresponding to the points of the synthetic BIN.

[0162] By moving the bin numbers sequentially according to the previously defined rules, a system of four linear equations can be constructed. This way, the parameter relationships of all the divided bins can be expressed using equations of the form (2)-(5). Finally, all the bin models (the coefficients in the model) are combined into a single model card. By defining a selection function, the corresponding bin can be selected at any size.

[0163] In some embodiments, the following selection function may be constructed according to the characteristics of the BIN structure:

[0164]

[0165]

[0166]

[0167]

[0168]

[0169] The BIN number can be accurately matched to the model size through equations (6)-(10).

[0170] Formula (6) is a constructed selection function used to select a value in different size ranges. For example, when NFIN=2, is the device length less than l1? If it is less than l1, ( Figure 10 As can be seen, if the value falls outside the matrix, the selected value is 1; if it is greater than l1 and less than l2, the selected value in the LG direction is 1; if it is greater than l2 and less than l3, the selected value in the LG direction is 2; if it is greater than l3 and less than l4, the selected value in the LG direction is 3. The last 3 in formula (6) means that when the value is greater than l4, the value is 3. Similarly, the selected value in the NFIN direction also meets the above rules.

[0171] Formula (7) constructs a selection function for selecting a bin number under different bin numbers. It is used to determine the bin to be selected in the Y direction (NFIN) based on the number of fins in the device. For example, for a device with three fins, the third bin is selected in the Y direction. The final 10000 in Formula (7) indicates that the default value is used if the value exceeds the limit.

[0172] Formula (8) is used to select bin_x of different sizes in the LG direction.

[0173] Formula (9) is used to select bin_y in the NFIN direction.

[0174] Formula (10) is a combination of (8) and (9) to obtain the corresponding Bins under different sizes. Specifically, Formula (10) is a function constructed based on the corresponding relationship between the selection function select4 and Bin, where the coefficient 3 can change according to the actual number of sizes, for example Figure 10 In the illustrated embodiment, the number of x-bins is 3, meaning that if the bin number is shifted by an integer +1 in the y-direction, the bin number increases by 3. Similarly, if the number of x-bins is 4, then if the bin number is shifted by an integer +1 in the y-direction, the bin number increases by 4, and so on.

[0175] By defining a selection function, it is possible to select the corresponding bin at any size, so that a set of equations can be constructed based on the grid points of the selected bin and solved to obtain the model (model parameters) corresponding to any point.

[0176] In the above embodiments, FINFETs are used as an example. It should be understood that the embodiments of the present disclosure are not limited thereto. Besides FINFETs, the methods of the embodiments of the present disclosure can also be applied to other devices, such as IGBTs, BJTs, diodes, resistors, MOS transistors, and the like. As mentioned above, the dimensional parameters of these components may only include length and width.

[0177] Some embodiments of the present disclosure provide methods for generating circuit simulation models. It should be understood that the embodiments shown above are merely illustrative of some embodiments of the present disclosure and are not intended to limit the present disclosure. The embodiments of the present disclosure may also have various other forms.

[0178] An embodiment of the present disclosure also discloses an electronic device. The electronic device includes a processor; and a memory coupled to the processor, the memory having instructions stored therein, which, when executed by the processor, cause the device to perform an action, the action including: performing simulation optimization on predetermined model parameters of respective initial models of a plurality of semiconductor process devices to determine simulation values ​​of target parameters related to the predetermined model parameters, wherein the plurality of semiconductor process devices respectively have different sizes; in response to the simulation values ​​of the target parameters satisfying predetermined criteria, determining the models corresponding to the simulation values ​​satisfying the predetermined criteria as corresponding optimization models; arranging grid points representing the respective optimization models into a matrix based on the size of the respective semiconductor process devices; and determining a circuit simulation model for simulating semiconductor process devices of respective sizes based on the relationship between the model parameters of the optimization models represented by the respective grid points in the matrix and the size of the corresponding semiconductor process device.

[0179] An embodiment of the present disclosure further discloses a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the method for generating a circuit simulation model according to an embodiment of the present disclosure is implemented.

[0180] The solutions in some embodiments of this disclosure implement automated SPICE model building, significantly reducing modeling time and achieving high accuracy. This provides powerful software and methodological support for DTCO. Furthermore, this method is applicable to extracting all SPICE models, regardless of device type (e.g., MOS type).

[0181] The BIN model creation method proposed in some embodiments of this disclosure can address the challenge of creating a full-matrix SPICE model within existing dimensions. The model card approach is concise and can serve as a standard SPICE model extraction (generation) process for wafer foundries.

[0182] In some embodiments of this disclosure, a new model extraction approach, based on the TCAD+ platform, has been designed for extracting SPICE models from TCAD, enabling automated extraction. For example, by configuring a target file and combining it with an optimization algorithm, optimization can be automatically achieved, significantly accelerating the DTCO process and reducing SPICE model extraction time by over two-thirds.

[0183] Figure 12 A schematic diagram showing the data structure of a target file according to some embodiments of the present disclosure is shown. Figure 12 The optimized data structure mentioned above is included in the figure, and the relevant parameters and specific parameter setting information are also shown. The specific content will not be described in detail here.

[0184] Figure 13 Schematic block diagrams of electronic devices according to some exemplary embodiments of the present disclosure are shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0185] like Figure 13 As shown, device 1300 includes a CPU 1301, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1302 or a computer program loaded from a storage unit 1308 into a random access memory (RAM) 1303. RAM 1303 may also store various programs and data required for the operation of device 1300. CPU 1301, ROM 1302, and RAM 1303 are connected to each other via a bus 1304. An input / output (I / O) interface 1305 is also connected to bus 1304.

[0186] Multiple components in device 1300 are connected to I / O interface 1305, including an input unit 1306, such as a keyboard and mouse; an output unit 1307, such as various types of displays and speakers; a storage unit 1308, such as a magnetic disk and optical disk; and a communication unit 1309, such as a network card, a modem, a wireless communication transceiver, etc. Communication unit 1309 allows device 1300 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0187] The various processes and processing described above, such as method 300, can be executed by CPU 1301. For example, in some embodiments, method 300 can be implemented as a computer software program that is tangibly embodied in a machine-readable medium, such as storage unit 1308. In some embodiments, part or all of the computer program can be loaded and / or installed on device 1300 via ROM 1302 and / or communication unit 1309. When the computer program is loaded into RAM 1303 and executed by CPU 1301, one or more steps in method 300 described above can be performed.

[0188] The solutions according to the embodiments of the present disclosure may be methods, devices, systems, and / or computer program products. The computer program product may include a computer-readable storage medium on which computer-readable program instructions for executing various aspects of the present disclosure are loaded. The computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable program instructions may be downloaded from the computer-readable storage medium to various computing / processing devices, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network.

[0189] Various embodiments of the present disclosure have been described above. The above descriptions are exemplary and are only optional embodiments of the present disclosure. They are not exhaustive and are not intended to limit the present disclosure. Although the claims in this application have been formulated for specific combinations of features, it should be understood that the scope of the present disclosure also includes any novel feature or any novel combination of features disclosed herein, whether explicitly or implicitly or in any generalization thereof, regardless of whether it relates to the same scheme in any claim currently claimed. The applicant hereby informs that new claims may be formulated to these features and / or combinations of these features during the examination of this application or in any further application derived therefrom.

[0190] The terminology used herein is selected to best explain the principles of the various embodiments, their practical applications, or technological improvements in the marketplace, or to enable others skilled in the art to understand the various embodiments disclosed herein. Various modifications and variations are readily apparent to those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this disclosure are intended to be included within the scope of protection of this disclosure.

Claims

1. A method for generating a circuit simulation model, comprising: Performing simulation optimization on predetermined model parameters of respective initial models of a plurality of semiconductor process devices to determine simulation values ​​of target parameters related to the predetermined model parameters, the plurality of semiconductor process devices having different sizes respectively; In response to the simulation value of the target parameter satisfying a predetermined standard, respectively determining the models corresponding to the simulation value satisfying the predetermined standard as corresponding optimization models; Arranging the grid points representing each of the optimization models into a matrix based on the size of each of the semiconductor process devices; as well as Based on the relationship between the model parameters of the optimization model represented by each grid point in the matrix and the size of the corresponding semiconductor process device, a circuit simulation model for simulating semiconductor process devices of various sizes is determined, specifically including: based on the size parameters of the model corresponding to any position in any square in the matrix and the model parameters of the optimization model corresponding to each grid point of the square, interpolation processing is performed between grid points to solve the model parameters of the model corresponding to any position to determine any model corresponding to the point at any position; and the combination of each of the any models and each of the optimization models corresponding to the each grid point is determined as the circuit simulation model.

2. The method according to claim 1, wherein simulating and optimizing predetermined model parameters of respective initial models of a plurality of semiconductor process devices comprises: Taking the curves of electrical characteristics of the plurality of semiconductor process devices as optimization targets; as well as The predetermined model parameters related to the target parameters corresponding to the points on the curve are simulated and optimized so that the difference between the simulation value corresponding to the target parameters and the target values ​​represented by the points on the curve becomes smaller during the iterative simulation process.

3. The method according to claim 1, wherein simulating and optimizing predetermined model parameters of respective initial models of a plurality of semiconductor process devices comprises: Taking a given value of a predetermined electrical parameter of the semiconductor process device as an optimization target; as well as The predetermined model parameter related to the predetermined electrical parameter is simulated and optimized so that the difference between the simulation value of the predetermined electrical parameter and the given value becomes smaller during the iterative simulation process.

4. The method according to claim 2 or 3, wherein simulating and optimizing predetermined model parameters of respective initial models of a plurality of semiconductor process devices comprises: Constructing a Jacobian matrix of each of the predetermined model parameters, wherein each of the predetermined model parameters serves as an input variable of a loss function in the Jacobian matrix, wherein the loss function is a function representing a difference between a simulated value of the target parameter and a target value represented by a point on the curve or a function representing a difference between a simulated value of the predetermined electrical parameter and the given value; as well as The predetermined model parameters are iteratively optimized in response to changes in the value of the loss function to obtain optimized model parameters.

5. The method according to claim 4, wherein determining that the simulated value of the target parameter meets a predetermined criterion is based on any one of the following: During the simulation, the value of the loss function is less than a predetermined threshold; During the simulation process, the ratio of the simulation values ​​of the two previous and subsequent iterations is less than a predetermined threshold; as well as The number of iterations or the iteration time during the simulation process reaches a predetermined threshold.

6. The method according to claim 1, wherein arranging the grid points representing each of the optimization models into a matrix based on the size of each semiconductor process device comprises: Arranging rows of the grid points along a first direction based on first size parameters of each of the semiconductor process devices; as well as The columns of the grid points are arranged along a second direction based on a second size parameter of each of the semiconductor process devices.

7. The method according to claim 6, wherein performing interpolation processing between the grid points in the matrix to determine the model corresponding to any position other than the grid points within the range corresponding to the matrix comprises: Constructing a set of equations based on a predetermined number of adjacent grid points within a predetermined range in the matrix, wherein each equation in the set of equations respectively represents a relationship between a parameter related to a size feature of each semiconductor process device and a model parameter of a model represented by each grid point; Solving the common characteristic parameters of the optimization model represented by each grid point in the matrix based on the equation group; as well as Based on the characteristic parameters, the parameters related to the size characteristics corresponding to the adjacent grid points, and the coordinates of the points at any position within the predetermined range, the model corresponding to the point at any position in the matrix is ​​determined.

8. The method according to claim 7, wherein the parameters related to the characteristics of each semiconductor process device include at least the following: Basis parameters, which are common parameters of each equation in the system of equations; the first size parameter; and The second size parameter.

9. The method according to claim 8, wherein the semiconductor process device is a fin field effect transistor, the first size parameter is the length of the fin field effect transistor, the second size parameter is the number of fins of the fin field effect transistor, and wherein, The parameters related to the characteristics of the semiconductor process device further include a third size parameter, which is the product of the length and the number of the fins.

10. The method according to claim 9, wherein determining any model corresponding to a point at any position within a range corresponding to the matrix based on the grid points of each square in the matrix comprises: Selecting a square corresponding to the size of the semiconductor process device from the matrix based on the first size parameter, the second size parameter, and the third size parameter of the semiconductor process device corresponding to any one of the positions; Constructing the set of equations based on the model parameters and size parameters of the optimization model corresponding to the grid points of the selected grid; as well as The set of equations is solved to determine the model parameters of the model corresponding to the point at any position, thereby determining any model corresponding to the point at any position.

11. The method according to claim 1, wherein before performing simulation optimization on predetermined model parameters of respective initial models of a plurality of semiconductor process devices, the method further comprises: Configuring in the target file a strategy for optimizing the model parameters and / or a strategy for secondary optimization of key target parameters; as well as The model parameters to be optimized are selected based on a strategy for optimizing the model parameters.

12. The method according to claim 11, wherein after the simulation value of the predetermined model parameter meets the predetermined standard, it further comprises: Based on the optimization flag indication, it is determined to perform the secondary optimization on the key target parameters to generate a further optimized model.

13. An electronic device, comprising: processor; as well as A memory coupled to the processor, the memory having instructions stored therein, the instructions causing the device to perform actions when executed by the processor, the actions comprising: Performing simulation optimization on predetermined model parameters of respective initial models of a plurality of semiconductor process devices to determine simulation values ​​of target parameters related to the predetermined model parameters, the plurality of semiconductor process devices having different sizes respectively; In response to the simulation value of the target parameter satisfying a predetermined standard, respectively determining the models corresponding to the simulation value satisfying the predetermined standard as corresponding optimization models; Arranging the grid points representing each of the optimization models into a matrix based on the size of each of the semiconductor process devices; and Based on the relationship between the model parameters of the optimization model represented by each grid point in the matrix and the size of the corresponding semiconductor process device, a circuit simulation model for simulating semiconductor process devices of various sizes is determined, specifically including: based on the size parameters of the model corresponding to any position in any square in the matrix and the model parameters of the optimization model corresponding to each grid point of the square, interpolation processing is performed between grid points to solve the model parameters of the model corresponding to any position to determine any model corresponding to the point at any position; and the combination of each of the any models and each of the optimization models corresponding to the each grid point is determined as the circuit simulation model.

14. A computer-readable storage medium having machine-executable instructions stored thereon, which, when executed by a processor, enables the processor to implement the method according to any one of claims 1 to 12.

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