Memory, storage device and electronic device

Abstract

The invention provides a memory, a storage device and an electronic device, relates to the technical field of semiconductors, and aims to solve the problems that the number of sensitive amplifiers is increased and the winding distance is reduced due to stacking of multiple storage layers. The memory comprises a plurality of stacked storage layers and further comprises a first gating circuit, a second gating circuit and a sensitive amplifier, the first gating circuit comprises a plurality of input ends and an output end, the input ends are connected with first bit lines of different storage layers in a one-to-one correspondence mode, and the output end is connected with the first input end of the sensitive amplifier; the second gating circuit comprises a plurality of input ends and an output end, the plurality of input ends are connected with second bit lines of different storage layers in a one-to-one correspondence manner, the output end is connected with a second input end of the sensitive amplifier circuit, and the first gating circuit is used for conducting one of the plurality of first bit lines with a first input end of the sensitive amplifier and conducting one of the plurality of second bit lines with a second input end of the sensitive amplifier. And the second gating circuit is used for conducting one of the plurality of second bit lines with the second input end of the sensitive amplifier.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a memory, a storage device and an electronic device. Background Art

[0002] In recent years, with the development of technology, storage devices can improve storage capacity and storage density by stacking multiple layers. However, after stacking multiple storage layers, the storage density increases exponentially, but the number of sense amplifiers (SA) interconnected with the storage device also increases exponentially, which will result in a larger area being occupied, resulting in tight winding resources for the sense amplifier, reduced winding spacing of the sense amplifier, and greater difficulty in the preparation process. Summary of the invention

[0003] Embodiments of the present application provide a memory, a storage device, and an electronic device for improving the problem that stacking of multiple storage layers will lead to an increase in the number of sensitive amplifiers and a decrease in the winding spacing of the sensitive amplifiers.

[0004] In a first aspect, an embodiment of the present application provides a memory, the memory comprising a substrate and a plurality of storage layers stacked on the substrate in a direction perpendicular to the substrate, each storage layer comprising a first bit line, a second bit line and a plurality of storage cells distributed in a direction parallel to the substrate, the first bit line and the second bit line are respectively connected to the plurality of storage cells, the memory further comprising a first gating circuit, a second gating circuit and a sensitive amplifier, the sensitive amplifier comprising a first input terminal and a second input terminal, wherein the first gating circuit comprises a selection terminal, an output terminal and a plurality of input terminals, the plurality of input terminals of the first gating circuit are connected one-to-one with the plurality of first bit lines, wherein the plurality of first bit lines are respectively located in different storage layers, the output terminals of the first gating circuit The output end is connected to the first input end of the sensitive amplifier, and the selection end of the first selection circuit is used to receive the first selection circuit selection control signal; the second selection circuit includes a selection end, an output end and multiple input ends, the multiple input ends of the second selection circuit are connected to the multiple second bit lines one by one, and the multiple second bit lines are respectively located in multiple storage layers. The output end of the second selection circuit is connected to the second input end of the sensitive amplifier circuit, and the selection end of the second selection circuit is used to receive the second selection circuit selection control signal; the first selection circuit is used to connect one of the multiple first bit lines to the first input end of the sensitive amplifier, and the second selection circuit is used to connect one of the multiple second bit lines to the second input end of the sensitive amplifier.

[0005] The memory provided by the embodiment of the present application improves the storage density by stacking multiple storage layers, and realizes sharing of the sensitive amplifier by different storage layers by setting the first selection circuit and the second selection circuit, wherein the first input end of the sensitive amplifier is connected to multiple first bit lines through the first selection circuit, and the multiple first bit lines are respectively located in different storage layers; the second input end of the sensitive amplifier is connected to multiple second bit lines through the second selection circuit, and the multiple second bit lines are respectively located in different storage layers, and the first selection circuit can select one from the multiple first bit lines connected to it to be connected to the first input end of the sensitive amplifier; the second selection circuit can select one from the multiple second bit lines connected to it to be connected to the second input end of the sensitive amplifier, so that the first bit lines and the second bit lines of different storage layers can be connected to the same sensitive amplifier, which can reduce the number of sensitive amplifiers required in the memory, reduce the area occupied by the sensitive amplifier, increase the winding spacing of the sensitive amplifier, and reduce the process difficulty.

[0006] In a possible implementation, the first gating circuit and the second gating circuit both include multiple switches, and the switches include a first end, a second end, and a control end; wherein each input end of the first gating circuit is connected to the output end of the first gating circuit through a switch, wherein the first end of the switch is connected to the input end of the first gating circuit, the second end of the switch is connected to the output end of the first gating circuit, and the control end of the switch is connected to the selection end of the first gating circuit; each input end of the second gating circuit is connected to the output end of the second gating circuit through a switch, wherein the control end of the switch of the second gating circuit is connected to the selection end of the second gating circuit, the first end of the switch is connected to the input end of the second gating circuit, and the second end of the switch is connected to the output end of the second gating circuit.

[0007] In the memory provided by the embodiment of the present application, each input end of the first selection circuit is connected to the output end through a switch, and the control end of the switch is connected to the selection end of the first selection circuit. The multiple switches of the first selection circuit can be selectively turned on according to the first selection circuit selection control signal of the selection end. When the first selection circuit selection control signal received by the selection end of the first selection circuit controls the switch to be turned on, the corresponding first bit line is turned on with the first input end of the sensitive amplifier; similarly, the multiple switches of the second selection circuit can be selectively turned on according to the second selection circuit selection control signal of the selection end of the second selection circuit. When the second selection circuit selection control signal received by the selection end of the second selection circuit controls the switch to be turned on, the corresponding second bit line is turned on with the second input end of the sensitive amplifier, thereby realizing that the bit lines of multiple storage layers share the sensitive amplifier.

[0008] In one possible implementation, the above-mentioned switch can be a transistor, and the transistor can be implemented using an N-type or P-type transistor in a traditional CMOS circuit, so that the first selection circuit and the second selection circuit can be implemented using a front-end process; or, the transistor here can be implemented using a thin film transistor based on an oxide semiconductor as a channel material, and a thin film transistor based on an oxide semiconductor as a channel material is compatible with a back-end process, so the first selection circuit and the second selection circuit can be implemented using a back-end process, in which case the selection transistors corresponding to each storage layer can be set on the same layer as the storage layer.

[0009] In a possible implementation, the first gating circuit includes a first input terminal, a second input terminal, a first switch, a second switch, a first selection terminal and a second selection terminal; the second gating circuit includes a first input terminal, a second input terminal, a first switch, a second switch, a first selection terminal and a second selection terminal; the first end of the first switch of the first gating circuit is connected to the first input terminal of the first gating circuit, the second end of the first switch is connected to the output terminal of the first gating circuit, and the control end of the first switch is connected to the first selection terminal of the first gating circuit; the first end of the second switch of the first gating circuit is connected to the second input terminal of the first gating circuit, the second end of the second switch is connected to the output terminal of the first gating circuit, and the control end of the second switch is connected to the second selection terminal of the first gating circuit; the first end of the first switch of the second gating circuit is connected to the first input terminal of the second gating circuit, the second end of the first switch is connected to the output terminal of the second gating circuit, and the control end of the first switch is connected to the first selection terminal of the second gating circuit; the first end of the second switch of the second gating circuit is connected to the second input terminal of the second gating circuit, the second end of the second switch is connected to the output terminal of the second gating circuit, and the control end of the second switch is connected to the second selection terminal of the second gating circuit.

[0010] In the memory provided by the embodiment of the present application, the first gating circuit includes a plurality of selection terminals, each selection terminal corresponds to an input terminal, for example, the first gating circuit selection control signal of the first selection terminal of the first gating circuit (also referred to as the first gating circuit first selection control signal) is used to control the conduction state between the first input terminal and the output terminal, and the first gating circuit selection control signal of the second selection terminal (also referred to as the first gating circuit second selection control signal) is used to control the conduction state between the second input terminal and the output terminal; similarly, for the second gating circuit, the second gating circuit selection control signal of its first selection terminal (also referred to as the second selection control signal) is used to control the conduction state between the second input terminal and the output terminal. The first selection control signal of the first selection circuit is used to control the conduction state of the first input terminal and the output terminal, and the second selection circuit selection control signal of the second selection terminal (also referred to as the second selection control signal of the second selection circuit) is used to control the conduction state of the second input terminal and the output terminal. The first selection circuit selection control signal at the selection end of the first selection circuit can realize the conduction of one of the multiple first bit lines connected to the first selection circuit to the first input terminal of the sensitive amplifier, and the second selection circuit selection control signal at the selection end of the second selection circuit can realize the conduction of one of the multiple second bit lines connected to the second selection circuit to the second input terminal of the sensitive amplifier.

[0011] In one possible implementation, the first selection end of the first selection circuit is used to receive a first selection control signal of the first selection circuit, the first selection end of the second selection circuit is used to receive a first selection control signal of the second selection circuit, and the first selection control signal of the first selection circuit and the first selection control signal of the second selection circuit are the same selection control signal; the second selection end of the first selection circuit is used to receive a second selection control signal of the first selection circuit, the second selection end of the second selection circuit is used to receive a second selection control signal of the second selection circuit, and the second selection control signal of the first selection circuit and the second selection control signal of the second selection circuit are the same selection control signal.

[0012] In the memory provided in the embodiment of the present application, the first selection circuit and the second selection circuit are used to realize that the first bit line and the second bit line of different storage layers share the same sense amplifier. Since the normal operation of the sense amplifier requires a pair of bit lines as a reference to read or write data, the selection ends of the first selection circuit and the second selection circuit can be connected to the same selection control signal. In this way, when the selection control signal can simultaneously control the selection of the first selection circuit and the second selection circuit, for example, the first selection end of the first selection circuit and the first selection end of the second selection circuit receive the same selection control signal (for example, the first selection control signal of the first selection circuit or the first selection control signal of the second selection circuit), the second selection end of the first selection circuit and the second selection end of the second selection circuit are used to receive the same selection control signal. A control signal (for example, the second selection control signal of the first selection circuit or the second selection control signal of the second selection circuit) is used. When the first selection control signal of the first selection circuit or the first selection control signal of the second selection circuit is enabled, the first bit line connected to the first selection end of the first selection circuit and the second bit line connected to the first selection end of the second selection circuit are turned on with the sense amplifier; when the second selection control signal of the first selection circuit or the second selection control signal of the second selection circuit is enabled, the first bit line connected to the second selection end of the first selection circuit and the second bit line connected to the second selection end of the second selection circuit are turned on with the sense amplifier, and the first selection end of the first selection circuit and the first selection end of the second selection circuit are connected to the same selection control signal, so that the number of signal lines used to transmit the selection control signal can be reduced.

[0013] In a possible implementation, the sensitive amplifier also includes a first power supply terminal, a second power supply terminal and a sensitive amplifier circuit, and the sensitive amplifier circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor; the first end of the first transistor is connected to the first input terminal, the first end of the second transistor is connected to the second input terminal, the second end of the first transistor and the second end of the second transistor are connected to the first power supply terminal, the gate of the first transistor is connected to the second input terminal, and the gate of the second transistor is connected to the first input terminal; the first end of the third transistor is connected to the first input terminal, the first end of the fourth transistor is connected to the second input terminal, the second end of the third transistor and the second end of the fourth transistor are connected to the second power supply terminal, the gate of the third transistor is connected to the second input terminal, and the gate of the fourth transistor is connected to the first input terminal.

[0014] In a possible implementation, the first transistor and the second transistor are N-type metal oxide semiconductor field effect transistors, and the third transistor and the fourth transistor are P-type metal oxide semiconductor field effect transistors.

[0015] In a possible implementation, the sensitive amplifier also includes a voltage-equalizing transistor and a pre-charging circuit; wherein the first end of the voltage-equalizing transistor is connected to the first input end of the sensitive amplifier, and the second end of the voltage-equalizing transistor is connected to the second input end of the sensitive amplifier circuit; the pre-charging circuit includes a first charging transistor and a second charging transistor, the first end of the first charging transistor is connected to the first input end of the sensitive amplifier, the first end of the second charging transistor is connected to the second input end of the sensitive amplifier, and the second end of the first charging transistor and the second end of the second charging transistor are connected to the reference voltage end; the gate of the voltage-equalizing transistor, the gate of the first charging transistor and the gate of the second charging transistor are used to receive an average control signal, and the first charging transistor and the second charging transistor are used to pre-charge the first input end and the second input end of the sensitive amplifier to the voltage of the reference voltage end in response to the average control signal; the voltage-equalizing transistor is used to make the voltages of the first input end and the second input end of the sensitive amplifier the same in response to the average control signal.

[0016] In a possible implementation, the voltage balancing transistor and the pre-charging circuit are implemented through a front-end process.

[0017] In one possible implementation, the sensitive amplifier also includes a voltage equalizing transistor and multiple pre-charging circuits; the first end of the voltage equalizing transistor is connected to the first input end of the sensitive amplifier, the second end of the voltage equalizing transistor is connected to the second input end of the sensitive amplifier circuit, the gate of the voltage equalizing transistor is used to receive an average control signal, and the voltage equalizing transistor is used to make the voltages of the first input end and the second input end of the sensitive amplifier the same in response to the average control signal; the multiple pre-charging circuits correspond one-to-one to the multiple storage layers, wherein the pre-charging circuit includes a first charging transistor and a second charging transistor, the first end of the first charging transistor is connected to the first bit line of the storage layer corresponding to the pre-charging circuit, the first end of the second charging transistor is connected to the second bit line of the storage layer corresponding to the pre-charging circuit, the second end of the first charging transistor and the second end of the second charging transistor are connected to the reference voltage end, and the gate of the first charging transistor and the gate of the second charging transistor are used to pre-charge the first bit line and the second bit line of the storage layer to the voltage of the reference voltage end in response to the pre-charging control signal corresponding to the storage layer.

[0018] In a possible implementation, the voltage balancing transistor is implemented through a front-end process, and the pre-charging circuit is implemented through a back-end process, or both the voltage balancing transistor and the pre-charging circuit are implemented through a front-end process.

[0019] The memory provided in the embodiment of the present application is provided with a voltage-equalizing transistor and a plurality of pre-charging circuits corresponding to the stacked multiple storage layers. The pre-charging circuit is used to charge the first bit line and the second bit line of the storage layer corresponding to the pre-charging circuit to the voltage of the reference voltage terminal (i.e., the reference voltage), so as to avoid the first bit line and the second bit line of the unselected storage layer from being in a floating state when the storage layer is not selected. In addition, the voltage-equalizing transistor can be implemented by a front-end process, and the pre-charging circuit can be implemented by either a front-end process or a back-end process. For example, the first charging transistor and the second charging transistor in the pre-charging circuit can be implemented by an N-type or P-type transistor in a traditional CMOS circuit and placed in the front-end, or can be implemented by a transistor based on an oxide semiconductor. In this case, the first charging transistor and the second charging transistor corresponding to each storage layer can be placed in the same layer as the storage layer.

[0020] In a possible implementation, the sensitive amplifier also includes a first power supply terminal, a second power supply terminal, a sensitive amplifier circuit and a drift compensation circuit. The sensitive amplifier circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor; the first end of the first transistor is connected to the first end of the third transistor, the first end of the second transistor is connected to the first end of the fourth transistor, the second end of the first transistor and the second end of the second transistor are connected to the first power supply terminal; the second end of the third transistor and the second end of the fourth transistor are connected to the second power supply terminal, the gate of the second transistor and the gate of the fourth transistor are connected to the first input terminal of the sensitive amplifier; the gate of the first transistor and the gate of the third transistor are connected to the second input terminal of the sensitive amplifier; the drift compensation circuit includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; the fifth transistor The first end is connected to the first end of the first transistor and the first end of the third transistor, and the second end of the fifth transistor is connected to the second input end of the sensitive amplifier; the first end of the sixth transistor is connected to the first end of the second transistor and the first end of the fourth transistor, and the second end of the sixth transistor is connected to the first input end of the sensitive amplifier, and the gate of the fifth transistor and the gate of the sixth transistor are used to receive the first drift compensation control signal; the first end of the seventh transistor is connected to the first end of the first transistor and the first end of the third transistor, and the second end of the seventh transistor is connected to the first input end of the sensitive amplifier; the first end of the eighth transistor is connected to the first end of the second transistor and the first end of the fourth transistor, and the second end of the eighth transistor is connected to the second input end of the sensitive amplifier, and the gate of the seventh transistor and the gate of the eighth transistor are used to receive the second drift compensation control signal.

[0021] A drift compensation circuit is set up to compensate for the threshold voltage drift of the first transistor, the second transistor, the third transistor, and the fourth transistor in the sensitive amplifier circuit caused by process reasons, thereby preventing the sensitive amplifier circuit from incorrectly sensing data on the first bit line or the second bit line due to the threshold voltage drift.

[0022] In one possible implementation, the sensitive amplifier also includes a charging transistor, a first end of the charging transistor is connected to a reference power supply end, a second end of the charging transistor is connected to a first input end of the sensitive amplifier, and a gate of the charging transistor is used to receive a pre-charging control signal and charge in response to the pre-charging control signal.

[0023] In a possible implementation, the first transistor and the second transistor are N-type metal oxide semiconductor field effect transistors, and the third transistor and the fourth transistor are P-type metal oxide semiconductor field effect transistors.

[0024] In a possible implementation, the memory has an open bit line structure, and the first bit line and the second bit line are located in different memory arrays.

[0025] In a possible implementation, the memory has a folded bit line structure, and the first bit line and the second bit line are located in the same memory array.

[0026] In a second aspect, an embodiment of the present application further provides a storage device, comprising a controller and a memory provided in any one of the implementations of the first aspect, wherein the controller is connected to the memory.

[0027] In a third aspect, an embodiment of the present application further provides an electronic device, the electronic device comprising a circuit board and a storage device connected to the circuit board, wherein the storage device is the storage device provided in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of an electronic device provided in an embodiment of the present application;

[0029] Figure 2 A schematic diagram of a storage unit provided in an embodiment of the present application;

[0030] Figure 3 A schematic diagram of the working principle of a storage unit provided in an embodiment of the present application;

[0031] Figure 4 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0032] Figure 5 A schematic diagram of a storage array provided in an embodiment of the present application;

[0033] Figure 6A schematic diagram of a sensitive amplifier provided in an embodiment of the present application;

[0034] Figure 7 A schematic diagram of an application scenario of a sensitive amplifier provided in an embodiment of the present application;

[0035] Figure 8 An equivalent schematic diagram of a sensitive amplifier provided in an embodiment of the present application;

[0036] Fig. 9 A timing diagram of access operations of a memory provided in an embodiment of the present application;

[0037] Fig.10 A schematic diagram of a pre-charge phase of a memory access operation provided by an embodiment of the present application;

[0038] Fig.11 A schematic diagram of a charge sharing phase of a memory access operation provided by an embodiment of the present application;

[0039] Fig.12 A schematic diagram of a sensing phase of a memory access operation provided by an embodiment of the present application;

[0040] Fig.13 A schematic diagram of a write-back phase of a memory access operation provided by an embodiment of the present application;

[0041] Fig.14 A schematic diagram of a memory array with a folded bit line structure provided by an embodiment of the present application;

[0042] Fig.15 A schematic diagram of the structure of another memory provided in an embodiment of the present application;

[0043] Fig.16 A schematic diagram of a memory array with an open bit line structure provided by an embodiment of the present application;

[0044] Fig.17 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0045] Fig.18 A schematic diagram of a memory provided for an embodiment of the present application;

[0046] Fig.19 A schematic diagram of a memory provided for an embodiment of the present application;

[0047] Fig. 20 Another schematic diagram of a memory provided in an embodiment of the present application;

[0048] Fig.21 A schematic diagram of the circuit structure of the memory provided in the embodiment of the present application;

[0049] Fig. 22 A schematic diagram of a circuit structure of a memory provided in another embodiment of the present application;

[0050] Fig.23 A timing diagram of memory access operation provided by another embodiment of the present application;

[0051] Fig.24 A schematic diagram of a circuit structure of a memory provided in yet another embodiment of the present application;

[0052] Fig.25 A timing diagram of memory access operation provided by another embodiment of the present application;

[0053] Fig.26 A schematic diagram of a circuit structure of a memory provided in yet another embodiment of the present application;

[0054] Fig. 27 A timing diagram of memory access operations provided in accordance with yet another embodiment of the present application. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0056] In the following, the terms "first", "second", etc. are used only for convenience of description and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more. For example, a plurality of processing units refers to two or more processing units.

[0057] In addition, in the embodiments of the present application, "upper", "lower", "left" and "right" are not limited to being defined relative to the orientation of the components schematically placed in the drawings. It should be understood that these directional terms can be relative concepts, which are used for description and clarification relative to the components, and can change accordingly according to the change in the orientation of the components placed in the drawings. In the drawings, for the sake of clarity, the thickness of the layers and regions is exaggerated, and the size ratio relationship between the parts in the drawings does not reflect the actual size ratio relationship.

[0058] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integrated connection; "connection" can be an electrical connection, or a direct connection, or an indirect connection through an intermediate medium.

[0059] In the embodiments of the present application, the term "module" is generally a functional structure divided according to logic, and the "module" can be implemented by pure hardware, or by a combination of software and hardware. In the embodiments of the present application, "and / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, B exists alone, and A and B exist at the same time.

[0060] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0061] In the embodiments of the present application, the transistor may be a metal-oxide-semiconductor field effect transistor (MOSFET), and the transistor is divided into two types: N (negative) type transistor (referred to as NMOS tube) and P (positive) type transistor (referred to as PMOS). The transistor includes a source, a drain and a gate, and the on or off of the transistor can be controlled by controlling the voltage of the input transistor gate. When the transistor is turned on, the source and the drain are turned on to generate an on current, and when the gate voltage of the transistor is different, the on current generated between the source and the drain is also different; when the transistor is cut off or turned off, the source and the drain will not be turned on and no current will be generated. In the embodiments of the present application, the source of the transistor is referred to as the first terminal, and the drain is referred to as the second terminal; or, the drain is referred to as the first terminal, and the source is referred to as the second terminal; the gate of the transistor is also referred to as the control terminal. In addition, when the level of the gate is high, the NMOS is turned on, the first terminal and the second terminal are turned on, and a conduction current is generated between the first terminal and the second terminal; when the level of the gate is low, the NMOS is turned off, the first terminal and the second terminal are not turned on, and no current is generated. When the level of the gate is low, the PMOS is turned on, the first terminal and the second terminal are turned on, and a conduction current is generated; when the level of the gate is high, the PMOS is turned off, the first terminal and the second terminal are not turned on, and no current is generated.

[0062] The memory provided in the embodiments of the present application can be applied to electronic devices, which may include mobile phones, personal computers, tablet computers (pads), televisions, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices and other electronic products, or may also be servers, workstations, etc. The embodiments of the present application do not impose any special restrictions on the specific forms of the above electronic devices.

[0063] Figure 1 A schematic diagram of an electronic device architecture provided in an embodiment of the present application, such as Figure 1 As shown, the electronic device 100 may include at least a processor 101, a memory controller 102, and a memory 103. Generally, the memory controller 102 may be integrated in the processor 101, and the memory 103 may be a main memory (or also referred to as a memory). Figure 1 In addition to the components shown, the electronic device 100 may also include other components such as a communication interface, a cache, and an auxiliary storage, which are not limited here.

[0064] The processor 101 is the computing core and control unit of the electronic device 100. The processor 101 may include multiple cores 104. An operating system and other software programs are installed in the processor 101, so that the processor 101 can access the memory 103, cache, auxiliary storage, etc. In an embodiment of the present application, the core 104 in the processor 101 may be a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor (digital signal processor), and a neural network processor, and may also be other specific integrated circuits (application specific integrated circuits, ASICs), etc.

[0065] The memory controller 102 is a bus circuit controller that controls the memory 103 inside the electronic device 100 and is used to manage and plan data transmission from the memory 103 to the core 104. Through the memory controller 102, data can be exchanged between the memory 103 and the core 104. The memory controller 102 can be a separate chip and connected to the core 104 through the system bus. The memory controller 102 can also be integrated into the processor 101. The embodiments of the present application do not limit the specific location of the memory controller 102. In practical applications, the memory controller 102 can control the necessary logic to write data into the memory 103 or read data from the memory 103.

[0066] The memory 103 is the main memory of the electronic device 100. The memory 103 is connected to the memory controller 102 via a bus. The memory 103 is usually used to store various running software in the operating system, input and output data, and information exchanged with external memory. The memory 103 usually adopts a random access memory (RAM), such as a ferroelectric random access memory (FeRAM), a dynamic random access memory (DRAM), etc.

[0067] Taking DRAM as an example, the smallest unit for storing data in DRAM is called a memory cell. Usually, a memory cell can store 1 bit of data, so it is also called a bit cell. Figure 2 The storage unit may include a storage capacitor C and an access transistor T. The storage capacitor C may store a bit of data in the form of electric charge or electrons. Generally speaking, if there is an electric charge on the storage capacitor C, it represents storage 1, and if there is no electric charge on the storage capacitor C, it represents storage 0; or, when there is an electric charge on the storage capacitor C, it represents storage 0, and if there is no electric charge on the storage capacitor C, it represents storage 1.

[0068] The first end of the access transistor T is connected to the bit line (BL), and the second end thereof is connected to the first end of the storage capacitor C. The gate of the access transistor T is connected to the word line (WL). The second end of the storage capacitor C can be grounded or connected to an equipotential point, wherein the voltage of the equipotential point can be half the power supply voltage or other set voltages, etc.

[0069] Figure 3A schematic diagram of the working principle of a storage unit provided in an embodiment of the present application, wherein an access transistor T can be used to access and read or write data of a storage capacitor C. Applying a voltage on a word line can turn on the access transistor T. When the access transistor T is turned on, electrons can flow through the conductive channel of the access transistor T, thereby turning on the storage capacitor C and the bit line. In this way, the storage capacitor C can be charged to write 1 to the storage capacitor C, or the storage capacitor C can be discharged to write 0 to the storage capacitor C. In addition, the data stored in the storage capacitor C can be read by measuring the amount of charge. When the word line is turned off, the access transistor T is also turned off, and the storage capacitor C is isolated from the bit line, thereby preserving the previously written data or charge.

[0070] In the above example, the DRAM storage cell includes 1 transistor and 1 capacitor. This structure is called a 1 transistor-1 capacitor structure (1T1C). DRAM also includes many other types of storage cell structures. If the DRAM storage cell includes two transistors and two capacitors, it is called 2T2C; if it includes two transistors and one capacitor, it is called 2T1C.

[0071] In practical applications, the storage cells of DRAM are usually arranged and distributed into a matrix, which we call a memory array. Each storage cell in the memory array stores 1 bit of data, and each DRAM usually includes multiple memory arrays.

[0072] Reference Figure 4 As shown, the memory 200 may include a command decoder 210, a control logic circuit, a storage array 230, and an input / output circuit 240. The specific embodiment is not limited thereto and may include fewer or greater number of components. The command decoder 210 may receive a command CMD (command, CMD) from the memory controller 102 and may decode the received command CMD. For example, the command CMD may include a write command (write, WR), a read command (read, RD), an active command (active, ACT), and / or a precharge command (precharge, PRE).

[0073] The memory array 230 may include a plurality of memory cells. The plurality of memory cells may be connected to a plurality of word lines and a plurality of bit lines. The word lines may be connected to a word line control circuit (or row decoder, word line resolver), and the bit lines may be connected to a bit line control circuit (or column decoder, bit line resolver). The memory controller 102 may locate any memory cell in the memory array 230, i.e., locate any bit of data, through a corresponding address line (e.g., word line, bit line) decoder.

[0074] The control logic circuit 220 may control the components of the memory 200 based on the decoding result from the command decoder 210. For example, in the case where the decoding result of the command decoder 210 indicates that the received command CMD is an activation command ACT, the control logic circuit 220 may control the word line control circuit so as to activate the word line corresponding to the row address (RA) received together with the activation command ACT. In this case, the data stored in the memory cell connected to the activated word line may be set (e.g., transferred, sent, output, etc.) to the input / output circuit 240 through the sense amplifier (SA). For example, in the case where the decoding result of the command decoder 210 indicates that the received command CMD is a read command RD, the control logic circuit 220 may control the input / output circuit 240 so as to output data from the bit line corresponding to the column address (CA) received together with the read command RD.

[0075] Figure 5 Show Figure 4 , the memory array 230 may include a plurality of memory cells (MC). The memory cell MC may include an access transistor T and a storage capacitor C. The first end of the access transistor T of the memory cell is connected to one of the bit lines BL1 to BLm, and the second end thereof is connected to the first end of the storage capacitor C. The gate of the access transistor T is connected to one of the word lines WL1 to WLn. In some embodiments, when any one of the word lines WL1 to WLn is selected and activated, the data stored in the memory cell connected to the selected word line may be provided to the input / output circuit 240 through the bit line and the sense amplifier; or, the data provided by the input / output circuit 240 may be written to the memory cell through the sense amplifier and the bit line.

[0076] The storage unit can store data by using the presence or absence of charge or the amount of charge on the storage capacitor C. When reading the data stored in the storage unit, the data stored in the storage capacitor C can also be read by measuring the amount of charge.

[0077] In a storage cell with a 1T1C structure, when the word line is activated to turn on the access transistor T, electrons can flow through the conductive channel of the access transistor T, thereby turning on the storage capacitor C and the bit line. In this way, the charge on the storage capacitor C will be shared with the bit line. If the charge on the storage capacitor C is large, the voltage of the bit line will be raised. If the charge on the storage capacitor C is small, the voltage of the bit line will be lowered. Therefore, the charge of the storage capacitor C can be judged by sensing the voltage change on the bit line, thereby judging whether the read value is 1 or 0.

[0078] In DRAM, the area of ​​each memory cell is very small, only about tens of nanometers in size. A bit line can connect hundreds or thousands or more memory cells. The capacitance of the storage capacitor C is much smaller than the capacitance of the bit line. Therefore, when the charge in the storage capacitor C is shared to the bit line, the voltage change generated on the bit line is relatively small, making it difficult to measure.

[0079] In DRAM devices, the voltage sensing problem is solved by using a sense amplifier, which is usually composed of a thin gate device that is sensitive to tiny voltages. The sense amplifier can compare the bit line voltage with a reference voltage and amplify the voltage difference between the bit line voltage and the reference voltage to read data.

[0080] See also Figure 6 , Figure 6 The structure diagram of a sensitive amplifier 30 provided in an embodiment of the present application is shown. The sensitive amplifier 30 includes a sensitive amplifier circuit 31, a first power supply terminal SAN, a second power supply terminal SAP, a first input terminal SABL and a second input terminal SA / BL. The sensitive amplifier circuit 31 includes four cross-connected transistors: a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4. The first transistor T1 and the second transistor T2 are NMOS transistors, the third transistor T3 and the fourth transistor T4 are PMOS transistors, and the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are all thin-gate devices, which are more sensitive to voltage changes and can sensitively sense voltage differences.

[0081] Among them, the first end of the first transistor T1 is connected to the first input terminal SABL, the first end of the second transistor T2 is connected to the second input terminal SA / BL, the first power supply terminal SAN, the second end of the first transistor T1 and the second end of the second transistor T2 are connected, the gate of the first transistor T1 is connected to the second input terminal SA / BL, and the gate of the second transistor T2 is connected to the first input terminal SABL.

[0082] A first end of the third transistor T3 is connected to the first input terminal SABL, a first end of the fourth transistor T4 is connected to the second input terminal SA / BL, a second end of the third transistor T3 and a second end of the fourth transistor T4 are connected to the second power supply terminal SAP, a gate of the third transistor T3 is connected to the second input terminal SA / BL, and a gate of the fourth transistor T4 is connected to the first input terminal SABL.

[0083] The first input terminal SABL can be used to connect the first bit line BL1, and the second input terminal SA / BL can be used to connect the second bit line BL2. The first bit line BL1 and the second bit line BL2 form a bit line pair. Based on this bit line pair, the sensitive amplifier circuit can read the data on the first bit line BL1 or the second bit line BL2. When reading the data of the storage unit on the first bit line BL1, the second bit line BL2 can be used as a reference, and when reading the data on the second bit line BL2, the first bit line BL1 can be used as a reference.

[0084] Combination Figure 7 The sensitive amplifier 30 also includes a voltage equalizing circuit 32, which is controlled by an equalization (EQ) signal. The voltage equalizing circuit 32 includes three transistors controlled by the EQ signal: a voltage equalizing transistor Teq, a first pre-charging transistor Tc1, and a first pre-charging transistor Tc2. One end of the first pre-charging transistor Tc1 and the first pre-charging transistor Tc2 are both connected to the reference signal end, and the other ends of the two pre-charging transistors are respectively connected to the first bit line BL1 (or can be considered as the first input end SABL of the sensitive amplifier 30) and the second bit line BL2 (or can be considered as the second input end SA / BL of the sensitive amplifier 30). The first end of the voltage equalizing transistor Teq is connected to the first bit line BL1 (or can be considered as the first input end SABL of the sensitive amplifier 30), and the second end of the voltage equalizing transistor Teq is connected to the second bit line BL2 (or can be considered as the second input end SA / BL of the sensitive amplifier 30).

[0085] When the EQ signal enables the first pre-charging transistor Tc1 and the first pre-charging transistor Tc2 in the voltage equalizing circuit 32 to be turned on, these two transistors can turn on both the first bit line BL1 and the second bit line BL2 to the reference signal terminal, and charge the voltage of the first bit line BL1 and the second bit line BL2 to the reference voltage Vref; at the same time, the EQ signal will also enable the voltage equalizing transistor Teq to be turned on. After the voltage equalizing transistor Teq is turned on, the first bit line BL1 and the second bit line BL2 are equivalent to being connected together. At this time, the voltage of the first bit line BL1 and the second bit line BL2 are the same. The voltage equalizing circuit 32 can ensure that the initial voltage on the bit line pair (for example, the first bit line BL1 and the second bit line BL2) connected to the sensitive amplifier 30 is as similar as possible. In this way, when a voltage difference appears on the bit line pair, the sensitive amplifier 30 can be used to accurately restore and amplify the voltage difference on the bit line pair.

[0086] The core circuit of the sensitive amplifier is a sensitive amplifier circuit 31 composed of four transistors, such as Figure 8As shown, the first transistor T1 and the third transistor T3 can constitute a first inverter INV1, the second transistor T2 and the fourth transistor T4 can constitute a second inverter INV2, and the first inverter INV1 and the second inverter INV2 are connected end to end, so that when the voltage of one of the two input ends of the sensitive amplifier circuit 31 is higher than that of the other end, under the action of the first inverter INV1 and the second inverter INV2, the voltage of the end with a higher voltage will become higher, and the voltage of the end with a lower voltage will become lower, and finally a stable state of a high level at one end and a low level at the other end is reached.

[0087] For example, the operation of a sense amplifier generally includes several stages: precharge, charge sharing, sensing, read / write, and write-back. Fig. 9 FIG. 4 shows an operation timing diagram of a sense amplifier (read 1), wherein the charge sharing phase and the sensing phase are also combined and referred to as an active (ACT) phase. Fig.10 FIG. 1 shows a schematic diagram of a precharge phase, which shows that before starting the process of reading data of a memory cell, the first bit line BL1 and the second bit line BL2 are precharged to a reference voltage Vref. In some implementations, an intermediate voltage VCC / 2 of a power supply voltage VCC is used as the reference voltage Vref. Fig.10 In the circuit shown in FIG. 4 , the EQ circuit is activated and simultaneously precharges the first bit line BL1 and the second bit line BL2 to the reference voltage Vref.

[0088] The precharge phase is followed by the access phase, also known as the charge sharing phase. Fig.11A schematic diagram of the access phase is shown. In this phase, for example, if the data stored in the storage unit connected to the first bit line BL1 is accessed, the storage unit includes an access transistor T0 and a storage capacitor C0, and WL is activated to turn on the access transistor T0. The storage capacitor C0 is connected to the first bit line BL1 through the access transistor T0 to share charge. Exemplarily, the embodiment of the present application is described by taking the storage capacitor C0 storing more charge, when the voltage is VCC, it represents storage 1, otherwise it represents storage 0. Assuming that the storage capacitor C0 stores 1, when the storage capacitor C0 is connected to the first bit line BL1, the storage capacitor C0 will discharge to the first bit line BL1, so the storage capacitor C0 shares the charge of the first bit line BL1, which will cause the voltage of the first bit line BL1 to increase on the basis of the reference voltage Vref, and the voltage of the first bit line BL1 changes to Vref+, while the voltage of the second bit line BL2 does not change and remains at Vref. In this way, the voltage of the first input terminal SABL of the sense amplifier is the same as the voltage of the first bit line BL1, which is Vref+, and the voltage of the second input terminal SA / BL is the same as the voltage of the second bit line BL2, which is Vref, wherein the first input terminal SABL is connected to the gates of the second transistor T2 and the fourth transistor T4, and the second input terminal SA / BL is connected to the gates of the first transistor T1 and the third transistor T3. The slight voltage difference between the first bit line BL1 and the second bit line BL2 makes the gate voltage of the second transistor T2 higher than the gate voltage of the first transistor T1, which drives the second transistor T2 to be more conductive than the first transistor T1, and the slight voltage difference between the first bit line BL1 and the second bit line BL2 makes the gate voltage of the fourth transistor T4 higher than the gate voltage of the third transistor T3, which drives the fourth transistor T4 to be less conductive than the third transistor T3.

[0089] Fig.12 The schematic diagram of the sensing stage is shown. In the sensing stage, the control signals of the first power supply terminal SAN and the second power supply terminal SAP of the sense amplifier 30 are activated. The signal of the first power supply terminal SAN can control the conduction state of the NMOS tube in the sense amplifier circuit 31, and the signal of the second power supply terminal SAP can control the conduction state of the PMOS tube in the sense amplifier circuit 31. Usually, the signal of the first power supply terminal SAN is a low-level signal representing 0, such as VSS; the signal of the second power supply terminal SAP is a high-level signal representing 1, such as VCC.

[0090] Since the second transistor T2 is more conductive than the first transistor T1 under the action of the voltage difference between the first bit line BL1 and the second bit line BL2, the voltage of the second input terminal SA / BL will be pulled lower on the basis of Vref by the voltage of the first power supply terminal SAN through the second transistor T2 under the action of the signal of the first power supply terminal SAN; since the fourth transistor T4 is less conductive than the third transistor T3, the voltage of the first input terminal SABL will be pulled higher on the basis of Vref+ by the voltage of the second power supply terminal SAP through the third transistor T3 under the action of the signal of the second power supply terminal SAP, so that the voltage of the second input terminal SA / BL is pulled down and the voltage of the first input terminal SABL is pulled up, which in turn makes the second transistor T2 more conductive than the first transistor T1. The fourth transistor T4 is less conductive than the third transistor T3, until a stable state is reached in which the second transistor T2 is turned on, the first transistor T1 is turned off, the third transistor T3 is turned on, and the fourth transistor T4 is turned off, so that the first input terminal SABL is turned on with the second power supply terminal SAP, and the voltage of the first input terminal SABL is driven to be the same as the voltage of the SAP signal, that is, the high level VCC representing 1; the second input terminal SA / BL is turned on with the first power supply terminal SAN, and the voltage of the second input terminal SA / BL is driven to be the same as the voltage of the first power supply terminal SAN, that is, the low level VSS representing 0, so that the voltage difference between the voltage (Vref+) of the first bit line BL1 and the voltage (Vref) of the second bit line BL2 is amplified to the state difference of two voltage extremes, such as VCC and VSS.

[0091] The input end of the sensitive amplifier circuit 31 is also the output end. After the voltage difference between the first bit line BL1 and the second bit line BL2 is amplified to the state difference of two voltage extremes such as VCC and VSS, the voltage of the first input end SABL is the same as the voltage of the first bit line BL1, and the voltage of the second input end SA / BL is the same as the voltage of the second bit line BL2, so that the amplified voltage difference can be read at the first input end SABL and the second input end SA / BL to read the data of the storage unit.

[0092] Fig.13The schematic diagram of the write-back phase is shown. After reading the data, in order to avoid rewriting the data of the storage unit during the reading process, the read data is written into the storage unit again, so it is called write-back. Write-back is actually a process of writing data. After the voltage of the first bit line BL1 is driven to the voltage VCC representing 1 or the voltage VSS representing 0, if WL is still in the activated state, the storage capacitor C0 can be connected to the first bit line BL1 through the access transistor T0, and the voltage on the first bit line BL1 can restore the original state of the storage capacitor C0 through the access transistor T0, such as charging the voltage of the storage capacitor C0 to VCC, or pulling down the voltage of the storage capacitor C0 to VSS, to complete the write-back.

[0093] The sense amplifier can amplify the slight voltage difference on the bit line pair, so as to accurately read the data. The use of the sense amplifier also puts forward certain requirements for the array structure of DRAM: the use of the sense amplifier means using a pair of bit lines instead of a single bit line to detect the voltage value contained in any DRAM storage cell. When reading the voltage on a bit line, the voltage on another reference bit line needs to be compared as a reference. The capacitance resistance (RC) parameters of this pair of bit lines need to match, otherwise in the sensing stage, the voltage on the end with a smaller RC parameter drops faster, which may cause the side with a higher voltage to be judged as the side with a lower voltage by the sensitive amplifier circuit due to the smaller capacitance and faster voltage drop, resulting in reading data errors. In order to ensure that this pair of bit lines is closely matched in terms of voltage and capacitance, this pair of bit lines needs to be closely matched in terms of path length and the number of connected storage cells. These requirements lead to two completely different array structures: folded bitline structure and open bitline structure.

[0094] In the folded bit line structure, the bit line pair for each sense amplifier comes from the same memory array. In a memory array, when any word line is activated, the access transistors of a row of memory cells connected to the word line will be turned on, which means that the storage capacitors of the memory cells in this row will share charge with the bit lines connected to them. The voltage of all the bit lines in the memory array will change. If the sense amplifier uses two independent bit lines in the memory array as a reference, then when the word line is activated, only one of the two bit lines that are referenced to each other is allowed to change voltage. See Fig.14 As shown, in a storage array with a folded bit line structure, alternately arranged storage cells are respectively connected to two adjacent bit lines (the first bit line BL1 and the second bit line BL2 shown in the figure) which refer to each other. For example, odd-numbered storage cells are connected to the first bit line BL1, and even-numbered storage cells are connected to the second bit line BL2. Therefore, such a structure is called a folded bit line structure.

[0095] In the folded bit line structure, the alternately arranged memory cells are connected to the sense amplifier through two bit lines. The memory cells connected to the first bit line BL1 and the second bit line BL2 are connected to different word lines. Therefore, when the selected word line is activated, only one of the voltages on the left bit line and the right bit line will change. Thus, the voltage of one of the left bit line and the right bit line can be used as a reference voltage to read data. The folded bit line structure enables the alternately arranged memory cells in the memory array to be connected to the sense amplifier through two independent bit lines, thereby doubling the number of bit lines and making the DRAM with the folded bit line structure occupy a larger area.

[0096] Based on the folded bit line structure, there is also a bit line structure that shares a sense amplifier, see Fig.15 , two bit line pairs BL1, BL2 and bit line pairs BL3, BL4 from different memory arrays can share a sense amplifier, and the sense amplifier can work with the bit line pairs BL1, BL2 to read or write data; or, the sense amplifier can work with the bit line pairs BL3, BL4 to read or write data, which can reduce the number of sense amplifiers by 1 / 2. However, due to the problem of increased number of bit lines and increased storage unit area caused by the folded bit line structure, this result has not been widely used.

[0097] The difference between an array with an open bitline structure and an array with a folded bitline structure is that in the folded bitline structure, the bitline pairs used by each sense amplifier come from the same array, while in the open bitline structure, the two bitline pairs connected to each sense amplifier come from different arrays. Fig.16 , the first bit line BL1 connected to the first input terminal of the sense amplifier comes from the memory array MAT1, and the second bit line BL2 connected to the second input terminal of the sense amplifier comes from the memory array MAT2. Usually in DRAM, the sizes of the memory arrays MAT1 and MAT2 are comparable, so the first bit line BL1 and the second bit line BL2, which are references to each other, have the same length, the number of connected memory cells matches, and the RC parameters of the first bit line BL1 and the second bit line BL2 match, so data can be read and written correctly.

[0098] The above examples introduce the structure of two-dimensional memory and the principles of reading and writing. However, with the continuous development of artificial intelligence (AI) and high performance computing (HPC), modern computing technology has gradually increased the demand for large-capacity and high-density memory. However, the size reduction of traditional two-dimensional memory has gradually encountered bottlenecks, and the improvement of storage capacity and density has become an urgent problem to be solved.

[0099] In recent years, the thin film transistor (TFT) process based on oxide semiconductor as the channel material is compatible with the back end of line (BEOL) process, which can realize the multi-layer stacking of memory devices to form a three-dimensional memory device, stacking multiple memory layers on the substrate, thereby improving the storage capacity and storage density. Fig.17 As shown, Fig.17 A plurality of storage layers are stacked on a substrate in a direction perpendicular to the substrate (Z direction shown in the figure), for example, storage layer L1, storage layer L2, storage layer L3 and storage layer L4. The storage layers here may also be referred to as storage array layers, wherein each storage layer includes the aforementioned Figure 5 In the memory array shown, each memory layer includes word lines, bit lines and multiple memory cells distributed in a direction parallel to the substrate (XZ plane direction), which is equivalent to stacking the memory cells in a direction perpendicular to the substrate. While occupying the same area, the storage density of the three-dimensional memory device can be several to several hundred times that of the two-dimensional memory device.

[0100] Combination Figure 5 , the memory device can be abstracted into a three-port memory device having a word line, a bit line and a ground (or a shared port such as a plate line), and the sense amplifier is connected to the bit line and amplifies the signal thereon.

[0101] However, vertical stacking of multiple storage layers will inevitably lead to tight winding resources for the sense amplifiers (SA) interconnected with them. For example, assuming that a storage layer needs to have n sense amplifiers, after stacking m storage layers, n×m sense amplifiers need to be set up, which will increase the winding and area, while the space of the memory is limited. Therefore, how to design a compact and efficient sense amplifier circuit is the key to achieving improved storage capacity density.

[0102] For a memory with multiple stacked storage layers, it may be considered to share control lines such as word lines and bit lines or sense amplifiers among multiple storage layers to reduce the number of control lines or sense amplifiers. In this way, for word lines, bit lines and sense amplifiers, whether to share them among multiple storage layers has the following situations, as shown in Table 1:

[0103]

[0104] Table 1

[0105] Combined with the above example Figure 5When any word line is activated, all access transistors connected to the word line will be turned on, which means that all bit lines of the memory array will share charge with the storage capacitor. If word lines and bit lines are shared between different memory layers, it will make it impossible to locate a specific memory cell and write or read data. Therefore, if word lines and bit lines are shared between multiple stacked memory layers, invalid stacking will result.

[0106] If multiple storage layers share word lines but not bit lines, this is equivalent to dividing a larger storage array (with longer word lines) into multiple layers and stacking them. If in this case different storage layers share the same sensitive amplifier, when any word line is activated, the bit lines on each storage layer will share charge, and the data on each bit line needs to be read. If the bit lines of multiple different storage layers share the sensitive amplifier, the sensitive amplifier is used to read the data on the bit lines of a selected storage layer, and the data on the bit lines of the unselected storage layers will be lost. If the sensitive amplifiers are not shared in this case, the number of sensitive amplifiers will still increase, the occupied area will increase, the winding spacing of the sensitive amplifiers will decrease, and the process requirements will be higher.

[0107] If multiple storage layers share bit lines but do not share word lines, this is equivalent to dividing a larger storage array (with longer bit lines) into multiple layers and stacking them. In the stacking direction, the bit lines of different storage layers are actually connected together. If different storage layers do not share sensitive amplifiers, and the bit lines of each storage layer are connected to a sensitive amplifier, then when reading the data of a storage cell on a certain bit line, since different storage layers share bit lines, the bit lines on different storage layers will all read the same data, so such a memory cannot work. If multiple storage layers share sensitive amplifiers, only one data can be read during reading, but sharing bit lines between different storage layers will cause the length of the bit lines to be too long, resulting in a larger capacitance. The capacitance of the storage capacitor is smaller than the capacitance of the bit line. In order to be able to measure the charge shared by the storage capacitor and the bit line, the capacitance value of the storage capacitor needs to be increased, such as Fig.17 As shown, the storage capacitor is in the shape of a cylinder. An increase in capacitance will lead to an increase in the height of the storage capacitor and an increase in the thickness of each storage layer, which is not process-friendly and cannot achieve multi-layer stacking.

[0108] Therefore, it is possible to consider not sharing word lines and bit lines between different storage layers, but only sharing sense amplifiers. The storage arrays of different storage layers are completely independent and do not affect each other, but the bit lines of different storage layers can share the same sense amplifier.

[0109] Illustratively, in order to solve the problems of an increased number of sensitive amplifiers, a larger occupied area, and a smaller winding pitch when stacking storage layers, an embodiment of the present application provides a new type of memory, in which multiple stacked storage layers can share sensitive amplifiers, thereby reducing the number of sensitive amplifiers, reducing the area occupied by the sensitive amplifiers, increasing the winding pitch of the sensitive amplifier lines, and reducing the process difficulty.

[0110] The present application embodiment provides a memory, referring to Fig.18 , Fig.18 The schematic diagram of the structure of the memory provided by the embodiment of the present application is shown, and the memory includes a plurality of storage layers stacked in a direction perpendicular to the substrate, for example Fig.18 As shown in the storage layer L1 to the storage layer L4, the bit lines of multiple storage layers can share a sensitive amplifier. For example, the bit line L1_BL1 of the storage layer L1, the bit line L2_BL1 of the storage layer L2, the bit line L3_BL1 of the storage layer L3, and the bit line L4_BL1 of the storage layer L4 are connected to the first input terminal of the sensitive amplifier SA1, and the bit line L1_BL2 of the storage layer L1, the bit line L2_BL2 of the storage layer L2, the bit line L3_BL2 of the storage layer L3, and the bit line L4_BL2 of the storage layer L4 are connected to the second input terminal of the sensitive amplifier SA1. In this way, the bit lines of different storage layers can share the sensitive amplifiers SA1~SAn, so that the number of sensitive amplifiers can be reduced when the storage layers are stacked, the area they occupy can be reduced, and the winding spacing of the sensitive amplifiers can be increased.

[0111] For example, see Fig.19 , Fig.19 The circuit structure diagram of the memory provided by the embodiment of the present application is shown in FIG. Fig.19 As shown, the memory includes a plurality of storage layers, a first gating circuit S1, a second gating circuit S2 and a sense amplifier 40, which can be combined with reference to Fig.18 and Fig.19 Each storage layer includes a storage array formed by a word line, a bit line and a plurality of storage cells, and the plurality of storage layers are stacked in a direction perpendicular to the substrate, wherein each storage layer includes a first bit line and a second bit line, and the sensitive amplifier 40 includes a first input terminal SABL and a second input terminal SA / BL.

[0112] The first selection circuit S1 includes a plurality of selection terminals, a plurality of input terminals and an output terminal. The output terminal S1_OUT of the first selection circuit S1 is connected to the first input terminal SABL of the sense amplifier 40. The plurality of input terminals of the first selection circuit S1 are connected to the plurality of first bit lines in a one-to-one correspondence. That is, the number of the input terminals of the first selection circuit S1 matches the number of the first bit lines. Each input terminal of the first selection circuit S1 is connected to a unique first bit line corresponding thereto. Here, the plurality of first bit lines are respectively located in a plurality of storage layers. For example, the input terminal S1_IN1 (also referred to as the first input terminal) of the first selection circuit S1 is connected to the first bit line L1_BL1. The input terminal S1_IN2 is connected to the first bit line L2_BL1, and the input terminal S1_IN3 of the first selection circuit S1 is connected to the first bit line L3_BL1. Here, the first bit line L1_BL1 is located in the storage layer L1 (also called the first storage layer), the first bit line L2_BL1 is located in the storage layer L2, and the first bit line L3_BL1 is located in the storage layer L3. The selection terminal of the first selection circuit S1 (such as the selection terminal S1_sw1, the selection terminal S1_sw2 and the selection terminal S1_sw3 shown in the figure) is used to receive the first selection circuit selection control signal to select one of the multiple first bit lines connected to the multiple input terminals to be turned on with the first input terminal SABL of the sensitive amplifier 40.

[0113] The second gating circuit S2 includes a plurality of selection terminals, a plurality of input terminals and an output terminal. The output terminal S2_OUT of the second gating circuit S2 is connected to the second input terminal SA / BL of the sense amplifier 40. The plurality of input terminals of the second gating circuit S2 are connected to the plurality of second bit lines in a one-to-one correspondence. That is, the number of the input terminals of the second gating circuit S2 matches the number of the second bit lines. Each input terminal of the second gating circuit S2 is connected to a unique second bit line corresponding thereto. Here, the plurality of second bit lines are respectively located in a plurality of storage layers. For example, the input terminal S2_IN1 (also referred to as the first input terminal) of the second gating circuit S2 is connected to the second bit line L1_BL2. The input terminal S2_IN2 of the pass circuit S2 is connected to the second bit line L2_BL2, and the input terminal S2_IN3 of the second selection circuit S2 is connected to the second bit line L3_BL2. Here, the second bit line L1_BL2 is located in the storage layer L1, the second bit line L2_BL2 is located in the storage layer L2, and the second bit line L3_BL2 is located in the storage layer L3. The selection terminal of the second selection circuit S2 (such as the selection terminal S2_sw1, the selection terminal S2_sw2 and the selection terminal S2_sw3 shown in the figure) is used to receive the second selection circuit selection control signal to select one of the multiple second bit lines connected to the multiple input terminals to be turned on with the second input terminal SA / BL of the sensitive amplifier 40.

[0114] The first selection circuit S1 is used to connect one of the plurality of first bit lines to the first input terminal SABL of the sense amplifier 40, and the second selection circuit S2 is used to connect one of the plurality of second bit lines to the second input terminal SA / BL of the sense amplifier 40, so that the two bit lines connected to the first input terminal SABL and the second input terminal SA / BL of the sense amplifier 40 can be used as references to each other, thereby reading out data. For example, when reading out the data of the storage unit on the bit line connected to the first input terminal SABL, the bit line connected to the second input terminal SA / BL can be used as a reference; when reading out the data of the storage unit on the bit line connected to the second input terminal SA / BL, the bit line connected to the first input terminal SABL can be used as a reference. By setting the first selection circuit and the second selection circuit, the first bit line and the second bit line of different storage layers can share the same sense amplifier, which can reduce the number of sense amplifiers, reduce the occupied area, increase the winding pitch of the sense amplifier, and reduce the process difficulty.

[0115] In the embodiment of the present application, the first input terminal SABL of the sense amplifier 40 can be connected to the first bit line located in different storage layers through the first gating circuit S1, and the second input terminal SA / BL of the sense amplifier 40 can be connected to the second bit line located in different storage layers through the second gating circuit S2, so as to realize that multiple storage layers share the sense amplifier. In a possible implementation, the first gating circuit S1 and the second gating circuit S2 each include a plurality of switches, the switch includes a control end, a first end and a second end, and each input end of the first gating circuit S1 is connected to the output end S1_OUT of the first gating circuit S1 through a switch, wherein the control end of the switch of the first gating circuit is connected to the selection end of the first gating circuit S1, the first end of the switch of the first gating circuit S1 is connected to the input end of the first gating circuit S1, and the second end of the switch of the first gating circuit S1 is connected to the output end of the first gating circuit S1. Similarly, each input end of the second selection circuit S2 is connected to the output end S2_OUT of the second selection circuit S2 through a switch, wherein the control end of the switch of the second selection circuit S2 is connected to the selection end of the second selection circuit S2, the first end of the switch of the second selection circuit S2 is connected to the input end of the second selection circuit S2, and the second end of the switch of the second selection circuit S2 is connected to the output end of the second selection circuit S2.

[0116] Exemplary, combined Fig. 20The first gating circuit S1 includes an input terminal S1_IN1, an input terminal S1_IN2, a switch TA1, a switch TA2, a selection terminal S1_sw1, a selection terminal S1_sw2 and an output terminal S1_OUT. The input terminal S1_IN1 of the first gating circuit S1 is connected to the first bit line L1_BL1 of the storage layer L1, the input terminal S1_IN1 of the first gating circuit S1 is connected to the first terminal of the switch TA1, the second terminal of the switch TA1 is connected to the output terminal S1_OUT of the first gating circuit S1, and the control terminal of the switch TA1 is connected to the selection terminal S1_sw1 of the first gating circuit S1; the input terminal S1_IN2 of the first gating circuit S1 is connected to the first bit line L2_BL1 of the storage layer L2, the input terminal S1_IN2 of the first gating circuit S1 is connected to the first terminal of the switch TA2, the second terminal of the switch TA2 is connected to the output terminal S1_OUT of the first gating circuit S1, and the control terminal of the switch TA2 is connected to the selection terminal S1_sw2 of the first gating circuit S1. Among them, the first selection circuit selection control signal of the selection terminal S1_sw1 can control the switch TA1 to be turned on, so that the first bit line L1_BL1 connected to the input terminal S1_IN1 of the first selection circuit S1 is turned on with the first input terminal SABL of the sense amplifier 40; the first selection circuit selection control signal of the selection terminal S1_sw2 can control the switch TA2 to be turned on, so that the first bit line L2_BL1 connected to the input terminal S1_IN2 of the first selection circuit S1 is turned on with the first input terminal SABL of the sense amplifier 40.

[0117] Similarly, the second gating circuit S2 includes an input terminal S2_IN1, an input terminal S2_IN2, a switch TB1, a switch TB2, a selection terminal S2_sw1, a selection terminal S2_sw2 and an output terminal S2_OUT. The input terminal S2_IN1 of the second gating circuit S2 is connected to the second bit line L1_BL2 of the storage layer L1, the input terminal S2_IN1 of the second gating circuit S2 is connected to the first terminal of the switch TB1, the second terminal of the switch TB1 is connected to the output terminal S2_OUT of the second gating circuit S2, and the control terminal of the switch TB1 is connected to the selection terminal S2_sw1 of the second gating circuit S2; the input terminal S2_IN2 of the second gating circuit S2 is connected to the second bit line L2_BL2 of the storage layer L2, the input terminal S2_IN2 of the second gating circuit S2 is connected to the first terminal of the switch TB2, the second terminal of the switch TB2 is connected to the output terminal S2_OUT of the second gating circuit S2, and the control terminal (gate) of the switch TB2 is connected to the selection terminal S2_sw2 of the second gating circuit S2. Among them, the second selection circuit selection control signal of the selection terminal S2_sw1 can control the switch TB1 to be turned on, so that the second bit line L1_BL2 connected to the input terminal S2_IN1 of the second selection circuit S2 is turned on with the first input terminal SABL of the sense amplifier 40; the second selection circuit selection control signal of the selection terminal S2_sw2 can control the switch TB2 to be turned on, so that the second bit line L2_BL2 connected to the input terminal S2_IN2 of the second selection circuit S2 is turned on with the first input terminal SABL of the sense amplifier 40.

[0118] In a possible implementation, the switch may be a transistor or a transmission gate or other switching device. For example, a transistor may be combined with Fig.21 Taking the switch TA1 as an example, the switch TA1 can be a transistor TA1, wherein the source (or drain) of the transistor TA1 can be used as the first end of the switch, the drain (or source) of the transistor TA1 can be used as the second end of the switch, and the gate of the transistor TA1 can be used as the control end of the switch. For example, the transistor TA1 can be an NMOS tube, and when the first selection circuit selection control signal received by the selection end S1_sw1 of the first selection circuit S1 is a high level signal, the transistor TA1 is turned on, and the first bit line L1_BL1 is turned on with the first input end SABL of the sense amplifier 40.

[0119] In combination with the foregoing content, it can be seen that by controlling the first selection circuit selection control signal connected to multiple selection terminals of the first selection circuit S1, one of the first bit lines located in different storage layers can be selectively connected to the first input terminal SABL of the sensitive amplifier 40; by controlling the second selection circuit selection control signal connected to multiple selection terminals of the second selection circuit S2, one of the second bit lines located in different storage layers can be selectively connected to the second input terminal SA / BL of the sensitive amplifier 40.

[0120] Since the sense amplifier 40 uses a pair of bit lines instead of a single bit line to detect the voltage value contained in any memory cell, it means that the first selection circuit S1 needs to connect a first bit line to the first input terminal SABL of the sense amplifier 40, and the second selection circuit S2 also needs to connect a second bit line to the second input terminal SA / BL of the sense amplifier 40.

[0121] Exemplarily, the first selection circuit S1 and the second selection circuit S2 can respectively receive different selection control signals. In this case, the number of control lines required for the first selection circuit selection control signal of the first selection circuit S1 is the same as the number of selection terminals of the first selection circuit S1; the number of control lines required for the second selection circuit selection control signal of the second selection circuit S2 is the same as the number of selection terminals of the second selection circuit S2. Assuming that the first selection circuit S1 and the second selection circuit S2 respectively include p selection terminals, a total of 2p control lines are required to achieve independent control of the first selection circuit S1 and the second selection circuit S2.

[0122] In some other implementations, the first selection circuit S1 and the second selection circuit S2 can share a selection control signal. For example, the first selection end of the first selection circuit S1 and the first selection end of the second selection circuit S2 are used to receive the same selection control signal; the second selection end of the first selection circuit S1 and the second selection end of the second selection circuit S2 are used to receive the same selection control signal.

[0123] For example, combining Fig.21 , the selection end S1_sw1 of the first gating circuit S1 receives the first selection control signal of the first gating circuit, and the selection end S2_sw1 of the second gating circuit S2 is used to receive the first selection control signal of the second gating circuit. Here, the first selection control signal of the first gating circuit and the first selection control signal of the second gating circuit are the same selection control signal, which can be collectively referred to as the first selection control signal SEL_L1. The selection end S1_sw2 of the first gating circuit S1 receives the second selection control signal of the first gating circuit, and the selection end S2_sw2 of the second gating circuit S2 is connected to the second selection control signal of the second gating circuit. Here, the second selection control signal of the first gating circuit and the second selection control signal of the second gating circuit are the same selection control signal, which can be collectively referred to as the second selection control signal SEL_L2; in this way, the number of control signal lines can be reduced and the circuit structure can be simplified.

[0124] In a possible implementation, the switches in the first gating circuit S1 and the second gating circuit S2 may be P-type transistors or N-type transistors. In addition, the above transistors may be implemented using N-type or P-type transistors in conventional CMOS circuits, so that the first gating circuit S1 and the second gating circuit S2 may be implemented using a front end of line (FEOL) process. In another possible implementation, the above transistors may be implemented using a thin film transistor (TFT) based on an oxide semiconductor as a channel material, and the thin film transistor based on an oxide semiconductor as a channel material is compatible with a back end of line (BEOL) process, so the first gating circuit S1 and the second gating circuit S2 may be implemented using a back end process, in which case the switches corresponding to each storage layer may be arranged in the same layer as the storage layer, for example, the transistor TA1 is used to control whether the first bit line L1_BL1 of the storage layer L1 is connected to the first input terminal SABL of the sense amplifier 40, and the transistor TA1 may be implemented in the same layer as the storage layer L1 using a back end process.

[0125] In addition, the memory provided in the embodiment of the present application may be an open-bitline structure. Fig.16 and Fig.18 In this case, the first bit line and the second bit line connected to the sense amplifier 40 may be located in the same storage layer, but from two different storage arrays, or the first bit line and the second bit line may be located in the same storage array, but in different storage layers; or the memory provided in the embodiment of the present application may also be a folded bit line structure, which can be combined with the aforementioned example. Fig.14 The first bit line and the second bit line connected to the sense amplifier 40 may be located in the same storage layer and in the same storage array.

[0126] Fig. 22 A schematic diagram of another memory provided by an embodiment of the present application is shown, wherein the sensitive amplifier 40 includes a first input terminal SABL, a second input terminal SA / BL, a sensitive amplifier circuit 41, a first power supply terminal SAN and a second power supply terminal SAP, and the sensitive amplifier circuit 41 includes four transistors: a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4, wherein the first input terminal SABL is connected to the output terminal S1_OUT of the first selection circuit S1, and the second input terminal SA / BL is connected to the output terminal S2_OUT of the second selection circuit S2.

[0127] A first end of the first transistor T1 is connected to the first input end SABL, a first end of the second transistor T2 is connected to the second input end SA / BL, a first power supply end SAN, a second end of the first transistor T1 and a second end of the second transistor T2 are coupled and connected, a gate of the first transistor T1 is connected to the second input end SA / BL, and a gate of the second transistor T2 is connected to the first input end SABL.

[0128] A first end of the third transistor T3 is connected to the first input end SABL, a first end of the fourth transistor T4 is connected to the second input end SA / BL, a second power supply end SAP, a second end of the third transistor T3 and a second end of the fourth transistor T4 are coupled and connected, a gate of the third transistor T3 is connected to the second input end SA / BL, and a gate of the fourth transistor T4 is connected to the first input end SABL.

[0129] The first transistor T1 and the second transistor T2 are NMOS transistors, and the third transistor T3 and the fourth transistor T4 are PMOS transistors. The first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are usually thin-gate devices, which are sensitive to voltage changes and can sensitively sense voltage differences. The first transistor T1 and the third transistor T3 can form a first inverter, the second transistor T2 and the fourth transistor T4 can form a second inverter, and the first inverter and the second inverter are connected end to end, so that the voltage of the first input terminal SABL (or the first bit line) and the second input terminal SA / BL (or the second bit line) can be pulled up or pulled down to two different states, for example, the voltage of the first bit line is pulled up to the voltage representing logic 1 connected to the second power supply terminal SAP, and the voltage of the second bit line is pulled down to the voltage representing logic 0 connected to the first power supply terminal SAN; or the voltage of the first bit line is pulled down and the voltage of the second bit line is pulled up.

[0130] The sense amplifier 40 further includes a voltage-equalizing transistor Teq and a pre-charging circuit 422. The first end of the voltage-equalizing transistor Teq is connected to the first input end SABL, and the second end of the voltage-equalizing transistor Teq is connected to the second input end SA / BL. The gate of the voltage-equalizing transistor Teq is used to receive an equalization (EQ) signal. When the equalization signal is enabled, the voltage-equalizing transistor Teq is turned on to turn on the first input end SABL and the second input end SA / BL of the sense amplifier 40, or it can be considered that the first bit line connected to the first input end SABL and the second bit line connected to the second input end SA / BL are turned on, so that the voltages of the two bits reach the same state.

[0131] The pre-charging circuit 422 includes a first charging transistor Tc1 and a second charging transistor Tc2, wherein the first end of the first charging transistor Tc1 is connected to the first input end SABL, the second end of the first charging transistor Tc1 is connected to the reference voltage end, and the gate of the first charging transistor Tc1 is used to receive the average signal; the first end of the second charging transistor Tc2 is connected to the second input end SA / BL, the second end of the second charging transistor Tc2 is connected to the reference voltage end, and the gate of the second charging transistor Tc2 is used to receive the above-mentioned average signal.

[0132] In the embodiment of the present application, the gate of the voltage-equalizing transistor Teq, the gate of the first charging transistor Tc1, and the gate of the second charging transistor Tc2 are used to receive the same average signal. When the average signal is enabled, the voltage-equalizing transistor Teq is turned on, and the first input terminal SABL and the second input terminal SA / BL of the sensitive amplifier 40 are turned on, and the first charging transistor Tc1 is turned on to charge the first input terminal SABL to the voltage of the reference voltage terminal (reference voltage Vref), and the second charging transistor Tc2 is turned on to charge the second input terminal SA / BL to the reference voltage. In this way, the first input terminal SABL and the second input terminal SA / BL of the sensitive amplifier 40 can be charged to the reference voltage, or it can be considered that the first bit line connected to the first input terminal SABL and the second bit line connected to the second input terminal SA / BL are charged to the reference voltage.

[0133] Since the first input terminal SABL of the sensitive amplifier 40 is connected to the first bit line, and the second input terminal SA / BL of the sensitive amplifier 40 is connected to the second bit line, under the joint action of the voltage equalizing transistor Teq and the pre-charging circuit 422, the first bit line and the second bit line are pre-charged to the same reference voltage. In this way, when reading the data of the storage cell on the first bit line or the second bit line, for example, taking the reading of the data of the storage cell on the first bit line as an example, the charge sharing between the storage cell and the first bit line will cause the voltage on the first bit line to increase or decrease based on the reference voltage, while the second bit line is used as a reference, is charged to the reference voltage and the voltage does not change. Therefore, a voltage difference appears between the first bit line and the second bit line, and the sensitive amplifier circuit 41 can amplify this voltage difference to read out the data.

[0134] Fig.23 The access timing diagram of the memory provided by the embodiment of the present application is shown to access Fig. 22 Take the memory cell connected to the intersection of the word line L1_L_WL1 and the bit line L1_BL1 in the memory layer L1 of the left memory array as an example.

[0135] In the preparation stage, the EQ signal is enabled, and the first bit line L1_BL1 of the storage layer L1 and the second bit line L1_BL2 of the storage layer L2 are charged to Vref. After the pre-charging is completed, the EQ signal is pulled low, and the pre-charging circuit 422 stops working. Since the data of the storage band unit located on the first bit line L1_BL1 of the storage layer L1 is read, the second selection control signal SEL_L2 corresponding to the unselected first bit line L2_BL1 is pulled low after the pre-charging is completed, and the first selection control signal SEL_L1 corresponding to the selected first bit line L1_BL1 remains in a normally open state.

[0136] In the active (ACT) phase, the word line L1_L_WL1 of the selected memory cell is turned on, the corresponding access transistor is turned on, and the positive charge stored in the storage capacitor (assuming that the memory cell stores logic "1") will flow to the first bit line L1_BL1 connected to it, and then the voltage of the first bit line L1_BL1 will be pulled up to Vref+; at this time, the first power supply terminal SAN of the sense amplifier 40 will be set to the voltage of logic "0", that is, 0 volts; the second power supply terminal SAP will be set to the voltage of logic "1", that is, VCC; the first power supply terminal SAN and the second power supply terminal SAP pull the second bit line L1_BL2 and the first bit line L1_BL1 to the voltage of logic "0" and the voltage of logic "1" respectively, and the voltages of the first bit line L1_BL1 and the second bit line L1_BL2 both enter a stable state.

[0137] In the read / write phase, the voltage of the first bit line L1_BL1 is transmitted to the input / output circuit; at this time, the first bit line L1_BL1 is at a stable logic "1" voltage VCC, which will charge the storage capacitor. After a specific period of time, the charge of the storage capacitor can be restored to the state before the read operation, completing the write-back, and the first power supply terminal SAN and the second power supply terminal SAP also return to the voltage value of the initial stage. Finally, the pre-charge phase is entered, the word line L1_L_WL1 is closed, and the voltages of the first bit line L1_BL1 and the second bit line L1_BL2 are pulled to Vref as the EQ signal is pulled high. At the same time, the second selection control signal SEL_L2 is also pulled high, so that the unselected bit lines are also charged to Vref, waiting for the arrival of the next read / write command.

[0138] In the embodiment of the present application, the first bit line connected to the first input terminal SABL and the second bit line connected to the second input terminal SA / BL of the sense amplifier 40 are located in the same storage layer. For example, the first bit line L1_BL1 and the second bit line L1_BL2 are located in the same storage layer, and the first bit line L2_BL1 and the second bit line L2_BL2 are located in the same storage layer. In combination with the above examples, it can be seen that the first selection circuit S1 and the second selection circuit S2 connect the first bit line and the second bit line of a selected storage layer to the sense amplifier 40 according to the selection control signal, while the first bit line and the second bit line of the unselected storage layer are not connected to the sense amplifier 40, and there is no voltage on the first bit line and the second bit line when they are not selected, and a floating state occurs.

[0139] Exemplarily, in order to avoid the floating state of the unselected first bit line and the second bit line, the sense amplifier 40 may include a plurality of pre-charging circuits 422, the number of which matches the number of storage layers, and the plurality of pre-charging circuits 422 correspond one-to-one to the plurality of storage layers, so as to charge the first bit line and the second bit line of the storage layer corresponding to the pre-charging circuit 422 to a reference voltage. In this way, regardless of whether the first bit line and the second bit line of the storage layer are selected or whether they are turned on by the sense amplifier, the first bit line and the second bit line of the storage layer can be charged to the reference voltage by the pre-charging circuit 422 to avoid the floating state.

[0140] Exemplarily, the sense amplifier 40 may include a plurality of pre-charging circuits 422, the number of pre-charging circuits 422 matches the number of storage layers, and the plurality of pre-charging circuits 422 correspond one-to-one to the plurality of storage layers. The pre-charging circuit 422 includes a first charging transistor Tc1 and a second charging transistor Tc2, the first end of the first charging transistor Tc1 is connected to the first bit line of the storage layer corresponding to the pre-charging circuit 422, the second end of the first charging transistor Tc1 is connected to the reference voltage end for accessing the reference voltage Vref, the first end of the second charging transistor Tc2 is connected to the second bit line of the storage layer corresponding to the pre-charging circuit 422, the second end of the second charging transistor Tc2 is connected to the reference voltage end for accessing the reference voltage Vref, and since the number of storage layers is multiple, the corresponding number of pre-charging circuits 422 is multiple, and the pre-charging circuits 422 corresponding to different storage layers can be connected to the pre-charging signals corresponding to different storage layers (for example, the first pre-charging signal L1_EQ, the second pre-charging signal L2_EQ) to charge the first bit line and the second bit line of the storage layer to the reference voltage to avoid the floating state of the unselected first bit line and the second bit line.

[0141] like Fig.24As shown, the sensitive amplifier 40 includes a voltage-equalizing transistor Teq, a first pre-charging circuit 422_L1 and a second pre-charging circuit 422_L2. The first end of the voltage-equalizing transistor Teq is connected to the first input end SABL of the sensitive amplifier, the second end of the voltage-equalizing transistor Teq is connected to the second input end SA / BL of the sensitive amplifier, and the gate of the voltage-equalizing transistor Teq is used to access the EQ signal.

[0142] The first precharge circuit 422_L1 corresponds to the memory layer L1 and is used to charge the first bit line L1_BL1 and the second bit line L1_BL2 of the memory layer L1. The first pre-charging circuit 422_L1 includes a first charging transistor L1_Tc1 and a second charging transistor L1_Tc2, wherein a first end of the first charging transistor L1_Tc1 is connected to a first bit line L1_BL1 of a storage layer L1, a second end of the first charging transistor L1_Tc1 is connected to a reference voltage end, and is used to access a reference voltage Vref, a first end of the second charging transistor L1_Tc2 is connected to a second bit line L1_BL2 of a storage layer L1, a second end of the second charging transistor L1_Tc2 is connected to a reference voltage end, and is used to access a reference voltage Vref, and gates of the first charging transistor L1_Tc1 and the second charging transistor L1_Tc2 are used to access a first pre-charging signal L1_EQ, and when the first pre-charging signal L1_EQ is enabled, the first charging transistor L1_Tc1 and the second charging transistor L1_Tc2 charge the first bit line L1_BL1 and the second bit line L1_BL2 of the storage layer L1 to the reference voltage.

[0143] The second pre-charging circuit 422_L2 corresponds to the storage layer L2 and is used to charge the first bit line L2_BL1 and the second bit line L2_BL2 of the storage layer L2. The second pre-charging circuit 422_L2 includes a first charging transistor L2_Tc1 and a second charging transistor L2_Tc2, wherein a first end of the first charging transistor L2_Tc1 is connected to a first bit line L2_BL1 of a storage layer L2, a second end of the first charging transistor L2_Tc1 is connected to a reference voltage end, and is used to access a reference voltage Vref, a first end of the second charging transistor L2_Tc2 is connected to a second bit line L2_BL2 of a storage layer L2, a second end of the second charging transistor L2_Tc2 is connected to a reference voltage end, and is used to access a reference voltage Vref, gates of the first charging transistor L2_Tc1 and the second charging transistor L2_Tc2 are used to access a second pre-charging signal L2_EQ, and when the second pre-charging signal L2_EQ is enabled, the first charging transistor L2_Tc1 and the second charging transistor L2_Tc2 charge the first bit line L2_BL1 and the second bit line L2_BL2 of the storage layer L2 to the reference voltage Vref.

[0144] Since the first pre-charging circuit 422_L1 and the second pre-charging circuit 422_L2 correspond to a storage layer respectively, and the first pre-charging circuit 422_L1 and the second pre-charging circuit 422_L2 are respectively connected to different pre-charging signals, the first pre-charging circuit 422_L1 and the second pre-charging circuit 422_L2 can respectively charge the first bit line and the second bit line of the corresponding storage layer to avoid the first bit line and the second bit line of the storage layer being suspended when the storage layer is not selected.

[0145] Exemplarily, the first charging transistor and the second charging transistor in the above-mentioned pre-charging circuit 422 can be implemented using N-type or P-type transistors in a traditional CMOS circuit and placed in the front-end, or they can be implemented using transistors based on oxide semiconductors. In this case, the first charging transistor and the second charging transistor corresponding to each storage layer can be placed on the same layer as the storage layer.

[0146] Fig.25 The access timing diagram of the memory provided by the embodiment of the present application is shown, taking the access to the memory cell at the intersection of the word line L1_L_WL1 and the bit line L1_BL1 in the memory layer L1 connected to the left memory array as an example. Fig.25 As shown, in the preparation stage, the first precharge signal L1_EQ is at a high level, and the EQ signal is also at a high level. The first bit line L1_BL1 and the second bit line L1_BL2 of the storage layer L1 are precharged to the reference voltage Vref by the first precharge circuit 422_L1. After the precharge is completed, the EQ signal and the first precharge signal L1_EQ corresponding to the selected storage layer L1 are pulled low, so that the corresponding voltage-equalizing transistor Teq and the first precharge circuit 422_L1 stop working; the unselected storage layer, for example, the second precharge signal L2_EQ corresponding to the storage layer L2 maintains a high level unchanged, so that the first bit line L2_BL1 and the second bit line L2_BL2 of the unselected storage layer L2 always maintain a state of being charged to the reference voltage. At the same time, since the data of the storage unit on the storage layer L1 is read, the second selection control signal SEL_L2 corresponding to the unselected storage layer L2 is turned off after the precharge is completed, and the first selection control signal SEL_L1 corresponding to the selected storage layer L1 remains normally open.

[0147] The operations in the activation phase and the read / write phase are the same as those in the aforementioned example. In the activation phase, the word line L1_L_WL1 of the selected memory cell is turned on, the corresponding access transistor is turned on, and the charge stored in the storage capacitor (assuming that the memory cell stores logic "1") flows to the first bit line L1_BL1 connected thereto, and then the voltage of the first bit line L1_BL1 is pulled up to Vref+; at this time, the first power supply terminal SAN of the sense amplifier is set to a voltage of logic "0", i.e., 0 volts, and the second power supply terminal SAP is set to a voltage of logic "1", i.e., VCC; the first power supply terminal SAN and the second power supply terminal SAP pull the second bit line L1_BL2 and the first bit line L1_BL1 to the voltage of logic "0" and the voltage of logic "1", respectively, and the voltages of the first bit line L1_BL1 and the second bit line L1_BL2 enter a stable state.

[0148] In the read / write stage, the voltage of the first bit line L1_BL1 is transmitted to the input / output circuit; at this time, the first bit line L1_BL1 is at a stable logic "1" voltage VCC, which will charge the storage capacitor. After a specific period of time, the charge of the storage capacitor can be restored to the state before the read operation, completing the write-back, and the first power supply terminal SAN and the second power supply terminal SAP also return to the voltage value of the initial stage.

[0149] Finally, the pre-charging stage is entered, the word line L1_L_WL1 is closed, and the voltages of the first bit line L1_BL1 and the second bit line L1_BL2 are charged to the reference voltage Vref as the EQ signal and the first pre-charging signal L1_EQ are pulled high. At the same time, the second selection control signal SEL_L2 is also pulled high, so that the first bit line L2_BL1 and the second bit line L2_BL2 of the unselected storage layer L2 are also charged to the reference voltage Vref, waiting for the arrival of the next read and write command.

[0150] In the embodiment of the present application, the first bit line connected to the first input terminal SABL and the second bit line connected to the second input terminal SA / BL of the sense amplifier 40 are located in the same storage layer, for example, the first bit line L1_BL1 and the second bit line L1_BL2 are located in the same storage layer, and the first bit line L2_BL1 and the second bit line L2_BL2 are located in the same storage layer; in some other possible implementations, the first bit line connected to the first input terminal SABL and the second bit line connected to the second input terminal SA / BL of the sense amplifier 40 may be located in different storage layers. For example, the multiple first bit lines connected to the first selection circuit S1 are respectively located in the storage layers L1, L2, and L3; the multiple second bit lines connected to the second selection circuit S2 are respectively located in the storage layers L4, L5, and L6, etc.

[0151] The structure of the sensitive amplifier circuit in the above example is a common four-transistor structure. As the process node evolves, the device size continues to shrink. The threshold voltage (Vt) drift of the transistor in the sensitive amplifier introduced by the process deviation during the manufacturing process has become the main reason for the amplifier reading failure. For example, please refer to Fig.12 Generally speaking, in the sensing stage, under the action of the voltage difference between the first bit line BL1 and the second bit line BL2, the second transistor T2 is more conductive than the first transistor T1. Then, under the action of the signal of the first power supply terminal SAN, the voltage of the second input terminal SA / BL will be pulled lower by the voltage of the first power supply terminal SAN through the second transistor T2 on the basis of Vref; but if the threshold voltage drift of the second transistor T2 causes the second transistor T2 to be more difficult to turn on than the first transistor T1, if the voltage difference between the first bit line BL1 and the second bit line BL2 is less than the threshold voltage drift of the second transistor T2, then even under the action of the voltage difference between the first bit line BL1 and the second bit line BL2, the second transistor T2 is still more difficult to turn on than the first transistor T1, which will cause an error in the sensing stage and fail to read data correctly. The reason for this error is that after the threshold voltage drift of the first transistor T1 and the second transistor T2, the threshold voltages of the two are different. This phenomenon is usually called Vt drift.

[0152] Vt drift may cause the sense amplifier to be unable to correctly sense and read data. In order to compensate for Vt drift, the embodiment of the present application further provides another memory, which adopts a sense amplifier structure different from that in the aforementioned example.

[0153] The memory provided in the embodiment of the present application also includes a stacked storage layer, a first gating circuit S1, a second gating circuit S2, and a sense amplifier 40, wherein the stacked storage layer, the first gating circuit, the second gating circuit, and other structures are basically the same as those in the above example, and the embodiment of the present application will not be described in detail. For example, refer to Fig.26 The sensitive amplifier 40 includes a first input terminal SABL, a second input terminal SA / BL, a sensitive amplifier circuit, a first power supply terminal SAN and a second power supply terminal SAP. The sensitive amplifier circuit includes four transistors: a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4, wherein the first input terminal SABL is connected to the output terminal of the first selection circuit (not shown in the figure), and the second input terminal SA / BL is connected to the output terminal of the second selection circuit (not shown in the figure).

[0154] The first end of the first transistor T1 is connected to the first end of the third transistor T3, the first end of the second transistor T2 is connected to the first end of the fourth transistor T4, the second end of the first transistor T1, the second end of the second transistor T2 and the first power supply terminal SAN are connected; the second end of the third transistor T3 and the second end of the fourth transistor T4 are connected to the second power supply terminal SAP, the gate of the second transistor T2 and the gate of the fourth transistor T4 are connected to the first input terminal SABL; the gate of the first transistor T1 and the gate of the third transistor T3 are connected to the second input terminal SA / BL.

[0155] The sense amplifier 40 further includes a drift compensation circuit, which includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8, wherein a first end of the fifth transistor T5 is connected to a first end of the first transistor T1 and a first end of the third transistor T3, and a second end of the fifth transistor T5 is connected to a second input terminal SA / BL; a first end of the sixth transistor T6 is connected to a first end of the second transistor T2 and a first end of the fourth transistor T4, and a second end of the sixth transistor T6 is connected to a first input terminal SABL; a first end of the seventh transistor T7 is connected to a first end of the first transistor T1 and a first end of the third transistor T3, and a second end of the seventh transistor T7 is connected to a first input terminal SABL; a first end of the eighth transistor T8 is connected to a first end of the second transistor T2 and a first end of the fourth transistor T4. A second end of the eighth transistor T8 is connected to a second input terminal SA / BL. In an embodiment of the present application, the drift compensation circuit compensates the first transistor T1, the second transistor T2, and also compensates the third transistor T3, and the fourth transistor T4, wherein the first transistor T1, the second transistor T2 are NMOS tubes, and the third transistor T3, the fourth transistor T4 are PMOS tubes, so the drift compensation circuit here is called a P / N-driven drift compensation circuit. In some other possible implementations, the drift compensation circuit may also only compensate for the NMOS tube, which is called an N-driven drift compensation circuit; or the drift compensation circuit may only compensate for the PMOS tube, which is called a P-driven drift compensation circuit.

[0156] The embodiment of the present application is described by taking a P / N-driven drift compensation circuit as an example. The gates of the fifth transistor T5 and the sixth transistor T6 are used to access the first drift compensation control signal VTS1, and the gates of the seventh transistor T7 and the eighth transistor T8 are used to access the second drift compensation control signal VTS2. When the first drift compensation control signal VTS1 enables the fifth transistor T5 and the sixth transistor T6 to be turned on, and the second drift compensation control signal VTS2 enables the seventh transistor T7 and the eighth transistor T8 to be turned on at the same time, the first input terminal SABL and the second input terminal SA / BL of the sensitive amplifier 40 are connected together through the turned-on fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8.

[0157] The sense amplifier 40 further includes a charging transistor Tc, a first end of which is connected to a reference power supply end for receiving a reference voltage Vref, a second end of which is connected to a first input end SABL of the sense amplifier 40, and a gate of which is used for receiving a pre-charge control signal (PCH).

[0158] When the first drift compensation control signal VTS1 enables the fifth transistor T5 and the sixth transistor T6 to be turned on, and the second drift compensation control signal VTS2 enables the seventh transistor T7 and the eighth transistor T8 to be turned on at the same time, the first input terminal SABL and the second input terminal SA / BL of the sense amplifier 40 are connected together through the turned-on fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8. In this case, the charging transistor Tc can charge the first input terminal SABL (that is, the first bit line connected to the first input terminal SABL) and the second input terminal SA / BL (that is, the second bit line connected to the second input terminal SA / BL) at the same time.

[0159] Fig. 27 An access timing diagram of the memory provided by an embodiment of the present application is shown, taking access to a memory cell at the intersection of a word line L1_L_WL1 and a bit line L1_BL1 in a memory layer L1 connected to a left memory array as an example.

[0160] In the offset cancellation (OC) stage, the first drift compensation control signal VTS1 is activated, the second drift compensation control signal VTS2 is turned off, the fifth transistor T5 and the sixth transistor T6 are turned on, the seventh transistor T7 and the eighth transistor T8 are turned off, the first transistor T1 and the third transistor T3 form an inverter, and the second transistor T2 and the fourth transistor T4 form an inverter.

[0161] Since the fifth transistor T5 is in the on state, the input terminal and the output terminal of the inverter formed by the first transistor T1 and the third transistor T3 are short-circuited together, so that the compensation voltage of the threshold voltage of the inverter is temporarily stored in the short-circuited voltage, and the voltage value is provided to the second input terminal SA / BL of the sense amplifier 40, and this voltage is recorded as Vtright; similarly, the input terminal and the output terminal of the inverter formed by the second transistor T2 and the fourth transistor T4 are also short-circuited together, so that the compensation voltage of the threshold voltage of the inverter is temporarily stored in the short-circuited voltage, and the voltage value is provided to the first input terminal SABL of the sense amplifier 40, and this voltage is recorded as Vtleft.

[0162] Then the first drift compensation control signal VTS1 is turned off, and the second drift compensation control signal VTS2 is turned on, and the charge sharing (CHS) stage is entered. Since the voltage of the first input terminal SABL of the sense amplifier 40 is Vtleft, and the voltage of the second input terminal SA / BL of the sense amplifier 40 is Vtright, in the sensing stage, the first input terminal SABL and the second input terminal SA / BL start sensing from the Vtright and Vtleft voltages respectively, thereby eliminating the influence of the threshold voltage drift. At this time, the structure of the sense amplifier 40 provided in the embodiment of the present application is the same as the structure of the sense amplifier 40 in the aforementioned example, and thereafter the charge sharing stage, the read / write stage, and the pre-charge stage are the same as the activation stage, the read / write stage, and the pre-charge stage in the aforementioned embodiment.

[0163] The memory provided in the embodiment of the present application improves the storage density by stacking multiple storage layers. For multiple storage layers, a gating circuit is set so that the bit lines of the multiple storage layers can be connected to the sensitive amplifier 40 through the gating circuit. The bit lines of the multiple storage layers can share the sensitive amplifier 40, so that under the same device size, the winding pitch of the sensitive amplifier 40 can be kept the same as the winding pitch of the sensitive amplifier 40 of the two-dimensional memory, and the process difficulty will not be increased due to the reduction in the winding pitch of the sensitive amplifier 40. Since the number of the sensitive amplifiers 40 is reduced, the transistor size in the sensitive amplifier 40 can be appropriately relaxed to reduce the signal drift caused by the process difference.

[0164] In the above example, the solution provided in the present application is described by taking the memory as DRAM as an example, but it is not limited to this. The memory provided in the embodiment of the present application can also be a memory of other structures, such as a ferroelectric memory or other memory.

[0165] Based on the memory provided in the foregoing embodiments, an embodiment of the present application further provides a storage device, including a controller and a memory, wherein the memory is connected to the controller for controlling the reading and writing of the memory.

[0166] Based on the storage device provided in the above embodiment, the embodiment of the present application further provides an electronic device, including a circuit board and a storage device connected to the circuit board. For example, the electronic device can be Figure 1 The electronic device shown.

[0167] Those skilled in the art should be aware that in one or more of the above examples, the functions described in this application can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of a computer program from one place to another. Storage media can be any available media that a general or special-purpose computer can access.

[0168] Finally, it should be noted that the above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A memory, characterized in that: The memory comprises a substrate and a plurality of storage layers stacked on the substrate in a direction perpendicular to the substrate, each of the storage layers comprises a first bit line, a second bit line and a plurality of storage cells distributed in a direction parallel to the substrate, and the first bit line and the second bit line are respectively connected to the plurality of storage cells; The memory further comprises a first gating circuit, a second gating circuit and a sense amplifier, wherein the sense amplifier comprises a first input terminal and a second input terminal; The first gating circuit comprises a selection end, an output end and a plurality of input ends, the plurality of input ends of the first gating circuit are connected to a plurality of the first bit lines in a one-to-one correspondence, the plurality of the first bit lines are respectively located in the plurality of storage layers, the output end of the first gating circuit is connected to the first input end of the sense amplifier, and the selection end of the first gating circuit is used to receive a first gating circuit selection control signal; The second selection circuit includes a selection end, an output end and multiple input ends. The multiple input ends of the second selection circuit are connected one-to-one with multiple second bit lines. The multiple second bit lines are respectively located in the multiple storage layers. The output end of the second selection circuit is connected to the second input end of the sensitive amplifier. The selection end of the second selection circuit is used to receive a second selection circuit selection control signal.

2. The memory according to claim 1, characterized in that: The first gating circuit and the second gating circuit each include a plurality of switches, each of the switches including a control end, a first end, and a second end; Each input end of the first gating circuit is connected to the output end of the first gating circuit through a switch, wherein the control end of the switch of the first gating circuit is connected to the selection end of the first gating circuit, the first end of the switch is connected to the input end of the first gating circuit, and the second end of the switch is connected to the output end of the first gating circuit; Each input end of the second gating circuit is connected to the output end of the second gating circuit through a switch, wherein the control end of the switch of the second gating circuit is connected to the selection end of the second gating circuit, the first end of the switch is connected to the input end of the second gating circuit, and the second end of the switch is connected to the output end of the second gating circuit.

3. The memory according to claim 2, characterized in that: The first gating circuit includes a first input terminal, a second input terminal, a first switch, a second switch, a first selection terminal and a second selection terminal; the second gating circuit includes a first input terminal, a second input terminal, a first switch, a second switch, a first selection terminal and a second selection terminal; A first end of the first switch of the first gating circuit is connected to the first input end of the first gating circuit, a second end of the first switch is connected to the output end of the first gating circuit, and a control end of the first switch is connected to the first selection end of the first gating circuit; A first end of the second switch of the first gating circuit is connected to the second input end of the first gating circuit, a second end of the second switch is connected to the output end of the first gating circuit, and a control end of the second switch is connected to the second selection end of the first gating circuit; A first end of the first switch of the second gating circuit is connected to the first input end of the second gating circuit, a second end of the first switch is connected to the output end of the second gating circuit, and a control end of the first switch is connected to the first selection end of the second gating circuit; The first end of the second switch of the second gating circuit is connected to the second input end of the second gating circuit, the second end of the second switch is connected to the output end of the second gating circuit, and the control end of the second switch is connected to the second selection end of the second gating circuit.

4. The memory according to claim 3, characterized in that: The first selection end of the first gating circuit is used to receive a first selection control signal of the first gating circuit, and the first selection end of the second gating circuit is used to receive a first selection control signal of the second gating circuit, and the first selection control signal of the first gating circuit and the first selection control signal of the second gating circuit are the same selection control signal; The second selection end of the first selection circuit is used to receive the second selection control signal of the first selection circuit, and the second selection end of the second selection circuit is used to receive the second selection control signal of the second selection circuit. The second selection control signal of the first selection circuit and the second selection control signal of the second selection circuit are the same selection control signal.

5. The memory according to any one of claims 1 to 4, characterized in that: The sensitive amplifier further comprises a first power supply terminal, a second power supply terminal and a sensitive amplifier circuit, wherein the sensitive amplifier circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor; The first end of the first transistor is connected to the first input end, the first end of the second transistor is connected to the second input end, the second end of the first transistor and the second end of the second transistor are connected to the first power supply end, the gate of the first transistor is connected to the second input end, and the gate of the second transistor is connected to the first input end; The first end of the third transistor is connected to the first input end, the first end of the fourth transistor is connected to the second input end, the second end of the third transistor and the second end of the fourth transistor are connected to the second power supply end, the gate of the third transistor is connected to the second input end, and the gate of the fourth transistor is connected to the first input end.

6. The memory according to claim 5, characterized in that: The first transistor and the second transistor are N-type metal oxide semiconductor field effect transistors, and the third transistor and the fourth transistor are P-type metal oxide semiconductor field effect transistors.

7. The memory according to claim 5 or 6, characterized in that: The sensitive amplifier also includes a voltage-equalizing transistor and a pre-charging circuit; The first end of the voltage balancing transistor is connected to the first input end of the sensitive amplifier, and the second end of the voltage balancing transistor is connected to the second input end of the sensitive amplifier circuit; The pre-charging circuit comprises a first charging transistor and a second charging transistor, wherein a first end of the first charging transistor is connected to the first input end of the sense amplifier, a first end of the second charging transistor is connected to the second input end of the sense amplifier, and a second end of the first charging transistor and a second end of the second charging transistor are connected to a reference voltage end; The gate of the voltage equalizing transistor, the gate of the first charging transistor and the gate of the second charging transistor are used to receive an average control signal, and the first charging transistor and the second charging transistor are used to pre-charge the first input terminal and the second input terminal of the sensitive amplifier to the voltage of the reference voltage terminal in response to the average control signal.

8. The memory according to claim 7, characterized in that: The voltage balancing transistor and the pre-charging circuit are implemented through a front-end process.

9. The memory according to claim 5 or 6, characterized in that: The sense amplifier further comprises a voltage balancing transistor and a plurality of pre-charging circuits; The first end of the voltage balancing transistor is connected to the first input end of the sensitive amplifier, the second end of the voltage balancing transistor is connected to the second input end of the sensitive amplifier circuit, and the gate of the voltage balancing transistor is used to receive an average control signal; The multiple pre-charging circuits correspond one-to-one to the multiple storage layers, wherein the pre-charging circuit includes a first charging transistor and a second charging transistor, the first end of the first charging transistor is connected to the first bit line of the storage layer corresponding to the pre-charging circuit, the first end of the second charging transistor is connected to the second bit line of the storage layer corresponding to the pre-charging circuit, the second end of the first charging transistor and the second end of the second charging transistor are connected to a reference voltage terminal, and the gate of the first charging transistor and the gate of the second charging transistor are used to pre-charge the first bit line and the second bit line of the storage layer to the voltage of the reference voltage terminal in response to a pre-charging control signal corresponding to the storage layer.

10. The memory according to claim 9, characterized in that: The voltage balancing transistor is implemented through a front-end process, and the pre-charging circuit is implemented through a back-end process, or both the voltage balancing transistor and the pre-charging circuit are implemented through a front-end process.

11. The memory according to any one of claims 1 to 4, characterized in that: The sensitive amplifier further comprises a first power supply terminal, a second power supply terminal, a sensitive amplifier circuit and a drift compensation circuit, and the sensitive amplifier circuit comprises a first transistor, a second transistor, a third transistor and a fourth transistor; The first end of the first transistor is connected to the first end of the third transistor, the first end of the second transistor is connected to the first end of the fourth transistor, the second end of the first transistor and the second end of the second transistor are connected to the first power supply terminal; the second end of the third transistor and the second end of the fourth transistor are connected to the second power supply terminal, the gate of the second transistor and the gate of the fourth transistor are connected to the first input terminal of the sense amplifier; the gate of the first transistor and the gate of the third transistor are connected to the second input terminal of the sense amplifier; The drift compensation circuit includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; a first end of the fifth transistor is connected to a first end of the first transistor and a first end of the third transistor, and a second end of the fifth transistor is connected to the second input end of the sense amplifier; a first end of the sixth transistor is connected to a first end of the second transistor and a first end of the fourth transistor, and a second end of the sixth transistor is connected to the first input end of the sense amplifier, and a gate of the fifth transistor and a gate of the sixth transistor are used to receive a first drift compensation control signal; The first end of the seventh transistor is connected to the first end of the first transistor and the first end of the third transistor, and the second end of the seventh transistor is connected to the first input end of the sensitive amplifier; the first end of the eighth transistor is connected to the first end of the second transistor and the first end of the fourth transistor, and the second end of the eighth transistor is connected to the second input end of the sensitive amplifier, and the gate of the seventh transistor and the gate of the eighth transistor are used to receive a second drift compensation control signal.

12. The memory according to claim 11, characterized in that: The sensitive amplifier also includes a charging transistor, a first end of the charging transistor is connected to a reference power supply end, a second end of the charging transistor is connected to a first input end of the sensitive amplifier, and a gate of the charging transistor is used to receive a pre-charging control signal, and the sensitive amplifier is charged in response to the pre-charging control signal.

13. The memory according to claim 11 or 12, characterized in that: The first transistor and the second transistor are N-type metal oxide semiconductor field effect transistors, and the third transistor and the fourth transistor are P-type metal oxide semiconductor field effect transistors.

14. The memory according to any one of claims 1 to 13, characterized in that: The memory has an open bit line structure, and the first bit line and the second bit line are located in different memory arrays.

15. The memory according to any one of claims 1 to 13, characterized in that: The memory has a folded bit line structure, and the first bit line and the second bit line are located in the same memory array.

16. A storage device, characterized in that: The storage device comprises a controller and a memory according to any one of claims 1 to 15, wherein the controller is connected to the memory.

17. An electronic device, characterized in that: It comprises a circuit board and a storage device connected to the circuit board, wherein the storage device is the storage device as claimed in claim 16.

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