Memory operation methods, memory and storage system

Abstract

This disclosure provides a memory operation method, a memory, and a memory system, relating to the field of memory technology. The method includes: applying a bias voltage to the bottom select line of a second memory block, including a memory block adjacent to a first memory block, during a first time period to turn on the bottom select transistor of the second memory block; then performing a first erase operation during a second time period after the first time period. This includes providing an erase operating voltage to the source line of the first memory block and setting the bottom select line of the second memory block to a floating state. This reduces the voltage drop caused by the parasitic capacitance of the common source array wall as the word line of the second memory block rises with channel voltage coupling, thereby allowing it to recover to a voltage closer to that before the voltage boost during the discharge phase. This reduces the voltage difference between the word line and the channel of the second memory block after multiple erase cycles, and reduces the loss of the memory's read window margin or the sum of voltage distribution intervals during the erase process.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and more specifically, to a memory operation method, a memory, and a storage system. Background Technology

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations can be performed on flash memory, such as reading, programming (writing), and erasing, to change the threshold voltage of each memory cell to a desired level. For NAND flash memory, erase operations can be performed at the block level, programming operations at the page level, and read operations at the page level.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a memory operation method, a memory, and a storage system.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, a memory operation method is provided, the memory including a plurality of memory blocks, each memory block including a bottom select transistor coupled to a bottom select line, the plurality of memory blocks including a first memory block and a second memory block, the method comprising: applying a bias voltage to the bottom select line of the second memory block during a first time period to turn on the bottom select transistor of the second memory block; performing a first erase operation during a second time period, the second time period being after the first time period, wherein performing the first erase operation includes: providing an erase operating voltage to the source line of the first memory block; and setting the bottom select line of the second memory block to a floating state.

[0007] According to one embodiment of this disclosure, performing the first erase operation further includes: applying an erase control voltage to the word line of the first memory block, wherein the erase operating voltage is greater than the erase control voltage.

[0008] According to one embodiment of this disclosure, the method further includes: applying a first voltage to the source line during a third time period, the third time period being after the second time period, the first voltage being less than the erase working voltage.

[0009] According to one embodiment of this disclosure, setting the bottom select line of the second memory block to a floating state includes: setting the bottom select line of the second memory block to a floating state so that the voltage of the bottom select line of the second memory block rises from the bias voltage along the source line to a second voltage, wherein the second voltage is not greater than the sum of the erase working voltage and the bias voltage.

[0010] According to one embodiment of this disclosure, the method further includes: maintaining the bottom select line of the second memory block in a floating state during a third time period, so that the voltage of the bottom select line of the second memory block drops from the second voltage to the bias voltage, so as to continue to keep the bottom select transistor of the second memory block on, wherein the third time period is after the second time period.

[0011] According to one embodiment of this disclosure, the sum of the erasure operating voltage and the bias voltage is less than a preset voltage threshold.

[0012] According to one embodiment of this disclosure, when performing the first erase operation, the method further includes: setting the word lines of the second storage block to a floating state; the method further includes: maintaining the word lines of the second storage block in a floating state for a third time period, the third time period being after the second time period.

[0013] According to one embodiment of this disclosure, the second storage block includes a third storage block, which is adjacent to the first storage block.

[0014] According to one embodiment of this disclosure, the method further includes: applying the bias voltage to the bottom select line of the second memory block during a fourth time period, the fourth time period being after the third time period; performing a second erase operation during a fifth time period, the fifth time period being after the fourth time period, wherein performing the second erase operation includes: providing the erase operating voltage to the source line of the first memory block; and setting the bottom select line of the second memory block to a floating state.

[0015] According to one embodiment of this disclosure, the bias voltage ranges from 1V to 7V.

[0016] According to one embodiment of the present disclosure, the memory includes a plurality of planes, the plurality of planes including a first plane, the first plane being a plane selected from the plurality of planes, and the plurality of memory blocks being on the first plane.

[0017] According to another aspect of this disclosure, a memory is provided, comprising: a memory cell array including a plurality of memory blocks, each memory block including a bottom select transistor coupled to a bottom select line, the plurality of memory blocks including a first memory block and a second memory block; and peripheral circuitry coupled to the memory cell array, configured to: apply a bias voltage to the bottom select line of the second memory block during a first time period to turn on the bottom select transistor of the second memory block; and perform a first erase operation during a second time period, the second time period being after the first time period, wherein performing the first erase operation includes: providing an erase operating voltage to the source line of the first memory block; and setting the bottom select line of the second memory block to a floating state.

[0018] According to one embodiment of this disclosure, the peripheral circuit includes a control circuit, a voltage generator, a bottom select line driver, and a source line driver, wherein: the voltage generator is used to generate the bias voltage; the control circuit is used to control the bottom select line driver to apply the bias voltage to the bottom select line of the second memory block during a first time period, so as to turn on the bottom select transistor of the second memory block; the voltage generator is also used to generate the erase working voltage; the control circuit is also used to control the source line driver to apply the erase working voltage to the source line of the first memory block during a second time period; the control circuit is also used to control the bottom select line driver to set the bottom select line of the second memory block to a floating state during the second time period.

[0019] According to one embodiment of this disclosure, the voltage generator is further configured to generate an erase control voltage, the erase operating voltage being greater than the erase control voltage; the peripheral circuitry further includes a word line driver; and the control circuitry is further configured to control the word line driver to apply the erase control voltage to the word lines of the first memory block during the second time period.

[0020] According to one embodiment of this disclosure, the voltage generator is further configured to generate a first voltage, the first voltage being less than the erase operating voltage; the control circuit is further configured to control the source line driver to apply the first voltage to the source line of the first memory block during a third time period, the third time period being after the second time period.

[0021] According to one embodiment of this disclosure, the control circuit is further configured to control the bottom select line driver to set the bottom select line of the second memory block to a floating state during the second time period, so that the voltage of the bottom select line of the second memory block rises from the bias voltage along the source line to a second voltage, the second voltage being no greater than the sum of the erase working voltage and the bias voltage.

[0022] According to one embodiment of this disclosure, the control circuit is further configured to control the bottom select line driver to keep the bottom select line of the second memory block in a floating state during a third time period, so that the voltage of the bottom select line of the second memory block drops from the second voltage to the bias voltage, so as to continue to keep the bottom select transistor of the second memory block on, wherein the third time period is after the second time period.

[0023] According to one embodiment of this disclosure, the sum of the erasure operating voltage and the bias voltage is less than a preset voltage threshold.

[0024] According to one embodiment of this disclosure, the control circuit is further configured to control the word line driver to set the word line of the second memory block to a floating state during the second time period; the control circuit is further configured to control the word line driver to keep the word line of the second memory block in a floating state during a third time period, the third time period being after the second time period.

[0025] According to one embodiment of this disclosure, the second storage block includes a third storage block, which is adjacent to the first storage block.

[0026] According to one embodiment of this disclosure, the peripheral circuit is further configured to: apply the bias voltage to the bottom select line of the second memory block during a fourth time period, the fourth time period being after the third time period; and perform a second erase operation during a fifth time period, the fifth time period being after the fourth time period, wherein performing the second erase operation includes: providing the erase operating voltage to the source line of the first memory block; and setting the bottom select line of the second memory block to a floating state.

[0027] According to one embodiment of this disclosure, the bias voltage ranges from 1V to 7V.

[0028] According to one embodiment of this disclosure, the storage cell array includes a plurality of planes, the plurality of planes including a first plane, the first plane being a plane selected from the plurality of planes, and the plurality of storage blocks being on the first plane.

[0029] According to another aspect of this disclosure, a storage system is provided, including a memory and a controller coupled to the memory, wherein: the memory includes a memory cell array and peripheral circuitry, the memory cell array includes a plurality of memory blocks, each memory block includes a bottom select transistor coupled to a bottom select line, the plurality of memory blocks include a first memory block and a second memory block, and the peripheral circuitry is coupled to the memory cell array; the controller is configured to control the peripheral circuitry to perform any of the methods described above.

[0030] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description

[0031] The above and other objects, features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0032] Figure 1 A schematic diagram of the structure of a non-volatile memory to which this disclosure can be applied is shown.

[0033] Figure 2 A schematic diagram of a memory cell array to which the NAND FLASH of this disclosure can be applied is shown.

[0034] Figure 3 A schematic diagram of a storage cell array comprising multiple storage blocks is shown, to which this disclosure can be applied.

[0035] Figure 4 It is based on Figure 3 The diagram shows the waveform of the first erase pulse in the relevant technology.

[0036] Figure 5 It is based on Figure 4 and Figure 3 The diagram shows the second erase pulse waveform in the relevant technology.

[0037] Figure 6 This is a flowchart illustrating a memory operation method according to an exemplary embodiment.

[0038] Figure 7 It shows Figure 6 The step S604 shown is a schematic diagram of the processing procedure in one embodiment.

[0039] Figure 8 according to Figure 6 This diagram illustrates the process of applying voltage to a selected memory block during the erase phase.

[0040] Figure 9 according to Figure 6 A schematic diagram of the process of applying voltage to unselected memory blocks during the erase phase is shown.

[0041] Figure 10 according to Figure 6 This diagram illustrates the operation process for an unselected memory block word line during the erase phase.

[0042] Figure 11 It is based on Figure 6 A flowchart of another memory data processing method is shown.

[0043] Figure 12It is based on Figures 6 to 11 The diagram shows a type of erase pulse waveform.

[0044] Figure 13 It is based on Figures 6 to 11 A block diagram of a memory structure is shown.

[0045] Figure 14 It is based on Figures 6 to 11 A schematic diagram of a memory system is shown. Detailed Implementation

[0046] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0047] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0048] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. The symbol " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0049] In this disclosure, unless otherwise expressly specified and limited, the term "connection" and similar terms should be interpreted broadly, for example, it can refer to an electrical connection or the ability to communicate with each other; it can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0050] Some memory systems can perform erase operations at the block level, meaning all memory cells in a selected block can be erased simultaneously. A single plane of a memory system can contain multiple blocks, with adjacent blocks sharing an Array Common Source (ACS) wall. The ACS wall typically serves to maintain chip stress. It can be treated with high resistance and low doping; for example, polysilicon can be lightly doped to form a near-insulating ACS wall. When the WL (wall gap) of adjacent blocks is coupled to the same ACS wall, the WL of two adjacent blocks and the high-resistivity, low-doped ACS wall can be considered equivalent to a capacitor, i.e., a parasitic capacitance. The WL of two adjacent blocks are like two plates, and the ACS wall is like the dielectric material between those plates. This parasitic capacitance couples to the WL voltage of the adjacent blocks on either side of it.

[0051] For example, during the erasure of a target memory block selected from multiple memory blocks on a plane, a low voltage is applied to the read window (WL) of the target memory block, while the WL of adjacent memory blocks is floating, and their voltages can be coupled with the channel boost potential. However, when there is a parasitic capacitance of a high-resistance, low-doped ACS wall between the adjacent memory blocks and the target memory block, the low voltage applied to the WL of the target memory block will be divided by the parasitic capacitance of the ACS wall, affecting the boost rate of the WL of the adjacent memory blocks. This results in a mismatch between the WL of the adjacent memory blocks and the channel boost, which creates a voltage difference after multiple erase cycles. This weakly erases the adjacent memory blocks, causing a shift in the threshold voltage of the memory cells in the adjacent memory blocks, thus reducing the read window margin or the edge sum (ESUM) of the memory.

[0052] Therefore, this disclosure provides a memory operation method, which involves applying a bias voltage to the bottom select line of a second memory block adjacent to a first memory block during a first time period to turn on the bottom select transistor of the second memory block, and then performing a first erase operation during a second time period after the first time period, including providing an erase operating voltage to the source line of the first memory block and setting the bottom select line of the second memory block to a floating state. During the discharge phase following the second time period, the bottom select line of the second memory block can be floated to the bias voltage, i.e., it remains in the on state. The gate-induced drain leakage (GIDL) potential generated in the channel due to the voltage division effect of the parasitic capacitance of the ACS wall during the boost phase can continue to discharge to the initial potential (e.g., Vss). The WL of the second memory block can then reduce the voltage division effect of the parasitic capacitance of the ACS wall as the channel voltage couples up. During the discharge phase, it can recover to a voltage closer to that before the boost phase. Therefore, there will be no voltage accumulation in the next erase cycle, which can reduce the voltage difference between the WL of the second memory block and the channel after multiple erase cycles, and reduce the loss of the memory read window margin or the total voltage distribution interval during the erase process.

[0053] Figure 1 A schematic diagram of the structure of a non-volatile memory to which this disclosure can be applied is shown. For example... Figure 1 As shown, the memory 10 may include a memory cell array 102 and peripheral circuitry 104 coupled to the memory cell array 102. The memory cell array 102 may be a NAND flash memory cell array, for example, Figure 2 A schematic diagram of a NAND flash memory cell array is shown. Peripheral circuitry 104 may include any suitable analog, digital, and mixed-signal circuitry for operating the memory cell array 102 by applying voltage and / or current signals to each target memory cell 10222 via bit lines (BL), WL, BSG lines, TSG lines, etc., and sensing voltage and / or current signals from each target memory cell 10222 (see reference). Figure 2 Peripheral circuitry 104 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 13 An exemplary peripheral circuit is shown.

[0054] Figure 2 A schematic diagram of a memory cell array to which the NAND FLASH of this disclosure can be applied is shown. For example... Figure 2As shown, in the memory cell array 102, the memory cells 10222 in the memory block 1020 are provided in the form of an array of NAND memory strings 1022, each NAND memory string 1022 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 1022 includes a plurality of memory cells 10222 that are series-coupled and vertically stacked. Each memory cell 10222 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 10222. Each memory cell 10222 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0055] In some embodiments, each memory cell 10222 may be a single-level cell (SLC) having two possible memory states and thus being able to store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range.

[0056] In some embodiments, each memory cell 10222 can be a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to that cell. A fourth nominal storage value can be used for the erase state.

[0057] like Figure 2As shown, each NAND memory string 1022 may include a bottom select transistor 10224 with a bottom select gate (BSG) at its source end and a top select transistor 10226 with a top select gate (TSG) at its drain end. The BSG and TSG can be configured to activate the selected NAND memory string 1022 (column of the array) during read and program operations. In some embodiments, the sources of NAND memory strings 1022 within the same memory block 1020 may be coupled via the same source line (SL), for example, a common source line. The SLs of adjacent memory blocks may be coupled together; in some embodiments, adjacent memory blocks BLK N and BLK N+1 may be coupled together.

[0058] In some embodiments, the TSG of each NAND memory string 1022 is coupled to a corresponding BL, and data can be read from or written to the BL via an output bus (not shown). In some embodiments, each NAND memory string 1022 is configured to be selected or deselected by applying a selection voltage (e.g., a threshold voltage above the transistor having the BSG) or a deselection voltage (e.g., 0V) to the corresponding BSG via one or more BSG lines.

[0059] like Figure 2 As shown, the NAND memory string 1022 can be organized into multiple memory blocks 1020, each of which can have a common source line SL. In some embodiments, each memory block 1020 is the basic data unit for erase operations, i.e., all memory cells 10222 on the same memory block 1020 are erased simultaneously. Within a memory block 1020, WL selects which row of memory cells 10222 is affected by read and program operations. In some embodiments, each WL is coupled to a page 1026 of memory cells 10222, which is the basic data unit for programming operations.

[0060] Figure 3 A schematic diagram of a storage cell array comprising multiple storage blocks is shown, to which this disclosure can be applied. The storage cell array may include multiple planes, and each plane may include multiple storage blocks. Figure 3 An illustrative plane is shown, hereinafter referred to as the first plane. When performing operations such as erasing on the memory cell array, one plane or multiple planes can be selected. In this embodiment of the disclosure, the first plane is used as an example selected from multiple planes for illustration.

[0061] like Figure 3As shown, the first plane includes multiple storage blocks BLK(Block) N, BLK N+1...BLK N+X (N and X are positive integers, X is greater than N). Storage blocks with adjacent indices such as BLK N, BLK N+1, etc., are adjacent storage blocks. The structure of each storage block can be referred to... Figure 2 The memory block 1020 is connected to the ACS wall 1023 via the WL of the adjacent memory block. In some embodiments, the ACS wall 1023 can be high-resistivity and low-doped, thus forming a parasitic capacitance with the WL of BLK N and the WL of BLK N+1 as the two plates (10232, 10236) and the ACS wall 1023 itself as the dielectric material 10234 between the plates 10232 and 10236.

[0062] In some embodiments, a high-voltage N-well (HVNW) 1024 may be formed in a substrate (not shown), with the source terminals of the NAND memory string 1022 in contact with the HVNW 1024. For example, an SL may be coupled to the HVNW 1024 to apply an erase working voltage (Verase) (e.g., a high positive voltage, which may be 20V or higher) to the SL via external circuitry during an erase operation, while the voltage is applied to the HVNW 1024 (i.e., the source terminal of the NAND memory string 1022). (Refer to...) Figure 3 Taking BLK N as the selected memory block (which may be referred to as the first memory block) as an example, in order to erase memory cell 10222 in the selected memory block BLK N, the source line SL of BLK N and the unselected memory blocks BLK N+1...BLK N+X on the same plane as BLK N can be coupled with a Verase bias. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any level with any suitable number of blocks or any suitable fraction of blocks.

[0063] Figure 4 It is based on Figure 3 The diagram shows the waveform of the first erase pulse in the relevant technology. (Refer to...) Figure 4In some embodiments, before the application of the first erase pulse at time t0, the BSG lines in BLK N+1…BLK N+X are connected to the common ground voltage (Vss), and the bottom select transistors 10224 with BSG in each NAND memory string 1022 are turned off. At time t0, the first erase pulse is applied, and Verase is applied to HVNW via SL, causing the source voltage of each NAND memory string 1022 in BLK N, BLK N+1…BLK N+X to rise from the initial voltage (e.g., the power supply voltage (Vss)) to Verase at time t1. At time t0, an erase control voltage (e.g., Vss) is applied to the WL of the selected memory block BLK N, causing the WL of BLK N to drop from the initial voltage (e.g., the system voltage (Vdd)) to the erase control voltage. At time t0, the bottom select transistor 10224 with BSG of each NAND memory string 1022 of the selected memory block BLK N receives voltage from the BSG line to generate GIDL current, which allows holes to flow through the semiconductor channel of each NAND memory string 1022 of the corresponding selected memory block BLK N, so that the threshold voltage of each memory cell 10222 of the selected memory block BLK N is shifted in a more negative direction, i.e., shifted to the erase state.

[0064] For unselected memory blocks BLK N+1…BLK N+X, at time t0, the BSG lines of these memory blocks are floating, causing the voltage on the BSG lines of BLK N+1…BLK N+X to rise with HVNW and reach Verase at time t1. Also at time t0, the WL of BLK N+1…BLK N+X is floating. During the BSG line voltage rise process between t0 and t1, the bottom select transistor 10224 of BLK N+1…BLK N+X is turned on, causing the channel potential of BLK N+1…BLK N+X to rise with HVNW, and the voltage of WL of BLK N+1…BLK N+X rises accordingly. Due to the voltage division effect of the parasitic capacitance between BLK N+1 and BLK N's WL, the voltage rise rate of BLK N+1's WL is slower than that of BLK N+X's WL. (Refer to...) Figure 4At time t1, the initial voltage (e.g., system voltage (Vdd)) on the WL of BLK N+X couples with the channel boost potential of BLK N+X to Verase+Vdd (or less than Verase+Vdd if a coupling coefficient exists), while the voltage increase on the WL of BLK N+1 is less than Verase+Vdd. The lower voltage on the WL of BLK N+1 generates a gate-induced drain leakage (GIDL) potential, causing the channel potential of BLK N+1 to rise, which in turn couples with the WL of BLK N+1, resulting in the voltage on the WL of BLK N+1 rising to near Verase+Vdd at time t2, after time t1. Erasure discharge begins at time t3. Due to the characteristics of the PN junction, the GIDL potential of the BLK N+1 channel prevents it from completely discharging to the initial potential Vss like the BLK N+X channel; instead, it discharges to Vgidl. Starting at time t3, WL of BLK N+1...BLK N+X is floated. However, due to its GIDL potential, WL of BLK N+1 cannot fall back to the system voltage Vdd under the effect of capacitive coupling, just like WL of BLK N+X. Instead, it drops to Vdd+Vgidl.

[0065] Figure 5 It is based on Figure 4 and Figure 3 The diagram shows the waveform of the second erase pulse in the related technology. The second erase pulse can be... Figure 4 The following erase pulse is shown after the first erase pulse. Figure 5 As shown, at time t0', the second erase pulse is applied, and the voltage applied to SL, the erase control voltage applied to WL of the selected memory block BLK N, and the floating of BSG and WL lines of the unselected memory blocks BLK N+1...BLK N+X are all the same as those of the first erase pulse.

[0066] Reference Figure 5For unselected memory blocks BLK N+1...BLK N+X, at time t0', the initial channel potential of BLK N+X is the same as at time t0, still Vss, while the initial channel potential of BLK N+1 is higher than at time t0, at Vgidl. At time t0', the initial voltage of WL of BLK N+X is the same as at time t0, still Vdd, while the initial voltage of WL of BLK N+1 is higher than at time t0, at Vdd+Vgidl. The WL of BLK N+X is almost unaffected and can still rise to Verase+Vdd at time t1' due to the coupling of the channel boost potential. Because the channel initial potential of BLK N+1 becomes higher, it no longer generates the same GIDL potential as WL of BLK N+1 at time t1'. Therefore, between time t1' and t2', the portion of WL of BLK N+1 that has increased due to coupling disappears or at least decreases, causing the voltage of WL of BLK N+1 to rise to a value lower than Verase+Vdd at time t2', for example, Verase+Vdd-Vgidl. At time t3', erasure discharge begins, and the channel of BLK N+1 discharges to a value of Vgidl', which is higher than Vgidl. The WL of BLK N+1 also decreases to a value of Vdd+Vgidl', which is higher than Vdd+Vgidl.

[0067] Similarly, after multiple erase pulse cycles, a voltage difference will accumulate between the WL of BLK N+1 and the channel, which is equivalent to a weak erase of BLK N+1, causing additional memory read window margin or voltage distribution ESUM loss during the erase process.

[0068] Figure 6 This is a flowchart illustrating a memory operation method according to an exemplary embodiment. Figure 6 The method shown can be applied, for example, to... Figure 3 The shown memory cell array is used to solve Figure 4 and Figure 5 The technical problem shown is that adjacent memory blocks of the selected memory block cause additional memory read window margin or voltage distribution ESUM loss.

[0069] refer to Figure 6 The method 60 provided in this embodiment may include the following steps.

[0070] In step S602, a bias voltage is applied to the bottom select line of the second memory block during the first time period to turn on the bottom select transistor of the second memory block.

[0071] In some embodiments, the first time period can be the time period before the erase pulse, for example, it can be... Figure 4 The time period before time t0 can also be Figure 5The time period before time t0'.

[0072] In some embodiments, the second storage block can be all unselected storage blocks (e.g., Figure 3 (BLK N+1……BLK N+X), or it can be just the third memory block adjacent to the selected memory block (e.g. Figure 3 In the context of BLK N+1, it can also refer to all memory blocks within a plane, including the selected memory block (e.g., BLK N, BLK N+1...BLK N+X). See [reference] Figure 2 By applying a bias voltage to the BSG line, the bottom select transistor 10224 of each NAND memory string 1022 on the second memory block can be turned on.

[0073] In some embodiments, when selecting the magnitude of the bias voltage, provided that it is determined to be greater than the threshold voltage of the bottom select transistor of the second memory block, it may be considered that the sum of the erase operating voltage and the bias voltage is less than a preset voltage threshold. The bias voltage can be in the range of 1V to 7V, for example, it can be 1V, 2V, 2.5V, 5V, 6V, 7V, etc.

[0074] In step S604, the first erasure operation is performed during the second time period, which is after the first time period.

[0075] In some embodiments, an erasing pulse may be applied at the beginning of the second time period, for example... Figure 4 Time t0 can be considered the start of the second time interval, and executing the first erase operation can be considered applying the first erase pulse. For example, Figure 5 The time t0' can also be the start of the second time period, and performing the first erase operation can be the application of the second erase pulse.

[0076] In some embodiments, performing the first erasure operation may include the steps S6042 and S6044.

[0077] In step S6042, an erase working voltage is provided to the source line of the first memory block.

[0078] In some embodiments, the erasure operating voltage can be a high positive voltage, such as 20V or higher, and can be represented as Verase as described above.

[0079] In some embodiments, the first storage block can be a selected storage block (e.g., Figure 3 In the case of BLK N), the second storage block can be any of the unselected storage blocks (e.g., BLK N). Figure 3 (BLK N+1……BLK N+X), or it can be used to select only the memory blocks adjacent to the selected memory blocks (e.g. Figure 3(BLK N+1 in the first memory block). Performing the first erase operation may also include applying an erase control voltage (e.g., Vss) to the word lines of the first memory block to erase the first memory block. Specific implementation details can be found in [reference needed]. Figure 7 . Reference Figure 3 By applying Verase to the HVNW 1024, an erase operating voltage can be provided to the source line of the first memory block, and an erase operating voltage can also be provided to the source line of the second memory block.

[0080] In step S6044, the bottom selection line of the second storage block is set to a floating state.

[0081] In various embodiments of the second storage block described above, setting the bottom selection line of the second storage block to a floating state includes selecting adjacent storage blocks (e.g., Figure 3 In the description of BLK N+1 (hereinafter referred to as BLK N+1), the bottom select line is set to a floating state, so that the voltage on the BSG line of BLK N+1 can rise from the bias voltage with the voltage on the source line. Since the bottom select transistor of BLK N+1 is turned on in the first time period before the first erase operation is performed in step S602, the bottom select transistor of BLK N+1 can be turned on continuously in the second time period. In the third time period, the bottom select line of BLK N+1 is still set to floating, which can be floated to the bias voltage. That is, during the discharge phase, the bottom select transistor of BLK N+1 can be in the conducting state. Then, Vgidl generated in the channel due to the voltage division effect of parasitic capacitance during the boost phase can continue to discharge to the initial potential Vss. Thus, during the discharge phase, WL of BLK N+1 can recover to a voltage closer to that before the boost phase. In this way, the voltage accumulation in the next erase cycle can be reduced or even eliminated. This can reduce the voltage difference between WL of the second memory block and the channel after multiple erase cycles, and reduce the memory read window margin or voltage distribution ESUM loss during the erase process.

[0082] Figure 7 It shows Figure 6 The step S604 shown is a schematic diagram of the processing procedure in one embodiment. Figure 7 and Figure 6 The connection is that, Figure 7 This illustration shows an implementation of performing a first erase operation when the first storage block is a selected storage block. Step S604 described above may include steps S702 to S706.

[0083] Step S702: Provide the erase operating voltage to the source line of the first memory block.

[0084] Reference Figure 3By applying Verase to the HVNW 1024, an erase operating voltage can be provided to the source line of the first memory block, and an erase operating voltage can also be provided to the source line of the second memory block.

[0085] Step S704: Apply an erase control voltage to the word line of the first memory block. The erase working voltage is greater than the erase control voltage.

[0086] In some embodiments, the erase control voltage is a low voltage lower than the erase operating voltage. Also during this phase (i.e., the second time period), a voltage is supplied to the bottom select line of the first memory block to the bottom select transistor to generate a GIDL current, which causes hole flow through the channels of the first memory block, shifting the threshold voltage of each memory cell in the first memory block in a more negative direction, i.e., shifting it to the erase state.

[0087] Step S706: Set the bottom selection line of the second storage block to a floating state.

[0088] In some embodiments, the specific implementation of step S706 can be referred to step S6044.

[0089] Figure 8 according to Figure 6 This diagram illustrates the process of applying voltage to a selected memory block during the erase phase. Figure 8 and Figure 6 The difference is that, Figure 8 The pressurization operation of the erasure discharge stage is also shown, that is, after step S6042 (step S802), it may further include step S804.

[0090] Step S802: During the second time period, an erase working voltage is provided to the source line of the first memory block.

[0091] In some embodiments, the specific implementation of step S802 can be referred to step S6042.

[0092] In step S804, a first voltage is applied to the source line during the third time period, which is after the second time period, and the first voltage is less than the erase working voltage.

[0093] by Figure 3 For example, in various embodiments of the first memory block described in step S6042, applying a first voltage to the source line of the first memory block can apply a first voltage to the source line of all memory blocks, including BLK N, BLK N+1...BLK N+X.

[0094] In some embodiments, Figure 12 It is based on Figures 6 to 11The diagram illustrates an erase pulse waveform. Taking the first erase pulse (i.e., the first erase operation) issued at time t0'' as an example, an erase working voltage (Verase) is applied to the source line by applying an erase working voltage to HVNW, which rises to the erase working voltage at time t1''. (Refer to...) Figure 12 The first time period can be the period before time t0'', the second time period can be the period between t0'' and t2'', and the third time period can be the period after time t2'', i.e., the erase / discharge phase. The first voltage is a low voltage, for example, Vss. Starting at time t2'', by applying the first voltage to HVNW, it is caused to drop from the erase operating voltage back to the first voltage, thus causing the source line voltage to drop back to the first voltage, ending the first erase operation, and waiting for the next erase pulse.

[0095] Figure 9 according to Figure 6 A schematic diagram of the process of applying voltage to unselected memory blocks during the erase phase is shown. Figure 9 yes Figure 6 The second storage block is an implementation where the storage block is not selected. Figure 9 It is shown that step S6044 may further include step S902, and after step S6044, it may further include step S904.

[0096] Step S902: During the second time period, the bottom select line of the second memory block is set to a floating state so that the voltage of the bottom select line of the second memory block rises from the bias voltage to the second voltage along with the source line. The second voltage is not greater than the sum of the erase working voltage and the bias voltage. The sum of the erase working voltage and the bias voltage is less than a preset voltage threshold. The range of the bias voltage is 1V~7V.

[0097] In some embodiments, at the beginning of the second time period, the voltage on the bottom select line of the second memory block is the bias voltage. After the bottom select line of the second memory block is floated, the voltage rises with the source line (e.g., through HVNW) to the sum of the erase working voltage and the bias voltage. If a coupling coefficient exists, it can be less than the sum of the erase working voltage and the bias voltage. When designing the magnitude of the bias voltage, it is advisable to make the sum of the erase working voltage and the bias voltage less than a preset voltage threshold to avoid damaging the bottom select transistor of the second memory block during the second time period.

[0098] In step S904, the bottom select line of the second memory block is kept in a floating state during the third time period so that the voltage of the bottom select line of the second memory block drops from the second voltage to the bias voltage, so as to keep the bottom select tube of the second memory block on.

[0099] In some embodiments, refer to Figure 12After the third time period, t2'', the bottom select line of the second memory block can be kept in a floating state. This allows the voltage of the bottom select line of the second memory block to drop from the second voltage to the bias voltage, thus keeping the bottom select transistor of the second memory block on until the next erase pulse begins. When the next erase pulse begins, the bottom select transistor of the second memory block remains on, thereby reducing the voltage difference between the WL of the second memory block and the channel during multiple erase cycles, and reducing the memory read window margin or voltage distribution ESUM loss during the erase process.

[0100] Figure 10 according to Figure 6 This diagram illustrates the operation process for an unselected memory block word line during the erase phase. Figure 10 yes Figure 6 The second storage block is an implementation where the storage block is not selected. Figure 10 It is shown that step S604 may further include steps S1002 and S1004.

[0101] Step S1002: Set the word line of the second storage block to a floating state during the second time period.

[0102] Using the second storage block as any unselected storage block (e.g.) Figure 3 Taking any block in BLK N+1...BLK N+X (hereinafter referred to as BLK N+X) as an example, refer to the implementation method. Figure 12 Since the bottom select transistor of BLK N+X is already turned on at time t0'', the voltage on the BSG line is Vbias. During the second time period, i.e., between t0'' and t1'', ​​the bottom select transistor of BLK N+X remains on during the BSG line voltage rise process. (Refer to...) Figure 12 At time t1'', ​​the initial voltage on WL of BLK N+X (e.g., the system voltage (Vdd)) is coupled with the channel boost potential of BLK N+X and rises to Verase+Vdd (which may be less than Verase+Vdd if there is a coupling coefficient). The voltage that rises with coupling on WL of BLK N+1 can also reach Verase+Vdd.

[0103] Step S1004: Keep the word line of the second storage block in a floating state during the third time period.

[0104] Taking the implementation where the second storage block is any unselected storage block BLK N+X as an example, refer to... Figure 12At time t2'', the erase discharge begins, keeping the WL of BLK N+X in a floating state. Starting at time t2'', since the bottom select line of BLK N+X is floating to the bias voltage, the bottom select transistor of BLK N+X remains in the conducting state. Therefore, regardless of whether X is 1 or not, the channel of BLK N+X can continue to discharge to its initial potential Vss. Consequently, the WL of BLK N+1 can also fall back to the system voltage Vdd, just like the WL of BLK N+X (where X is not 1). Thus, until the next erase pulse, the initial channel potential of BLK N+1 remains unchanged at Vss, and the initial voltage of BLK N+1's WL also remains unchanged at Vdd. That is, the waveform of the next erase pulse can still be... Figure 12 This demonstrates how to eliminate the voltage difference between the read window margin (WL) and the channel of the second memory block during multiple erase cycles, thereby reducing the memory's read window margin or voltage distribution ESUM loss during the erase process. In practical applications, this can reduce losses by 100mV.

[0105] Figure 11 It is based on Figure 6 A flowchart of another memory data processing method is shown. Figure 11 and Figure 6 The connection is that, Figure 11 The second erase operation shown is the next erase operation after the first erase operation in a multi-erasure cycle.

[0106] refer to Figure 11 The method 110 provided in this embodiment may include the following steps.

[0107] In step S1102, a bias voltage is applied to the bottom select line of the second memory block during a fourth time period, which follows the third time period.

[0108] In step S1104, the second erase operation is performed during the fifth time period, which follows the fourth time period.

[0109] In step S11042, an erase working voltage is provided to the source line of the first memory block.

[0110] In step S11044, the bottom selection line of the second storage block is set to a floating state.

[0111] In some embodiments, the fourth time period corresponds to the first time period, and the fifth time period corresponds to the second time period. The specific implementation of steps S1102 to S11044 can be referred to the specific implementation of steps S602 to S6044.

[0112] Figure 13 It is based on Figures 6 to 11 A block diagram of a memory structure is shown. Figure 13 The storage cell array 1302 shown is Figure 1 An example of the memory cell array 102, i.e., the peripheral circuitry 104, may include a page buffer / sensor amplifier 1304, a column decoder / BL driver 1306, a source line driver 1307, a row decoder / WL driver / BSG driver 1308, a voltage generator 1310, control circuitry 1312, a register 1314, input / output circuitry 1316, and so on. It should be understood that in some examples, it may also include... Figure 13 Additional peripheral circuitry not shown.

[0113] Page buffer / sensor amplifier 1304 can be configured to read data from memory cell array 1302 and program (write) data to memory cell array 1302 according to control signals from control circuitry 1312. In one example, refer to... Figure 2 The page buffer / sensor amplifier 1304 can store a page of programming data (write data) to be programmed into a page 1026 of the memory cell array 102. In another example, the page buffer / sensor amplifier 1304 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell 10222 coupled to the selected memory block 1020. In yet another example, the page buffer / sensor amplifier 1304 can also sense a low-power signal from the BL representing the data bits stored in the memory cell 10222 and amplify a small voltage swing to a recognizable logic level during a read operation. The column decoder / B driver 1306 can be configured to be controlled by the control circuitry 1312 and to select one or more NAND memory strings 1022 by applying a bit line voltage generated from the voltage generator 1310.

[0114] The source line driver 1307 can be configured to be controlled by the control circuit 1312 and to provide a source voltage, such as an erase working voltage, a first voltage, etc., to one or more NAND memory strings 1022 by applying a source voltage generated from the voltage generator 1310.

[0115] The line decoder / WL driver / BSG driver 1308 can be configured to be controlled by the control circuit 1312 to drive the WL using the WL voltage generated from the voltage generator 1310, and can also be selected / deselected and drive the BSG lines. The voltage generator 1310 can be configured to be controlled by the control circuit 1312 to generate the WL voltage to be supplied to the memory cell array 1302, such as an erase control voltage, etc., and can also be configured to be controlled by the control circuit 1312 to generate the BSG line voltage to be supplied to the memory cell array 1302, such as a bias voltage, etc.

[0116] As part of the peripheral circuitry, control circuitry 1312 can be coupled to other peripheral circuits described above and configured to control the operation of those peripheral circuits. Register 1314 can be coupled to control circuitry 1312 and includes a status register, command register, and address register for storing status information, command opcodes (e.g., OP codes), and command addresses for controlling the operation of each peripheral circuit. Input / output circuitry 1316 can be coupled to control circuitry 1312 and serves as a control buffer to buffer and relay control commands received from the host (not shown) and status information received from the host. Input / output circuitry 1316 can also be coupled to column decoder / BL driver 1306 via a data bus (not shown) and serves as a data input / output interface and data buffer to buffer and relay data to and from memory cell array 1302.

[0117] Figure 14 It is based on Figures 6 to 11 A schematic diagram of the structure of a storage system is shown. Figure 3 A block diagram of an exemplary storage system 140 having memory devices according to some aspects of this disclosure is shown. Storage system 140 may be a memory system in a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory devices, connected to a host (not shown) within the electronic device. The host may be a processor (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)) of the electronic device. The host may be configured to send data to or receive data from system 140.

[0118] Storage system 140 may include any memory device disclosed in embodiments of this disclosure, such as NAND flash memory devices (e.g., three-dimensional (3D) NAND flash memory devices) that can reduce the read window margin or voltage distribution ESUM loss of the memory during erase operations.

[0119] like Figure 14As shown, the storage system 140 may include a storage cell array 1402, peripheral circuitry 1404, and a controller 1406, the storage cell array 1402 and peripheral circuitry 1404 constituting a memory device. The controller 1406 is coupled to the peripheral circuitry 1404 and a host, and is configured to control the peripheral circuitry 1404 to operate the storage cell array 1402. The controller 1406 can manage data stored in the storage cell array 1402 and communicate with the host. In some embodiments, the controller 1406 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 1406 is designed to operate in a high duty cycle environment using a solid-state drive (SSD) or embedded multi-media card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., and for enterprise storage arrays. Controller 1406 can be configured to control the operation of peripheral circuitry 1404 on the storage cell array 1402, such as read, erase, and program operations. Controller 1406 can also be configured to manage various functions regarding data stored or to be stored in the storage cell array 1402, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 1406 is also configured to process error correction codes (ECC) regarding data read from or written to the storage cell array 1402. Controller 1406 can also perform any other suitable functions, such as formatting the memory device. Controller 1406 can communicate with external devices (e.g., a host) according to a specific communication protocol.For example, the controller 1406 can communicate with external devices through at least one of various interface protocols, such as Universal Serial Bus (USB), Multi Media Card (MMC), Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic (IDE), Firewire, etc.

[0120] The controller 1406 and one or more memory devices, including the memory cell array 1402 and peripheral circuitry 1404, can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the system 140 can be implemented and packaged into different types of end electronic products.

[0121] Exemplary embodiments of this disclosure have been specifically shown and described above. It should be understood that this disclosure is not limited to the detailed structures, arrangements, or implementations described herein; rather, this disclosure is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended claims.

Claims

1. A memory operation method, characterized in that, The memory includes multiple memory blocks, each memory block including a bottom select transistor coupled to a bottom select line, the multiple memory blocks including a first memory block and a second memory block, the method including: A bias voltage is applied to the bottom select line of the second memory block during the first time period to turn on the bottom select transistor of the second memory block. The first erase operation is performed during a second time period, which follows the first time period. During the third time period, the bottom select line of the second memory block is kept in a floating state so that the voltage of the bottom select line of the second memory block drops from the second voltage to the bias voltage, so as to continue to keep the bottom select transistor of the second memory block on. The third time period is after the second time period. The first erasure operation includes: Provide an erase operating voltage to the source line of the first memory block; A voltage is supplied to the bottom select line of the first memory block to cause the bottom select transistor of the first memory block to generate a gate-induced drain leakage current. Set the bottom selection line of the second storage block to a floating state.

2. The method according to claim 1, characterized in that, Performing the first erasure operation further includes: An erase control voltage is applied to the word line of the first memory block, wherein the erase operating voltage is greater than the erase control voltage.

3. The method according to claim 2, characterized in that, Also includes: A first voltage is applied to the source line during a third time period, which is after the second time period, and the first voltage is less than the erase working voltage.

4. The method according to claim 1, characterized in that, Setting the bottom selection line of the second storage block to a floating state includes: The bottom select line of the second memory block is set to a floating state so that the voltage of the bottom select line of the second memory block rises from the bias voltage along the source line to the second voltage, and the second voltage is not greater than the sum of the erase working voltage and the bias voltage.

5. The method according to claim 1, characterized in that, The sum of the erasure working voltage and the bias voltage is less than a preset voltage threshold.

6. The method according to claim 1, characterized in that, Performing the first erasure operation further includes: Set the word lines of the second memory block to a floating state; The method further includes: The word line of the second storage block is kept in a floating state during the third time period, which is after the second time period.

7. The method according to any one of claims 1 to 6, characterized in that, The second storage block includes a third storage block, which is adjacent to the first storage block.

8. The method according to any one of claims 1, 3, and 6, characterized in that, Also includes: The bias voltage is applied to the bottom select line of the second memory block during a fourth time period, which follows the third time period. A second erase operation is performed during a fifth time period, which follows the fourth time period. Performing the second erase operation includes: Provide the erase operating voltage to the source line of the first memory block; Set the bottom selection line of the second storage block to a floating state.

9. The method according to claim 1, characterized in that, The bias voltage ranges from 1V to 7V.

10. The method according to claim 1, characterized in that, The memory includes multiple planes, including a first plane selected from the multiple planes, and the multiple memory blocks are located on the first plane.

11. A memory, characterized in that, include: A storage cell array, the storage cell array comprising a plurality of storage blocks, each storage block comprising a bottom select transistor coupled to a bottom select line, the plurality of storage blocks comprising a first storage block and a second storage block; Peripheral circuitry, coupled to the memory cell array, is used for: A bias voltage is applied to the bottom select line of the second memory block during the first time period to turn on the bottom select transistor of the second memory block. The first erase operation is performed during a second time period, which follows the first time period. During the third time period, the bottom select line of the second memory block is kept in a floating state so that the voltage of the bottom select line of the second memory block drops from the second voltage to the bias voltage, so as to continue to keep the bottom select transistor of the second memory block on. The third time period is after the second time period. The first erasure operation includes: Provide an erase operating voltage to the source line of the first memory block; A voltage is supplied to the bottom select line of the first memory block to cause the bottom select transistor of the first memory block to generate a gate-induced drain leakage current. Set the bottom selection line of the second storage block to a floating state.

12. The memory according to claim 11, characterized in that, The peripheral circuitry includes a control circuit, a voltage generator, a bottom select line driver, and a source line driver, wherein: The voltage generator is used to generate the bias voltage; The control circuit is used to control the bottom select line driver to apply the bias voltage to the bottom select line of the second memory block during the first time period, so as to turn on the bottom select transistor of the second memory block. The voltage generator is also used to generate the erasure working voltage; The control circuit is also used to control the source line driver to apply the erase working voltage to the source line of the first memory block during the second time period; The control circuit is also used to control the bottom select line driver to set the bottom select line of the second memory block to a floating state during the second time period.

13. The memory according to claim 12, characterized in that, The voltage generator is also used to generate an erase control voltage, wherein the erase operating voltage is greater than the erase control voltage; The peripheral circuitry also includes a word line driver; The control circuit is also used to control the word line driver to apply the erase control voltage to the word line of the first memory block during the second time period.

14. The memory according to claim 13, characterized in that, The voltage generator is also used to generate a first voltage, which is less than the erase working voltage; The control circuit is further configured to control the source line driver to apply the first voltage to the source line of the first memory block during a third time period, the third time period being after the second time period.

15. The memory according to claim 12, characterized in that, The control circuit is further configured to control the bottom select line driver to set the bottom select line of the second memory block to a floating state during the second time period, so that the voltage of the bottom select line of the second memory block rises from the bias voltage along the source line to a second voltage, wherein the second voltage is not greater than the sum of the erase working voltage and the bias voltage.

16. The memory according to claim 15, characterized in that, The control circuit is further configured to control the bottom select line driver to keep the bottom select line of the second memory block in a floating state during a third time period, so that the voltage of the bottom select line of the second memory block drops from the second voltage to the bias voltage, so as to continue to keep the bottom select tube of the second memory block on, the third time period being after the second time period.

17. The memory according to claim 11, characterized in that, The sum of the erasure working voltage and the bias voltage is less than a preset voltage threshold.

18. The memory according to claim 13, characterized in that, The control circuit is also used to control the word line driver to set the word line of the second memory block to a floating state during the second time period; The control circuit is also used to control the word line driver to keep the word line of the second memory block in a floating state during a third time period, the third time period being after the second time period.

19. The memory according to any one of claims 11 to 18, characterized in that, The second storage block includes a third storage block, which is adjacent to the first storage block.

20. The memory according to any one of claims 11, 14, 16 and 18, characterized in that, The peripheral circuit is also used for: The bias voltage is applied to the bottom select line of the second memory block during a fourth time period, which follows the third time period. A second erase operation is performed during a fifth time period, which follows the fourth time period. Performing the second erase operation includes: Provide the erase operating voltage to the source line of the first memory block; Set the bottom selection line of the second storage block to a floating state.

21. The memory according to claim 11, characterized in that, The bias voltage ranges from 1V to 7V.

22. The memory according to claim 11, characterized in that, The storage cell array includes multiple planes, including a first plane selected from the multiple planes, and the multiple storage blocks are located on the first plane.

23. A storage system, characterized in that, Includes a memory and a controller coupled to the memory, wherein: The memory includes a memory cell array and peripheral circuitry. The memory cell array includes multiple memory blocks, each memory block includes a bottom select transistor coupled to a bottom select line, and the multiple memory blocks include a first memory block and a second memory block. The peripheral circuitry is coupled to the memory cell array. The controller is used to control the peripheral circuit to perform the memory operation method as described in any one of claims 1 to 10.

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