Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the structure comprises: a substrate; a gate structure and a plurality of source / drain doping layers, the gate structure is located on the substrate, and the source / drain doping layers are located in the substrate on both sides of the gate structure; a first conductive structure and a second conductive structure, the first conductive structure is located on the source / drain doping layers, and the second conductive structure is located on the gate structure; a first filling opening which exposes the side wall of the first conductive structure and the gate structure; a first filling layer located in the first filling opening, and the first filling layer has a first air gap therein. Since there is no other filling material between the first conductive structure and the gate structure, the first filling layer has a larger filling space, and the cavity of the first air gap in the first filling layer is larger. When the cavity of the first air gap is larger, the dielectric constant between the first conductive structure and the gate structure is smaller, and the parasitic capacitance between the first conductive structure and the gate structure is smaller, so that the performance of the semiconductor structure finally formed is better.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration, such as using flash memory as a storage device in electronic devices like digital cameras, laptops, or tablets. Therefore, reducing the size of flash memory cells and thus lowering the cost of flash memory is one direction of technological development. For NOR gate electrically erasable tunneling oxide flash memory, the conductive structures on the source and drain surfaces can be fabricated using self-aligned contact technology, thereby meeting the need to manufacture smaller flash memory sizes.

[0003] However, the performance of semiconductor structures formed by self-aligned electrical contact processes in existing technologies still needs to be improved. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the final semiconductor structure.

[0005] To address the aforementioned problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including a base and a fin located on the base; an isolation layer located on the substrate, the isolation layer covering a portion of the sidewalls of the fin, and the top surface of the isolation layer being lower than the top surface of the fin; a gate structure located on the substrate, the gate structure spanning the fin; source / drain doped layers located within the fins on both sides of the gate structure; a first conductive structure and a second conductive structure, the first conductive structure located on the source / drain doped layers, and the second conductive structure located on the gate structure; a first filling opening, the first filling opening exposing the sidewalls of the first conductive structure and the gate structure; and a first filling layer located within the first filling opening, the first filling layer having a first air gap.

[0006] Optionally, it further includes: a first dielectric layer, the first dielectric layer covering the sidewall of the gate structure, and the first filling opening located between the first dielectric layer and the gate structure.

[0007] Optionally, it further includes: a second dielectric layer located on the first dielectric layer, the second dielectric layer covering the first conductive structure and the second conductive structure, and the second dielectric layer exposing the top surfaces of the first conductive structure and the second conductive structure.

[0008] Optionally, it also includes: a first sidewall located on the sidewall of the gate structure.

[0009] Optionally, the first conductive structure includes: a first conductive plug located on the source / drain doped layer, and a first conductive layer located on the first conductive plug.

[0010] Optionally, the gate structure includes: a gate dielectric layer and a gate layer located on the gate dielectric layer; the gate structure includes a plurality of first regions and a second region located between the first regions, the source and drain doped layers are located on both sides of the second region, and the second conductive structure is located on the second region.

[0011] Optionally, it further includes: a second filling opening, which communicates with the first filling opening, the second filling opening being located between the first conductive structure and the second conductive structure, and the second filling opening exposing the sidewalls of the first conductive structure and the second conductive structure.

[0012] Optionally, it may also include: a second filling layer located within the second filling opening, the second filling layer having a second air gap.

[0013] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a base and fins located on the base; forming an isolation layer on the substrate, the isolation layer covering a portion of the sidewalls of the fins, and the top surface of the isolation layer being lower than the top surface of the fins; forming a gate structure and a plurality of source / drain doped layers, the gate structure spanning the fins, and the sidewalls of the gate structure having sacrificial sidewalls, the source / drain doped layers being located within the fins on both sides of the gate structure; forming a first conductive structure and a second conductive structure, the first conductive structure being located on the source / drain doped layers, and the second conductive structure being located on the gate structure; removing the sacrificial sidewalls to expose the sidewalls of the first conductive structure and the gate structure, forming a first filling opening; forming a first filling layer within the first filling opening, the first filling layer having a first air gap.

[0014] Optionally, the method for forming the gate structure and the source / drain doped layer includes: forming a dummy gate structure on the substrate; forming a sidewall structure on the sidewall of the dummy gate structure; etching the fin using the dummy gate structure and the sidewall structure as a mask to form a source / drain opening in the fin; forming the source / drain doped layer in the source / drain opening; forming a first dielectric layer on the substrate, the first dielectric layer covering the sidewall of the dummy gate structure; removing the dummy gate structure to form a gate opening in the first dielectric layer; and forming the gate structure in the gate opening.

[0015] Optionally, the sidewall structure includes: a first sidewall located on the sidewall of the pseudo-gate structure, and a second sidewall located on the sidewall of the first sidewall; after forming the source / drain doped layer, the method further includes: removing the second sidewall.

[0016] Optionally, the sacrificial sidewall includes: a first sacrificial sidewall layer and a second sacrificial sidewall layer located on the first sacrificial sidewall layer, wherein the material of the first sacrificial sidewall layer is different from the material of the second sacrificial sidewall layer.

[0017] Optionally, the material of the first sacrificial sidewall layer includes silicon carbide; the material of the second sacrificial sidewall layer includes silicon oxide.

[0018] Optionally, the method for forming the sacrificial sidewall includes: forming an initial first sacrificial sidewall layer on the sidewall of the pseudo-gate structure; forming an opening in the initial first sacrificial sidewall layer such that the initial first sacrificial sidewall layer forms the first sacrificial sidewall layer; and forming a second sacrificial sidewall layer in the opening.

[0019] Optionally, the first conductive structure includes: a first conductive plug located on the source / drain doped layer, and a first conductive layer located on the first conductive plug.

[0020] Optionally, the method for forming the first conductive structure includes: forming a first conductive opening within the first dielectric layer, the first conductive opening exposing the top surface of the source / drain doped layer and the sidewall of the sacrificial sidewall; forming a first conductive plug within the first conductive opening; forming a first capping layer within the first conductive opening; forming a second dielectric layer on the first dielectric layer; forming a second conductive opening within the second dielectric layer, the first capping layer, and the first sacrificial sidewall layer, the second conductive opening exposing the top surface of the first conductive plug and the sidewall of the sacrificial sidewall; and forming the first conductive layer within the second conductive opening.

[0021] Optionally, the gate structure includes: a gate dielectric layer, a gate layer located on the gate dielectric layer, and a second capping layer located on the gate layer, wherein the material of the second capping layer is different from the material of the first sidewall; the gate structure includes a plurality of first regions and a second region located between the first regions, wherein the source and drain doped layers are located on both sides of the second region, and the second conductive structure is located on the second region.

[0022] Optionally, the method for forming the second conductive structure includes: removing the second capping layer and a portion of the second dielectric layer to form a third conductive opening, the third conductive opening exposing the gate structure and the first sidewall; and forming the second conductive structure within the third conductive opening.

[0023] Optionally, the method for removing the sacrificial sidewall includes: removing the second sacrificial sidewall layer using a first etching process; and removing the first sacrificial sidewall layer using a second etching process.

[0024] Optionally, the second etching process employs a remote plasma etching process.

[0025] Optionally, the process parameters of the remote plasma etching process include: etching gas including NH4, O2, and NF3; etching temperature greater than 200 degrees Celsius.

[0026] Optionally, the process of forming the first filling opening further includes: removing a portion of the second dielectric layer, forming a second filling opening within the second dielectric layer, the second filling opening exposing the first filling opening, and the second filling opening exposing the sidewalls of the first conductive structure and the second conductive structure.

[0027] Optionally, after forming the first filling layer, the method further includes: forming a second filling layer within the second filling opening, the second filling layer having a second air gap.

[0028] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0029] The structure of the technical solution of the present invention includes: a first filling opening, which exposes the sidewalls of the first conductive structure and the gate structure; and a first filling layer located within the first filling opening, the first filling layer having a first air gap. Since there is no other filling material between the first conductive structure and the gate structure, the first filling layer has a large filling space, resulting in a large cavity for the first air gap within the first filling layer. When the cavity of the first air gap is large, the dielectric constant between the first conductive structure and the gate structure is small, resulting in a small parasitic capacitance between the first conductive structure and the gate structure, thereby improving the performance of the final semiconductor structure.

[0030] In the method for forming the technical solution of the present invention, the sidewalls of the first conductive structure and the gate structure are exposed by removing the sacrificial sidewall, forming a first filling opening; a first filling layer is formed within the first filling opening, and the first filling layer has a first air gap. Since there is no other filling material between the first conductive structure and the gate structure, the first filling layer has a large filling space, thereby making the cavity of the first air gap in the first filling layer larger. When the cavity of the first air gap is larger, the dielectric constant between the first conductive structure and the gate structure is smaller, resulting in a smaller parasitic capacitance between the first conductive structure and the gate structure, thereby improving the performance of the finally formed semiconductor structure.

[0031] Furthermore, the sidewall structure includes: a first sidewall located on the sidewall of the dummy gate structure, and a second sidewall located on the sidewall of the first sidewall; after forming the source / drain doped layer, the method further includes: removing the second sidewall. Removing the second sidewall increases the space between the first conductive structure and the gate structure, thereby increasing the filling space of the first filling layer and consequently increasing the cavity of the first air gap in the first filling layer. This reduces the parasitic capacitance between the first conductive structure and the gate structure, improving the performance of the final semiconductor structure.

[0032] Furthermore, the second etching process employs a remote plasma etching process; the process parameters of the remote plasma etching process include: etching gases including NH4, O2, and NF3; and an etching temperature greater than 200 degrees Celsius. This remote plasma etching process effectively reduces the difficulty of removing the first sacrificial sidewall layer.

[0033] Furthermore, the sacrificial sidewall comprises a first sacrificial sidewall layer and a second sacrificial sidewall layer located on the first sacrificial sidewall layer, wherein the material of the first sacrificial sidewall layer is different from that of the second sacrificial sidewall layer. By forming the first and second sacrificial sidewall layers with different materials, the purpose is to reduce the difficulty of the photolithography process by forming the subsequent first conductive layer through a self-aligned electrical contact process. Additionally, during the subsequent removal of the first and second sacrificial sidewall layers, removing the second sacrificial sidewall layer first increases the exposed surface area of ​​the first sacrificial sidewall layer, thereby reducing the difficulty of removing the first sacrificial sidewall layer. Attached Figure Description

[0034] Figures 1 to 3 This is a schematic diagram of a semiconductor structure.

[0035] Figures 4 to 16 This is a schematic diagram of the steps in an embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0036] As described in the background section, the performance of semiconductor structures formed by self-aligned electrical contact processes in the prior art still needs improvement. This will be explained in detail below with reference to the accompanying drawings.

[0037] Please refer to Figure 1 and Figure 2 , Figure 1 This is a top view of a semiconductor structure, omitting the filling structure, the first conductive plug, the first conductive layer, and the second conductive layer. Figure 2 yes Figure 1A cross-sectional schematic diagram along line AA includes: a substrate 100 having fins 101 extending along a first direction X; a gate structure 102 and a plurality of source / drain doped layers 103 formed therein, the gate structure 102 spanning the fins 101 along a second direction Y perpendicular to the first direction X; the gate structure 102 including a first region I and a plurality of second regions II arranged along the second direction Y, the first region I being located between adjacent second regions II; the source / drain doped layers 103 being located within the fins 101 on both sides of the first region I; a first conductive plug 104 formed on the source / drain doped layers 103; and the substrate 100 having a first conductive plug 104 formed therein. A sacrificial sidewall is formed on the first conductive plug 104 and the sidewall of the gate structure 102. The sacrificial sidewall includes a first sacrificial sidewall layer 105 and a second sacrificial sidewall layer 106 located on the first sacrificial sidewall layer 105, and the first sacrificial sidewall layer 105 and the second sacrificial sidewall layer 106 are made of different materials. A first conductive layer 107 and a second conductive layer 108 are formed. The first conductive layer 107 is located on the first conductive plug 104, and the second conductive layer 108 is located on the first region I. A dielectric layer 109 is formed, which covers the sidewalls of the first conductive layer 107 and the second conductive layer 108.

[0038] Please refer to Figure 3 , Figure 3 and Figure 2 With the view direction consistent, the second sacrificial sidewall layer 106 and part of the medium layer 109 are removed to form a filling opening (not shown); a first filling layer 110 is formed in the filling opening, and the first filling layer 110 has a first air gap 111; a second filling layer 112 is formed on the first filling layer 110, the second filling layer 112 fills the filling opening, and the second filling layer 112 has a second air gap 113.

[0039] In this embodiment, by forming the first sacrificial sidewall layer 105 and the second sacrificial sidewall layer 106 with different materials, the purpose is to form the first conductive layer 107 through a self-aligned electrical contact process, thereby reducing the difficulty of the photolithography process. Furthermore, by forming the second conductive layer 108 (Contact on Active Gate, COAG) on the first region I of the gate structure 102, the area occupied by the formed transistor can be effectively reduced, thereby improving the integration density of the semiconductor structure.

[0040] Since the first conductive layer 107 is located on the first region I, the spacing between the first conductive plug 104 and the first conductive layer 107 and the second conductive layer 108 is reduced, resulting in an increase in parasitic capacitance. Therefore, in this embodiment, by forming a first filling layer 110 with a first air gap 111 and a second filling layer 112 with a second air gap 113, the dielectric constant between the first conductive plug 104 and the first conductive layer 107 and the second conductive layer 108 and the gate structure 102 is increased, thereby reducing the parasitic capacitance between the first conductive plug 104 and the first conductive layer 107 and the second conductive layer 108 and the gate structure 102.

[0041] However, in this embodiment, due to the high difficulty in removing the first sacrificial sidewall layer 105, it is retained. However, the retained first sacrificial sidewall layer 105 occupies part of the space between the first conductive plug 104 and the first conductive layer 107, and the second conductive layer 108 and the gate structure 102, reducing the filling space of the first filling layer 110 and consequently resulting in a smaller cavity in the final air gap 111. When the cavity of the first air gap 110 is small, the dielectric constant between the first conductive plug 104 and the first conductive layer 107, and the second conductive layer 108 and the gate structure 102 is large, resulting in a large parasitic capacitance between the first conductive plug 104 and the first conductive layer 107, and the second conductive layer 108 and the gate structure 102, thereby reducing the performance of the final semiconductor structure.

[0042] Based on this, the present invention provides a semiconductor structure and a method for forming the same. There is no other filling material between the first conductive structure and the gate structure, thus allowing the first filling layer to have a large filling space, and consequently, a large cavity for the first air gap in the first filling layer. When the cavity for the first air gap is large, the dielectric constant between the first conductive structure and the gate structure is small, resulting in a small parasitic capacitance between the first conductive structure and the gate structure, thereby improving the performance of the final semiconductor structure.

[0043] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] Figures 4 to 16 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0045] Please refer to Figure 4 A substrate is provided, the substrate including: a base 200 and a fin 201 located on the base 200.

[0046] In other embodiments, the substrate may also be a planar structure.

[0047] In this embodiment, the substrate 200 has a device layer (not shown), and the device layer has several device structures, including one or more of the following: PMOS transistors, NMOS transistors, CMOS transistors, resistors, capacitors, and inductors. The PMOS transistors, NMOS transistors, and CMOS transistors all include basic gate, source, and drain structures.

[0048] In other embodiments, the substrate may not have the device layer.

[0049] In this embodiment, the method for forming the substrate includes: providing an initial substrate (not shown) having a mask layer (not shown) on the initial substrate, the mask layer exposing a portion of the top surface of the initial substrate; and etching the initial substrate using the mask layer as a mask to form the substrate.

[0050] In this embodiment, the fin 201 is made of silicon; in other embodiments, the fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.

[0051] Please refer to Figure 5 An isolation layer 202 is formed on the substrate, the isolation layer 202 covers part of the sidewall of the fin 201, and the top surface of the isolation layer 202 is lower than the top surface of the fin 201.

[0052] In this embodiment, the method for forming the isolation layer 202 includes: forming an initial isolation layer (not shown) on the substrate; etching away a portion of the initial isolation layer to form the isolation layer 202, wherein the top surface of the isolation layer 202 is lower than the top surface of the fin 201.

[0053] The insulating layer 202 is made of an insulating material, including silicon oxide or silicon oxynitride; in this embodiment, the insulating layer 202 is made of silicon oxide.

[0054] After forming the isolation layer 202, a gate structure and several source / drain doped layers are formed. The gate structure is located on the substrate, and its sidewalls have sacrificial sidewalls. The source / drain doped layers are located within the substrate on both sides of the gate structure. For a detailed formation process, please refer to [reference needed]. Figures 6 to 11 .

[0055] Please refer to Figure 6 A pseudo-gate structure 203 is formed on the substrate.

[0056] In this embodiment, the pseudo-gate structure 203 includes: a pseudo-gate dielectric layer, and a pseudo-gate layer (not shown) located on the pseudo-gate dielectric layer.

[0057] In this embodiment, the dummy gate dielectric layer is made of silicon oxide; in other embodiments, the dummy gate dielectric layer may also be made of silicon oxynitride.

[0058] In this embodiment, the pseudo-gate layer is made of polycrystalline silicon.

[0059] In this embodiment, the pseudo-gate structure 203 spans the fin 201 and covers part of the sidewall and top surface of the fin 201.

[0060] Please refer to Figure 7 A sidewall structure is formed on the sidewall of the pseudo-gate structure 203; the fin 201 is etched using the pseudo-gate structure 203 and the sidewall structure as a mask, and a source / drain opening (not shown) is formed in the fin 201; the source / drain doped layer 204 is formed in the source / drain opening.

[0061] In this embodiment, the sidewall structure includes: a first sidewall 205 located on the sidewall of the pseudo-grid structure 203, and a second sidewall 206 located on the sidewall of the first sidewall 205.

[0062] In this embodiment, the first sidewall 205 is made of silicon oxide; the second sidewall 206 is made of silicon nitride.

[0063] In this embodiment, the method for forming the source / drain doped layer 204 within the source / drain opening includes: forming an epitaxial layer (not shown) within the source / drain opening using an epitaxial growth process; performing source / drain ion implantation after forming the epitaxial layer to form an ion implantation region (not shown), wherein the ion implantation region and the epitaxial layer together constitute the source / drain doped layer 204.

[0064] Please refer to Figure 8 After the source / drain doped layer 204 is formed, the second sidewall 206 is removed.

[0065] In this embodiment, removing the second sidewall 206 increases the space between the subsequently formed first conductive structure and the gate structure, further increasing the filling space of the subsequently formed first filling layer, and consequently increasing the cavity of the first air gap in the first filling layer. This reduces the parasitic capacitance between the first conductive structure and the gate structure, improving the performance of the final semiconductor structure.

[0066] Please refer to Figure 9 A sacrificial sidewall is formed on the sidewall of the first sidewall 205.

[0067] In this embodiment, the sacrificial sidewall includes a first sacrificial sidewall layer 207 and a second sacrificial sidewall layer 208 located on the first sacrificial sidewall layer 207, and the material of the first sacrificial sidewall layer 207 is different from the material of the second sacrificial sidewall layer 208.

[0068] In this embodiment, the material of the first sacrificial sidewall layer 207 includes silicon carbide; the material of the second sacrificial sidewall layer 208 includes silicon oxide.

[0069] In this embodiment, by forming the first sacrificial sidewall layer 207 and the second sacrificial sidewall layer 208 of different materials, the aim is to form the subsequent first conductive layer through a self-aligned electrical contact process, thereby reducing the difficulty of the photolithography process. Furthermore, during the subsequent removal of the first sacrificial sidewall layer 207 and the second sacrificial sidewall layer 208, removing the second sacrificial sidewall layer 208 first increases the exposed surface area of ​​the first sacrificial sidewall layer 207, thereby reducing the process difficulty of removing the first sacrificial sidewall layer 207.

[0070] In this embodiment, the method for forming the sacrificial sidewall includes: forming an initial first sacrificial sidewall layer (not shown) on the sidewall of the first sidewall 205; forming an opening (not shown) in the initial first sacrificial sidewall layer, such that the initial first sacrificial sidewall layer forms the first sacrificial sidewall layer 207; and forming a second sacrificial sidewall layer 208 in the opening.

[0071] Please refer to Figure 10 and Figure 11 , Figure 10 This is a top view of the semiconductor structure. Figure 11 yes Figure 10 A schematic cross-sectional view along the BB line shows that a first dielectric layer 209 is formed on the substrate, and the first dielectric layer 209 covers the sidewall of the dummy gate structure 203; the dummy gate structure 203 is removed, and a gate opening (not shown) is formed in the first dielectric layer 209; the gate structure 210 is formed in the gate opening.

[0072] In this embodiment, the first dielectric layer 209 is made of silicon oxide; in other embodiments, the first dielectric layer may also be made of a low-k dielectric material (referring to a dielectric material with a relative permittivity of less than 3.9) or an ultra-low-k dielectric material (referring to a dielectric material with a relative permittivity of less than 2.5).

[0073] In this embodiment, the gate structure 210 includes: a gate dielectric layer, a gate layer located on the gate dielectric layer, and a second capping layer (not shown) located on the gate layer. The material of the second capping layer is different from the material of the first sidewall 205. The gate structure 210 includes a plurality of first regions I and a second region II located between the first regions I. The source and drain doped layers 204 are located on both sides of the second region II.

[0074] After forming the gate structure 210, the process further includes forming a first conductive structure and a second conductive structure, wherein the first conductive structure is located on the source / drain doped layer 204, and the second conductive structure is located on the gate structure 210. Please refer to [reference needed] for the detailed formation process. Figures 12 to 14 .

[0075] Please refer to Figure 12 A first conductive opening (not shown) is formed in the first dielectric layer 209, the first conductive opening exposing the top surface of the source / drain doped layer 204 and the sidewall of the sacrificial sidewall; a first conductive plug 211 is formed in the first conductive opening; a first cover layer 212 is formed in the first conductive opening, the first cover layer 212 being located on the first conductive plug 211.

[0076] In this embodiment, the material of the first conductive plug 211 includes a metal, such as tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the material of the first conductive plug 211 is tungsten.

[0077] Please refer to Figure 13 A second dielectric layer 213 is formed on the first dielectric layer 209.

[0078] In this embodiment, the material of the second dielectric layer 213 is silicon oxide; in other embodiments, the material of the second dielectric layer may also be a low-k dielectric material (referring to a dielectric material with a relative permittivity of less than 3.9) or an ultra-low-k dielectric material (referring to a dielectric material with a relative permittivity of less than 2.5).

[0079] Please refer to Figure 14 A second conductive opening (not shown) is formed within the second dielectric layer 213, the first capping layer 212, and the first sacrificial sidewall layer 207, exposing the top surface of the first conductive plug 211 and the sidewall of the sacrificial sidewall; the second capping layer and part of the second dielectric layer 213 are removed to form a third conductive opening (not shown), exposing the gate structure 210 and the sidewall of the first sidewall 205; the first conductive layer 214 is formed within the second conductive opening; and the second conductive structure 215 is formed within the third conductive opening.

[0080] In this embodiment, the first conductive structure is composed of the first conductive plug 211 and the first conductive layer 214.

[0081] In this embodiment, the third conductive opening exposes the top surface of the gate layer of the gate structure 210.

[0082] In this embodiment, the second conductive structure 215 is located on the second region II of the gate structure 210, which can effectively reduce the area occupied by the formed transistor and thus improve the integration of the semiconductor structure.

[0083] In this embodiment, a self-aligned electrical contact process is used in the formation of the first conductive layer 214 and the second conductive structure 215, which can effectively reduce the difficulty of the photolithography process.

[0084] Please refer to Figure 15 The sacrificial sidewall is removed to expose the sidewalls of the first conductive structure and the gate structure 210, forming a first filling opening 216.

[0085] In this embodiment, the method for removing the sacrificial sidewall includes: removing the second sacrificial sidewall layer 208 using a first etching process; and removing the first sacrificial sidewall layer 207 using a second etching process.

[0086] In this embodiment, the second etching process employs a remote plasma etching process. The process parameters of the remote plasma etching process include: etching gases comprising NH4, O2, and NF3; and an etching temperature greater than 200 degrees Celsius. This remote plasma etching process effectively reduces the difficulty of removing the first sacrificial sidewall layer.

[0087] Please continue to refer to this. Figure 15 In this embodiment, the process of forming the first filling opening 216 further includes: removing a portion of the second dielectric layer 213, forming a second filling opening 217 in the second dielectric layer 213, the second filling opening 217 exposing the first filling opening 216, and the second filling opening 217 exposing the sidewalls of the first conductive structure and the second conductive structure 215.

[0088] Please refer to Figure 16 A first filling layer 218 is formed within the first filling opening 216, and the first filling layer 218 has a first air gap 219.

[0089] In this embodiment, by removing the sacrificial sidewalls to expose the sidewalls of the first conductive structure and the gate structure 210, a first filling opening 216 is formed. A first filling layer 218 is formed within the first filling opening 216, and the first filling layer 218 has a first air gap 219. Since there is no other filling material between the first conductive structure and the gate structure 210, the first filling layer 218 has a large filling space, which in turn makes the cavity of the first air gap 219 in the first filling layer 218 larger. When the cavity of the first air gap 219 is larger, the dielectric constant between the first conductive structure and the gate structure 210 is smaller, resulting in a smaller parasitic capacitance between the first conductive structure and the gate structure 210, thereby improving the performance of the finally formed semiconductor structure.

[0090] Please continue to refer to this. Figure 16 In this embodiment, after forming the first filling layer 218, the method further includes forming a second filling layer 220 within the second filling opening 217, wherein the second filling layer 220 has a second air gap 221.

[0091] Accordingly, an embodiment of the present invention also provides a semiconductor structure, please refer to [link / reference needed]. Figure 16 The device includes: a substrate, the substrate comprising: a base 200 and fins 201 located on the base 200; an isolation layer 202 located on the substrate, the isolation layer 202 covering a portion of the sidewalls of the fins 201, and the top surface of the isolation layer 202 being lower than the top surface of the fins 201; a gate structure 210 located on the substrate; source / drain doped layers 204 located within the fins 201 on both sides of the gate structure 210; a first conductive structure and a second conductive structure 215, the first conductive structure being located on the source / drain doped layers 204, and the second conductive structure 215 being located on the gate structure 210; a first filling opening 216 exposing the sidewalls of the first conductive structure and the gate structure 210; and a first filling layer 218 located within the first filling opening 216, the first filling layer 218 having a first air gap 219.

[0092] In this embodiment, it further includes: a first dielectric layer 209, which covers the sidewall of the gate structure 210, and the first filling opening 216 is located between the first dielectric layer 209 and the gate structure 210.

[0093] In this embodiment, it further includes a second dielectric layer 213 located on the first dielectric layer 209, the second dielectric layer 213 covering the first conductive structure and the second conductive structure 215, and the second dielectric layer 213 exposing the top surfaces of the first conductive structure and the second conductive structure 215.

[0094] In this embodiment, it also includes a first sidewall 205 located on the sidewall of the gate structure 210.

[0095] In this embodiment, the first conductive structure includes: a first conductive plug 211 located on the source / drain doped layer 204, and a first conductive layer 214 located on the first conductive plug 211.

[0096] In this embodiment, the gate structure 210 includes a gate dielectric layer and a gate layer located on the gate dielectric layer; the gate structure includes a plurality of first regions I and a second region II located between the first regions I, the source and drain doped layers 204 are located on both sides of the second region II, and the second conductive structure 215 is located on the second region II.

[0097] In this embodiment, it further includes: a second filling opening 217, which communicates with the first filling opening 216, the second filling opening 217 is located between the first conductive structure and the second conductive structure 215, and the second filling opening 217 exposes the sidewalls of the first conductive structure and the second conductive structure 215.

[0098] In this embodiment, it further includes: a second filling layer 220 located within the second filling opening 217, the second filling layer 220 having a second air gap 221.

[0099] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a base and fins located on the base; An isolation layer is located on the substrate, the isolation layer covers a portion of the sidewall of the fin, and the top surface of the isolation layer is lower than the top surface of the fin; A gate structure located on the substrate, the gate structure spanning the fin; Source and drain doped layers located within the fins on both sides of the gate structure; A first conductive structure and a second conductive structure, wherein the first conductive structure is located on the source / drain doped layer and the second conductive structure is located on the gate structure; A first filling opening exposes the sidewalls of the first conductive structure and the gate structure; A first filling layer located within the first filling opening, the first filling layer having a first air gap.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: A first dielectric layer covers the sidewalls of the gate structure, and the first filling opening is located between the first dielectric layer and the gate structure.

3. The semiconductor structure as described in claim 2, characterized in that, Also includes: A second dielectric layer is located on the first dielectric layer, the second dielectric layer covers the first conductive structure and the second conductive structure, and the second dielectric layer exposes the top surfaces of the first conductive structure and the second conductive structure.

4. The semiconductor structure as described in claim 1, characterized in that, Also includes: The first sidewall located on the sidewall of the gate structure.

5. The semiconductor structure as described in claim 1, characterized in that, The first conductive structure includes: a first conductive plug located on the source / drain doped layer, and a first conductive layer located on the first conductive plug.

6. The semiconductor structure as described in claim 1, characterized in that, The gate structure includes: a gate dielectric layer and a gate layer located on the gate dielectric layer; the gate structure includes a plurality of first regions and a second region located between the first regions, the source and drain doped layers are located on both sides of the second region, and the second conductive structure is located on the second region.

7. The semiconductor structure as described in claim 1, characterized in that, Also includes: A second filling opening communicates with the first filling opening, the second filling opening is located between the first conductive structure and the second conductive structure, and the second filling opening exposes the sidewalls of the first conductive structure and the second conductive structure.

8. The semiconductor structure as described in claim 7, characterized in that, Also includes: A second filling layer located within the second filling opening, the second filling layer having a second air gap.

9. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a base and fins located on the base; An isolation layer is formed on the substrate, the isolation layer covering a portion of the sidewall of the fin, and the top surface of the isolation layer is lower than the top surface of the fin; A gate structure and several source / drain doped layers are formed, the gate structure spans the fin, and the sidewalls of the gate structure have sacrificial sidewalls, and the source / drain doped layers are located inside the fins on both sides of the gate structure; A first conductive structure and a second conductive structure are formed, wherein the first conductive structure is located on the source / drain doped layer and the second conductive structure is located on the gate structure; Remove the sacrificial sidewall to expose the sidewalls of the first conductive structure and the gate structure, forming a first filling opening; A first filling layer is formed within the first filling opening, and the first filling layer has a first air gap.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the gate structure and the source / drain doped layer includes: forming a dummy gate structure on the substrate; forming a sidewall structure on the sidewall of the dummy gate structure; etching the fin using the dummy gate structure and the sidewall structure as a mask to form a source / drain opening in the fin; forming the source / drain doped layer in the source / drain opening; forming a first dielectric layer on the substrate, the first dielectric layer covering the sidewall of the dummy gate structure; removing the dummy gate structure to form a gate opening in the first dielectric layer; and forming the gate structure in the gate opening.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The sidewall structure includes: a first sidewall located on the sidewall of the pseudo-gate structure, and a second sidewall located on the sidewall of the first sidewall; after forming the source / drain doped layer, the structure further includes: removing the second sidewall.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The sacrificial sidewall includes a first sacrificial sidewall layer and a second sacrificial sidewall layer located on the first sacrificial sidewall layer, wherein the material of the first sacrificial sidewall layer is different from the material of the second sacrificial sidewall layer.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The material of the first sacrificial sidewall layer includes silicon carbide; the material of the second sacrificial sidewall layer includes silicon oxide.

14. The method for forming a semiconductor structure as described in claim 12, characterized in that, The method for forming the sacrificial sidewall includes: forming an initial first sacrificial sidewall layer on the sidewall of the pseudo-gate structure; forming an opening in the initial first sacrificial sidewall layer such that the initial first sacrificial sidewall layer forms the first sacrificial sidewall layer; and forming a second sacrificial sidewall layer in the opening.

15. The method for forming a semiconductor structure as described in claim 11, characterized in that, The first conductive structure includes: a first conductive plug located on the source / drain doped layer, and a first conductive layer located on the first conductive plug.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The method of forming the first conductive structure includes: forming a first conductive opening in the first dielectric layer, the first conductive opening exposing the top surface of the source / drain doped layer and the sidewall of the sacrificial sidewall; forming a first conductive plug in the first conductive opening; forming a first capping layer in the first conductive opening; forming a second dielectric layer on the first dielectric layer; forming a second conductive opening in the second dielectric layer, the first capping layer and the first sacrificial sidewall layer, the second conductive opening exposing the top surface of the first conductive plug and the sidewall of the sacrificial sidewall; and forming the first conductive layer in the second conductive opening.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The gate structure includes: a gate dielectric layer, a gate layer located on the gate dielectric layer, and a second capping layer located on the gate layer, wherein the material of the second capping layer is different from the material of the first sidewall; the gate structure includes a plurality of first regions and a second region located between the first regions, wherein the source and drain doped layers are located on both sides of the second region, and the second conductive structure is located on the second region.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The method for forming the second conductive structure includes: removing the second capping layer and a portion of the second dielectric layer to form a third conductive opening, the third conductive opening exposing the gate structure and the first sidewall; and forming the second conductive structure within the third conductive opening.

19. The method for forming a semiconductor structure as described in claim 12, characterized in that, The method for removing the sacrificial sidewall includes: removing the second sacrificial sidewall layer using a first etching process; and removing the first sacrificial sidewall layer using a second etching process.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, The second etching process employs a remote plasma etching process.

21. The method for forming a semiconductor structure as described in claim 20, characterized in that, The process parameters of the remote plasma etching process include: etching gases including NH4, O2, and NF3; and etching temperature greater than 200 degrees Celsius.

22. The method for forming a semiconductor structure as described in claim 16, characterized in that, The process of forming the first filling opening further includes: removing a portion of the second dielectric layer, forming a second filling opening within the second dielectric layer, the second filling opening exposing the first filling opening, and the second filling opening exposing the sidewalls of the first conductive structure and the second conductive structure.

23. The method for forming a semiconductor structure as described in claim 22, characterized in that, After forming the first filling layer, the method further includes: forming a second filling layer within the second filling opening, the second filling layer having a second air gap.

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