Memory device including memory cells storing calibration data and method of operation

Abstract

A memory device and an operating method thereof are provided. The memory device may include: a cell array including a first portion and a second portion sharing a plurality of word lines, the plurality of word lines including a first group of word lines and a second group of word lines; a first column decoder configured to select at least one bit line in a first group of bit lines connected to the first portion; a second column decoder configured to select at least one bit line in a second set of bit lines connected to the second portion; and a read circuit configured to output a data signal based on a comparison between an output of the first column decoder and an output of the second column decoder. The first portion includes a plurality of first memory cells connected to at least one word line of the first set of word lines and configured to store bits of calibration data for calibrating the memory device, and the second portion includes a plurality of second memory cells connected to at least one word line of the first set of word lines and configured to store bits of calibration data for calibrating the memory device. A plurality of second memory cells are connected to the at least one word line and configured to store negated bits of the calibration data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority of Korean Patent Application No. 10-2023-0088633 filed on July 7, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0154567 filed on November 9, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0003] Aspects of the inventive concept relate to an integrated circuit, and more particularly, to a memory device including a memory cell storing calibration data and an operating method thereof. Background Art

[0004] Memory devices manufactured by semiconductor processes may have variations due to various factors. For example, the reference used when reading data written to a memory cell may vary due to factors such as process, voltage, temperature, and aging. The memory device may be calibrated to compensate for the variations, and calibration data may be generated as a result of the calibration. The calibration data may be referenced before the memory device is driven, and the memory device may be set based on the calibration data. Summary of the invention

[0005] Aspects of the inventive concept provide a memory device for efficiently providing calibration data and an operating method thereof.

[0006] According to one aspect of the inventive concept, a memory device includes: a cell array including a first portion and a second portion sharing a plurality of word lines, the plurality of word lines including a first group of word lines and a second group of word lines; a first column decoder configured to select at least one bit line of a first group of bit lines connected to the first portion; a second column decoder configured to select at least one bit line of a second group of bit lines connected to the second portion; and a read circuit configured to output a data signal based on a comparison between an output of the first column decoder and an output of the second column decoder. The first portion includes a plurality of first memory cells connected to at least one word line of the first group of word lines and configured to store bits of calibration data for calibrating the memory device, and the second portion includes a plurality of second memory cells connected to the at least one word line and configured to store inverted bits of bits of the calibration data.

[0007] According to one aspect of the inventive concept, a memory device includes: a cell array including a first portion and a second portion sharing a plurality of word lines; a first column decoder connected to the first portion through a first group of bit lines among a plurality of bit lines; a second column decoder connected to the second portion through a second group of bit lines among the plurality of bit lines; a read circuit configured to output a data signal based on a comparison between an output of the first column decoder and an output of the second column decoder; and an address decoder configured to provide column addresses corresponding to each other to the first column decoder and the second column decoder, respectively, when reading calibration data for calibrating the memory device.

[0008] According to one aspect of the inventive concept, a memory device includes a cell array, the cell array includes a first portion and a second portion sharing a plurality of word lines. An operating method of the memory device includes: writing bits of calibration data for calibrating the memory device into a first region of the first portion in response to at least one first write command, and writing inverted bits of the bits of the calibration data into a second region of the second portion; and reading bits of the calibration data by simultaneously detecting bits stored in the first region and inverted bits stored in the second region in response to a first read command. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of a memory device according to an embodiment;

[0011] Figure 2A and Figure 2B are diagrams respectively showing a memory cell and a reference cell according to an embodiment;

[0012] Figure 3 is a graph showing distribution of a memory cell and a reference according to an embodiment;

[0013] Figure 4A and Figure 4B is a block diagram of a memory device for reading user data according to an embodiment;

[0014] Figure 5 is a block diagram of a memory device for reading calibration data according to an embodiment;

[0015] Figure 6 is a graph showing distribution of memory cells according to an embodiment;

[0016] Fig. 7A and Figure 7B is a block diagram of an example of a memory device according to an embodiment;

[0017] Figure 8is a graph showing distribution of memory cells according to an embodiment;

[0018] Fig. 9 is a flow chart of an operating method of a memory device according to an embodiment;

[0019] Fig.10 is a flow chart of an operating method of a memory device according to an embodiment;

[0020] Fig.11 is a flow chart of an operating method of a memory device according to an embodiment;

[0021] Fig.12 is a flow chart of an operating method of a memory device according to an embodiment;

[0022] Fig.13 is a block diagram of a memory system including a memory device according to an embodiment;

[0023] and

[0024] Fig.14 is a block diagram of a system on chip including a memory device according to an embodiment. DETAILED DESCRIPTION

[0025] Figure 1 is a block diagram of a memory device 10 according to an embodiment. Figure 1 , the memory device 10 may receive a command CMD and an address ADDR, and may receive or output data DATA. For example, the memory device 10 may receive a command CMD such as a write command or a read command and an address ADDR corresponding to the command CMD from a memory controller. In addition, the memory device 10 may receive data DATA (i.e., write data) from the memory controller or provide data DATA (i.e., read data) to the memory controller. In some embodiments, at least two of the command CMD, the address ADDR, and the data DATA may be received or output through the same channel. Figure 1 As shown, the memory device 10 may include a cell array 11, a row decoder 12, a first column decoder 13, a second column decoder 14, a read circuit 15, an address decoder 16, a data buffer 17, a control circuit 18, and an input / output (I / O) circuit 19.

[0026] The cell array 11 may include a first portion SEC1 and a second portion SEC2, and the first portion SEC1 and the second portion SEC2 may share a plurality of word lines with each other. For example, each of the first portion SEC1 and the second portion SEC2 may include a plurality of memory cells connected to a plurality of first word lines WL1 (e.g., a first group of word lines) and at least one second word line WL2 (e.g., a second group of word lines). The memory cells connected to a word line may be referred to as pages, and data may be read or written on a page basis. Ordinals such as "first", "second", "third", etc. may simply be used as marks for certain elements, steps, etc. to distinguish such elements, steps, etc. from each other. Terms that are not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. In addition, terms referenced by a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere using a different ordinal number (e.g., "second" in the specification or another claim).

[0027] The memory cell may be a nonvolatile memory cell, and the stored value is not lost even if the power supply to the memory device 10 is cut off. In some embodiments, the memory cell is a flash memory cell, and the value may be stored according to the threshold voltage of the transistor. In some embodiments, each memory cell may include a variable resistance element (e.g., Figure 2A MTJ in the memory cell), and the variable resistance element may have a resistance corresponding to the value (or bit) stored in the memory cell. When the memory cell includes a variable resistance element, the memory device 10 may be referred to as a resistive memory device. For example, as a non-limiting example, the memory device 10 may include a cell array 11 having a structure such as a phase change random access memory (PRAM) and a ferroelectric random access memory (FRAM), or include a cell array 11 having a magnetic random access memory (MRAM) structure such as a spin transfer torque magnetic random access memory (STT-MRAM), a spin transfer torque magnetization switching RAM (spin-RAM), and a spin momentum transfer RAM (SMT-RAM). As described below with reference to Figure 2A As described, the embodiments are mainly described with reference to MRAM, but the embodiments are not limited thereto.

[0028] Each of the first part SEC1 and the second part SEC2 may include a plurality of reference cells connected to a plurality of first word lines WL1 and at least one second word line WL2. The reference cells may be used to determine the values ​​stored in the memory cells. For example, the first part SEC1 and the second part SEC2 may have the same or symmetrical structure. When one of the plurality of word lines is activated by the row decoder 12, not only the memory cells connected to the activated word line but also the reference cells connected to the activated word line may be selected. In order to compensate for errors caused by parasitic resistance of the conductors, the reference cells of the second part SEC2 may be used when determining the values ​​stored in the memory cells of the first part SEC1, and the reference cells of the first part SEC1 may be used when determining the values ​​stored in the memory cells of the second part SEC2. Refer to the following Figure 4A and Figure 4B An example of an operation using a reference cell is described.

[0029] A plurality of first word lines WL1 may be connected to a plurality of memory cells for storing user data (such as data to be written to the memory device 10 by a host using the memory device 10 or data read from the memory device 10 by a host using the memory device 10). In addition, at least one second word line WL2 may be connected to a plurality of memory cells for storing calibration data for calibrating the memory device 10. A memory device manufactured by a semiconductor process may have variations due to various factors. For example, a variable resistance element included in a memory cell may have a resistance that varies due to factors such as process, voltage, temperature, and aging. The memory device 10 may be calibrated to compensate for the variations, and calibration data may be generated as a result of the calibration. For example, the memory device 10 may be tested during the manufacturing stage, and calibration data may be generated based on the test results. The calibration data may be referenced before driving the memory device 10, and variations in the memory device 10 may be compensated by setting the memory device 10 based on the calibration data. For example, the calibration data may be used to adjust the voltage applied to the memory cell during a memory access operation. Therefore, the calibration data may be stored in a non-volatile storage space so that the calibration data is not lost even if power to the memory device 10 is cut off.

[0030] The cell array 11 may include not only memory cells for storing user data (e.g., memory cells connected to a plurality of first word lines WL1), but also memory cells for storing calibration data (e.g., memory cells connected to at least one second word line WL2). As described below with reference to the accompanying drawings, the memory device 10 may store calibration data with high reliability, and therefore, variations in the memory device 10 may be accurately and safely compensated. In addition, since the cell array 11 and the peripheral circuit for user data may be used as they are for calibration data, the memory device 10 may have a simple structure and low cost. In addition, since a separate nonvolatile storage device for storing calibration data may be omitted, a system including the memory device 10 may have a simple structure and low cost. In addition, since the calibration data stored in the cell array 11 may be updated, the memory device 10 may be useful to the user, and variations due to aging may be compensated. In addition, since a memory cell for storing calibration data may be easily added, calibration for storing various variations may be possible.

[0031] The row decoder 12 may be connected to the first portion SEC1 and the second portion SEC2 through a plurality of first word lines WL1 and at least one second word line WL2. The row decoder 12 may activate at least one of the plurality of first word lines WL1 and the plurality of second word lines WL2 based on a row address ROW received from the address decoder 16, and may select memory cells and reference cells connected to the activated word lines. For example, while the row decoder 12 activates one of the plurality of first word lines WL1 in response to the row address ROW to write or read user data, the row decoder 12 may activate at least one of the at least one second word line WL2 to write or read calibration data.

[0032] The first column decoder 13 may be connected to the first portion SEC1 through a plurality of first bit lines BL1 (e.g., a first group of bit lines), and the second column decoder 14 may be connected to the second portion SEC2 through a plurality of second bit lines BL2 (e.g., a second group of bit lines). The first column decoder 13 may select one of the plurality of first bit lines BL1 based on a first column address COL1 received from the address decoder 16, and may be connected to the first output bit line BLO1. In addition, the second column decoder 14 may select one of the plurality of second bit lines BL2 based on a second column address COL2 received from the address decoder 16, and may be connected to the second output bit line BLO2.

[0033] The read circuit 15 may be connected to the first column decoder 13 via a first output bit line BLO1, and may be connected to the second column decoder 14 via a second output bit line BLO2. The read circuit 15 may determine the value stored in the memory cell based on the signal received via the first output bit line BLO1 and the second output bit line BLO2, and generate a data signal D_OUT including the determined value. In some embodiments, the read circuit 15 may provide a voltage of a predetermined magnitude to each of the memory cell and the reference cell, and determine the value stored in the memory cell by detecting a current passing through the memory cell and the reference cell (e.g., by comparing the currents or determining the difference between the currents). In some embodiments, the read circuit 15 may provide a current of a predetermined magnitude to the memory cell and the reference cell, and determine the value stored in the memory cell by detecting a voltage applied to or output from the memory cell and the reference cell. Although it is assumed that the value stored in the memory cell is determined by detecting the current, the embodiments are not limited thereto. Although Figure 1 Although not shown in the figure, the memory device 10 may further include a write circuit for writing data into the memory cells.

[0034] The variable resistor circuit VR may provide a variable resistance and may be connected to the read circuit 15. When reading a memory cell storing user data (e.g., a memory cell connected to a plurality of first word lines WL1) (e.g., during reading user data from the memory cell), the read circuit 15 may electrically connect one of the first output bit line BLO1 and the second output bit line BLO2 to the variable resistor circuit VR and determine a value stored in the memory cell. In addition, when reading a memory cell storing calibration data (e.g., a memory cell connected to at least one second word line WL2) (e.g., during reading calibration data from the memory cell), the read circuit 15 may electrically disconnect the variable resistor circuit VR from the first output bit line BLO1 and the second output bit line BLO2 and determine a value stored in the memory cell. The variable resistor circuit VR may provide a resistance corresponding to a value included in the calibration data. For example, the control circuit 18 described below may identify a resistance based on calibration data read from the cell array 11, and provide a control signal to the variable resistor circuit VR to have the identified resistance. Therefore, the calibration data stored in and read from the cell array 11 can be used to determine and control the resistance of the variable resistor circuit VR, and the read circuit 15 uses the resistance of the variable resistor circuit VR to determine the value of the user data stored in the memory cell storing the user data. In some embodiments, the resistance can be controlled to take into account variations in process, voltage, and temperature, as well as device aging.

[0035] The address decoder 16 may generate a row address ROW, a first column address COL1, and a second column address COL2 based on an address received via the I / O circuit 19. The data buffer 17 may receive a data signal D_OUT from the read circuit 15 and store data corresponding to the data signal D_OUT. The data buffer 17 may provide the stored data to the I / O circuit 19.

[0036] The I / O circuit 19 may provide a memory interface. For example, the I / O circuit 19 may receive a command CMD and an address ADDR from the outside, and receive data DATA from the outside or output the data DATA to the outside. The I / O circuit 19 may generate a decoding signal DEC by decoding the command CMD, and provide the address ADDR to the address decoder 16. The I / O circuit 19 may provide the received data DATA to the data buffer 17, and output the data DATA received from the data buffer 17 to the outside.

[0037] The control circuit 18 may receive the decode signal DEC from the I / O circuit 19 and control the elements of the memory device 10 based on the decode signal DEC. For example, the control circuit 18 may recognize an indication of a write operation or a read operation based on the decode signal DEC and control the elements to perform the write operation or the read operation.

[0038] In some embodiments, the memory device 10 may be set to a calibration mode for writing or reading calibration data or a normal mode for writing or reading user data. In some embodiments, a command CMD for indicating the calibration mode or the normal mode may be received, and the command CMD may set the memory device 10 to the calibration mode or the normal mode based on the decode signal DEC. In some embodiments, when an access to a memory cell connected to a plurality of first word lines WL1 is recognized, the address decoder 16 may set the memory device 10 to the normal mode based on the address, and when an access to a memory cell connected to at least one second word line WL2 is recognized, the address decoder 16 may set the memory device 10 to the calibration mode.

[0039] Figure 2A and Figure 2B 2 are diagrams showing a memory cell 20a and a reference cell 20b according to an embodiment, respectively. Figure 1 The cell array 11 may include Figure 2A The memory cell 20a and Figure 2B In the following, the reference unit 20b is omitted. Figure 2A and Figure 2B The description is the same as the description of .

[0040] Reference Figure 2A, the memory cell 20a may include a variable resistance element MTJ and a cell transistor CTj connected in series with each other between a source line SLj and a bit line BLj. In some embodiments, different from Figure 2A As shown in , the cell transistor CTj may be connected to the source line SLj and the variable resistance element MTJ may be connected to the bit line BLj. The variable resistance element MTJ may include a free layer FL and a pinned layer PL, and may include a barrier layer BL between the free layer FL and the pinned layer PL. Figure 2A As shown by the arrow in , while the magnetization direction of the pinned layer PL is fixed, the magnetization direction of the free layer FL may be the same as or opposite to the magnetization direction of the pinned layer PL. When the pinned layer PL and the free layer FL have the same magnetization direction, the variable resistance element MTJ may be referred to as being in a parallel state P, and when the pinned layer PL and the free layer FL have magnetization directions opposite to each other, the variable resistance element MTJ may be referred to as being in an antiparallel state AP. In some embodiments, the variable resistance element MTJ may further include an antiferromagnetic layer so that the pinned layer PL has a fixed magnetization direction.

[0041] The variable resistance element MTJ may have a relatively low resistance R in the parallel state P. P , but can have a relatively high resistance R in the antiparallel state AP AP In this paper, when the variable resistance element MTJ in the parallel state P has a low resistance R P When the memory cell 20a is assumed to store "0", the variable resistance element MTJ in the antiparallel state AP has a relatively high resistance R AP , the memory cell 20a is assumed to store "1". In addition, in this article, the resistance R corresponding to "0" P Can be called parallel resistance, and corresponds to the resistance R of "1" AP can be referred to as an anti-parallel resistor. However, this embodiment is only an example, and in other embodiments, a relatively low resistance R P The parallel state P can be set to store "1" while having a relatively high resistance R AP The anti-parallel state AP can be set to store "0".

[0042] The cell transistor CTj may have a gate connected to the word line WLi, and a source and a drain connected to the bit line BLj and the variable resistance element MTJ. The cell transistor CTj may electrically connect or disconnect the variable resistance element MTJ and the bit line BLj according to the signal applied to the word line WLi. For example, in a write operation, in order to write "0" to the memory cell 20a, the cell transistor CTj may be turned on, and the current from the source line SLj to the bit line BLj may pass through the variable resistance element MTJ and the cell transistor CTj. In addition, in order to write "1" to the memory cell 20a, the cell transistor CTj may be turned on, and the current from the bit line BLj to the source line SLj may pass through the cell transistor CTj and the variable resistance element MTJ. In a read operation, the cell transistor CTj may be turned on, and the current from the source line SLj to the bit line BLj or the current from the bit line BLj to the source line SLj (e.g., a read current) may pass through the cell transistor CTj and the variable resistance element MTJ. Herein, it is assumed that a read current flows from the source line SLj to the bit line BLj.

[0043] Reference Figure 2B , the reference cell 20b may include a cell transistor CTk connected between a source line SLk and a bit line BLk. Figure 2A Compared with the memory cell 20a in FIG. 1 , the variable resistance element MTJ can be omitted in the reference cell 20b, and the reference cell 20b can be referred to as a short-circuit cell. Figure 1 As described, the memory device 10 may include a variable resistor circuit VR outside the cell array 11, and in order to determine the value stored in the memory cell 20a, the resistance of the variable resistor element MTJ may be compared with the resistance of the variable resistor circuit VR due to the reference cell 20b being a short-circuited cell. For example, if the resistance of the variable resistor element MTJ is greater than the resistance of the variable resistor circuit VR, the value stored in the memory cell 20a may be a first value (e.g., a "1" bit), and if the resistance of the variable resistor element MTJ is less than the resistance of the variable resistor circuit VR, the value stored in the memory cell 20a may be a second value (e.g., a "0" bit). The variable resistor circuit VR may facilitate the adjustment of resistance and provide more favorable characteristics than the variable resistor element MTJ. In the following, it is assumed that the reference cell is similar to Figure 2B However, the reference cell may be a reference cell including a variable resistance element MTJ. Herein, the reference cell and the variable resistor circuit VR may be collectively referred to as a reference circuit.

[0044] Figure 3 is a graph showing the distribution of memory cells and reference circuits according to an embodiment. For example, Figure 3The graph in shows memory cells in the parallel state P and in the antiparallel state AP, and shows the state of a reference cell. Distributions 31, 32, and 33 represent the current through the memory cell in the antiparallel state AP, the current through the reference cell, and the current through the memory cell in the parallel state P. Figure 3 In the graph of , the current passing through the reference unit may correspond to the current passing through the short-circuit unit and the variable resistor circuit VR.

[0045] The resistance of the variable resistance elements MTJ of a group of memory cells may have a distribution, and therefore, when a constant voltage is applied to the variable resistance elements MTJ of the group of memory cells, a current distribution may occur. Figure 3 As shown, the average current I AP distribution 31, and the average current I in the memory cell storing "0" P In addition, the reference circuit presents an average current I REF Therefore, when determining the value stored in the memory cell based on the current, the memory cell in the antiparallel state AP may have a read margin M AP , and the memory cell in the parallel state P may have a read margin M P . With the reading margin M AP and M P The reliability of the memory device can be improved by increasing the reference current. The reference current can be defined by calibration data. For example, as mentioned above Figure 1 As described above, the resistance of the variable resistor circuit VR can be adjusted by the calibration data, and the calibration data can be generated by testing the memory device 10 so that a large read margin M appears in the memory device 10. AP and M P .

[0046] Figure 4A and Figure 4B 4 is a block diagram of a memory device 40 for reading user data according to an embodiment. For example, Figure 4A The block diagram in FIG. 4 shows the memory device 40 in a situation in which it reads user data stored in the first portion SEC1, and Figure 4B The block diagram in shows the memory device 40 in a situation in which it reads the user data stored in the second portion SEC2. Figure 4A and Figure 4B In the , lines and blocks that are activated or used in the read operation are shown in bold or shaded. Figure 4A and Figure 4B , the same description as that given above with reference to the accompanying drawings is omitted.

[0047] like Figure 4A and Figure 4B As shown, the memory device 40 may include a cell array 41, a row decoder 42, a first column decoder 43, a second column decoder 44, a read circuit 45, and a variable resistor circuit VR. The cell array 41 may include a first portion SEC1 and a second portion SEC2. The first portion SEC1 may include memory cells M11 and M12 and reference cells R11 and R12, and the second portion SEC2 may include memory cells M21 and M22 and reference cells R21 and R22. The memory cells M11 and the reference cells R11 of the first portion SEC1 and the memory cells M21 and the reference cells R21 of the second portion SEC2 may be connected to a first word line WL1, and the memory cells M12 and the reference cells R12 of the first portion SEC1 and the memory cells M22 and the reference cells R22 of the second portion SEC2 may be connected to a second word line WL2. Reference cells R11 and R12 of the first section SEC1 may be connected to a first bit line BL11 of the first group of bit lines, and memory cells M11 and M12 of the first section SEC1 may be connected to a second bit line BL12 of the first group of bit lines. Reference cells R21 and R22 of the second section SEC2 may be connected to a first bit line BL21 of the second group of bit lines, and memory cells M21 and M22 of the second section SEC2 may be connected to a second bit line BL22 of the second group of bit lines.

[0048] Reference Figure 4A , in order to read the value stored in the memory cell M11 of the first section SEC1, the row decoder 42 may activate the first word line WL1 in response to the row address ROW. While the first column decoder 43 may select the second bit line BL12 connected to the memory cell M11 in response to the first column address COL1, the second column decoder 44 may select the first bit line BL21 connected to the reference cell R21 in response to the second column address COL2. Therefore, the first output bit line BLO1 may be electrically connected to the second bit line BL12 in the first group of bit lines, and the second output bit line BLO2 may be electrically connected to the first bit line BL21 in the second group of bit lines.

[0049] The read circuit 45 can be Figure 1 The address decoder 16 in the embodiment receives the partial signal SEC and can be Figure 1 The control circuit 18 in receives the mode signal MD. In some embodiments, Figure 1The address decoder 16 in the I / O circuit 19 may identify access to a memory cell storing user data or a memory cell storing calibration data based on an address received from the I / O circuit 19, and thus, the mode signal MD may be generated by the address decoder 16. The partial signal SEC may indicate a portion including a memory cell to be read, i.e., a first portion SEC1, and the mode signal MD may indicate a mode in which an operation of reading user data is performed, i.e., a normal mode. The read circuit 45 may electrically connect the second output bit line BLO2 to the variable resistor circuit VR in response to the partial signal SEC. Thus, the read circuit 45 may determine a value stored in the memory cell M11 by comparing a current passing through the memory cell M11 and a current passing through the variable resistor circuit VR with each other, and generate a data signal D_OUT including the determined value (e.g., if the current passing through the memory cell M11 is greater than the current passing through the variable resistor circuit VR, then the data signal D_OUT will have a first value, and if the current passing through the memory cell M11 is less than the current passing through the variable resistor circuit VR, then the data signal D_OUT will have a second value). For example, in some embodiments, a comparison between the outputs may be used to determine a difference between the outputs (eg, a difference between the currents), and based on the difference, a particular value will be output via the data signal D_OUT.

[0050] Reference Figure 4B , in order to read the value stored in the memory cell M21 of the second section SEC2, the row decoder 42 may activate the first word line WL1 in response to the row address ROW. While the first column decoder 43 may select the first bit line BL11 connected to the reference cell R11 in response to the first column address COL1, the second column decoder 44 may select the second bit line BL22 connected to the memory cell M21 in response to the second column address COL2. Therefore, the first output bit line BLO1 may be electrically connected to the first bit line BL11, and the second output bit line BLO2 may be electrically connected to the second bit line BL22.

[0051] The read circuit 45 may electrically connect the first output bit line BLO1 to the variable resistor circuit VR in response to the partial signal SEC representing the second portion SEC2. Therefore, the read circuit 45 may determine the value stored in the memory cell M21 by comparing the current passing through the memory cell M21 and the current passing through the variable resistor circuit VR with each other, and generate a data signal D_OUT including the determined value.

[0052] Figure 5 FIG. 5 is a block diagram of a memory device 50 for reading calibration data according to an embodiment. Figure 5 In the example, lines and blocks that are activated or used in a read operation can be displayed in bold or shaded. Figure 5 The memory device 50 in the embodiment may have Figure 4A and Figure 4B The same structure as the memory device 40 in FIG. Figure 5 , the same description as that given above with reference to the accompanying drawings is omitted.

[0053] like Figure 5 As shown, the memory device 50 may include a cell array 51, a row decoder 52, a first column decoder 53, a second column decoder 54, a read circuit 55, and a variable resistor circuit VR. The cell array 51 may include a first portion SEC1 and a second portion SEC2. The first portion SEC1 may include memory cells M11 and M12 and reference cells R11 and R12, and the second portion SEC2 may include memory cells M21 and M22 and reference cells R21 and R22. The memory cells M11 and the reference cells R11 of the first portion SEC1 and the memory cells M21 and the reference cells R21 of the second portion SEC2 may be connected to a first word line WL1, and the memory cells M12 and the reference cells R12 of the first portion SEC1 and the memory cells M22 and the reference cells R22 of the second portion SEC2 may be connected to a second word line WL2. Reference cells R11 and R12 of the first section SEC1 may be connected to a first bit line BL11 of the first group of bit lines, and memory cells M11 and M12 of the first section SEC1 may be connected to a second bit line BL12 of the first group of bit lines. Reference cells R21 and R22 of the second section SEC2 may be connected to a first bit line BL21 of the second group of bit lines, and memory cells M21 and M22 of the second section SEC2 may be connected to a second bit line BL22 of the second group of bit lines.

[0054] While the memory cells included in the first portion SEC1 may store bits of calibration data, the memory cells included in the second portion SEC2 may store inverted bits of the bits of calibration data. For example, while the memory cell M12 of the first portion SEC1 connected to the second word line WL2 may store the first bit of calibration data, the memory cell M22 of the second portion SEC2 connected to the second word line WL2 may store the inverted first bit (e.g., where the first bit is "1" and the inverted first bit is "0", or vice versa). In this document, the inverted first bit may be an inverted version of the first bit and may be referred to as a first inverted bit. To this end, in the process of testing the memory device 50, the bits of calibration data may be written into the first portion SEC1, and the inverted bits of calibration data may be written into the second portion SEC2.

[0055] In order to read the calibration data, the row decoder 52 may activate the second word line WL2 in response to the row address ROW. While the first column decoder 53 may select the second bit line BL12 connected to the memory cell M12 in response to the first column address COL1, the second column decoder 54 may select the second bit line BL22 connected to the memory cell M22 in response to the second column address COL2. Therefore, the first output bit line BLO1 may be electrically connected to the second bit line BL12, and the second output bit line BLO2 may be electrically connected to the second bit line BL22.

[0056] In some embodiments, Figure 1 The address decoder 16 in the embodiment can receive the mode signal MD from the control circuit 18. When the mode signal MD indicates the normal mode, as shown in the above reference Figure 4A and Figure 4B As described, the address decoder 16 can generate the first column address COL1 and the second column address COL2 so that one of the first output bit line BLO1 and the second output bit line BLO2 is electrically connected to the reference cell. In addition, when the mode signal MD indicates the calibration mode, as shown in FIG. Figure 5 As shown, the address decoder 16 may generate a first column address COL1 and a second column address COL2 so that the first output bit line BLO1 and the second output bit line BLO2 are electrically connected to the memory cells, respectively. The address decoder 16 may generate a first column address COL1 and a second column address COL2 included in a column address pair from one address in a calibration mode to access a memory cell M12 and a memory cell M22 storing a first bit and an inverted first bit of calibration data, respectively. For example, the memory cell M12 and the memory cell M22 may correspond to the same column address, and therefore, the first column address COL1 and the second column address COL2 may be identical to each other. Herein, the first column address COL1 and the second column address COL2 included in the column address pair may be referred to as corresponding to each other.

[0057] The read circuit 55 may electrically disconnect the first output bit line BLO1 and the second output bit line BLO2 from the variable resistor circuit VR in response to the mode signal MD indicating the calibration mode. Therefore, the read circuit 55 may determine the bit of the calibration data by comparing the current passing through the memory cell M12 with the current passing through the memory cell M22, and generate the data signal D_OUT including the determined bit. As described above, the memory cell M12 and the memory cell M22 may respectively store mutually inverted bits, and therefore, as described below with reference to Figure 6 As described, the read circuit 55 can determine the bits of calibration data with a high read margin.

[0058] Figure 6 is a graph showing the distribution of memory cells according to an embodiment. For example, Figure 6The graphs in show distributions 61 and 62 of current passing through a memory cell in a parallel state P and a memory cell in an anti-parallel state AP to store calibration data.

[0059] The memory cell storing the calibration data may have the same structure as other memory cells (eg, memory cells storing user data), and Figure 6 The distributions 61 and 62 in Figure 3 The distributions 31 and 32 in are the same. Figure 3 As described above, the read operation of the memory cell storing the user data may have a read margin M based on the reference circuit. AP and M P However, since the memory cells store bits that are inverted from each other, the read operation of the memory cell storing the calibration data may be performed as follows. Figure 6 The larger read margin M CAL Therefore, the operation of reading calibration data can be performed without a reference circuit, and the calibration data defining the reference circuit set before the operation of reading user data is performed can be securely stored and read with high reliability.

[0060] Fig. 7A and Figure 7B is a block diagram of an example of a memory device according to an embodiment. For example, Fig. 7A and Figure 7B The block diagrams in FIG. 7 show memory devices 70a and 70b that perform operations to read calibration data, respectively. As described below, memory devices 70a and 70b may redundantly store bits of calibration data for greater read margin. Fig. 7A and Figure 7B In , the bits of calibration data are redundantly stored in two memory cells. However, it will be appreciated that the bits of calibration data may be redundantly stored in three or more memory cells. Fig. 7A and Figure 7B In the , you can show in bold or shaded font the lines and blocks that are activated or used in the read operation. Fig. 7A and Figure 7B , the same description as that given above with reference to the accompanying drawings is omitted.

[0061] Reference Fig. 7A, the memory device 70a may include a cell array 71, a row decoder 72, a first column decoder 73, a second column decoder 74, a read circuit 75, and a variable resistor circuit VR. The cell array 71 may include a first portion SEC1 and a second portion SEC2. The first portion SEC1 may include memory cells M121 and M122 and reference cells R121 and R122, and the second portion SEC2 may include memory cells M221 and M222 and reference cells R221 and R222. The memory cells M121 and the reference cells R121 of the first portion SEC1 and the memory cells M221 and the reference cells R221 of the second portion SEC2 may be connected to a first word line WL21 of the second group of word lines, and the memory cells M122 and the reference cells R122 of the first portion SEC1 and the memory cells M222 and the reference cells R222 of the second portion SEC2 may be connected to a second word line WL22 of the second group of word lines. Reference cells R121 and R122 of the first section SEC1 may be connected to a first bit line BL11 of the first group of bit lines, and memory cells M121 and M122 of the first section SEC1 may be connected to a second bit line BL12 of the first group of bit lines. Reference cells R221 and R222 of the second section SEC2 may be connected to a first bit line BL21 of the second group of bit lines, and memory cells M221 and M222 of the second section SEC2 may be connected to a second bit line BL22 of the second group of bit lines. Fig. 7A Unlike shown in FIG. 1 , in some embodiments, word lines WL21 and WL22 may not be adjacent to each other, and an additional word line may be disposed between word lines WL21 and WL22 .

[0062] As mentioned above Figure 5 As described, the memory cells included in the first portion SEC1 may store bits of calibration data, and the memory cells included in the second portion SEC2 may store inverted bits of calibration data. For example, while the memory cell M121 of the first portion SEC1 connected to the word line WL21 may store the first bit of calibration data, the memory cell M221 of the second portion SEC2 connected to the word line WL21 may store the inverted first bit. In addition, the memory cells may store bits of calibration data redundantly. For example, the memory cell M122 of the first portion SEC1 connected to the word line WL22 may store the first bit stored in the memory cell M121 commonly connected to the bit line BL12, and the memory cell M222 of the second portion SEC2 connected to the word line WL22 may store the first inverted bit stored in the memory cell M221 commonly connected to the bit line BL22.

[0063] The row decoder 72 may activate two or more word lines so that memory cells storing bits redundantly are selected at the same time. Fig. 7AAs shown, the row decoder 72 may simultaneously activate the word line WL21 and the word line WL22 in response to the row address ROW, and may simultaneously select the memory cells M121 and M122 of the first section SEC1 and the memory cells M221 and M222 of the second section SEC2. Therefore, the memory cells M121 and M122 may be electrically connected to each other in parallel, and the memory cells M221 and M222 may be electrically connected to each other in parallel. While the first column decoder 73 may select the bit line BL12 connected to the memory cells M121 and M122 in response to the first column address COL1, the second column decoder 74 may select the bit line BL22 connected to the memory cells M221 and M222 in response to the second column address COL2. Therefore, the first output bit line BLO1 may be electrically connected to the bit line BL12, and the second output bit line BLO2 may be electrically connected to the bit line BL22.

[0064] The read circuit 75 may determine the bit of the calibration data by comparing the sum of the currents passing through the memory cells M121 and M122 of the first section SEC1 with the sum of the currents passing through the memory cells M221 and M222 of the second section SEC2, and generate a data signal D_OUT including the determined bit. The current passing through two memory cells connected in parallel to each other may have a larger magnitude than the current passing through one memory cell, and therefore, a large read margin may be possible, as described below with reference to Figure 8 As described.

[0065] Reference Figure 7B , the memory device 70b may include a cell array 71, a row decoder 72, a first column decoder 73, a second column decoder 74, a read circuit 75, and a variable resistor circuit VR. The cell array 71 may include a first portion SEC1 and a second portion SEC2. The first portion SEC1 may include memory cells M121 and M122 and a reference cell R12, and the second portion SEC2 may include memory cells M222 and M221 and a reference cell R22. The memory cells M121 and M122 and the reference cell R12 of the first portion SEC1 and the memory cells M221 and M222 and the reference cell R22 of the second portion SEC2 may be connected to the second word line WL2. The reference cell R12 and the memory cells M121 and M122 of the first portion SEC1 may be connected to the bit lines BL11, BL12, and BL13 of the first group of bit lines, respectively, and the reference cell R22 and the memory cells M221 and M222 of the second portion SEC2 may be connected to the bit lines BL21, BL22, and BL23 of the second group of bit lines, respectively.

[0066] As mentioned above Figure 5As described, the memory cells included in the first portion SEC1 may store bits of calibration data, and the memory cells included in the second portion SEC2 may store inverted bits of calibration data. For example, while the memory cell M121 of the first portion SEC1 connected to the second word line WL2 may store the first bit of calibration data, the memory cell M221 of the second portion SEC2 connected to the second word line WL2 may store the first inverted bit. In addition, the memory cells may store bits of calibration data redundantly. For example, the memory cell M122 of the first portion SEC1 connected to the bit line BL13 may store the first bit stored in the memory cell M121 commonly connected to the second word line WL2, and the memory cell M222 of the second portion SEC2 connected to the bit line BL23 may store the first inverted bit stored in the memory cell M221 commonly connected to the second word line WL2.

[0067] The row decoder 72 may activate the second word line WL2 in response to the row address ROW. Each of the first column decoder 73 and the second column decoder 74 may select two or more bit lines so that memory cells storing bits redundantly are selected at the same time. Figure 7B As shown, the first column decoder 73 may select two bit lines BL12 and BL13 in response to the first column address COL1, and may simultaneously select the memory cells M121 and M122 of the first section SEC1. In addition, the second column decoder 74 may select two bit lines BL22 and BL23 in response to the second column address COL2, and may simultaneously select the memory cells M221 and M222 of the second section SEC2. Therefore, the memory cells M121 and M122 may be electrically connected to each other in parallel, and the memory cells M221 and M222 may be electrically connected to each other in parallel. In addition, the first output bit line BLO1 may be electrically connected to the two bit lines BL12 and BL13, and the second output bit line BLO2 may be electrically connected to the two bit lines BL22 and BL23.

[0068] The read circuit 75 may determine the bit of the calibration data by comparing the sum of the currents passing through the memory cells M121 and M122 of the first section SEC1 with the sum of the currents passing through the memory cells M221 and M222 of the second section SEC2, and generate a data signal D_OUT including the determined bit. The current passing through two memory cells connected in parallel to each other may have a larger magnitude than the current passing through one memory cell, and therefore, a large read margin may be possible, as described below with reference to Figure 8 as described.

[0069] Figure 8 is a graph showing the distribution of memory cells according to an embodiment. For example, Figure 8The graph in shows the distributions 81, 82, 83 and 84 of the currents passing through the memory cell in the parallel state P and the memory cell in the anti-parallel state AP to store calibration data.

[0070] As mentioned above Figure 6 As described above, the operation of reading calibration data from memory cells that respectively store mutually inverted bits may have a read margin M defined by distributions 81 and 82. CAL As mentioned above Fig. 7A and Figure 7B As described above, when two memory cells redundantly store bits of calibration data, the current passing through the two memory cells can be increased by about one time. Therefore, an average current I AP' Distribution 83(I AP' =2I AP ), and may present an average current I in the two memory cells in the parallel state P P' Distribution 84(I P' =2I P ). Due to the distributions 83 and 84, a larger read margin M may occur. CAL The read margin M CAL' . As a result, calibration data can be securely stored and read out with greater reliability.

[0071] Fig. 9 is a flowchart of an operating method of a memory device according to an embodiment. Fig. 9 The flowchart in FIG. 1 shows a method of operating a memory device for writing and reading calibration data. In some embodiments, Fig. 9 The method can be performed in calibration mode. Fig. 9 As shown, the operating method of the memory device may include a plurality of operations S110, S120 and S130. In some embodiments, Fig. 9 The method can be Figure 5 The memory device 50 in the embodiment of the present invention is executed. In the following, reference is made to Figure 5 describe Fig. 9 .

[0072] Reference Fig. 9 In operation S110, the bits of calibration data may be written into the first region of the first portion SEC1. The first region may include memory cells in the first portion SEC1 for storing calibration data, for example, memory cells connected to the second word line WL2. The row decoder 52 may activate the second word line WL2, and the bits of calibration data may be written into the memory cells M12 in the first portion SEC1 connected to the second word line WL2. Fig.10 An example of operation S110 is described.

[0073] In operation S120, the inverted bit of the calibration data may be written into the second region of the second portion SEC2. The second region may include memory cells in the second portion SEC2 for storing the calibration data, for example, memory cells connected to the second word line WL2. The row decoder 52 may activate the second word line WL2, and the inverted bit of the calibration data may be written into the memory cell M22 connected to the second word line WL2 in the second portion SEC2. Fig.10 An example of operation S120 is described.

[0074] In some embodiments, Fig. 9 As shown, operations S110 and S120 may be performed in parallel. For example, operations S110 and S120 may be performed in parallel in response to one command CMD indicating a write operation. The memory device 50 may receive an address ADDR and data DATA together with the command CMD. The address ADDR may correspond to the first region and the second region, and the data DATA may include a bit of calibration data and an inverted bit.

[0075] In some embodiments, Fig. 9 , operations S110 and S120 may be performed sequentially. For example, the memory device 50 may receive a command CMD indicating a write operation, an address ADDR, and data DATA. The address ADDR may correspond to the first region, and the data DATA may include a bit of calibration data. Next, the memory device 50 may receive a command CMD indicating a write operation, an address ADDR, and data DATA. The address ADDR may correspond to the second region, and the data DATA may include an inverted bit of calibration data.

[0076] In operation S130, the bits of the calibration data may be read. For example, the memory device 50 may receive a command CMD indicating a read operation and an address ADDR corresponding to the first region and the second region. The memory device 50 may determine the bits of the calibration data by simultaneously detecting the bits stored in the first region in operation S110 and the inverted bits stored in the second region in operation S120, and output the bits of the calibration data. Fig.10 and Fig.11 An example of operation S130 is described below. Subsequently, the calibration data may be used to calibrate a cell array of the memory device, for example, by setting a resistance of a variable resistor used during a normal read operation.

[0077] Fig.10 is a flow chart of an operating method of a memory device according to an embodiment. For example, Fig.10 The flowchart in FIG. 1 shows a method of operating a memory device for writing and reading calibration data. Fig.10As shown, the operating method of the memory device may include a plurality of operations S111, S112, S121, S122, and S130', and the operation S130' may include operations S131 and S132. In some embodiments, Fig.10 Operations S111 and S112 in may be included in Fig. 9 In operation S110, Fig.10 Operations S121 and S122 in may be included in Fig. 9 In operation S120, and Fig.10 Operation S130′ in may be Fig. 9 In some embodiments, Fig.10 The method can be Fig. 7A Executed by the memory device 70a in the following. Fig. 7A describe Fig.10 , and omit Fig.10 With reference to the accompanying drawings Fig. 7A The description is the same as the description of .

[0078] Reference Fig.10 In operation S111, the first bit of the calibration data may be written into a memory cell connected to one of the two word lines in the first portion SEC1. For example, the row decoder 72 may activate the word line WL21, and the first bit of the calibration data may be written into the memory cell M121 connected to the word line WL21 in the first portion SEC1.

[0079] In operation S121, the first inverted bit of the calibration data may be written into a memory cell connected to one of the two word lines in the second portion SEC2. For example, the row decoder 72 may activate the word line WL21, and the first inverted bit of the calibration data may be written into the memory cell M221 connected to the word line WL21 in the second portion SEC2.

[0080] In operation S112, the first bit of the calibration data may be written into a memory cell connected to the other of the two word lines in the first portion SEC1. For example, the row decoder 72 may activate the word line WL22, and the first bit of the calibration data may be written into the memory cell M122 connected to the word line WL22 in the first portion SEC1.

[0081] In operation S122, the first inverted bit of the calibration data may be written into a memory cell connected to the other of the two word lines in the second portion SEC2. For example, the row decoder 72 may activate the word line WL22, and the first inverted bit of the calibration data may be written into the memory cell M222 connected to the word line WL22 in the second portion SEC2.

[0082] In some embodiments, Fig.10 As shown, operations S111 and S121 may be performed in parallel, and operations S112 and S122 may be performed in parallel. Fig.10 Unlike shown in , operations S111, S121, S112, and S122 may be performed independently of each other.

[0083] In operation S131, two word lines connected to the memory cells storing calibration data in a group of word lines may be activated at the same time. For example, the memory device 70a may receive a command CMD indicating a read operation and an address ADDR corresponding to the two word lines. The row decoder 72 may activate the two word lines WL21 and WL22 at the same time, and therefore, the memory cells M121 and M122 of the first section SEC1 and the memory cells M221 and M222 of the second section SEC2 may be selected at the same time.

[0084] In operation S132, the first bit may be read. For example, the read circuit 75 may compare the currents of the memory cells M121 and M122 passing through the first section SEC1 with the currents of the memory cells M221 and M222 passing through the second section SEC2, and determine the first bit corresponding to the comparison result. The read circuit 75 may output the data signal D_OUT including the determined first bit.

[0085] Fig.11 is a flow chart of an operating method of a memory device according to an embodiment. For example, Fig.11 The flowchart shows Fig. 9 As shown above with reference to the example of operation S130 in Fig. 9 As described, Fig.11 In operation S130 in the embodiment, the calibration data is read. Fig.11 As shown, operation S130" may include operations S133 and S134. In some embodiments, Fig.11 Operation S130" in Figure 7B Executed by the memory device 70b in the embodiment. Figure 7B describe Fig.11 , and omit Fig.11 With reference to the accompanying drawings Figure 7B The description is the same as the description of .

[0086] Reference Fig.11, in operation S133, the repeated bits in the first region and the repeated inverted bits in the second region may be detected simultaneously. For example, the memory device 70b may receive a command CMD indicating a read operation, and an address ADDR and data DATA corresponding to the first region and / or the second region. The data DATA may include repeated bits, and the repeated bits may be written to the memory cells M121 and M122 of the first portion SEC1 that are commonly connected to the second word line WL2, respectively. In addition, the repeated inverted bits may be written to the memory cells M221 and M222 of the second portion SEC2 that are commonly connected to the second word line WL2, respectively. For example, the memory device 70b may receive a command CMD indicating a read operation, and an address ADDR corresponding to the first region and / or the second region. The row decoder 72 may activate the second word line WL2. The first column decoder 73 may select two bit lines BL12 and BL13, and the second column decoder 74 may select two bit lines BL22 and BL23. The read circuit 75 can simultaneously detect the sum of the currents of the memory cells M121 and M122 passing through the first portion SEC1 and the sum of the currents of the memory cells M221 and M222 passing through the second portion SEC2 and compare the sum of the currents of the memory cells M121 and M122 passing through the first portion SEC1 with the sum of the currents of the memory cells M221 and M222 passing through the second portion SEC2, and determine the first bit corresponding to the comparison result. The read circuit 75 can output the data signal D_OUT including the determined first bit.

[0087] Fig.12 is a flow chart of an operating method of a memory device according to an embodiment. For example, Fig.12 The flowchart in FIG. 1 shows a method of operating a memory device for writing and reading user data. In some embodiments, Fig.12 The method can be executed in normal mode. Fig.12 As shown, the operating method of the memory device may include a plurality of operations S210, S220, S230 and S240. In some embodiments, Fig.12 The method can be Figure 4A and Figure 4B Executed by the memory device 40 in the embodiment. Figure 4A and Figure 4B describe Fig.12 .

[0088] Reference Fig.12, in operation S210, bits of first user data may be written into the third region of the first portion SEC1. The third region may include memory cells in the first portion SEC1 for storing user data, for example, memory cells connected to the first word line WL1. The row decoder 42 may activate the first word line WL1, and may write bits of the first user data into the memory cells M11 in the first portion SEC1 connected to the first word line WL1.

[0089] In operation S220, bits of the second user data may be written into a fourth region of the second portion SEC2. The fourth region may include memory cells in the second portion SEC2 for storing user data, for example, memory cells connected to the first word line WL1. The row decoder 42 may activate the first word line WL1, and bits of the second user data may be written into the memory cells M21 in the second portion SEC2 connected to the first word line WL1.

[0090] In some embodiments, Fig.12 As shown, operations S210 and S220 may be performed sequentially. For example, the memory device 40 may receive a command CMD indicating a write operation, an address ADDR, and data DATA. The address ADDR may correspond to the third region, and the data DATA may include bits of the first user data. Next, the memory device 40 may receive a command CMD indicating a write operation, an address ADDR, and data DATA. The address ADDR may correspond to the fourth region, and the data DATA may include bits of the second user data.

[0091] In some embodiments, Fig.12 Unlike the example shown, operations S210 and S220 may be performed in parallel. For example, operations S210 and S220 may be performed in parallel in response to one command CMD indicating a write operation. The memory device 40 may receive an address ADDR and data DATA together with the command CMD. The address ADDR may correspond to the third region and the fourth region, and the data DATA may include bits of the first user data and bits of the second user data.

[0092] In operation S230, a bit of the first user data may be read. For example, the memory device 40 may receive a command CMD indicating a read operation and an address ADDR corresponding to the third region. The read circuit 45 may determine a bit of the first user data stored in the memory cell M11 based on the memory cell M11 of the first portion SEC1 and the reference cell R21 of the second portion SEC2, and generate a data signal D_OUT including the determined bit.

[0093] In operation S240, the bit of the second user data may be read. For example, the memory device 40 may receive a command CMD indicating a read operation and an address ADDR corresponding to the fourth region. The read circuit 45 may determine the bit of the second user data stored in the memory cell M21 based on the memory cell M21 of the second portion SEC2 and the reference cell R11 of the first portion SEC1, and generate a data signal D_OUT including the determined bit.

[0094] In some embodiments, operations S230 and S240 may be sequentially performed in response to one command CMD indicating a read operation. For example, the address ADDR received together with the command CMD may correspond to the third region and the fourth region, and the memory device 40 may read the value stored in the memory cell M21 of the second portion SEC2 after reading the value stored in the memory cell M11 of the first portion SEC1.

[0095] Fig.13 1 is a block diagram of a memory system 131 including a memory device according to an embodiment. Fig.13 As shown, the memory system 131 may communicate with the host 132 and may include a controller MC and a memory device MEM.

[0096] The interface 133 that communicates with the memory system 131 and the host 132 may use electrical signals and / or optical signals, and may be implemented as a non-limiting example as a Serial Advanced Technology Attachment (SATA) interface, a SATA Express (SATAe) interface, a Serial Attached Small Computer System Interface (Serial Attached SCSI; SAS), a Peripheral Component Interconnect Express (PCIe) interface, a Non-Volatile Memory Express (NVMe) interface, a Universal Flash Memory (UFS) interface, an Advanced Host Controller Interface (AHCI), or a combination of two or more thereof.

[0097] In some embodiments, the memory system 131 can communicate with the host 132 by being removably coupled to the host 132. As a resistive memory, the memory device MEM can be a non-volatile memory, and the memory system 131 can also be referred to as a storage system. For example, as a non-limiting example, the memory system 131 can be implemented as a solid state drive or solid state disk (SSD), an embedded SSD (eSSD), a multimedia card (MMc), an embedded multimedia card (eMMC), etc.

[0098] The controller MC may control the memory device MEM in response to a request received from the host 132 via the interface 133. For example, in response to a write request, the controller MC may write data received together with the write request into the memory device MEM, and in response to a read request, the controller MC may provide data stored in the memory device MEM to the host 132.

[0099] The memory system 131 may include at least one memory device MEM, and the memory device MEM may include a memory cell and a reference cell having a variable resistance element. As described above with reference to the accompanying drawings, the memory device MEM may store calibration data for calibrating the memory device MEM in a cell array, and when the memory system 131 is powered, the controller MC or the memory device MEM may read the calibration data and set the memory device MEM based on the calibration data. Therefore, a separate storage device for storing calibration data may be omitted. During operation, the controller MC may also include a control circuit system configured to (e.g., in response to a command received from the host 132) control the memory device MEM to perform a combination of Figures 1 to 12 Therefore, the memory device MEM and the memory system 131 may be configured to perform the various read operations, write operations, and calibration operations described herein.

[0100] Fig.14 1 is a block diagram of a system on chip 140 including a memory device according to an embodiment. SoC 140 may refer to an integrated circuit that integrates components of a computing system or other electronic system. For example, an application processor (AP), which is one of SoC 140, may include a processor and components for other functions. Fig.14 As shown, SoC 140 may include a core 141, a digital signal processor (DSP) 142, a graphics processing unit (GPU) 143, a built-in memory 144, a communication interface 145, and a memory interface 146. The elements of SoC 140 may communicate with each other via a bus 147.

[0101] The core 141 may process instructions and control the operations of the elements included in the SoC 140. For example, the core 141 may process a series of instructions and drive an operating system, and execute an application on the operating system. The DSP 142 may generate useful data by processing a digital signal (e.g., a digital signal provided from the communication interface 145). The GPU 143 may generate data for an image output through a display device from image data provided from the built-in memory 144 or the memory interface 146, and encode the image data.

[0102] The built-in memory 144 may store data necessary for the operation of the core 141, the DSP 142, and the GPU 143. The built-in memory 144 may include a memory device according to an embodiment, and therefore, a storage device for storing calibration data of the memory device may be omitted in the SoC 140. The communication interface 145 may provide an interface for a communication network or one-to-one communication. The memory interface 146 may provide an interface to an external memory (e.g., a dynamic random access memory (DRAM) and a flash memory) of the SoC 140.

[0103] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory device, comprising: a cell array including a first portion and a second portion sharing a plurality of word lines, the plurality of word lines including a first group of word lines and a second group of word lines; a first column decoder configured to select at least one bit line of a first set of bit lines connected to the first portion; a second column decoder configured to select at least one bit line of a second set of bit lines connected to the second portion; as well as a read circuit configured to output a data signal based on a comparison between an output of the first column decoder and an output of the second column decoder, wherein the first portion includes a plurality of first memory cells connected to at least one word line of the first group of word lines and configured to store bits of calibration data for calibrating the memory device, and The second portion includes a plurality of second memory cells connected to the at least one word line and configured to store inverted bits of the calibration data. 2 . The memory device of claim 1 , further comprising an address decoder configured to provide column addresses corresponding to each other to the first column decoder and the second column decoder, respectively, as part of reading the calibration data.

3. The memory device of claim 1, wherein: The first portion further includes a plurality of third memory cells connected to the second group of word lines and configured to store first user data, and The second portion also includes a plurality of fourth memory cells connected to the second group of word lines and configured to store second user data.

4. The memory device of claim 3, wherein: The first portion also includes a plurality of first reference cells connected to the second set of word lines, and The second portion also includes a plurality of second reference cells connected to the second set of word lines.

5. The memory device of claim 4, wherein: The first column decoder is configured to select a first bit line connected to the plurality of first reference cells from the first group of bit lines as part of reading the second user data, and The second column decoder is configured to select a second bit line connected to the plurality of second reference cells from the second group of bit lines as part of reading the first user data.

6. The memory device of claim 4 , further comprising a variable resistor circuit configured to provide a variable resistance, in, The read circuit is configured to electrically connect the variable resistor circuit to a second bit line connected to the plurality of second reference cells in the second group of bit lines as a portion for reading the first user data, and to electrically connect the variable resistor circuit to a first bit line connected to the plurality of first reference cells in the first group of bit lines as a portion for reading the second user data.

7. The memory device according to claim 6, wherein: The read circuit is configured to electrically disconnect the variable resistor circuit from the first and second sets of bit lines as part of reading the calibration data.

8. The memory device of claim 1, wherein: The first group of word lines includes a plurality of word lines, and The memory device also includes a row driver configured to simultaneously activate two or more word lines of the first set of word lines as part of reading the calibration data.

9. The memory device of claim 1, wherein: The first column decoder is configured to simultaneously select two or more bit lines from the first group of bit lines as part of reading the calibration data, and The second column decoder is configured to simultaneously select two or more second bit lines from the second group of bit lines as part of reading the calibration data.

10. A memory device comprising: a cell array including a first portion and a second portion sharing a plurality of word lines; a first column decoder connected to the first portion via a first set of bit lines from a plurality of bit lines; a second column decoder connected to the second portion via a second set of bit lines of the plurality of bit lines; a read circuit configured to output a data signal based on a comparison between an output of the first column decoder and an output of the second column decoder; as well as An address decoder is configured to provide the first column decoder and the second column decoder with column addresses corresponding to each other, respectively, when calibration data for calibrating the memory device is read.

11. The memory device of claim 10, wherein: The first portion includes a plurality of first memory cells connected to at least one word line of a first group of word lines of the plurality of word lines and configured to store bits of the calibration data, and The second portion includes a plurality of second memory cells connected to the at least one word line and configured to store inverted bits of the bits of the calibration data.

12. The memory device of claim 11, wherein: The first portion further includes a plurality of third memory cells connected to a second group of word lines among the plurality of word lines and configured to store first user data, and The second portion also includes a plurality of fourth memory cells connected to the second group of word lines and configured to store second user data.

13. A method for operating a memory device, wherein: The memory device includes a cell array, the cell array includes a first portion and a second portion sharing a plurality of word lines, and the operating method includes: In response to at least one first write command, write bits of calibration data for calibrating the memory device into a first area of ​​the first portion, and write inverse bits of the bits of the calibration data into a second area of ​​the second portion; and The bits of the calibration data are read by simultaneously detecting the bits stored in the first area and the inverted bits stored in the second area in response to a first read command.

14. The operating method according to claim 13, wherein: The first region and the second region share at least one word line of the plurality of word lines, and Reading a bit of the calibration data includes activating the at least one word line.

15. The operating method according to claim 13, further comprising: In response to at least one second write command, bits of first user data are written into a third area of ​​the first portion, and bits of second user data are written into a fourth area of ​​the second portion.

16. The operating method according to claim 15, wherein: Each of the first portion and the second portion includes a reference cell, and The operation method also includes: In response to a second read command, reading bits of the first user data based on bits stored in the third area and reference cells of the second portion; or In response to the second read command, bits of the second user data are read based on bits stored in the fourth area and reference cells of the first portion.

17. The operating method according to claim 16, wherein: The memory device is configured to be set to a calibration mode or a normal mode, receiving the at least one first write command and the first read command in the calibration mode, and The at least one second write command, the second read command and a third read command are received in the normal mode.

18. The operating method according to claim 13, wherein: The bits written to the calibration data include: writing a first bit of the calibration data into a memory cell in the first portion connected to a first word line of the plurality of word lines; and writing the first bit to a memory cell in the first portion connected to a second word line of the plurality of word lines, and Writing the negated bit includes: writing a first inverted bit of a first set of bits of the calibration data into a memory cell in the second portion connected to the first word line; and The first bar bit is written to memory cells in the second portion connected to the second word line.

19. The operating method according to claim 18, wherein: Reading a bit of the calibration data includes activating the first word line and the second word line simultaneously.

20. The operating method according to claim 13, wherein: The bits of the calibration data include repeated bits, The inverted bits of the calibration data bits include repeated inverted bits, and Reading bits of the calibration data includes simultaneously detecting repeated bits stored in two or more memory cells of the first region and repeated inverted bits stored in two or more memory cells of the second region.

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