In-depth evaluation method and system for on-die ECC memory

Abstract

The present invention provides a deep evaluation method and system for an on-die ECC memory. The deep evaluation method and system for the on-die ECC memory introduce ECS to record the number of actual repairs and errors in the memory. Specifically, by turning on and off the manual ECS mode of the on-die ECC memory, multiple rounds of cyclic ECS tests are performed on the on-die ECC memory according to gradually tightened test parameters to obtain a fault number evolution table, and then the fault number evolution table is compared with a pre-acquired natural test fault table of the on-die ECC memory to obtain the test parameter margin, the maximum tolerable fault number, and the remaining percentage of the maximum tolerable fault number of the on-die ECC memory, thereby reflecting the actual evaluation situation of the on-die ECC memory, avoiding the situation where test distortion due to ECC self-repair is caused, and improving the accuracy and authenticity of the memory test.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor testing technology, and more specifically, to a method and system for evaluating a memory. Background Art

[0002] DRAM (Dynamic Random Access Memory) chips are unique in design, and chip failures in various application scenarios have always been difficult to eliminate. Therefore, DRAM chip testing and quality control has always been a difficult issue. With the emergence of On-Die ECC (On-Die Error-Correcting Code) technology, ECC's powerful error correction capability can well conceal quality problems inside the chip, which will cause errors in testing. As a result, the following existing test methods will produce distorted results, which cannot reflect the true aging and test effects:

[0003] 1. Chip aging and packaging reliability testing: High Temperature Storage (HTS), High Temperature Operating Life (HTOL), Temperature Cycling, Highly Accelerated Life Testing (HALT), High Humidity Storage (HHS), Bias Temperature Humidity (BTH).

[0004] 2. Test algorithm stress test: The test algorithm will develop in a diversified manner according to the test scenarios and equipment and can be roughly divided into three types: a) voltage and current test; b) chip timing and functional test; c) interface signal and power integrity test.

[0005] The above two types of tests are the main test methods for DRAM, which are used as chip quality inspection standards. Both are effective methods for testing ordinary DRAM chips, and their judgment methods usually have standard values. For example, assuming that the test standard is tRCD=15ns, the measured value of this parameter is 16ns. If it exceeds the standard, it can be judged as a substandard product. However, this method has been broken by the emergence of On Die ECC. When the same chip is equipped with ECC function, the measurement parameters will be greatly improved (less than 15ns) through its correction ability, so it is judged as a superior product. The function of ECC greatly increases the reliability of the application end, but the goal of the test inspection is to inspect the chip process and design performance. The development of ECC's design performance has led to serious errors in our previous method of detecting chip process capabilities, which seriously affects the test's recognition standard for quality control.

[0006] Therefore, there is an urgent need for an in-depth evaluation method and system for on-die ECC memory that can truly reflect the internal status of the on-die ECC memory and improve detection accuracy. Summary of the invention

[0007] In view of the above problems, the purpose of the present invention is to provide a deep evaluation method for on-die ECC memory to solve the problem that the On-Die ECC (On-Die Error-Correcting Code) technology emerges. The powerful error correction capability of ECC can well conceal the quality problems existing inside the chip, which will bring errors to the test. As a result, the following existing test methods will obtain distorted results, which cannot reflect the technical problem of its true aging and test effect.

[0008] The present invention provides a deep evaluation method for an on-die ECC memory, comprising:

[0009] Performing multiple rounds of cyclic ECS tests on the on-die ECC memory by turning on and off the manual ECS mode of the on-die ECC memory to obtain a failure number evolution table; wherein the test parameters of each round of testing are gradually tightened according to a preset gradient;

[0010] The fault number evolution table is compared with the pre-acquired natural test fault table of the on die ECC memory to obtain the test parameter margin, the maximum tolerable fault number, and the remaining percentage of the maximum tolerable fault number of the on die ECC memory; wherein,

[0011] The step of pre-acquiring a natural test fault table of the on-die ECC memory comprises:

[0012] The ondie ECC memory is subjected to multiple rounds of natural testing in sequence according to the order of the test parameters used when obtaining the fault frequency evolution table to obtain a natural test fault table; wherein,

[0013] The natural test fault data in the natural test fault table correspond to the number of fault occurrences in the fault number evolution table in a one-to-one manner in an order in which the test parameters are gradually tightened;

[0014] The process of obtaining natural test failure data during each round of natural testing includes:

[0015] Writing the background data used for the ECS test corresponding to the current round of natural testing into the on-die ECC memory for testing to obtain process missing data;

[0016] Writing the test data used in the ECS test corresponding to the current round of natural testing into the on-die ECC memory to perform write and read tests respectively to obtain write fault data and read fault data;

[0017] adding the process missing data, the write failure data and the read failure data to obtain natural test failure data;

[0018] The step of comparing the failure number evolution table with a pre-acquired natural test failure table of the on-die ECC memory comprises:

[0019] The test parameters that are gradually tightened according to the preset gradient are used as the horizontal axis, and the number of fault occurrences and natural test fault data corresponding to the test parameters are used as the vertical axis corresponding to the test parameters, so that the fault number evolution table and the natural test fault table are overlapped on the horizontal axis, and the fault number evolution table and the natural test fault table are distinguished by different colors to form a composite bar chart with different colors as a comparison chart;

[0020] The process of obtaining the maximum tolerable fault number of the on-die ECC memory includes:

[0021] Traversing the natural test failure data in the comparison chart in sequence, locking the first histogram whose natural test failure data is greater than zero as the initial ECC failure histogram;

[0022] Taking the test parameter on the abscissa where the initial ECC fault histogram is located as the maximum tolerated fault number;

[0023] The process of obtaining the test parameter margin of the on die ECC memory includes:

[0024] Obtain standard test parameter values ​​set by chip vendors in accordance with JEDEC or test standards;

[0025] Subtract the standard test parameter value from the maximum tolerated fault number to obtain a test parameter margin;

[0026] The process of obtaining the remaining percentage of the maximum number of tolerated failures of the on-die ECC memory includes:

[0027] The number of fault occurrences corresponding to the standard test parameter value is obtained as the initial number of fault occurrences; the number of fault occurrences corresponding to the maximum tolerated fault number is obtained as the maximum tolerated actual number of fault occurrences;

[0028] The maximum tolerated actual fault occurrence number is used as the denominator, and the difference between the maximum tolerated actual fault occurrence number and the initial fault occurrence number is used as the numerator to obtain the remaining percentage of the maximum tolerated fault number.

[0029] Preferably, the step of performing multiple rounds of cyclic ECS testing to obtain a failure frequency evolution table includes:

[0030] Each round of ECS testing is performed in sequence according to different test parameters to generate the number of failures corresponding to each round of ECS testing;

[0031] The fault occurrence times are arranged in a corresponding order according to the order of the test parameters to form a fault number evolution table.

[0032] Preferably, the step of generating the number of failure occurrences corresponding to each round of ECS testing includes:

[0033] Writing background information about test parameters for the on die ECC memory, and sending an MPC instruction through the on die ECC memory to turn on the manual ECS mode of the on die ECC memory, so that the ECS counter of the on die ECC memory obtains the number of process misses of the on die ECC memory, and turns off the manual ECS mode;

[0034] Writing the test data about the test parameters into the on die ECC memory, and sending an MPC instruction through the on die ECC memory to start the manual ECS mode of the on die ECC memory, so that the ECS counter of the on die ECC memory obtains the number of write failures related to the write action of the on die ECC memory, and closes the manual ECS mode;

[0035] Enable the on-die ECC memory to read the data to be tested, and send an MPC instruction through the on-die ECC memory to enable a manual ECS mode of the on-die ECC memory, so that an ECS counter of the on-die ECC memory obtains a number of read failures of the on-die ECC memory related to a read action, and disables the manual ECS mode;

[0036] The number of process misses, the number of write failures, and the number of read failures are added together to form the number of failure occurrences.

[0037] The present invention also provides a deep evaluation system for an on-die ECC memory, wherein the deep evaluation method for an on-die ECC memory as described above is implemented, including:

[0038] An actual fault number verification module is used to perform multiple rounds of cyclic ECS tests on the on-die ECC memory by turning on and off the manual ECS mode of the on-die ECC memory to obtain a fault number evolution table; wherein the test parameters of each round of testing are gradually tightened according to a preset gradient;

[0039] The actual and natural fault comparison module is used to compare the fault number evolution table with the pre-acquired natural test fault table of the on die ECC memory to obtain the test parameter margin, the maximum number of tolerable faults, and the remaining percentage of the maximum number of tolerable faults of the on die ECC memory; wherein the step of pre-acquiring the natural test fault table of the on die ECC memory includes:

[0040] The ondie ECC memory is subjected to multiple rounds of natural testing in sequence according to the order of the test parameters used when obtaining the fault frequency evolution table to obtain a natural test fault table; wherein,

[0041] The natural test fault data in the natural test fault table correspond to the number of fault occurrences in the fault number evolution table in a one-to-one manner in an order in which the test parameters are gradually tightened;

[0042] The process of obtaining natural test failure data during each round of natural testing includes:

[0043] Writing the background data used for the ECS test corresponding to the current round of natural testing into the on-die ECC memory for testing to obtain process missing data;

[0044] Writing the test data used in the ECS test corresponding to the current round of natural testing into the on-die ECC memory to perform write and read tests respectively to obtain write fault data and read fault data;

[0045] adding the process missing data, the write failure data and the read failure data to obtain natural test failure data;

[0046] The step of comparing the failure number evolution table with a pre-acquired natural test failure table of the on-die ECC memory comprises:

[0047] The test parameters that are gradually tightened according to the preset gradient are used as the horizontal axis, and the number of fault occurrences and natural test fault data corresponding to the test parameters are used as the vertical axis corresponding to the test parameters, so that the fault number evolution table and the natural test fault table are overlapped on the horizontal axis, and the fault number evolution table and the natural test fault table are distinguished by different colors to form a composite bar chart with different colors as a comparison chart;

[0048] The process of obtaining the maximum tolerable fault number of the on-die ECC memory includes:

[0049] Traversing the natural test failure data in the comparison chart in sequence, locking the first histogram whose natural test failure data is greater than zero as the initial ECC failure histogram;

[0050] Taking the test parameter on the abscissa where the initial ECC fault histogram is located as the maximum tolerated fault number;

[0051] The process of obtaining the test parameter margin of the on die ECC memory includes:

[0052] Obtain standard test parameter values ​​set by chip vendors in accordance with JEDEC or test standards;

[0053] Subtract the standard test parameter value from the maximum tolerated fault number to obtain a test parameter margin;

[0054] The process of obtaining the remaining percentage of the maximum number of tolerated failures of the on-die ECC memory includes:

[0055] The number of fault occurrences corresponding to the standard test parameter value is obtained as the initial number of fault occurrences; the number of fault occurrences corresponding to the maximum tolerated fault number is obtained as the maximum tolerated actual number of fault occurrences;

[0056] The maximum tolerated actual fault occurrence number is used as the denominator, and the difference between the maximum tolerated actual fault occurrence number and the initial fault occurrence number is used as the numerator to obtain the remaining percentage of the maximum tolerated fault number.

[0057] It can be seen from the above technical scheme that the in-depth evaluation method and system for on-die ECC memory provided by the present invention introduce ECS to record the actual number of repairs and errors inside the memory. Specifically, by turning on and off the manual ECS mode of the on-die ECC memory, the on-die ECC memory is subjected to multiple rounds of cyclic ECS testing according to gradually tightened test parameters to obtain a fault number evolution table, and then the fault number evolution table is compared with the pre-acquired natural test fault table of the on-die ECC memory to obtain the test parameter margin, the maximum tolerable number of faults, and the remaining percentage of the maximum tolerable number of faults of the on-die ECC memory, thereby reflecting the actual evaluation situation of the on-die ECC memory, avoiding the test distortion caused by ECC self-repair, and improving the accuracy and authenticity of the memory test. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more clear and easy to understand. In the accompanying drawings:

[0059] Figure 1 A flowchart of a depth evaluation method for an on-die ECC memory according to an embodiment of the present invention;

[0060] Figure 2 A schematic diagram of performing an ECS test in a deep evaluation method for an on-die ECC memory according to an embodiment of the present invention;

[0061] Figure 3 A comparison diagram of tREFI test parameter evaluation in a deep evaluation method for an on-die ECC memory according to an embodiment of the present invention;

[0062] Figure 4 A comparison diagram of tRP test parameter evaluation in a deep evaluation method for an on-die ECC memory according to an embodiment of the present invention;

[0063] Figure 5 Schematic diagram of a deep evaluation system for an on-die ECC memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0064] The emergence of On-Die ECC (On-Die Error-Correcting Code) technology and the powerful error correction capability of ECC can effectively conceal the quality problems inside the chip, which will cause errors in the test. As a result, the following existing test methods will produce distorted results, which cannot reflect the true aging and test effects.

[0065] In view of the above problems, the present invention provides a method and system for in-depth evaluation of on-die ECC memory. The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0066] In order to illustrate the in-depth evaluation method and system for on-die ECC memory provided by the present invention, Figure 1-Figure 4 The embodiments of the present invention are exemplarily indicated.

[0067] The following description of exemplary embodiments is merely illustrative in nature and is not intended to limit the present invention and its application or use. Technologies and devices known to ordinary technicians in the relevant field may not be discussed in detail, but in appropriate cases, the technologies and devices should be considered as part of the specification.

[0068] like Figure 1 , Figure 2 As shown together, the in-depth evaluation method for on-die ECC memory provided by the present invention includes:

[0069] S1: performing multiple rounds of ECS tests on the on-die ECC memory by turning on and off a manual ECS (Error check and scrub) mode of the on-die ECC memory to obtain a failure count evolution table; wherein the test parameters of each round of the test are gradually tightened according to a preset gradient;

[0070] S2: Compare the fault count evolution table with the pre-acquired natural test fault table of the on die ECC memory to obtain the test parameter margin, the maximum tolerable fault number, and the remaining percentage of the maximum tolerable fault number of the on die ECC memory.

[0071] In this embodiment, Figure 2The steps of performing multiple rounds of ECS testing are shown. Step S1 is essentially to obtain the number of actual failures in the on-die ECC memory through ECS. In the on-die ECC memory, there is a component called ECS address counters. The function of On Die ECC is to logically correct bit flip errors, and it cannot repair the errors of the storage units inside the chip. The function of ECS is to locate the error address inside the chip according to the results of ECC, thereby repairing the storage units inside the chip, and the ECS address counters count the failures and the number of repairs. However, in actual use, the repair function of the ECS cannot be started. Therefore, by manually turning on the ECS, the actual number of errors in the storage units inside the chip can be obtained through the ECS counter. However, it should be noted that when ECS is manually turned on for testing, the On Die ECC function is also running synchronously. By counting the actual number of errors recorded by the ECS counter for test parameters of different intensities and the number of errors made by test parameters of different intensities under normal testing, the repair capability and fault conditions of the On Die ECC function can be clearly obtained, thereby making an in-depth evaluation of the on die ECC memory.

[0072] Specifically, the step of performing multiple rounds of cyclic ECS tests in step S1 to obtain a fault frequency evolution table includes:

[0073] S11: performing each round of ECS testing in sequence according to different test parameters to generate the number of fault occurrences corresponding to each round of ECS testing;

[0074] S12: Arrange the fault occurrence times in a corresponding order according to the order of the test parameters to form a fault frequency evolution table.

[0075] Among them, Figure 2 As shown, the steps of generating the number of failures corresponding to each round of ECS testing include:

[0076] S111: writing background information about test parameters for the on die ECC memory, and sending an MPC instruction through the on die ECC memory to enable a manual ECS mode of the on die ECC memory, so that an ECS counter of the on die ECC memory obtains the number of process misses of the on die ECC memory, and closes the manual ECS mode;

[0077] S112: writing the test data about the test parameters into the on-die ECC memory, and sending an MPC instruction through the on-die ECC memory to enable the manual ECS mode of the on-die ECC memory, so that the ECS counter of the on-die ECC memory obtains the number of write failures related to the write action of the on-die ECC memory, and closes the manual ECS mode;

[0078] S113: enabling the on die ECC memory to read the data to be tested, and sending an MPC instruction through the on die ECC memory to enable a manual ECS mode of the on die ECC memory, so that an ECS counter of the on die ECC memory obtains a number of read failures related to a read action of the on die ECC memory, and disables the manual ECS mode;

[0079] S114: Add the number of process misses, the number of write failures, and the number of read failures to form a number of failure occurrences.

[0080] like Figure 3 As shown, Figure 3 The test parameter is tREFI, Figure 4 The test parameter is tRP, that is, the on-die ECC memory is tested in terms of tREFI and tRP. Figure 3 , Figure 4 The gray bar graph shown is the number of faults of the on-die ECC memory under different test parameters when the manual ECS mode is enabled. In the figure, the tRP parameter is gradually tightened from left to right. As shown in the figure, as the test parameters are tightened, the number of faults recorded by the ECS counter also gradually increases. That is, the gray part refers to the number of faults read from the ECS count (ECS counter). Most of the faults in this part will be repaired by the ECS and the built-in ECC that are manually enabled after we execute the MPC (manual ECS mode) command. Therefore, no faults will occur during normal reading, and only the number of repairs will be recorded in the ECS count. The number of repairs is the total number of actual faults. The black part is the number of data faults read when the MPC command is not enabled, that is, when the manual ECS mode is not enabled, the number of faults that exist when only ECC repairs are used. In other words, it is the number of faults that cannot be repaired by ECC.

[0081] The reason for the gradual increase is that the test parameters are gradually tightened, resulting in an increasing number of failures. This phenomenon occurs regardless of ECS count or normal reading. The gray color must appear earlier than the black color (test parameters), and the number of gray colors must be greater than the black color (only when ECS and ECC cannot repair the part successfully will it be reflected in black).

[0082] ECS repairs and records the number of errors by sending MPC commands (manual ECS mode). Each time an MPC command is sent, the chip will perform a self-check on 128 bits (the amount of data in a read command), and when an error is found in the new chip, the correct data will be automatically copied to the storage unit and recorded in the ECS count (ECS counter).

[0083] The function of On Die ECC is to logically correct the error of bit flipping, but it cannot repair the error of storage unit inside the chip. The function of ECS is to locate the error address according to the result of ECC, so as to repair the storage unit. As mentioned above, this quality assessment method is applicable to the relevant parameters that may cause bit flipping inside the chip as test parameters, such as: Trcd, Twr, Trp, Trc, Trefi, Trfc, tCCD, tWTR, and its flow chart is shown above in a more specific embodiment:

[0084] First, write the initial background data (full chip): The purpose of this action is to solidify the background data of the parameters to be tested to avoid errors in the measurement of the parameters to be tested, which affects the fairness of the test.

[0085] Perform the first ECS reading: Since no test parameter debugging is performed, the ECScount that appears at the moment reflects the number of serious deficiencies in the chip process (the part of the ECS count that does not change after parameter debugging), and can also be used as an ECS count deduction item during chip parameter debugging (whether to deduct can be determined independently, which is a part of quality assessment). In this specific embodiment, no deduction is made, that is, the number of process deficiencies.

[0086] Writing of data to be tested: debugging of test parameters related to chip writing action (the test parameters can be Twr or Trp or Trfc or Trefi or tCCD). Second ECS reading: confirm the ECS count caused by the test parameters related to writing, and record its value in the gray line part of ECS error&Test Parameter. If the debugging of the test parameters does not exist in the writing process, it is omitted. Reading of data to be tested: debugging of test parameters related to chip reading action (the test parameters can be Trcd or Trp or tRFCt or REFI or tCCD), that is, the number of write failures is formed.

[0087] The third ECS read: Confirm the ECS count caused by the test parameters related to the read, and record its value in the gray line part of ECS error&Test Parameter, that is, the number of read failures. If the parameter debugging to be tested does not exist in the reading process, it will be omitted.

[0088] The total number of failures is calculated by adding them up.

[0089] By gradually increasing the difficulty of the test parameters and repeating the above steps, the results of the gray line part can be obtained. Among them, the on-die ECC circuit cannot be turned off. The exact time of taking effect is when a read command is issued to the DRAM (Dynamic Random Access Memory), and an ECC check will be performed on the read command (128bit). The ECS count reading is triggered by other commands and will not trigger the on-die ECC at the moment. MPC (manual ECS mode) has an internal circuit with the same function as the on-die ECC (shareable), but adds storage unit repair and records the number of repair times. Another difference is that on-die ECC feeds back the corrected data on the IO interface, but the errors on the chip storage unit are not corrected. MPC (manual ECS) actually repairs the errors in the storage unit but does not feed back the results to IO. The black line part removes all ECS counts in the process, and the data can be obtained directly from the number of faults read from the data to be tested. The above is an explanation of the complete process of ECS count reading. In the process, it should be noted that the activation of ECS will actually repair the errors of the faulty pen bit. Adjust the ECS running time point and reset the ECS count according to the test requirements to avoid errors in the test.

[0090] Step S2 is a process of comparing the fault frequency evolution table with the pre-acquired natural test fault table of the on die ECC memory to obtain the test parameter margin, the maximum tolerable fault number, and the remaining percentage of the maximum tolerable fault number of the on die ECC memory.

[0091] The step of pre-obtaining the natural test fault table of the on-die ECC memory includes:

[0092] The ondie ECC memory is subjected to multiple rounds of natural testing in sequence according to the order of the test parameters used when obtaining the fault frequency evolution table to obtain a natural test fault table; wherein,

[0093] The natural test failure data in the natural test failure table correspond one-to-one to the number of failure occurrences in the failure number evolution table in the order in which the test parameters are gradually tightened.

[0094] This is the same cycle as the one above for obtaining the number of fault occurrences, except that there is no need to manually turn on the ECS mode through MPC.

[0095] Specifically, the process of obtaining natural test failure data during each round of natural testing includes:

[0096] Writing the background data used for the ECS test corresponding to the current round of natural testing into the on-die ECC memory for testing to obtain process missing data;

[0097] Writing the test data used in the ECS test corresponding to the current round of natural testing into the on-die ECC memory to perform write and read tests respectively to obtain write fault data and read fault data;

[0098] The process miss data, the write failure data, and the read failure data are added together to obtain natural test failure data.

[0099] The step of comparing the failure number evolution table with a pre-acquired natural test failure table of the on-die ECC memory comprises:

[0100] S21: Use the test parameters that are gradually tightened according to the preset gradient as the horizontal axis, and use the number of fault occurrences and natural test failure data corresponding to the test parameters as the vertical axis corresponding to the test parameters, so that the fault number evolution table and the natural test failure table are overlapped on the horizontal axis, and use different colors to distinguish the fault number evolution table and the natural test failure table to form a composite bar chart with different colors as a comparison chart.

[0101] The comparison chart is Figure 3 , Figure 4 As shown in the figure, the horizontal axis from left to right represents gradually tightened test parameters, the gray part is the failure frequency evolution table, and each gray bar graph is the number of failures corresponding to different test parameters; the black part is the natural test failure table, and the black bar graph is the natural test failure data corresponding to different test parameters.

[0102] In a more specific embodiment,

[0103] The process of obtaining the maximum tolerable fault number of the on-die ECC memory includes:

[0104] S221: traverse the natural test failure data in the comparison chart in sequence, and lock the first histogram whose natural test failure data is greater than zero as the initial ECC failure histogram;

[0105] S222: Taking the test parameter on the horizontal axis where the initial ECC fault histogram is located as the maximum tolerated fault number.

[0106] In simple terms, the maximum number of faults tolerated is Figure 3 , Figure 4 The horizontal axis value of the part marked with 2, that is, the horizontal axis value corresponding to the black part that appears at the beginning, also means the test parameter value corresponding to the fault that ECC cannot completely solve at the beginning under natural use conditions, that is, the test parameter value is the maximum tolerable number of faults of the on-die ECC memory.

[0107] The process of obtaining the test parameter margin of the on die ECC memory includes:

[0108] S231: Obtain standard test parameter values ​​formulated by the chip supplier according to JEDEC or test standards;

[0109] S232: Subtract the standard test parameter value from the maximum tolerated fault number to obtain a test parameter margin.

[0110] in, Figure 3 , Figure 4 The horizontal axis value of the part with winning bid 3 is the standard test parameter value specified by the chip supplier JEDEC or the test standard, that is, Figure 3 , Attachment Figure 4 The horizontal axis "TEST PARAMETER" in the figure means the test parameters; Figure 3 , Attachment Figure 4The vertical axis "ERROR COUNT" means the number of failures; the gray part "ECS error count" is the number of failures in ECS mode, which can also be called the number of failures in error check and erase mode; the black part "After ECC error count" is the number of failures in on die ECC mode, also called the number of failures in internal error correction mode, which is the natural test failure data in this embodiment; the value of the horizontal axis of the part marked with 2 minus the value of the horizontal axis of the part marked with 3 is the test parameter margin, which also means the margin that the on die ECC memory exceeds the test standard.

[0111] The process of obtaining the remaining percentage of the maximum number of tolerated failures of the on-die ECC memory includes:

[0112] S241: Obtain the number of fault occurrences corresponding to the standard test parameter value as the initial number of fault occurrences; obtain the number of fault occurrences corresponding to the maximum tolerated fault number as the maximum tolerated actual number of fault occurrences;

[0113] S242: Taking the maximum tolerated actual fault occurrence number as a denominator, and taking the difference between the maximum tolerated actual fault occurrence number and the initial fault occurrence number as a numerator to obtain a remaining percentage of the maximum tolerated fault number.

[0114] exist Figure 3 , Figure 4 In the comparison chart shown, the remaining percentage takes the vertical axis data of the gray bar graph marked with 2 as the denominator, and the difference between the vertical axis data of the gray bar graph marked with 2 and the vertical axis data of the gray bar graph marked with 3 as the numerator. The resulting ratio is the remaining percentage of the maximum number of tolerant failures, which can reflect the usage potential of the on dieECC memory.

[0115] also, Figure 3 , Figure 4 The horizontal dotted line marked with 4 represents the percentage warning line, that is, if this line is exceeded when using the on-die ECC memory, the chip is prone to inevitable failure. It only serves as a reference.

[0116] Depend on Figure 3 , Figure 4It can be known that the correction ability of on-die ECC memory to various parameters is different. In other words, simply conducting traditional tests on on-die ECC memory can only get the black part, and cannot correctly estimate whether the parameters to be tested have risks during operation. Because through various parameter tests, the number of tolerable failures and the number remaining during standard operation are used to redefine the test standards and quality levels (remaining margin / maximum tolerable number) of each parameter under the On Die ECC condition. In the user's use state, the ECS count of each parameter can also be monitored regularly to set the correct ECS count warning line to prevent poor operation caused by chip aging.

[0117] Figure 3 , Figure 4 The parts of bid 1, bid 2, bid 3, and bid 4 can be used as the basis for chip aging and stress testing, and can also be used as dynamic monitoring indicators for application scenarios. The acquisition of these four data items needs to be added in the past procedures according to the description of JEDEC (Solid State Technology Association, the leading standard organization in the microelectronics industry) to read the ECS error count (the number of failures in ECS mode) to improve the efficiency of data acquisition. Then it reflects the real evaluation of on-die ECC memory, avoids test distortion caused by ECC self-repair, and improves the accuracy and authenticity of memory testing.

[0118] The difficulties faced by individual chip suppliers at the manufacturing process nodes are that the chip factory's shipping standard before DDR4 was 0 errors, but after the introduction of on-die ECC, the standard has become that as long as the on-die ECC can be corrected, it can be shipped. Therefore, in the chip factory process, some difficulties that cannot be overcome will be hidden by on-die ECC, and these will have a great probability of occurring during user use (lack of reliability). In summary, the in-depth evaluation method for on-die ECC memory in this embodiment can solve the above problems. Through the relevant measurement of ECS count, possible problems can be estimated in advance, and the repair ability of ON Die ECC for various parameters (including comprehensive parameter value labels) can be evaluated. The remaining margin percentage of each parameter can be used as a basis for quality control and monitoring alert, which is convenient for chip manufacturers to conduct factory screening of on-die ECC memory.

[0119] In addition, if Figure 5 As shown, the present invention also provides a deep evaluation system 100 for an on-die ECC memory, which implements the deep evaluation method for an on-die ECC memory as described above, including:

[0120] The actual failure number verification module 101 is used to perform multiple rounds of cyclic ECS tests on the on-die ECC memory by turning on and off the manual ECS mode of the on-die ECC memory to obtain a failure number evolution table; wherein the test parameters of each round of testing are gradually tightened according to a preset gradient;

[0121] The actual and natural fault comparison module 102 is used to compare the fault number evolution table with the pre-acquired natural test fault table of the ondie ECC memory to obtain the test parameter margin, the maximum tolerable fault number, and the remaining percentage of the maximum tolerable fault number of the on die ECC memory.

[0122] The specific implementation example can refer to the specific implementation method of the above-mentioned in-depth evaluation method for on-die ECC memory, which will not be described in detail again.

[0123] As described above, the depth evaluation method and system for on-die ECC memory proposed according to the present invention are described by way of example with reference to the accompanying drawings. However, those skilled in the art should understand that various improvements can be made to the depth evaluation method and system for on-die ECC memory proposed by the present invention without departing from the content of the present invention. Therefore, the protection scope of the present invention should be determined by the content of the attached claims.

Claims

1. A deep evaluation method for on-die ECC memory, characterized in that: include: Performing multiple rounds of cyclic ECS tests on the on-die ECC memory by turning on and off the manual ECS mode of the on-die ECC memory to obtain a failure number evolution table; wherein the test parameters of each round of testing are gradually tightened according to a preset gradient; The fault number evolution table is compared with the pre-acquired natural test fault table of the on die ECC memory to obtain the test parameter margin, the maximum tolerable fault number, and the remaining percentage of the maximum tolerable fault number of the on die ECC memory; wherein, The step of pre-acquiring a natural test fault table of the on-die ECC memory comprises: The on-dieECC memory is subjected to multiple rounds of natural testing in sequence according to the order of the test parameters used when obtaining the fault frequency evolution table to obtain a natural test fault table; wherein, In the order of gradually tightening the test parameters, the natural test fault data in the natural test fault table correspond one to one with the number of fault occurrences in the fault number evolution table; The process of obtaining natural test failure data during each round of natural testing includes: Writing the background data used for the ECS test corresponding to the current round of natural testing into the on-die ECC memory for testing to obtain process missing data; Writing the test data used in the ECS test corresponding to the current round of natural testing into the on-die ECC memory to perform write and read tests respectively to obtain write fault data and read fault data; adding the process missing data, the write failure data and the read failure data to obtain natural test failure data; The step of comparing the failure number evolution table with a pre-acquired natural test failure table of the on-die ECC memory comprises: The test parameters that are gradually tightened according to the preset gradient are used as the horizontal axis, and the number of fault occurrences and natural test fault data corresponding to the test parameters are used as the vertical axis corresponding to the test parameters, so that the fault number evolution table and the natural test fault table are overlapped on the horizontal axis, and the fault number evolution table and the natural test fault table are distinguished by different colors to form a composite bar chart with different colors as a comparison chart; The process of obtaining the maximum tolerable fault number of the on-die ECC memory includes: Traversing the natural test failure data in the comparison chart in sequence, locking the first histogram whose natural test failure data is greater than zero as the initial ECC failure histogram; Taking the test parameter on the abscissa where the initial ECC fault histogram is located as the maximum tolerated fault number; The process of obtaining the test parameter margin of the on die ECC memory includes: Obtain standard test parameter values ​​set by chip vendors in accordance with JEDEC or test standards; Subtract the standard test parameter value from the maximum tolerated fault number to obtain a test parameter margin; The process of obtaining the remaining percentage of the maximum number of tolerated failures of the on-die ECC memory includes: The number of fault occurrences corresponding to the standard test parameter value is obtained as the initial number of fault occurrences; the number of fault occurrences corresponding to the maximum tolerated fault number is obtained as the maximum tolerated actual number of fault occurrences; The maximum tolerated actual fault occurrence number is used as the denominator, and the difference between the maximum tolerated actual fault occurrence number and the initial fault occurrence number is used as the numerator to obtain the remaining percentage of the maximum tolerated fault number.

2. The in-depth evaluation method for on-die ECC memory according to claim 1, characterized in that: The steps for performing multiple rounds of ECS testing to obtain a failure count evolution table include: Each round of ECS testing is performed in sequence according to different test parameters to generate the number of failures corresponding to each round of ECS testing; The fault occurrence times are arranged in a corresponding order according to the order of the test parameters to form a fault number evolution table.

3. The in-depth evaluation method for on-die ECC memory according to claim 2, characterized in that: The steps for generating the number of failures corresponding to each round of ECS testing include: Writing background information about test parameters for the on die ECC memory, and sending an MPC instruction through the on die ECC memory to turn on the manual ECS mode of the on die ECC memory, so that the ECS counter of the on die ECC memory obtains the number of process misses of the on die ECC memory, and turns off the manual ECS mode; Writing the test data about the test parameters into the on-die ECC memory, and sending an MPC instruction through the on-die ECC memory to enable the manual ECS mode of the on-die ECC memory, so that the ECS counter of the on-die ECC memory obtains the number of write failures related to the write action of the on-die ECC memory, and closes the manual ECS mode; Enable the on-die ECC memory to read the data to be tested, and send an MPC instruction through the on-die ECC memory to enable a manual ECS mode of the on-die ECC memory, so that an ECS counter of the on-die ECC memory obtains a number of read failures of the on-die ECC memory related to a read action, and disables the manual ECS mode; The number of process misses, the number of write failures, and the number of read failures are added together to form the number of failure occurrences.

4. A deep evaluation system for on-die ECC memory, characterized in that: Implementing the in-depth evaluation method for an on-die ECC memory as described in any one of claims 1 to 3, comprising: An actual fault number verification module is used to perform multiple rounds of cyclic ECS tests on the on-die ECC memory by turning on and off the manual ECS mode of the on-die ECC memory to obtain a fault number evolution table; wherein the test parameters of each round of testing are gradually tightened according to a preset gradient; The actual and natural fault comparison module is used to compare the fault number evolution table with the pre-acquired natural test fault table of the on die ECC memory to obtain the test parameter margin, the maximum tolerable fault number, and the remaining percentage of the maximum tolerable fault number of the on die ECC memory; wherein the step of pre-acquiring the natural test fault table of the on die ECC memory includes: The on-dieECC memory is subjected to multiple rounds of natural testing in sequence according to the order of the test parameters used when obtaining the fault frequency evolution table to obtain a natural test fault table; wherein, In the order of gradually tightening the test parameters, the natural test fault data in the natural test fault table correspond one to one with the number of fault occurrences in the fault number evolution table; The process of obtaining natural test failure data during each round of natural testing includes: Writing the background data used for the ECS test corresponding to the current round of natural testing into the on-die ECC memory for testing to obtain process missing data; Writing the test data used in the ECS test corresponding to the current round of natural testing into the on-die ECC memory to perform write and read tests respectively to obtain write fault data and read fault data; adding the process missing data, the write failure data and the read failure data to obtain natural test failure data; The step of comparing the failure number evolution table with a pre-acquired natural test failure table of the on-die ECC memory comprises: The test parameters that are gradually tightened according to the preset gradient are used as the horizontal axis, and the number of fault occurrences and natural test fault data corresponding to the test parameters are used as the vertical axis corresponding to the test parameters, so that the fault number evolution table and the natural test fault table are overlapped on the horizontal axis, and the fault number evolution table and the natural test fault table are distinguished by different colors to form a composite bar chart with different colors as a comparison chart; The process of obtaining the maximum tolerable fault number of the on-die ECC memory includes: Traversing the natural test failure data in the comparison chart in sequence, locking the first histogram whose natural test failure data is greater than zero as the initial ECC failure histogram; Taking the test parameter on the abscissa where the initial ECC fault histogram is located as the maximum tolerated fault number; The process of obtaining the test parameter margin of the on die ECC memory includes: Obtain standard test parameter values ​​set by chip vendors in accordance with JEDEC or test standards; Subtract the standard test parameter value from the maximum tolerated fault number to obtain a test parameter margin; The process of obtaining the remaining percentage of the maximum number of tolerated failures of the on-die ECC memory includes: The number of fault occurrences corresponding to the standard test parameter value is obtained as the initial number of fault occurrences; the number of fault occurrences corresponding to the maximum tolerated fault number is obtained as the maximum tolerated actual number of fault occurrences; The maximum tolerated actual fault occurrence number is used as the denominator, and the difference between the maximum tolerated actual fault occurrence number and the initial fault occurrence number is used as the numerator to obtain the remaining percentage of the maximum tolerated fault number.

Images