Edge-emitting laser chip and its manufacturing method

Abstract

The present application provides an edge-emitting laser chip and a manufacturing method thereof, including a reference electrode, an N-type injection layer, an active region, and a P-type injection layer sequentially arranged above the reference electrode. At least two electrically isolated regions are arranged in the P-type injection layer. A first channel is formed between the at least two electrically isolated regions, and second channels are respectively formed on both sides of the at least two electrically isolated regions facing away from the first channel; a positive electrode and at least two negative electrodes are arranged on the side of the P-type injection layer facing away from the active region, and the positive electrode is located between the at least two negative electrodes; the positive electrode has a positive potential compared with the reference electrode. When a positive voltage is applied to the positive electrode, holes are injected into the quantum wells of the active region through the first channel, and electrons are also injected into the quantum wells; the at least two negative electrodes have a negative potential compared with the reference electrode. When a reverse voltage is applied to the at least two negative electrodes, the holes on one side of the quantum wells flow into the positive electrode through the second channels, and the electrons on the other side of the quantum wells flow into the reference electrode.

Description

Technical Field

[0001] This application belongs to the technical field of lasers, and particularly relates to an edge-emitting laser chip and a manufacturing method thereof. Background Art

[0002] In many fields such as optical communication and laser processing, high-performance laser chips have always been key components. With the continuous development of technology, the performance requirements for laser chips are increasing day by day, such as higher power output, better stability, and lower energy consumption, etc.

[0003] Traditional edge-emitting laser chips have certain limitations in structure and performance, and are prone to the phenomenon of end-face COD (Catastrophic Optical Damage), which greatly affects the reliability and service life of laser chips. Summary of the Invention

[0004] Therefore, the technical problem to be solved by this application is to provide an edge-emitting laser chip and a manufacturing method thereof, which can reduce the temperature of the active region of the chip, improve the high-temperature saturation output power of the chip, and avoid the occurrence of chip thermal failure and COD phenomenon.

[0005] To solve the above problems, on the one hand, this application provides an edge-emitting laser chip, including a reference electrode, on one side of the reference electrode, an N-type injection layer, an active region, and a P-type injection layer are sequentially arranged. At least two electrical isolation regions are arranged in the P-type injection layer. A first channel is formed between at least two electrical isolation regions, and second channels are respectively formed on both sides of at least two electrical isolation regions facing away from the first channel;

[0006] A positive electrode and at least two negative electrodes are arranged on the side of the P-type injection layer facing away from the active region, and the positive electrode is located between at least two negative electrodes;

[0007] The positive electrode has a positive potential compared with the reference electrode. When a positive voltage is applied to the positive electrode, holes are injected into the quantum well of the active region through the first channel, and electrons are also injected into the quantum well;

[0008] At least two negative electrodes have a negative potential compared with the reference electrode. When a reverse voltage is applied to at least two negative electrodes, the holes on one side of the quantum well flow into the negative electrode through the second channel, and the electrons on the other side of the quantum well flow into the reference electrode.

[0009] Optionally, the active region includes an optical gain layer, the optical gain layer is an InGaAsP layer, the thickness of the optical gain layer is 6nm - 8nm, and the symmetry center of the optical gain layer coincides with the symmetry center of the positive electrode.

[0010] Optionally, on the vertical direction, non-doped waveguide layers are respectively disposed on both sides of the optical gain layer; on the horizontal direction, N-type doped waveguide layers are respectively disposed on both sides of the optical gain layer.

[0011] Optionally, the orthographic projection of the optical gain layer on the N-type injection layer is separated from or at least partially overlaps with the orthographic projections of at least two of the electrical isolation regions on the N-type injection layer.

[0012] Optionally, the electrical isolation region penetrates through the P-type injection layer.

[0013] Optionally, the electrical isolation region does not penetrate through the P-type injection layer, and the distance between the electrical isolation region and the active region is 100 nm to 400 nm.

[0014] Optionally, the electrical isolation region is a groove formed on the P-type injection layer.

[0015] Optionally, the groove is filled with an electrically isolating N-type material, and the electrically isolating N-type material is InP.

[0016] On the other hand, the present application provides a method for manufacturing an edge-emitting laser chip, including:

[0017] Growing an N-type injection layer on one side of a substrate;

[0018] Growing an active region on the side of the N-type injection layer facing away from the substrate;

[0019] Growing a P-type injection layer on the side of the active region facing away from the N-type injection layer;

[0020] Removing a part of the material of the P-type injection layer to form at least two grooves;

[0021] Growing an electrically isolating N-type material in at least two of the grooves to form at least two electrical isolation regions;

[0022] Fabricating a forward electrode on the side of the P-type injection layer facing away from the active region and at a position corresponding to the quantum well of the active region, and fabricating reverse electrodes at intervals on both sides in the horizontal direction of the forward electrode;

[0023] Thinning the substrate to fabricate a reference electrode.

[0024] Optionally, the step of growing an active region on the side of the N-type injection layer facing away from the substrate includes:

[0025] Growing a non-doped waveguide layer, an optical gain layer, and a non-doped waveguide layer in sequence on the side of the N-type injection layer facing away from the substrate;

[0026] Remove the undoped waveguide layer, the optical gain layer, and the undoped waveguide layer in the first region;

[0027] Grow an N-type doped waveguide layer in the first region;

[0028] Wherein, the first region is at least a partial region outside the projection range of the forward electrode in the active region.

[0029] Advantageous Effects

[0030] Embodiments of the present invention provide an edge-emitting laser chip and a manufacturing method thereof. When the edge-emitting laser chip operates, a forward voltage is applied to the forward electrode, promoting the injection of holes and electrons into the quantum wells of the active region. At this time, although the quantum wells generate gain, part of the energy will be lost in the form of thermal radiation, leading to a temperature rise. However, when a reverse voltage is applied to the reverse electrode, the holes on one side of the quantum wells will flow reversely into the forward electrode, and the electrons on the other side will flow reversely into the reference electrode, while carrying heat to the forward electrode and the reference electrode. Thus, the heat is quickly transferred from the region near the quantum wells to the surface of the edge-emitting laser chip, thereby reducing the temperature near the quantum wells. And by controlling the bias voltage of the reverse electrode, the temperature of the quantum wells can be flexibly adjusted, enabling the edge-emitting laser chip to effectively control the temperature of the quantum wells even under high-temperature and high-current operating conditions, ensuring its stable operation. At the same time, the precise control of the temperature of the quantum wells can enable the edge-emitting laser chip to obtain a large high-temperature saturation output power in a high-temperature environment. In addition, controlling the temperature of the quantum wells at the end face can also increase the current threshold and power threshold of COD (catastrophic optical damage), significantly reduce the occurrence probability of catastrophic optical damage at the end face, greatly improve the reliability of the edge-emitting laser chip, and extend its service life. Moreover, the unique electrode structure design and the carrier injection and outflow mechanism of the edge-emitting laser chip can achieve precise control of the carriers and temperature in the quantum wells, avoiding performance fluctuations caused by problems such as excessive temperature or carrier accumulation, thereby enhancing the performance stability of the edge-emitting laser chip under different operating conditions. Description of the Drawings

[0031] Figure 1 A cross-sectional view of an edge-emitting laser chip according to an alternative embodiment of the present application;

[0032] Figure 2 A top view of an edge-emitting laser chip according to an alternative embodiment of the present application;

[0033] Figure 3 A flowchart of a manufacturing method of an edge-emitting laser chip according to an alternative embodiment of the present application;

[0034] Figure 4 A schematic structural diagram of one of the steps of manufacturing an edge-emitting laser chip according to the present application;

[0035] Figure 5 Schematic structural diagram of one of the steps for fabricating an edge-emitting laser chip according to the present application;

[0036] Figure 6 Schematic structural diagram of one of the steps for fabricating an edge-emitting laser chip according to the present application;

[0037] Figure 7 Schematic structural diagram of one of the steps for fabricating an edge-emitting laser chip according to the present application;

[0038] Figure 8 Schematic structural diagram of one of the steps for fabricating an edge-emitting laser chip according to the present application;

[0039] Figure 9 Schematic structural diagram of one of the steps for fabricating an edge-emitting laser chip according to the present application;

[0040] Figure 10 Schematic structural diagram of one of the steps for fabricating an edge-emitting laser chip according to the present application;

[0041] Figure 11 Schematic structural diagram of one of the steps for fabricating an edge-emitting laser chip according to the present application;

[0042] Figure 12 Schematic structural diagram of one of the steps for fabricating an edge-emitting laser chip according to the present application.

[0043] Reference numerals are represented as:

[0044] 1, reference electrode; 2, N-type injection layer; 3, active region; 31, optical gain layer; 32, undoped waveguide layer; 33, N-type doped waveguide layer; 4, P-type injection layer; 5, electrical isolation region; 6, forward electrode; 7, reverse electrode; 8, substrate. Detailed implementation manners

[0045] In the description of the present application, it should be understood that the orientation or positional relationships indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0046] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined.

[0047] In this application, unless otherwise clearly specified and defined, terms such as "mounted", "connected", "coupled", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0048] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only for explaining and illustrating the present invention and are not used to limit the present invention.

[0049] See Figure 1 and Figure 2 As shown, an embodiment of the first aspect of the present application provides an edge-emitting laser chip, including a reference electrode 1. On one side of the reference electrode 1, an N-type injection layer 2, an active region 3, and a P-type injection layer 4 are sequentially arranged. At least two electrically isolated regions 5 are arranged in the P-type injection layer 4. A first channel is formed between the at least two electrically isolated regions 5, and second channels are respectively formed on both sides of the at least two electrically isolated regions 5 facing away from the first channel; on the side of the P-type injection layer 4 facing away from the active region 3, a positive electrode 6 and at least two negative electrodes 7 are arranged, and the positive electrode 6 is located between the at least two negative electrodes 7; the positive electrode 6 has a positive potential compared with the reference electrode 1. When a positive voltage is applied to the positive electrode 6, holes are injected into the quantum well of the active region 3 through the first channel, and electrons are also injected into the quantum well; the at least two negative electrodes 7 have a negative potential compared with the reference electrode 1. When a negative voltage is applied to the at least two negative electrodes 7, the holes on one side of the quantum well flow into the negative electrode 7 through the second channel, and the electrons on the other side of the quantum well flow into the reference electrode 1.

[0050] It should be noted that when the edge-emitting laser chip is working, a forward voltage is applied to the forward electrode 6 to promote the injection of holes and electrons into the quantum wells of the active region 3. At this time, although the quantum wells generate gain, part of the energy will be lost in the form of thermal radiation, resulting in a temperature rise. However, when a reverse voltage is applied to the reverse electrode 7, the holes on one side of the quantum wells will flow reversely into the reverse electrode 7, and the electrons on the other side will flow reversely into the reference electrode 1, while taking the heat to the reverse electrode 7 and the reference electrode 1. Thus, the heat is quickly transferred from the area near the quantum wells to the surface of the edge-emitting laser chip, thereby reducing the temperature near the quantum wells. Moreover, by controlling the bias voltage of the reverse electrode 7, the temperature of the quantum wells can be flexibly adjusted, enabling the edge-emitting laser chip to effectively control the temperature of the quantum wells even under the working conditions of high temperature and high current, ensuring its stable operation. At the same time, the precise control of the temperature of the quantum wells can enable the edge-emitting laser chip to obtain a large high-temperature saturation output power in a high-temperature environment. In addition, controlling the temperature of the quantum wells at the end face can also increase the current threshold and power threshold of COD (catastrophic optical damage), significantly reduce the occurrence probability of catastrophic optical damage at the end face, greatly improve the reliability of the edge-emitting laser chip, and extend its service life. Furthermore, the unique electrode structure design and the carrier injection and outflow mechanism of the edge-emitting laser chip can achieve precise control of the carriers and temperature in the quantum wells, avoiding performance fluctuations caused by problems such as too high temperature or carrier accumulation, thereby enhancing the performance stability of the edge-emitting laser chip under different working conditions.

[0051] Among them, the reference electrode 1, the forward electrode 6, and the reverse electrode 7 can all be made of metals such as titanium, platinum, or gold. For example, when the reference electrode 1, the forward electrode 6, and the reverse electrode 7 are made of titanium, the thicknesses of the reference electrode 1, the forward electrode 6, and the reverse electrode 7 are 30 nm to 130 nm; when the reference electrode 1, the forward electrode 6, and the reverse electrode 7 are made of platinum, the thicknesses of the reference electrode 1, the forward electrode 6, and the reverse electrode 7 are 30 nm to 130 nm; when the reference electrode 1, the forward electrode 6, and the reverse electrode 7 are made of gold, the thicknesses of the reference electrode 1, the forward electrode 6, and the reverse electrode 7 are 450 nm to 550 nm.

[0052] Among them, the reference electrode 1 is arranged on the back surface of the edge-emitting laser chip, the forward electrode 6 and the reverse electrode 7 are arranged on the front surface of the edge-emitting laser chip, and the forward electrode 6 and the reverse electrode 7 are coplanar.

[0053] Among them, an N-type injection layer 2, an active region 3, and a P-type injection layer 4 are arranged between the reference electrode 1 and the forward electrode 6 and the reverse electrode 7. The active region 3 is located between the N-type injection layer 2 and the P-type injection layer 4. The N-type injection layer 2 is located on the side of the active region 3 close to the reference electrode 1, and the P-type injection layer 4 is located on the side of the active region 3 close to the forward electrode 6 and the reverse electrode 7.

[0054] Specifically, the P-type injection layer 4 can be made of an electro-injected P-type material. After electro-injection into the P-type material, a large number of holes will be generated in the P-type material; the N-type injection layer 2 can be made of an electro-injected N-type material. After electro-injection into the N-type material, a large number of electrons will be generated in the N-type material. It can be understood that the P-type injection layer 4 and the N-type injection layer 2 are used to provide a carrier source for the active region 3. When holes and electrons are injected into the active region 3, the holes and electrons recombine in the active region 3 to generate photons, thereby realizing the emission or amplification of light.

[0055] Among them, both the electro-injected P-type material and the electro-injected N-type material can be InP, and the thicknesses of both the P-type injection layer 4 and the N-type injection layer 2 can be 1000 nm to 1400 nm.

[0056] Among them, holes are carriers with positive charges, and electrons are carriers with negative charges.

[0057] Among them, holes will move in the direction of lower potential, and electrons will move in the direction of higher potential.

[0058] Specifically, the potential value of the positive electrode 6 is higher than that of the reference electrode 1. When a positive voltage is applied to the positive electrode 6, the holes generated in the P-type injection layer 4 will move towards the reference electrode 1 and then flow into the active region 3 located between the positive electrode 6 and the reference electrode 1. At the same time, the electrons generated in the N-type injection layer 2 will move towards the positive electrode 6 and also flow into the active region 3 located between the positive electrode 6 and the reference electrode 1; similarly, the potential value of the reverse electrode 7 is lower than that of the reference electrode 1. When a reverse voltage is applied to the reverse electrode 7, the holes generated in the P-type injection layer 4 will move towards the reverse electrode 7 and flow into the reverse electrode 7. And the electrons generated in the N-type injection layer 2 will move towards the reference electrode 1 and flow to the reference electrode 1. It can be understood that the holes flowing into the reverse electrode 7 and the electrons flowing into the reference electrode 1 are used to carry heat to the reverse electrode 7 and the reference electrode 1. Thus, the heat is quickly transferred from the area near the active region 3 to the surface of the edge-emitting laser chip, thereby reducing the temperature of the active region 3.

[0059] Among them, the reference electrode 1 can be a zero-potential electrode, the positive electrode 6 can be a two-volt positive-potential electrode, and the reverse electrode 7 can be a two-volt negative-potential electrode.

[0060] Specifically, only one positive electrode 6 can be provided, and the positive electrode 6 is located in the middle of the front surface of the edge-emitting laser chip; at least two negative electrodes 7 can be provided, and the at least two negative electrodes 7 are located at the edge of the front surface of the edge-emitting laser chip and are oppositely arranged. It can be understood that the positive electrode 6 is located in the middle of the front surface of the edge-emitting laser chip, which can concentrate the injection of holes and electrons into the active region 3 to ensure that the quantum well is stably excited to generate light under normal operating conditions. And the at least two negative electrodes 7 are arranged at the edge, which can extract heat from the quantum well in at least two directions. At the same time, the at least two oppositely arranged negative electrodes 7 can form a more uniform electric field distribution, so that the heat flows out more uniformly from around the quantum well during the extraction process, avoiding local overheating or overcooling, and further improving the accuracy of temperature control. That is to say, this layout helps to achieve the dynamic balance of carrier injection and extraction, improve the utilization efficiency of carriers in the quantum well, and thus enhance the light emission or amplification effect.

[0061] Among them, in this embodiment, two negative electrodes 7 are provided.

[0062] Among them, the positive electrode 6 is located between the two negative electrodes 7, and the positive electrode 6 is spaced a certain distance from both negative electrodes. It can be understood that spacing a certain distance can avoid the electric field interference between the positive electrode 6 and the negative electrode 7, ensuring that the carrier injection and extraction processes are more orderly and stable. When a reverse voltage is applied to the negative electrode 7, heat conducts from the quantum well to the two-side negative electrodes 7. Since the positive electrode 6 is spaced a certain distance from the negative electrode 7, it will not hinder the heat flow path, so that the heat can be transferred from the area near the quantum well to the chip surface more quickly and uniformly, reducing the temperature near the quantum well. This helps to improve the accuracy of temperature control and avoid damage to the chip performance caused by local overheating.

[0063] Among them, at least two electrical isolation regions 5 are provided in the P-type injection layer 4 for dividing the channel regions of the P-type injection layer 4 to ensure the orderly flow of carriers in different channels and avoid unnecessary cross-interference.

[0064] It should be noted that the number of electrical isolation regions 5 provided depends on the number of positive electrodes 6 provided. For example, when one positive electrode 6 is provided, two electrical isolation regions 5 are provided; when two positive electrodes 6 are provided, three electrical isolation regions 5 are provided; when three positive electrodes 6 are provided, four electrical isolation regions 5 are provided. In this embodiment, one positive electrode 6 is provided and two electrical isolation regions 5 are provided.

[0065] Specifically, the two electrical isolation regions 5 extend along the thickness direction of the P-type injection layer 4, thereby successfully constructing a first channel between the two electrical isolation regions 5, and second channels are respectively formed on both sides of the two electrical isolation regions 5 facing away from the first channel.

[0066] Among them, in the thickness direction of the P-type injection layer 4, the first channel is disposed opposite to the positive electrode 6, and the second channel is disposed opposite to the negative electrode 7.

[0067] Specifically, when a positive voltage is applied to the positive electrode 6, holes can accurately inject into the quantum well of the active region 3 through the first channel disposed opposite to the positive electrode 6, realizing efficient carrier injection. At the same time, when a negative voltage is applied to the negative electrode 7, the holes on one side of the quantum well can smoothly flow into the negative electrode 7 through the second channel disposed opposite to the negative electrode 7, completing the heat transfer process.

[0068] In some specific examples, the projections of the positive electrode 6 and the negative electrode 7 on the P-type injection layer 4 coincide with at least a part of the electrical isolation region 5.

[0069] In other specific examples, the projections of the positive electrode 6 and the negative electrode 7 on the P-type injection layer 4 are separated from the electrical isolation region 5.

[0070] In some possible implementation embodiments disclosed in the present application, as shown in Figure 1 the active region 3 includes a light gain layer 31. The light gain layer 31 is an InGaAsP layer, the thickness of the light gain layer 31 is 6 nm to 8 nm, and the symmetry center of the light gain layer 31 coincides with the symmetry center of the positive electrode 6. Thus, the carriers injected from the positive electrode 6 can be more evenly distributed in the light gain layer 31. This helps the efficient recombination of carriers in the light gain layer 31, further enhancing the generation and amplification effect of light. At the same time, it also helps to avoid local overheating phenomena and improve the thermal stability of the edge-emitting laser chip. When the negative electrode 7 applies a negative voltage for temperature regulation, the heat can be more effectively transferred from the area near the light gain layer 31 to the surface of the emitting laser chip, reducing the temperature near the light gain layer 31.

[0071] Among them, the light gain layer 31 can be made of InGaAsP material, which has good light gain characteristics.

[0072] Among them, the thickness of the optical gain layer 31 can be 6 nm to 8 nm. For example, the thickness of the optical gain layer 31 is 6.0 nm, or 6.1 nm, or 6.2 nm, or 6.3 nm, or 6.4 nm, or 6.5 nm, or 6.6 nm, or 6.7 nm, or 6.8 nm, or 6.9 nm, or 7.0 nm, or 7.1 nm, or 7.2 nm, or 7.3 nm, or 7.4 nm, or 7.5 nm, or 7.6 nm, or 7.7 nm, or 7.8 nm, or 7.9 nm, or 8.0 nm. It can be understood that the thickness of the optical gain layer 31 can also be other values outside the above-mentioned values, as long as the thickness range of the optical gain layer 31 is 6 nm to 8 nm. The optical gain layer 31 with a thickness of 6 nm to 8 nm can achieve efficient optical amplification in the active region 3. When the forward electrode 6 applies a forward voltage, holes and electrons are injected into the active region 3 and recombine in the optical gain layer 31 to generate photons. Due to the appropriate thickness of the optical gain layer 31, the photons can be fully enhanced therein, thereby improving the light emission efficiency.

[0073] In some specific examples, the projection of the optical gain layer 31 on the N-type injection layer 2 is separated from the projections of the two electrical isolation regions 5 on the N-type injection layer 2. Thereby, the interference of the electrical isolation regions 5 on the carrier flow in the optical gain layer 31 can be reduced. Carriers can participate in the recombination process more smoothly in the optical gain layer 31, improving the optical gain efficiency.

[0074] In other specific examples, the orthographic projection of the optical gain layer 31 on the N-type injection layer 2 and the orthographic projections of the two electrical isolation regions 5 on the N-type injection layer 2 at least partially overlap. Thereby, the carriers can be guided to flow more concentratedly into the optical gain layer 31, increasing the concentration of carriers in the optical gain layer 31, and thus enhancing the optical gain effect.

[0075] In some possible implementation embodiments disclosed in the present application, as shown in Figure 1 As shown, in the vertical direction, non-doped waveguide layers 32 are respectively arranged on both sides of the optical gain layer 31.

[0076] It can be understood that the non-doped waveguide layer 32 and the optical gain layer 31 form a refractive index difference in the vertical direction. This difference restricts the propagation of light in the vertical direction, and more light is confined to the optical gain layer 31 and its nearby regions, thereby improving the utilization rate of light. This helps to enhance the optical gain effect and makes the edge-emitting laser chip perform better in terms of light emission or amplification. At the same time, by effectively confining the light, the non-doped waveguide layer 32 can reduce the possibility of light leakage from the optical gain layer 31 to the surrounding regions, ensuring that the propagation of light inside the edge-emitting laser chip is more concentrated and stable, and improving the intensity and quality of the optical signal.

[0077] Among them, the vertical direction can be the thickness direction of the optical gain layer 31. On both sides of the optical gain layer 31 in the vertical direction, undoped waveguide layers 32 are respectively arranged, that is to say, undoped waveguide layers 32 are arranged above and below the optical gain layer 31.

[0078] Among them, the undoped waveguide layer 32 can be made of InGaAsP material. The InGaAsP material can provide a refractive index matching that of the optical gain layer 31, enabling better confinement of light in the vertical direction. Light undergoes total reflection or partial reflection at the interface between the undoped waveguide layer 32 and the optical gain layer 31, thereby restricting the light to the optical gain layer 31 and its nearby regions and improving the light transmission efficiency and optical gain effect.

[0079] Among them, the thickness of the undoped waveguide layer 32 can be 150 nm to 250 nm.

[0080] Among them, the width of the undoped waveguide layer 32 can be the same as that of the optical gain layer 31.

[0081] In some possible implementation embodiments disclosed in the present application, as shown in Figure 1 In the horizontal direction, N-type doped waveguide layers 33 are respectively arranged on both sides of the optical gain layer 31.

[0082] It can be understood that the N-type doped waveguide layer 33 has a certain heat conduction ability. The heat generated by the optical gain layer 31 can diffuse to both sides through the N-type doped waveguide layer 33, so that when a reverse voltage is applied to the reverse electrode 7, holes and electrons can carry heat and flow into the reverse electrode 7 and the reference electrode 1 respectively to complete heat dissipation. In addition, the N-type doped waveguide layer 33 can also serve as an additional heat dissipation channel to conduct heat away from the vicinity of the optical gain layer 31.

[0083] Among them, the horizontal direction can be the width direction of the optical gain layer 31. In the horizontal direction, N-type doped waveguide layers 33 are respectively arranged on both sides of the optical gain layer 31, that is to say, N-type doped waveguide layers 33 are arranged on the left and right sides of the optical gain layer 31.

[0084] Among them, the N-type doped waveguide layer 33 can also be made of InGaAsP material. The InGaAsP material itself has a certain heat conduction ability, and its heat conduction performance may be further improved after N-type doping. When the edge-emitting laser chip operates to generate heat, the N-type doped waveguide layer 33 can conduct the heat away faster, reducing the temperature of the optical gain layer 31 and other parts of the edge-emitting laser chip.

[0085] Among them, the thickness of the N-type doped waveguide layer 33 can also be 150 nm to 250 nm.

[0086] Specifically, the thickness of the N-type doped waveguide layer 33 is the sum of the thickness of the optical gain layer 31 and the thicknesses of the two undoped waveguide layers 32.

[0087] In some possible embodiments disclosed in the present application, as shown in Figure 12 Figure, the electrical isolation region 5 penetrates through the P-type injection layer 4. Thus, the P-type injection layer can be completely divided into different regions, ensuring that the carriers in each channel flow strictly along the predetermined path, avoiding the cross-interference of carriers between different channels, and improving the orderliness and controllability of carrier flow. That is to say, compared with the partially isolated design, the through-type electrical isolation region 5 can provide a stronger electrical isolation effect, reduce the risk of leakage and crosstalk, and improve the electrical performance stability of the edge-emitting laser chip.

[0088] In addition, the electrical isolation region 5 can also be arranged in the following ways:

[0089] As shown in Figure 1 Figure, the electrical isolation region 5 does not penetrate through the P-type injection layer 4, and the spacing distance between the electrical isolation region 5 and the active region 3 is 100 nm to 400 nm. Thus, the stress concentration caused by the structural mutation can be reduced. This helps to reduce the performance fluctuations and damage risks of the edge-emitting laser chip during operation due to factors such as thermal expansion and mechanical stress, and improves the mechanical stability and reliability of the edge-emitting laser chip. That is to say, compared with the through-type design, the non-through electrical isolation region 5 may be easier to implement and control in the manufacturing process. The specific spacing distance also provides a certain margin for the control of process accuracy, improving the feasibility and yield of manufacturing the edge-emitting laser chip.

[0090] In some possible embodiments disclosed in the present application, as shown in Figure 9 Figure, the electrical isolation region 5 is a groove opened on the P-type injection layer 4. It can be understood that the groove as the electrical isolation region 5 can clearly define the boundaries of different carrier channels. The flow of carriers in the P-type injection layer is strictly restricted within a specific region, avoiding the disordered diffusion and cross-interference of carriers, and improving the directionality and controllability of carrier flow. At the same time, the shape and position of the groove are relatively fixed, providing a stable structural support for the carrier channels. This helps to maintain the stability of the carrier channels under different working conditions, ensuring that the carriers can be continuously and stably injected into the quantum wells of the active region 3.

[0091] Among them, the groove can be a rectangular groove or the like.

[0092] In some possible embodiments disclosed in the present application, as shown in Figure 10As shown, the groove is filled with an electrically isolated N-type material, and the electrically isolated N-type material is InP. It is understandable that InP, as an electrically isolated N-type material, is filled in the groove, which can effectively prevent the lateral diffusion of carriers between different channels. Since InP has specific electrical properties, it can form a high-resistance area to limit the flow of carriers, thereby enhancing the electrical isolation effect and ensuring that the carriers in each channel can flow independently and orderly. At the same time, the InP material has a certain thermal conductivity. When the groove is filled with InP, it can serve as a heat conduction channel to help conduct the heat generated near the quantum well. At the same time, the thermal expansion coefficient of InP is relatively matched with the P-type injection layer 4 and other surrounding materials, which reduces the thermal stress caused by the difference in thermal expansion and helps to improve the thermal stability of the chip.

[0093] In this application, the edge-emitting laser chip can use the materials, thicknesses and refractive indices shown in the following table. It is understandable that in other implementations, the materials, thicknesses and refractive indices of each layer are adjusted by the staff according to actual needs, and this application does not strictly limit them.

[0094] Table 1 Materials, thickness and refractive index of each layer of edge-emitting laser chip

[0095]

[0096] For an embodiment of the second aspect of the present application, see Figures 3 to 12 As shown, a method for manufacturing an edge-emitting laser chip is provided. By sequentially growing an N-type injection layer 2, an active area 3 and a P-type injection layer 4 on a substrate 8, the thickness and material quality of each layer can be precisely controlled. This growth method can ensure a clear interface between the layers, reduce interface defects, and improve the performance and reliability of the chip. At the same time, by removing part of the material of the P-type injection layer 4 to form a groove, and then growing an electrically isolated N-type material in the groove, the position, shape and size of the electrically isolated area 5 can be precisely controlled. This method can achieve accurate division of the carrier channel and improve the flow efficiency and isolation effect of the carriers. At the same time, on the side of the P-type injection layer 4 away from the active area 3, a forward electrode 6 is made relative to the quantum well position of the active area 3, and reverse electrodes 7 are made at a certain distance on both sides of the forward electrode 6 in the horizontal direction. This layout helps to achieve efficient injection and extraction of carriers, improve the utilization efficiency of carriers in the quantum well, and thus enhance the emission or amplification effect of light. At the same time, the spacing distance between the forward electrode 6 and the reverse electrode 7 can be precisely adjusted according to actual needs to avoid electric field interference and ensure that the injection and extraction process of carriers is more orderly and stable. At the same time, reasonable electrode spacing can also optimize the heat conduction path and improve the thermal stability of the chip.

[0097] Please follow the steps below to implement:

[0098] Step S101: Grow an N-type implantation layer 2 on one side of the substrate 8.

[0099] Among them, the substrate 8 is a basic supporting material for chip manufacturing, providing a stable platform for the growth of subsequent layers. It has good mechanical strength, thermal stability and chemical stability, and can withstand various process steps and external environmental influences during chip manufacturing.

[0100] Among them, the growth of the N-type implantation layer 2 can adopt semiconductor epitaxial growth techniques, such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), etc. These techniques can precisely control parameters such as temperature, pressure, gas flow rate and doping concentration during the growth process, so as to achieve high-quality and uniform growth of the N-type implantation layer 2.

[0101] Specifically, first, clean and pre-treat the substrate 8 to remove surface impurities and contaminants to ensure the cleanliness and flatness of the substrate 8 surface. Then, place the substrate 8 into the growth equipment and adjust the parameters of the growth equipment, such as temperature, pressure, gas flow rate, etc., to prepare for the growth of the N-type implantation layer 2. In the growth equipment, by introducing a precursor gas containing an N-type dopant, such as phosphine, etc., and other reaction gases, such as arsine, hydrogen, etc., a chemical reaction occurs under specific temperature and pressure conditions to deposit and form the N-type implantation layer 2 on the substrate 8 surface. During the growth process, parameters such as growth rate, doping concentration and layer thickness need to be strictly controlled to ensure that the quality and performance of the N-type implantation layer 2 meet the requirements. After the growth is completed, detect and analyze the N-type implantation layer 2, such as measuring the layer thickness, doping concentration, crystal quality, etc. If problems are found, appropriate post-treatment, such as annealing, etching, etc., can be carried out to improve the performance of the N-type implantation layer 2.

[0102] Step S201: Grow an active region 3 on the side of the N-type implantation layer 2 facing away from the substrate 8.

[0103] Among them, the N-type implantation layer 2 is a semiconductor layer with specific electrical properties, providing a basis for the growth of the active region 3. Growing the active region 3 on the side of the N-type implantation layer 2 facing away from the substrate 8, on the one hand, the N-type implantation layer 2 can provide electron carriers for the active region 3, and in the subsequent working process of the active region 3, electrons and holes recombine in this region to generate photons, realizing light emission or amplification; on the other hand, this layered structure helps to achieve directional injection and recombination of carriers, improving the light generation efficiency.

[0104] Among them, the active region 3 is the core part of the edge-emitting laser chip, which determines the optical performance of the chip. The active region 3 contains structures such as the optical gain layer 31. Its main function is to generate photons through the recombination of electrons and holes and achieve optical amplification. Specifically, when a forward voltage is applied to the forward electrode 6, electrons from the N-type injection layer 2 and holes from the P-type injection layer 4 are injected into the active region 3. In the active region 3, electrons and holes recombine under specific conditions (such as in a quantum well structure), releasing energy and generating photons. These photons are continuously reflected and amplified within the active region 3, and finally form a laser output.

[0105] Among them, the active region 3 has the same epitaxial growth method as the N-type injection layer 2, which will not be elaborated here.

[0106] Step S301: Grow the P-type injection layer 4 on the side of the active region 3 facing away from the N-type injection layer 2.

[0107] Among them, the P-type injection layer 4 can be made of an electrically injected P-type material. For example, it can be formed by subjecting semiconductor materials such as InP to a specific doping process. The doped impurities are usually acceptor impurities such as zinc, etc. These impurities can form holes in the material and increase the hole concentration.

[0108] Among them, the P-type injection layer 4 has certain electrical conductivity and can provide a channel for the transport of holes. It, together with the N-type injection layer 2 and the active region 3, constitutes a PN junction structure. Under the action of a forward voltage, it promotes the injection and recombination of carriers.

[0109] Among them, the P-type injection layer 4 has the same epitaxial growth method as the active region 3, which will not be elaborated here.

[0110] Step S401: Remove part of the material of the P-type injection layer 4 to form at least two grooves.

[0111] Among them, the grooves are used to achieve electrical isolation. By removing part of the material of the P-type injection layer 4 to form grooves, different regions can be divided in the chip, preventing the flow of carriers in unwanted directions, thereby improving the electrical performance and stability of the chip.

[0112] Specifically, photolithography and etching techniques can be used to remove part of the material of the P-type injection layer 4 to form a groove. First, a layer of photoresist is coated on the surface of the P-type injection layer 4, and then a specific pattern is exposed on the photoresist using a lithography machine. The exposed photoresist will undergo a chemical change, so that during the development process, the exposed part or the unexposed part is dissolved, thus forming a mask (SiO2) on the photoresist that is the same as the required groove pattern. Next, an etching process is used to remove the part of the P-type injection layer 4 that is not protected by the photoresist. The etching process can be dry etching or wet etching. Dry etching usually uses techniques such as plasma or reactive ion etching, which has high etching accuracy and selectivity; wet etching uses a chemical solution to dissolve the material of the P-type injection layer 4, usually having a high etching rate, but relatively low etching accuracy and selectivity.

[0113] Step S501: Grow electrically isolated N-type material in at least two grooves to form at least two electrically isolated regions 5.

[0114] It can be understood that by growing electrically isolated N-type material in the grooves, the electrical isolation between different regions can be further enhanced. This helps to prevent the flow of carriers in unwanted directions, reduce problems such as leakage and crosstalk, and improve the electrical performance and stability of the edge-emitting laser chip.

[0115] Among them, an N-type material with good electrical insulation performance can be selected as the electrically isolated material. For example, semiconductor materials such as InP and AlGaAs can be selected and made to have N-type conductivity through doping and other means. These materials can form good interfaces with the surrounding semiconductor layers during the growth process to ensure the electrical isolation effect.

[0116] Specifically, during the growth process, the electrically isolated material will gradually fill the groove until it is flush with or slightly higher than the surrounding semiconductor layer. To ensure good filling effect, techniques such as multi-layer growth or gradient growth can be used to avoid the appearance of voids or unevenness.

[0117] Step S601: Fabricate a forward electrode 6 on the side of the P-type injection layer 4 facing away from the active region 3 and at a position relative to the quantum well of the active region 3, and fabricate reverse electrodes 7 at a certain distance on both sides in the horizontal direction of the forward electrode 6.

[0118] It can be understood that the positive electrode 6 is fabricated on the side of the P-type injection layer facing away from the active region 3 and at the position of the quantum well relative to the active region 3, mainly to achieve efficient carrier injection. The quantum well is the main region of optical gain. By setting the positive electrode 6 near this position, the injected carriers can enter the quantum well more directly, improving the recombination efficiency of carriers and photons, thereby enhancing the light emission or amplification effect; the reverse electrodes 7 are fabricated at a certain distance on both sides in the horizontal direction of the positive electrode 6 to achieve a specific electric field distribution and carrier extraction function. The electric field between the reverse electrode 7 and the positive electrode 6 can control the flow direction and distribution of carriers in the chip, and also contributes to heat dissipation and temperature control. Setting a certain distance can avoid short circuits and interference between the electrodes, and also provides a certain degree of flexibility for the chip structure design and performance optimization.

[0119] Specifically, first, the surface of the P-type injection layer 4 is cleaned and processed to ensure good adhesion of the electrodes. Then, according to the design requirements, the positions and sizes of the positive electrode 6 and the reverse electrode 7 are determined, and a mask for the electrode pattern is fabricated on the chip surface using techniques such as photolithography. Then, a suitable electrode material is selected, such as a metal (such as gold, aluminum, etc.) or a conductive oxide, etc., and the electrode material is deposited on the chip surface by physical vapor deposition (PVD), chemical vapor deposition (CVD) or electroplating, etc. During the deposition process, parameters such as the deposition rate, thickness, and uniformity need to be controlled to ensure the quality and performance of the electrodes. Finally, techniques such as etching are used to remove the excess electrode material to form the desired positive electrode 6 and reverse electrode 7 patterns. Attention needs to be paid to controlling the etching depth and accuracy during the etching process to avoid damaging other parts of the chip.

[0120] Step S701: Thinning the substrate 8 to fabricate the reference electrode 1.

[0121] It can be understood that thinning the substrate 8 can reduce the overall thickness of the edge-emitting laser chip, making it more convenient to operate in subsequent processes such as fabricating the reference electrode 1. The thinner substrate 8 can reduce the material usage and cost, and in some applications, a thinner edge-emitting laser chip is more conducive to integration and packaging. At the same time, thinning the substrate 8 can increase the heat dissipation area of the edge-emitting laser chip and improve the heat dissipation efficiency. When the edge-emitting laser chip is working, it will generate a certain amount of heat. If the heat cannot be dissipated in time, it may affect the performance and lifespan of the edge-emitting laser chip. By thinning the substrate 8, the heat can be dissipated more quickly, reducing the operating temperature of the edge-emitting laser chip.

[0122] Among them, methods such as mechanical grinding, chemical mechanical polishing (CMP), or dry etching can be used to thin the substrate 8. These methods can precisely control the thickness of the substrate 8 and ensure the surface flatness and smoothness after thinning. During the thinning process, attention needs to be paid to avoiding damage to other parts of the chip.

[0123] Among them, a reference electrode 1 is fabricated on the thinned substrate 8. Process steps such as metal deposition, photolithography, and etching can be used to form the pattern of the reference electrode 1. Appropriate electrode materials, such as gold, aluminum, copper, etc., are selected to ensure good conductivity and stability. During the fabrication process, the thickness, shape, and position of the electrode need to be strictly controlled to meet the design requirements.

[0124] In some possible embodiments provided by the present application, step S201 includes:

[0125] Step S2011: A non-doped waveguide layer 32, an optical gain layer 31, and a non-doped waveguide layer 32 are sequentially grown on the side of the N-type injection layer 2 facing away from the substrate 8.

[0126] Specifically, semiconductor epitaxial growth techniques, such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), etc., are used to grow the non-doped waveguide layer 32 on the N-type injection layer 2. After the growth of the non-doped waveguide layer 32 is completed, the optical gain layer 31 is continuously grown. Finally, the non-doped waveguide layer 32 is grown again on the optical gain layer 31 to form a sandwich structure.

[0127] Step S2012: Remove the non-doped waveguide layer 32, the optical gain layer 31, and the non-doped waveguide layer 32 in the first region.

[0128] Among them, the first region is at least part of the region outside the projection range of the positive electrode 6 in the active region 3.

[0129] Specifically, a layer of photoresist is coated on the surface of the layered structure formed in step S2011, and then a specific pattern is exposed on the photoresist using a lithography machine, so that the first region is defined on the photoresist. The exposed photoresist will undergo a chemical change, and during the development process, the exposed part or the unexposed part is dissolved, thereby forming a mask on the photoresist with the same pattern as the region to be removed. Next, an etching process is used to remove the layers of materials in the region not protected by the photoresist. The etching process can be dry etching or wet etching.

[0130] Step S2013: Grow an N-type doped waveguide layer 33 in the first region.

[0131] Specifically, before growing the N-type doped waveguide layer 33, the surface of the first region needs to be treated to ensure its surface is clean and flat so that new materials can grow well. Then, a suitable waveguide material, such as InGaAsP, etc., is selected, and by introducing a precursor gas containing an N-type dopant, such as phosphine, etc., epitaxial growth is carried out under specific growth conditions. By precisely controlling the concentration of the dopant and the parameters during the growth process, the desired N-type doping level and waveguide layer performance can be achieved.

[0132] It is easy for those skilled in the art to understand that, on the premise of no conflict, the above advantageous ways can be freely combined and superimposed.

[0133] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application. The above is only the preferred implementation manner of the present application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the technical principle of the present application, several improvements and variations can also be made, and these improvements and variations should also be regarded as within the protection scope of the present application.

Claims

1. An edge-emitting laser chip, characterized in that: The invention comprises a reference electrode (1), wherein an N-type injection layer (2), an active area (3) and a P-type injection layer (4) are sequentially arranged on one side of the reference electrode (1), at least two electrical isolation areas (5) are arranged in the P-type injection layer (4), a first channel is formed between at least two of the electrical isolation areas (5), and second channels are respectively formed on two sides of at least two of the electrical isolation areas (5) away from the first channel; A forward electrode (6) and at least two reverse electrodes (7) are provided on the side of the P-type injection layer (4) facing away from the active area (3), and the forward electrode (6) is located between the at least two reverse electrodes (7); The forward electrode (6) has a positive potential compared to the reference electrode (1), and when a forward voltage is applied to the forward electrode (6), holes are injected into the quantum well of the active region (3) through the first channel, and electrons are also injected into the quantum well; At least two of the reverse electrodes (7) have a negative potential compared to the reference electrode (1); when a reverse voltage is applied to at least two of the reverse electrodes (7), the holes on one side of the quantum well flow into the reverse electrode (7) through the second channel, and the electrons on the other side of the quantum well flow into the reference electrode (1).

2. The edge-emitting laser chip according to claim 1, characterized in that: The active region (3) comprises a light gain layer (31), the light gain layer (31) is an InGaAsP layer, the thickness of the light gain layer (31) is 6nm-8nm, and the symmetry center of the light gain layer (31) coincides with the symmetry center of the forward electrode (6).

3. The edge-emitting laser chip according to claim 2, characterized in that: In the vertical direction, non-doped waveguide layers (32) are respectively arranged on both sides of the optical gain layer (31); in the horizontal direction, N-type doped waveguide layers (33) are respectively arranged on both sides of the optical gain layer (31).

4. The edge-emitting laser chip according to claim 2, characterized in that: The orthographic projection of the optical gain layer (31) on the N-type injection layer (2) is separated from or at least partially overlaps with the orthographic projections of at least two electrical isolation regions (5) on the N-type injection layer (2).

5. The edge-emitting laser chip according to claim 1, characterized in that: The electrical isolation region (5) penetrates the P-type injection layer (4).

6. The edge-emitting laser chip according to claim 1, characterized in that: The electrical isolation region (5) does not penetrate the P-type injection layer (4), and the distance between the electrical isolation region (5) and the active region (3) is 100 nm to 400 nm.

7. The edge-emitting laser chip according to claim 1, characterized in that: The electrical isolation region (5) is a groove opened on the P-type injection layer (4).

8. The edge-emitting laser chip according to claim 7, characterized in that: The groove is filled with an electrically isolated N-type material, and the electrically isolated N-type material is InP.

9. A method for manufacturing an edge-emitting laser chip, characterized in that: include: Growing an N-type implantation layer (2) on one side of the substrate (8); Growing an active region (3) on a side of the N-type injection layer (2) facing away from the substrate (8); Growing a P-type injection layer (4) on a side of the active region (3) away from the N-type injection layer (2); Removing part of the material of the P-type injection layer (4) to form at least two grooves; Growing electrically isolated N-type material in at least two of the grooves to form at least two electrically isolated regions (5); A forward electrode (6) is fabricated on a side of the P-type injection layer (4) away from the active region (3) and at a position relative to the quantum well of the active region (3), and reverse electrodes (7) are fabricated at a certain distance on both sides of the forward electrode (6) in a horizontal direction; The substrate (8) is thinned to produce a reference electrode (1), and the reference electrode (1) is produced by depositing metal on the back of the thinned substrate (8) and patterning it.

10. The method for manufacturing an edge-emitting laser chip according to claim 9, characterized in that: The step of growing an active region (3) on a side of the N-type injection layer (2) facing away from the substrate (8) comprises: Growing a non-doped waveguide layer (32), an optical gain layer (31) and a non-doped waveguide layer (32) in sequence on a side of the N-type injection layer (2) facing away from the substrate (8); removing the non-doped waveguide layer (32), the optical gain layer (31) and the non-doped waveguide layer (32) in the first region; Growing an N-type doped waveguide layer (33) in the first region; The first region is at least a portion of the positive electrode (6) outside the projection range of the active region (3).

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