A driving circuit for signal power composite isolation transmission

Abstract

The application discloses a kind of signal power composite isolation transmission drive circuit, belong to the field of power electronics.The drive circuit includes main transmission circuit and the forward time slot allocation circuit, reverse time slot allocation circuit, forward signal circuit, reverse signal circuit connected therewith;Two ends of main transmission circuit are connected with main control unit and power device respectively, and main transmission circuit accepts the input power of main control unit and the driving signal of forward signal circuit, and output driving voltage controls the turn-on and turn-off of power device;Main transmission circuit adjusts operating state according to the feedback signal received;Forward time slot allocation circuit is connected with forward signal circuit and main control unit, and reverse time slot allocation circuit is connected with reverse signal circuit and power device;Main control unit carries out early warning according to the fault signal received;Forward time slot allocation circuit and reverse time slot allocation circuit control the working state of main transmission circuit according to different signals.The driving signal and driving power are simultaneously transmitted through single isolation channel.

Description

Technical Field

[0001] The present invention belongs to the field of power electronics, and more specifically, relates to a driving circuit for signal power composite isolation transmission. Background Art

[0002] Improvements in the withstand voltage of power devices have significantly improved the size, efficiency, and cost of medium- and high-voltage converter systems, spurring rapid market growth in medium- and high-voltage applications such as solid-state transformers, medium-voltage drives, and medium-voltage converters. However, these developments present specific challenges for converter design, with isolated gate drive design being a major concern. Conventional isolated gate drives use digital isolators to transmit drive signals, but their operating voltage levels are limited to 1.7 kV. For voltages of 3.3 kV and above, optical fiber or optocouplers are required for isolated signal transmission, but these are costly, bulky, and sensitive to high temperatures (-40°C to 85°C), making integration difficult. The combined transmission of drive signals and power will lead to more integrated drive technologies and will also facilitate the integration of isolated gate drivers into chip and power device module packaging, improving reliability and optimizing switching characteristics.

[0003] In existing single-isolation channel composite transmission methods, the drive signal is used directly as the control signal for the drive power, or after being modulated by a high-frequency carrier, forming a power flow with signal characteristic information. However, the drive signal and power share the same modulation method, and the power switching frequency is the signal carrier frequency. This reduces the degree of modulation freedom, resulting in a low drive signal transmission rate and a narrow frequency and duty cycle range. This also affects the drive power transmission efficiency, output voltage regulation, and power density. Summary of the Invention

[0004] In view of the defects of the related art, the purpose of the present invention is to provide a driving circuit for signal-power composite isolated transmission, aiming to solve the problem that the driving signal and power share the same modulation path, the modulation freedom is low, and the transmission efficiency is low.

[0005] To achieve the above-mentioned object, the present invention provides a driving circuit for signal power composite isolation transmission, comprising a main transmission circuit and a forward time slot allocation circuit, a reverse time slot allocation circuit, a forward signal circuit, and a reverse signal circuit connected thereto;

[0006] The input end of the main transmission circuit is connected to the main control unit, and the output end is connected to the power device;

[0007] The forward time slot allocation circuit is connected to the forward signal circuit and the main control unit. The forward signal circuit is used to modulate the drive signal output by the main control unit and demodulate the fault signal and feedback signal modulated by the reverse signal circuit. The forward time slot allocation circuit is used to detect the drive signal. When the drive signal is present, the main transmission circuit is controlled to isolate and transmit the modulated drive signal from the primary side to the secondary side. The main control unit is used to issue an early warning based on the demodulated fault signal, and the main transmission circuit is used to adjust the operating state of the main transmission circuit based on the demodulated feedback signal.

[0008] The reverse time slot allocation circuit is connected to the reverse signal circuit and the power device. The reverse signal circuit is used to modulate the fault signal generated by the power device and the feedback signal generated by the main transmission circuit, and demodulate the drive signal transmitted by the main transmission circuit. The main transmission circuit is also used to output a drive voltage according to the demodulated drive signal to control the on and off of the power device. The reverse time slot allocation circuit is used to detect the feedback signal, the fault signal and the drive signal. When the feedback signal and the fault signal are present and the drive signal is absent, the reverse time slot allocation circuit controls the main transmission circuit to isolate and transmit the modulated feedback signal and the fault signal from the secondary side to the primary side.

[0009] The main transmission circuit is further used to transmit the input power of the main control unit from the primary side to the secondary side when there is no driving signal, feedback signal or fault signal.

[0010] Optionally, the reverse signal circuit is further used to modulate the restored driving signal obtained by demodulation, and the main transmission circuit is further used to isolate and transmit the modulated restored driving signal from the secondary side to the primary side;

[0011] The forward signal circuit is further configured to demodulate the modulated restored driving signal and compare it with the driving signal. If they are different, the driving signal is modulated and transmitted again.

[0012] Optionally, the main transmission circuit includes a DC-DC circuit, a voltage divider circuit and an output circuit;

[0013] The DC-DC circuit is used for driving the transmission channel of power and bidirectional signals;

[0014] The voltage divider circuit is used to generate a source reference potential to enable negative voltage driving of the power device;

[0015] The output circuit is used to achieve signal amplification and provide current to drive power devices.

[0016] Optionally, the DC-DC circuit is an LLC circuit, including: a first MOS transistor Q1, a second MOS transistor Q2, a first inductor L1, a first capacitor C1, a transformer TF, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, and a second capacitor C2;

[0017] The input voltage VIN is input to the drain of the first MOS transistor Q1 , and the source of the first MOS transistor Q1 is connected to the drain of the second MOS transistor Q2 and one end of the first inductor L1 , which is recorded as a first connection point;

[0018] The source of the second MOS transistor Q2 is grounded and connected to one end of the first capacitor C1. The other end of the first capacitor C1 is connected to one end of the primary winding of the transformer TF. The other end of the primary winding of the transformer TF is connected to the other end of the first inductor L1. The two ends of the secondary winding of the transformer TF are respectively connected to the input ends of the full-bridge rectifier circuit composed of the third diode D3, the fourth diode D4, the fifth diode D5 and the sixth diode D6, which are marked as the second connection point and the third connection point; the output end of the full-bridge rectifier circuit is connected to the two ends of the second capacitor C2, which are marked as the fourth connection point and the fifth connection point.

[0019] Optionally, the voltage divider circuit includes a second resistor R2 and a voltage stabilizing diode Z;

[0020] The second resistor R2 and the voltage stabilizing diode Z are connected in series and then connected in parallel across the second capacitor C2.

[0021] Optionally, the output circuit includes: a sixth MOS transistor Q6 and a seventh MOS transistor Q7;

[0022] The connection point is connected to the drain of the sixth MOS transistor Q6, the source of the sixth MOS transistor Q6 is connected to the source of the seventh MOS transistor Q7, and the connection point is a driving output end;

[0023] The gates of the sixth MOS transistor Q6 and the seventh MOS transistor Q7 are short-circuited, and the connection point is connected to the reverse signal circuit.

[0024] Optionally, the forward time slot allocation circuit includes: a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3 and a first resistor R1;

[0025] The first MOS transistor Q1 and the second MOS transistor Q2 are shared with the LLC circuit. The source of the third MOS transistor Q3 is grounded, and the drain is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to the first capacitor C1 and connected to one end of the primary winding of the transformer TF.

[0026] Optionally, a reverse time slot distribution circuit includes: a fourth MOS transistor Q4, a fifth MOS transistor Q5, a first diode D1, and a second diode D2;

[0027] The source of the fourth MOS transistor Q4 is connected to the driving output terminal, the drain is connected to the anode of the first diode D1, and the cathode of the first diode D1 is connected to one end of the secondary winding of the transformer TF;

[0028] The source of the fifth MOS transistor Q5 is connected to the fifth connection point, the drain is connected to the cathode of the second diode D2, and the anode of the second diode D2 is connected to the other end of the secondary winding of the transformer TF.

[0029] Compared with the prior art, the above technical solutions conceived by the present invention can achieve the following beneficial effects:

[0030] 1. The present invention provides a driving circuit for composite isolated transmission of signal and power, which transmits driving signals and driving power simultaneously through a single isolation channel, switches the main transmission circuit to transmit signals or power in different time slots according to whether there is a signal through a time slot allocation circuit, and uses independent branches to transmit signal streams and power streams respectively in different time slots, so that the driving signal and the driving power control signal are independent of each other in time, and the time slot occupied by signal transmission is much smaller than the power transmission time slot, thereby constructing a decoupled transmission architecture, and the circuits can be flexibly designed to meet the requirements of signal and power transmission, solving the problem that the driving signal and power share the same modulation path, the modulation freedom is low, and the transmission efficiency is low. High fidelity of the driving signal and efficient transmission of the driving power are achieved. Compared with the traditional driving architecture, no additional isolated power supply module or signal isolation unit is required, no digital processor and dedicated chip are required, the number of components is small, the cost is low, and the volume is small.

[0031] 2. The present invention provides a driving circuit for composite isolated transmission of signal power, and designs a forward signal circuit, a forward time slot allocation circuit, a reverse signal circuit and a reverse time slot allocation circuit respectively, so as to solve the problem that the signal for real-time monitoring of the power side status needs to be transmitted separately, and realizes the support of reverse signal transmission function, including device fault signals (device overcurrent, overvoltage and overheating signals), restored driving signals and driving power supply feedback signals (power supply output voltage or current information), to ensure efficient and reliable operation of the drive and devices.

[0032] 3. The present invention provides a driving circuit for signal-power composite isolated transmission. The time slot allocation circuit realizes rapid switching of signal and power states by maximizing the reuse of switching devices in the main transmission circuit. The number and volume of additional devices are small, and no floating ground drive is required. The control circuit is simple and efficient, which significantly improves the system integration and cost-effectiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a working concept diagram of the signal power time-sharing composite isolation drive provided by the present invention;

[0034] Figure 2 This is a circuit framework diagram of the signal power time-sharing composite isolation drive provided by the present invention;

[0035] Figure 3 A circuit diagram of a signal power time-sharing composite isolation drive provided by an embodiment of the present invention;

[0036] Figure 4 This is the overall transmission waveform diagram of the signal power time-sharing composite isolation drive provided by the embodiment of the present invention;

[0037] Figure 5 Operation effect diagram of signal power time-sharing composite isolation drive according to an embodiment of the present invention;

[0038] Figure 6 A multi-pulse test circuit for a signal power time-sharing composite isolation drive application according to an embodiment of the present invention;

[0039] Figure 7 1 is a diagram showing the switching waveforms of power devices in a signal power time-sharing composite isolation drive application according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0041] The contents involved in the above embodiment are described below in conjunction with a preferred embodiment.

[0042] like Figure 2 As shown, a driving circuit for signal power composite isolation transmission includes a main transmission circuit and a forward time slot allocation circuit, a reverse time slot allocation circuit, a forward signal circuit, and a reverse signal circuit connected thereto;

[0043] The input end of the main transmission circuit is connected to the main control unit, and the output end is connected to the power device;

[0044] The forward time slot allocation circuit is connected to the forward signal circuit and the main control unit. The forward signal circuit is used to modulate the drive signal output by the main control unit and demodulate the fault signal and feedback signal modulated by the reverse signal circuit. The forward time slot allocation circuit is used to detect the drive signal. When the drive signal is present, the main transmission circuit is controlled to isolate and transmit the modulated drive signal from the primary side to the secondary side. The main control unit is used to issue an early warning based on the demodulated fault signal, and the main transmission circuit is used to adjust the operating state of the main transmission circuit based on the demodulated feedback signal.

[0045] The reverse time slot allocation circuit is connected to the reverse signal circuit and the power device. The reverse signal circuit is used to modulate the fault signal generated by the power device and the feedback signal generated by the main transmission circuit, and demodulate the drive signal transmitted by the main transmission circuit. The main transmission circuit is also used to output a drive voltage according to the demodulated drive signal to control the on and off of the power device. The reverse time slot allocation circuit is used to detect the feedback signal, the fault signal and the drive signal. When the feedback signal and the fault signal are present and the drive signal is absent, the reverse time slot allocation circuit controls the main transmission circuit to isolate and transmit the modulated feedback signal and the fault signal from the secondary side to the primary side.

[0046] The main transmission circuit is further used to transmit the input power of the main control unit from the primary side to the secondary side when there is no driving signal, feedback signal or fault signal.

[0047] Optionally, the reverse signal circuit demodulates the driving signal transmitted by the main transmission circuit to obtain a restored driving signal;

[0048] The reverse signal circuit is further used to modulate the restored driving signal, and the main transmission circuit is further used to isolate and transmit the modulated restored driving signal from the secondary side to the primary side;

[0049] The forward signal circuit is further configured to demodulate the modulated restored driving signal and compare it with the driving signal. If they are different, the driving signal is modulated and transmitted again.

[0050] like Figure 1 As shown, this solution adopts time division multiplexing technology to modulate the power and bidirectional signals including the drive signal, fault signal, recovery drive signal and feedback signal respectively and transmit them through a single isolation channel in different time slots. The time slot occupied by signal transmission is much smaller than the power transmission time slot, and the signal and power transmission do not conflict with each other.

[0051] like Figure 2 As shown, the input power of the main control unit is connected to the primary side of the main transmission circuit, and the secondary side of the main transmission circuit outputs a driving voltage, which is connected to the gate-source of the power device to control the opening and closing of the power device; the input end of the forward time slot allocation circuit and the forward signal circuit is connected to the main control unit, receives the driving signal, and outputs a fault signal, and the output end is connected to the main transmission circuit; the fault signal is connected to the input end of the reverse time slot allocation circuit and the reverse signal circuit, and the output end of the reverse time slot allocation circuit and the reverse signal circuit is connected to the main transmission circuit.

[0052] The driving circuit for signal power composite isolation transmission provided by this solution includes a signal transmission working state and a power transmission working state. The signal transmission working state is divided into two states: forward transmission and reverse transmission.

[0053] During forward transmission: the main control unit transmits the driving signal to the forward signal circuit for modulation, the forward time slot allocation circuit controls the main transmission circuit to switch to the signal transmission working state, the main transmission circuit isolates and transmits the modulated driving signal from the primary side to the secondary side, and demodulates the modulated driving signal through the reverse signal circuit. The demodulated driving signal is then output through the main transmission circuit to control the opening and closing of the power device.

[0054] When transmitting in reverse:

[0055] The fault signal generated by the power device and the restored drive signal are transmitted to the reverse signal circuit, which modulates them. The reverse time slot allocation circuit controls the main transmission circuit to switch to the signal transmission operating state. The main transmission circuit isolates and transmits the modulated fault signal from the secondary side to the primary side. The modulated fault signal is demodulated by the forward signal circuit and then output to the main control unit through the forward signal circuit. The main control unit issues an early warning based on the fault signal. The demodulated restored drive signal is compared with the drive signal input to the main control unit. If there is a difference, the drive signal input to the main control unit is forwarded again. The feedback signal is the output voltage and current information of the main transmission circuit. During operation, the main transmission circuit samples the output voltage and current information and transmits it back to the primary side of the isolation transformer. The feedback signal controls the operating state of the main transmission circuit, achieving an output closed loop. For example, if the output voltage is greater than the set voltage (for example, the sampled voltage is 22V and the set voltage is 20V), the primary side switch tube is turned off, causing the main transmission circuit to stop running and the output voltage to gradually decrease. Conversely, when the output voltage drops below the set voltage, the switch tube is turned on, and the output voltage gradually increases, realizing an output closed loop. Specifically, the reverse signal circuit obtains the feedback signal from the main transmission circuit and pre-processes it. After the signal is modulated, it is reversely transmitted to the secondary side of the main transmission circuit through the reverse time slot allocation circuit, and then transmitted from the secondary side of the main transmission circuit to the primary side. The feedback signal is then demodulated by the forward time slot allocation circuit and the forward signal circuit connected to the primary side. The feedback signal is transmitted to the main transmission circuit for closed-loop control.

[0056] When there is no signal transmission, the time slot allocation circuit switches the circuit to the power transmission mode. When a forward signal (drive signal) or a reverse signal (fault signal / recovery drive signal / feedback signal) arrives, the circuit switches to the signal transmission state.

[0057] Optionally, the main transmission circuit includes a DC-DC circuit, a voltage divider circuit and an output circuit;

[0058] The DC-DC circuit is used for driving the transmission channel of power and bidirectional signals;

[0059] The voltage divider circuit is used to generate a source reference potential to enable negative voltage driving of the power device;

[0060] The output circuit is used to achieve signal amplification and provide current to drive power devices.

[0061] The output power of the DC-DC circuit is 1.5W, and the resonant frequency and switching frequency are both set to 20MHz, thereby achieving high driving power density and low signal transmission delay.

[0062] like Figure 3 As shown, optionally, the DC-DC circuit is an LLC circuit, including: a first MOS transistor Q1, a second MOS transistor Q2, a first inductor L1, a first capacitor C1, a transformer TF and a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, and a second capacitor C2;

[0063] The input voltage VIN is input to the drain of the first MOS transistor Q1 , and the source of the first MOS transistor Q1 is connected to the drain of the second MOS transistor Q2 and one end of the first inductor L1 , which is recorded as a first connection point;

[0064] The source of the second MOS transistor Q2 is grounded and connected to one end of the first capacitor C1. The other end of the first capacitor C1 is connected to one end of the primary winding of the transformer TF. The other end of the primary winding of the transformer TF is connected to the other end of the first inductor L1. The two ends of the secondary winding of the transformer TF are respectively connected to the input ends of the full-bridge rectifier circuit composed of the third diode D3, the fourth diode D4, the fifth diode D5 and the sixth diode D6, which are marked as the second connection point and the third connection point; the output end of the full-bridge rectifier circuit is connected to the two ends of the second capacitor C2, which are marked as the fourth connection point and the fifth connection point.

[0065] The voltage at the first connection point is v SW , the voltage at the second connection point is v A , the voltage of the third connection point is v B , where the second and third connection points are the two midpoint voltages of the rectifier bridge, and the voltage of the fourth connection point is V O , the voltage of the fifth connection point is GND_S, wherein the fourth connection point and the fifth connection point are grounded for the secondary side of the transformer TF, and the primary side and the secondary side are grounded differently.

[0066] Optionally, the voltage divider circuit includes a second resistor R2 and a voltage stabilizing diode Z;

[0067] The second resistor R2 and the voltage stabilizing diode Z are connected in series and then connected in parallel across the second capacitor C2.

[0068] The voltage divider circuit is used to generate a 5V reference voltage, provide a driving negative voltage reference potential and provide auxiliary power to the secondary side. The voltage at the series connection point of the second resistor R2 and the voltage stabilizing diode Z is 5V_S.

[0069] Optionally, the output circuit includes: a sixth MOS transistor Q6 and a seventh MOS transistor Q7;

[0070] The connection point is connected to the drain of the sixth MOS transistor Q6, the source of the sixth MOS transistor Q6 is connected to the source of the seventh MOS transistor Q7, and the connection point is a driving output end;

[0071] The gates of the sixth MOS transistor Q6 and the seventh MOS transistor Q7 are short-circuited, and the connection point is connected to the reverse signal circuit.

[0072] The connection point between the source of the sixth MOS transistor Q6 and the source of the seventh MOS transistor Q7 is recorded as the sixth connection point, and the voltage of the driving output terminal is v G The connection point where the gates of the sixth MOS transistor Q6 and the seventh MOS transistor Q7 are short-circuited is recorded as the seventh connection point. The seventh connection point is the input end of the push-pull circuit, and the voltage is v drive .

[0073] Optionally, the forward time slot allocation circuit includes: a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3 and a first resistor R1;

[0074] The first MOS transistor Q1 and the second MOS transistor Q2 are shared with the LLC circuit. The source of the third MOS transistor Q3 is grounded, and the drain is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to the first capacitor C1 and connected to one end of the primary winding of the transformer TF.

[0075] The third MOS transistor Q3 and the first resistor R1 are used to accelerate the discharge speed of the first capacitor C1, thereby accelerating the transient response speed of the LLC circuit.

[0076] The forward time slot allocation circuit is used to switch the working state of the main transmission circuit in different time slots according to the driving signal. The main transmission circuit isolates and transmits the modulated driving signal; thereby realizing the cutting off or transmission of signals and power to realize the time slot allocation function.

[0077] Optionally, a reverse time slot distribution circuit includes: a fourth MOS transistor Q4, a fifth MOS transistor Q5, a first diode D1, and a second diode D2;

[0078] The source of the fourth MOS transistor Q4 is connected to the driving output terminal, the drain is connected to the anode of the first diode D1, and the cathode of the first diode D1 is connected to one end of the secondary winding of the transformer TF;

[0079] The source of the fifth MOS transistor Q5 is connected to the fifth connection point, the drain is connected to the cathode of the second diode D2, and the anode of the second diode D2 is connected to the other end of the secondary winding of the transformer TF.

[0080] The reverse signal circuit is used to switch the working state of the main transmission circuit in different time slots according to the feedback signal and the fault signal, so as to realize the demodulation of the forward signal and the modulation of the reverse signal.

[0081] Specifically, Figure 4 This is the overall transmission waveform of the signal power time-sharing composite isolation drive provided by the embodiment of the present invention. GD Is the driving signal, SIG FB is the feedback signal, SIG Fault is the fault signal, v clock is the 20MHz oscillation signal voltage.

[0082] like Figure 4 As shown, at time t0, the driving signal SIG GD From low level to high level, the channel time slot is allocated to the rising edge transmission of the driving signal. S1-S5 are the control signals of the primary side switching devices in the main transmission circuit. Figure 4 S1-S5 control the first MOS transistor Q1 to the fifth MOS transistor Q5. 00 At this moment, the driving power stops transmitting, that is, S1~S2 are reset, S3 is set, and v sw 、v C and v A After the damped oscillation occurs, it decays to zero. 01 At this moment, S1 is modulated into three short pulses with a certain time interval, correspondingly at v sw and v A Three short pulses are generated on the 02 At this moment, the driving signal is restored, that is, SIG Re-GD From low level to high level. 03 At this moment, the driving power is transmitted normally, S3 is closed, and S1 and S2 are restored to 20MHz complementary square wave signals with dead time. When the driving signal is transmitted at the falling edge, see moment t2, its working principle is similar. The difference is that S1 is modulated into two short pulses with a certain time interval, correspondingly at v sw and v A Two short pulses are generated on the 22 At this moment, the driving signal falling edge is restored.

[0083] At time t1, the feedback signal SIG FB From low level to high level, the channel time slot is allocated to the rising edge transmission of the feedback signal. Specifically, at t10 At this moment, S5 is set for a certain time, and then 11 Original side v C Falling, triggering the S3 set signal, S1 ~ S2 reset, power transmission shut down. Then, at t 12 At this moment, according to the three signal states, S4 and S5 are modulated into three short pulses with a certain time interval, and correspondingly at v sw and v A Three short pulses are generated on the 13 The restored feedback signal is obtained by signal demodulation at time t 14 At this moment, the driving power is transmitted normally, and S1 to S3 return to their previous state. When the feedback signal is transmitted along the falling edge, see moment t3, the working principle is similar. The difference is that due to the different signal states, the modulation waveforms of S4 and S5 are different. For example, at t 32 At this moment, according to the three signal states, S4 and S5 are modulated into a short pulse, and accordingly at v sw and v A A short pulse is generated on the 33 The restored feedback signal is obtained by signal demodulation at all times. Similarly, when the fault signal SIG Fault When the rising edge comes, only the waveforms of S4 and S5 modulation need to be changed. For example, at t 42 At this moment, the restored driving signal and feedback signal are both high level, and S4 and S5 are modulated into four short pulses with a certain time interval, so that at t 43 The restored fault signal is obtained at all times through signal demodulation.

[0084] Figure 5 This is an operating effect diagram of a driving circuit for signal power composite isolation transmission according to an embodiment of the present invention (wherein, V O Set to 20V). Figure 6 As shown, the feedback signal is successfully transmitted to the primary side, and by controlling the primary-side LLC switch, the output voltage is stabilized at 20V, with a voltage ripple less than 0.3V, demonstrating a good closed-loop effect. The drive signal is successfully restored on the secondary side with a transmission delay of only 70ns. Simultaneously, the fault signal is accurately transmitted to the primary side, providing an alarm.

[0085] The composite isolation driving circuit provided by the embodiment of the present invention can be applied to high-speed driving of power semiconductor devices in upper and lower bridge arm circuits. Figure 6 This is a multi-pulse test circuit for a signal power time-sharing composite isolation drive application according to an embodiment of the present invention; the driven power switch tubes T1 and T2 have four connection terminals, that is, a power switch tube with four pins is used, including a gate G, a drain D, a source S, and a Kelvin source KS.

[0086] The driven power switch T1 can be a Si MOSFET, IGBT, SiC MOSFET, or GaN HEMT device. When the driven power switch T1 is a three-terminal device, the Kelvin source KS and the source S can be considered to be the same point.

[0087] Figure 7 FIG1 is a power device switching waveform diagram of a driving circuit for signal power composite isolation transmission according to an embodiment of the present invention. Figure 7 As shown, v GS is the gate-source voltage of the driven power switch tube T1, the switching frequency is 100kHz, which follows the driving signal well, and v GS The turn-on and turn-off voltages are stable at +15V / -5V respectively, indicating that the drive circuit can ensure the stability of drive power and voltage while transmitting signals. DS is the drain-source voltage of the driven power switch tube T1, i D is the drain current of the driven power switch tube T1. Before and after the on and off pulses of the driving signal arrive, v DS and i D The ability to switch the switch state normally indicates that the isolation driver has the ability to drive the power switch tube at high speed. L When the load inductor current reaches 125A, the overcurrent protection and fault signal are triggered. After the power switch tube is turned off, an alarm is successfully sent to the primary side, demonstrating the reliability of the isolated driver.

[0088] The embodiments of the present invention simultaneously transmit the drive signal and drive power through a single isolated channel. A time slot allocation circuit switches the operating state of the main transmission circuit in different time slots, making the drive signal and the drive power control signal temporally independent. The time slot occupied by signal transmission is much smaller than the power transmission time slot, thereby constructing a decoupled transmission architecture. Circuits can be flexibly designed to meet signal and power transmission requirements, resolving the issue of shared modulation paths for the drive signal and power, resulting in low modulation freedom and transmission efficiency. This approach achieves high-fidelity drive signal and efficient drive power transmission, reduces the number of components required for the drive circuit, and achieves the advantages of low cost and compact size.

[0089] It will be easily understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A driving circuit for signal power composite isolation transmission, characterized in that: It includes a main transmission circuit and a forward time slot allocation circuit, a reverse time slot allocation circuit, a forward signal circuit, and a reverse signal circuit connected thereto; The input end of the main transmission circuit is connected to the main control unit, and the output end is connected to the power device; The forward time slot allocation circuit is connected to the forward signal circuit and the main control unit. The forward signal circuit is used to modulate the drive signal output by the main control unit and demodulate the fault signal and feedback signal modulated by the reverse signal circuit. The forward time slot allocation circuit is used to detect the drive signal. When the drive signal is present, the main transmission circuit is controlled to isolate and transmit the modulated drive signal from the primary side to the secondary side. The main control unit is used to issue an early warning based on the demodulated fault signal, and the main transmission circuit is used to adjust the operating state of the main transmission circuit based on the demodulated feedback signal. The reverse time slot allocation circuit is connected to the reverse signal circuit and the power device. The reverse signal circuit is used to modulate the fault signal generated by the power device and the feedback signal generated by the main transmission circuit, and demodulate the drive signal transmitted by the main transmission circuit. The main transmission circuit is also used to output a drive voltage according to the demodulated drive signal to control the on and off of the power device. The reverse time slot allocation circuit is used to detect the feedback signal, the fault signal and the drive signal. When the feedback signal and the fault signal are present and the drive signal is absent, the reverse time slot allocation circuit controls the main transmission circuit to isolate and transmit the modulated feedback signal and the fault signal from the secondary side to the primary side. The main transmission circuit is also used to transmit the input power of the main control unit from the primary side to the secondary side when there is no driving signal, feedback signal and fault signal; The reverse time slot distribution circuit includes: a fourth MOS transistor Q4, a fifth MOS transistor Q5, a first diode D1 and a second diode D2; The source of the fourth MOS transistor Q4 is connected to the driving output terminal, the drain is connected to the anode of the first diode D1, and the cathode of the first diode D1 is connected to one end of the secondary winding of the transformer TF; The source of the fifth MOS transistor Q5 is connected to the fifth connection point, the drain is connected to the cathode of the second diode D2, and the anode of the second diode D2 is connected to the other end of the secondary winding of the transformer TF.

2. The driving circuit according to claim 1, wherein: The reverse signal circuit is further used to modulate the restored driving signal obtained by demodulation, and the main transmission circuit is further used to isolate and transmit the modulated restored driving signal from the secondary side to the primary side; The forward signal circuit is further configured to demodulate the modulated restored driving signal and compare it with the driving signal. If they are different, the driving signal is modulated and transmitted again.

3. The driving circuit according to claim 1, wherein: The main transmission circuit includes a DC-DC circuit, a voltage divider circuit and an output circuit; The DC-DC circuit is used for driving the transmission channel of power and bidirectional signals; The voltage divider circuit is used to generate a source reference potential to enable negative voltage driving of the power device; The output circuit is used to achieve signal amplification and provide current to drive power devices.

4. The driving circuit according to claim 3, wherein: The DC-DC circuit is an LLC circuit, including: a first MOS transistor Q1, a second MOS transistor Q2, a first inductor L1, a first capacitor C1, a transformer TF, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, and a second capacitor C2; The input voltage VIN is input to the drain of the first MOS transistor Q1 , and the source of the first MOS transistor Q1 is connected to the drain of the second MOS transistor Q2 and one end of the first inductor L1 , which is recorded as a first connection point; The source of the second MOS transistor Q2 is grounded and connected to one end of the first capacitor C1. The other end of the first capacitor C1 is connected to one end of the primary winding of the transformer TF. The other end of the primary winding of the transformer TF is connected to the other end of the first inductor L1. The two ends of the secondary winding of the transformer TF are respectively connected to the input ends of the full-bridge rectifier circuit composed of the third diode D3, the fourth diode D4, the fifth diode D5 and the sixth diode D6, which are marked as the second connection point and the third connection point; the output end of the full-bridge rectifier circuit is connected to the two ends of the second capacitor C2, which are marked as the fourth connection point and the fifth connection point.

5. The driving circuit according to claim 4, wherein: The voltage divider circuit includes a second resistor R2 and a voltage stabilizing diode Z; The second resistor R2 and the voltage stabilizing diode Z are connected in series and then connected in parallel across the second capacitor C2.

6. The driving circuit according to claim 4, wherein: The output circuit includes: a sixth MOS transistor Q6 and a seventh MOS transistor Q7; The connection point is connected to the drain of the sixth MOS transistor Q6, the source of the sixth MOS transistor Q6 is connected to the source of the seventh MOS transistor Q7, and the connection point is a driving output end; The gates of the sixth MOS transistor Q6 and the seventh MOS transistor Q7 are short-circuited, and the connection point is connected to the reverse signal circuit.

7. The driving circuit according to claim 4, wherein: The forward time slot allocation circuit includes: a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3 and a first resistor R1; The first MOS transistor Q1 and the second MOS transistor Q2 are shared with the LLC circuit. The source of the third MOS transistor Q3 is grounded, and the drain is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to the first capacitor C1 and connected to one end of the primary winding of the transformer TF.

Images