Constant charge control for DC-DC converters

Abstract

Embodiments of the present disclosure relate to constant charge control for DC-DC converters. Disclosed herein is a DC-DC converter comprising: a high-side power switch coupled between an input voltage and a switching node; and a low-side power switch coupled between the switch node and ground. An inductor is coupled between the switch node and the output node. An output capacitor is coupled between the output node and ground. The control circuit is configured to operate the high-side power switch in a constant charge mode of operation to vary the on-time of the high-side power switch to maintain a constant amount of charge transferred to the output capacitor during each charge cycle regardless of a change in the input voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of power electronics, and more particularly to regulating and controlling output voltage ripple in a DC-DC converter using pulse frequency modulation (PFM) and constant on-time (COT) control. Background Art

[0002] DC-DC converters are used for power management in a variety of electronic devices to convert input direct current (DC) at one voltage level to output DC at another voltage level. By adjusting the voltage levels in this way, DC-DC converters facilitate efficient power distribution within the device.

[0003] Common elements of known basic DC-DC converters such as buck converters and boost converters include power transistors and inductors. A power transistor, acting as a switch, is used to control the flow of current through a circuit. An inductor stores energy in its magnetic field when current flows through it, and subsequently releases that energy when the current flow is reduced or stopped.

[0004] One technique for controlling these converters involves the use of pulse frequency modulation (PFM). PFM control is a switch mode power supply control method in which the frequency of the power transformer is modulated to maintain regulation based on load conditions. One method of achieving pulse frequency modulation involves constant on-time (COT) control, which is a control technique in which the on-time of the power transistor is maintained constant while the off-time varies based on load conditions. In combination, PFM control and COT control can allow for fast and efficient control of DC-DC converters in certain situations. However, these controls can be affected by changes in output voltage ripple due to changes in line voltage.

[0005] Continuous conduction mode (CCM) control is a conventional approach used to address this challenge. In this mode, current flows continuously through the inductor and the converter is independent of the input voltage. However, CCM control is less efficient under light load conditions, where the constant switching frequency reduces the efficiency of the converter.

[0006] Another known method is adaptive constant on-time (ACOT) control, which incorporates an integral loop to adapt the on-time or peak current threshold based on the line voltage. However, this may result in slower converter response and consumes a larger physical area due to the presence of the integrator.

[0007] Therefore, there is a need for an improved control technique for a DC-DC converter that can maintain consistent charge injection into the output capacitor regardless of variations in line voltage. Preferably, such improved control techniques are expected to reduce output ripple, improve DC regulation, maintain high efficiency performance under various load conditions, and reduce system complexity. Summary of the invention

[0008] A DC-DC converter is disclosed herein, the DC-DC converter comprising: a high-side power switch coupled between an input voltage and a switched node; a low-side power switch coupled between the switched node and ground; an inductor coupled between the switched node and an output node; an output capacitor coupled between the output node and ground; and a control circuit. The control circuit is configured to operate the high-side power switch in a constant charge mode of operation to vary the on-time of the high-side power switch so as to maintain a constant amount of charge transferred to the output capacitor during each charging cycle, regardless of changes in the input voltage.

[0009] The control circuit may include: a peak inductor current threshold generator configured to generate a threshold voltage based on an input voltage and an output voltage at an output node, the threshold voltage indicating a desired peak current through the inductor; a peak current control circuit configured to compare the threshold voltage with a ramp voltage, the ramp voltage indicating a current through the inductor; and a controller configured to turn off the low-side power switch while turning on the high-side power switch until the ramp voltage becomes equal to the threshold voltage, and then turn off the high-side power switch while turning on the low-side power switch.

[0010] The peak current control circuit may include a comparator configured to compare a ramp voltage indicating a current through the inductor with a threshold voltage and generate a control signal based on the comparison. The peak current control circuit may also include a current subtractor configured to generate an output by subtracting a current indicating an output voltage from a current indicating an input voltage, the output including a ramp current, and a switch. The switch is configured to couple the peak current capacitor to ground when the control signal is asserted, and to couple the peak current capacitor to receive the ramp current when the control signal is de-asserted.

[0011] The peak inductor current threshold generator may include a current divider configured to generate a division current based on a division operation performed on a current indicative of an input voltage and an output of a current subtractor, and a rooting circuit configured to perform a square root operation on the division current and produce an output of the square root operation as a threshold voltage.

[0012] The current mirror may be configured to mirror the distributed current generated by the current divider to the root finding circuit.

[0013] The rooting circuit may include a first transistor coupled between a supply voltage and a first node, a gate of the first transistor coupled to be controlled according to the distribution current. The rooting circuit may also include a second transistor coupled between the first node and ground, a gate of the second transistor coupled to be controlled according to the voltage at the second node. The rooting circuit may also include a third transistor coupled between the second node and ground, a gate of the third transistor coupled to be controlled according to the voltage at the second node.

[0014] The root finding circuit further includes a fourth transistor coupled between the supply voltage and the second node, the fourth transistor being controlled according to the voltage at the third node.

[0015] The root finding circuit may further include a fifth transistor diode coupled between the fourth node and ground, wherein the distribution current is supplied to the fourth node.

[0016] The first transistor may be a first n-channel transistor, the first n-channel transistor having a drain connected to a supply voltage, a source connected to the first node, and a gate connected to a fourth node. The second transistor may be a second n-channel transistor, the second n-channel transistor having a drain connected to the first node, a source connected to the ground, and a gate connected to the second node. The third transistor may be a third n-channel transistor, the third n-channel transistor having a drain connected to the second node, a source connected to the ground, and a gate connected to the second node. The fourth transistor may be a first p-channel transistor, the first p-channel transistor having a source connected to the supply voltage, a drain connected to the second node, and a gate connected to the third node. The fifth transistor may be a fourth n-channel transistor, the fourth n-channel transistor having a drain connected to the fourth node, a source connected to the ground, and a gate connected to the fourth node.

[0017] The current mirror may be configured to mirror the distributed current generated by the current distributor to the root-finding circuit. The current mirror may include: a sixth transistor coupled to receive the distributed current; a seventh transistor coupled to the sixth transistor in a mirror relationship, thereby absorbing a copy of the distributed current from the third node; an eighth transistor coupled to have a copy of the distributed current absorbed from the eighth transistor; a ninth transistor coupled to the eighth transistor in a mirror relationship, thereby supplying the distributed current to the fourth node; and a tenth transistor coupled to the ninth transistor in a mirror relationship.

[0018] The sixth transistor may be a fifth n-channel transistor, the fifth n-channel transistor having: a drain coupled to receive the distribution current; a gate connected to the drain of the fifth n-channel transistor; and a source connected to the ground. The seventh transistor may be a sixth n-channel transistor, the sixth n-channel transistor having: a drain connected to the third node; a source connected to the ground; and a gate connected to the third node, the seventh transistor being in a mirror relationship with the sixth transistor. The eighth transistor may be a second p-channel transistor (MP1), the second p-channel transistor having: a source connected to the supply voltage; a drain connected to the third node; and a gate connected to the third node. The ninth transistor may be a third p-channel transistor, the third p-channel transistor having: a source connected to the supply voltage; a drain connected to the fourth node; and a gate connected to the third node. The tenth transistor may be a fourth p-channel transistor, the fourth p-channel transistor having: a source connected to the supply voltage; a drain connected to the ground; and a gate connected to the third node.

[0019] Method aspects are also disclosed herein. For example, a method of operating a DC-DC converter is disclosed herein, the method comprising: in response to each time a feedback voltage is equal to or lower than a reference voltage, turning off a low-side power switch and turning on a high-side power switch, thereby starting a charging cycle. The method may also include setting an on-time of the high-side power switch to maintain a constant amount of charge transferred from an input node to an output capacitor in cooperation with an inductor during each charging cycle, regardless of changes in the input voltage at the input node.

[0020] Setting the on-time of the high-side power switch to maintain a constant amount of charge transferred from the input node to the output capacitor with the cooperation of the inductor during each charging cycle, regardless of the input voltage at the input node, can be performed by: generating a threshold voltage based on the input voltage and the output voltage at the output node, the threshold voltage indicating a desired peak current through the inductor; comparing the threshold voltage with a ramp voltage, the ramp voltage indicating the current through the inductor; and turning on the high-side power switch while turning off the low-side power switch until the peak voltage becomes equal to the threshold voltage, then turning on the low-side power switch while turning off the high-side power switch, and then turning off the low-side power switch when the current through the inductor passes through zero.

[0021] Generating the threshold voltage may include: generating a distributed current based on a distribution operation performed on an output of a current indicating an input voltage and a difference between the current indicating the input voltage and a current indicating an output voltage; and performing a square root operation on the distributed current and producing an output of the square root operation as the threshold voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a block diagram of the DC-DC converter disclosed in this article.

[0023] Figure 2 yes Figure 1 Block diagram of the peak inductor current threshold generator and peak current control circuit.

[0024] Figure 3 yes Figure 2 Schematic diagram of the peak inductor current threshold generator.

[0025] Figure 4 It is shown that when operating according to the prior art Figure 1 A graph of the inductor current of a DC-DC converter varying with time.

[0026] Figure 5 is a graph showing the constant charge control technique of the present disclosure when operating. Figure 1 A graph of the inductor current of a DC-DC converter varying with time.

[0027] Figure 6 is a graph showing the constant charge control technique of the present disclosure when operating. Figure 1 A graph showing the output voltage ripple variation over time of a DC-DC converter relative to the ripple variation of a converter operated according to the prior art. DETAILED DESCRIPTION

[0028] The following disclosure enables those skilled in the art to make and use the subject matter described herein. Without departing from the spirit and scope of the present disclosure, the general principles outlined in the present disclosure may be applied to embodiments and applications other than those detailed above. It is not intended to limit the present disclosure to the embodiments shown, but rather to have the widest scope consistent with the principles and features disclosed or suggested herein.

[0029] Note that in the following description, unless otherwise stated, any resistor or resistance mentioned is a discrete device and is not merely an electrical lead between two points. Therefore, any resistor or resistance connected between two points has a higher resistance than the lead between the two points, and such a resistor or resistance cannot be interpreted as a lead. Similarly, unless otherwise stated, any capacitor or capacitance mentioned is a discrete device and is not a parasitic element unless otherwise stated. In addition, unless otherwise stated, any inductor or inductance mentioned is a discrete device and is not a parasitic element unless otherwise stated.

[0030] The synchronous buck converter 10 is now described. The synchronous buck converter 10 includes a first MOS TR1 connected to an input voltage V INand a switching node N, wherein the gate of the first MOS TR1 is driven by the output of the high-side driver 11. The synchronous buck converter 10 further includes a second MOS TR2, which is located between the switching node N and ground, wherein the gate of the second MOS TR2 is driven by the output of the low-side driver 12. The inductor L is connected between the switching node N and the output voltage node No. The output capacitor C is connected between the output node No and ground, and an output voltage V is generated at the output node No. OUT . is expressed as the absorbed load current l LOAD The load 33 of the current source is illustrated as being connected between the output node No and the ground. A feedback ladder formed by resistors RUP and RDN is connected in series between the output node No and the ground, wherein a feedback voltage V is generated at a tap node Nf located between the resistors. FBK The comparator 16 receives the feedback voltage V at its non-inverting input terminal. FBK , and receives a reference voltage V at its inverting input terminal REF , and generates an output comparison signal V based on the comparison COMPARE ——As an example, V COMPARE The feedback voltage V FBK Equal to or greater than the reference voltage V REF As an alternative, comparator 16 may be configured such that V COMPARE The feedback voltage V FBK Less than the reference voltage V REF The control circuit 19 is responsible for determining the logic high when the comparison signal V COMPARE Pre-driving signals are generated to the high-side driver 11 and the low-side driver 12 , and thus the control circuit 19 can be considered to operate to turn on or off the transistors TR1 and TR2 .

[0031] First, the operation of the synchronous buck converter 10 in the conventional constant on-time (COT) mode is described. In this mode, the output voltage V OUT The charging cycle starts when the input voltage V drops below the specified reference level, thereby triggering the charging cycle. During this charging cycle, the transistor TR1 is turned on by the control circuit 19, thereby charging the inductor L to the input voltage V IN. Thereafter, transistor TR1 is turned off while transistor TR2 is turned on by control circuit 19, thereby connecting switch node N to ground. In this mode of operation, the duration of the on-time of transistor TR1 is constant, while the duration of the on-time of transistor TR2 is variable. This dynamic switching action of transistors TR1 and TR2 generates a square wave at node N, which is filtered by the LC filter formed by inductor L and output capacitor C and allows the input voltage V IN Gradually decrease.

[0032] However, considering the input voltage V IN If the on-time of transistor TR1 is kept constant, the peak value of inductor current IL I LPEAK will change, causing the amount of charge injected into the output capacitor C to change. This causes regulation error because when the input voltage V IN changes, it causes a lack of stable output voltage V OUT .

[0033] Therefore, the purpose of the control circuit 19 is to control the synchronous buck converter 10 to be in a constant charge mode of operation, in which the amount of charge transferred during each charging cycle is maintained constant, with respect to the input voltage V IN This is done by controlling the high-side transistor TR1 based on the input voltage V IN and output voltage V OUT Changing the peak inductor current I LPEAK To achieve.

[0034] The charge ΔQ injected into the output capacitor C can be expressed mathematically as shown below, which shows its relationship with the peak inductor current I LPEAK 、Input voltage V IN , output voltage V OUT 、Load current I LOAD And the relationship between the inductance L of the inductor.

[0035]

[0036] This equation can be rearranged to solve for I LPEAK :

[0037]

[0038] The switching frequency (Fsw) of transistor TR1 can then be adjusted by dividing the load current I LOAD Divide by the change in charge ΔQ to calculate:

[0039]

[0040] The voltage ripple ΔV can also be calculated by dividing the change in charge ΔQ by the capacitance C:

[0041]

[0042] This information is utilized through a feed-forward mechanism provided by the peak inductor current threshold generator 17 and the peak current control circuit 18 to predict the input voltage V IN This mechanism allows the peak inductor current I to be adjusted accordingly LPEAK , to maintain a constant amount of charge being transferred to the output capacitor C during each charging cycle.

[0043] In the context of the block diagram, the input voltage V IN The peak current is monitored by the peak current control circuit 18 and the peak inductor current threshold generator 17. The peak inductor current threshold generator 17 adapts the threshold to the input voltage V IN , and the peak current control circuit 18 tracks the current flowing through the inductor L, together generating a digital signal to the asynchronous finite state machine (AFSM) circuit 15, which in turn sets the duration of the on-time of transistor TR1. During the off-time of transistor TR1, the AFSM circuit 15 turns on transistor TR2. This together provides a constant charge on capacitor C during each charging cycle, regardless of the input voltage V IN This in turn allows maintaining a constant output voltage V OUT and switching frequency Fsw, regardless of the input voltage V IN changes.

[0044] This constant charge mode of operation (and the circuit arrangement implementing it) is the subject of the present disclosure and will now be explained in detail. Operation in this mode is carried out at an output voltage V OUT When the feedback voltage V FBK drops below the reference voltage V that triggers a charging cycle REF Indicates that the on-time of the high-side transistor TR1 is thus set by the control circuit 19. Specifically, during the off-time period, the AFSM circuit 15 turns on the transistor TR2, and during the on-time period, the transistor TR1 is turned on as described above while the transistor TR2 is turned off.

[0045] The control circuit 19 includes a peak inductor current threshold generator 17 that generates a peak inductor current threshold value indicative of a desired peak inductor current I LPEAK The voltage V THPEAK Based on this voltage, the peak current control circuit 18 generates a peak current control signal CTRL PK . Peak current control signal CTRLPK And the comparison signal V COMPARE is received as input by the AFSM circuit 15. Based on these inputs, the AFSM circuit 15 generates a high-side start signal START H and low-side start signal START L , where the high-side stop signal STOP H Equivalent to the low-side start signal START L In particular, when the comparator 16 responds to the feedback voltage V FBK becomes lower than the reference voltage V REF While asserting the output comparison signal V COMPARE When the AFSM circuit 15 asserts the high-side start signal START H To cause transistor TR1 to turn on and assert the low-side stop signal STOP L When the AFSM 15 asserts the peak current control signal CTRL in response to the peak current control circuit 18 PK While asserting the high-side stop signal STOP H This causes transistor TR1 to turn off, which is also the low-side start signal START L The assertion of the low-side stop signal STOP causes the transistor TR2 to turn on, wherein once the zero-crossing detector 29 asserts the low-side stop signal STOP L , then the transistor TR2 is subsequently turned off, thereby causing the transistor TR2 to turn off in response to the zero crossing of the coil current IL.

[0046] The control circuit 19 includes a high-side pre-driver 13 and a low-side pre-driver 14. The high-side pre-driver 13 is based on the high-side start signal START. H And the high-side stop signal STOP H Generates a pre-driving signal for the high-side driver 11, and the low-side pre-driver 14 is based on the low-side start signal START L And the low-side stop signal STOP L A pre-drive signal for the low-side driver 14 is generated.

[0047] Now refer to Figure 2 A general embodiment of the peak inductor current threshold generator 17 and the peak current control circuit 18 is described. The peak current control circuit 18 effectively replicates the information contained in equation (2) above about the current IL flowing through the inductor L, while the peak inductor current threshold generator 17 sets a value indicating the desired peak inductor current I LPEAK The voltage V THPEAK .

[0048] The peak inductor current threshold generator 17 includes a current subtracting junction 21. The current subtracting junction 21 is connected to the output voltage V OUT Proportional current From the input voltage V IN Another current proportional to This operation essentially produces Represents the current, which is related to the input voltage V IN With the output voltage V OUT is proportional to the difference between them.

[0049] Current and I SUB It is then fed into the current divider 22. The output current of this component The current I DIV Indicates the subtracted current I SUB With input voltage V IN The ratio between the current I DIV is sent to the rooting circuit 24. The rooting circuit performs a square root operation and a current-to-voltage conversion. The resulting voltage applied to the negative input terminal of the comparator 20 of the peak current control circuit 18 is is an indication of the desired peak inductor current I LPEAK The voltage threshold can be expressed as:

[0050]

[0051] The peak current control circuit 18 is now described. The switch SW connects the capacitor C PEAK discharge to ground, or connect the current subtraction node 21 to the capacitor C PEAK , to receive equal to I SUB The ramp current I SUB ; The switch SW is closed at the end of each high-side conduction cycle (at the end of each cycle of transistor TR1), resetting the capacitor C PEAK The voltage across the capacitor C PEAK The voltage across the two ends is V RAMP (representing the current IL through the inductor L) is zero.

[0052] Therefore, comparator 20 receives voltage V at its non-inverting input terminal RAMP , and receives at its inverting input a voltage V generated by the rooted and converted current from the rooting circuit 24 THPEAK , and in response to V RAMP becomes at least equal to V THPEAK And assert that its output CTRLPK .

[0053] Adaptive control circuit 19 helps to ensure that the voltage at the positive input of comparator 20 is equal to the input voltage V IN The proportional voltage ramp simulates the behavior of the inductor current IL. The capacitor C PEAK is chosen so that the equation is satisfied, causing the ramp current I RAMP Has the desired waveform.

[0054] This approach allows the adaptive control circuit 19 to help ensure that changes in the input voltage correspondingly adjust the peak inductor current threshold I L，peakTH And an efficient peak current flows through the inductor L. This maintains efficient operation of the DC-DC converter and provides a stable output voltage regardless of changes in the input voltage.

[0055] Reference now Figure 3 The transistor level design of FIG. 1 gives additional details of the peak inductor current threshold generator 17. Note here that current generator 31 sinks current IB from shunt 22, which converts Divide by I SUB , generating the distributed current I DIV .

[0056] The current mirror 23 is now described. The current mirror 23 includes an n-channel transistor MN1 having a drain coupled to receive the distributed current I DIV ; a source connected to ground; and a gate connected to the gate of the n-channel transistor MN2. The source of the n-channel transistor MN2 is further connected to ground, and the drain of the n-channel transistor MN2 is connected to the node A2. The p-channel transistor MP1 has: a source connected to the power supply voltage VDD; a drain connected to the node A2; and a gate connected to the node A2. The p-channel transistor MP2 has: a source connected to the power supply voltage VDD; a drain connected to the node A3; and a gate connected to the node A2.

[0057] The rooting circuit 24 is now described, and includes a diode-coupled n-channel transistor M2 connected between node A3 and ground. The n-channel transistor M1 has a drain connected to the power supply voltage VDD, a source connected to node A4, and a gate connected to node A3. The n-channel transistor MN3 has a drain connected to node A4, a source connected to ground, and a gate connected to node A5. The p-channel transistor MP3 has a source connected to the power supply voltage VDD, a drain connected to node A5, and a gate connected to node A2. The n-channel transistor MN4 has a drain connected to node A5, a source connected to ground, and a gate connected to node A5. The voltage V THPEAK is generated at node A4.

[0058] Now describe Figure 3 The operation of the peak inductor current threshold generator 17. The rooting circuit 24 converts the distributed current I generated by the shunt 22 into DIV As input, this divided current is thereby mirrored and fed to the diode coupled transistor M2, so that the gate to source voltage of M2 is:

[0059]

[0060] The threshold voltage V of transistor M2 TH is subtracted via transistor M1, which has a sufficiently large aspect ratio to allow the overdrive voltage V OV Can be ignored. Output voltage V THPEAK for:

[0061]

[0062] refer to Figures 4 to 6 The benefits of the synchronous buck converter 10 disclosed herein can be appreciated. If the synchronous buck converter 10 were to be controlled according to a prior art COT control system operating with a standard constant on-time, then Figure 4 FIG. 3 shows the variation of the inductor current IL with time. Figure 5 FIG. 1 shows that if the synchronous buck converter 10 is controlled according to the constant charge scheme disclosed herein, the variation of the inductor current IL over time causes the charge transferred to the output capacitor C to vary with the input voltage V IN independent of the output voltage V OUT From this curve, it can also be seen that the voltage V THPEAK With the input voltage V IN Finally, from Figure 6In the graphs of FIG. 1 , it can be seen that the ripple variation of the prior art COT control system is high compared to the ripple variation of the constant charge scheme disclosed herein. High ripple can cause noise, cause undesirable interference in the circuit, and may negatively affect the life of the capacitors in the converter.

[0063] Finally, it is obvious that modifications and variations may be made to what has been described and illustrated herein without departing from the scope of the present disclosure.

[0064] Although the present disclosure has been described with a limited number of embodiments, those skilled in the art having benefit of the present disclosure may conceive of other embodiments that do not depart from the scope of the disclosure. In addition, those skilled in the art may conceive of embodiments that represent various combinations of the embodiments disclosed herein in various ways.

Claims

1. A DC-DC converter, comprising: a high-side power switch coupled between the input voltage and a switch node; a low-side power switch coupled between the switch node and ground; an inductor coupled between the switch node and an output node; an output capacitor coupled between the output node and ground; as well as A control circuit is configured to operate the high-side power switch in a constant charge mode of operation to vary the on-time of the high-side power switch to maintain a constant amount of charge transferred to the output capacitor during each charging cycle regardless of changes in the input voltage.

2. The DC-DC converter according to claim 1, wherein the control circuit comprises: a peak inductor current threshold generator configured to generate a threshold voltage based on the input voltage and an output voltage at the output node, the threshold voltage being indicative of a desired peak current through the inductor; a peak current control circuit configured to compare the threshold voltage to a ramp voltage indicative of a current through the inductor; as well as A controller is configured to turn off the low-side power switch while turning on the high-side power switch until the ramp voltage becomes equal to the threshold voltage, and then turn off the high-side power switch while turning on the low-side power switch.

3. The DC-DC converter according to claim 2, wherein the peak current control circuit comprises: a comparator configured to compare the ramp voltage indicative of the current through the inductor with the threshold voltage and to generate a control signal based on the comparison; a current subtractor configured to generate an output by subtracting a current indicative of the output voltage from a current indicative of the input voltage, the output comprising a ramp current; Peak current capacitor; as well as A switch is configured to couple the peak current capacitor to ground when the control signal is asserted, and to couple the peak current capacitor to receive the ramp current when the control signal is de-asserted.

4. The DC-DC converter of claim 3, wherein the peak inductor current threshold generator comprises: a current distributor configured to generate a distribution current based on a distribution operation performed on the current indicative of the input voltage and the output of the current subtractor; as well as The root finding circuit is configured to perform a square root operation on the distributed current and generate an output of the square root operation as the threshold voltage. 5 . The DC-DC converter according to claim 4 , further comprising a current mirror configured to mirror the distributed current generated by the current distributor to the root-finding circuit.

6. The DC-DC converter according to claim 4, wherein the root-finding circuit comprises: a first transistor coupled between a supply voltage and a first node, a gate of the first transistor coupled to be controlled according to the distributed current; a second transistor coupled between the first node and ground, a gate of the second transistor coupled to be controlled according to a voltage at a second node; as well as A third transistor is coupled between the second node and ground, and a gate of the third transistor is coupled to be controlled according to the voltage at the second node. 7 . The DC-DC converter according to claim 6 , wherein the root finding circuit further comprises a fourth transistor coupled between the supply voltage and the second node, the fourth transistor being controlled according to a voltage at a third node. 8 . The DC-DC converter of claim 7 , wherein the root finding circuit further comprises a fifth transistor diode coupled between a fourth node and ground, wherein the distribution current is supplied to the fourth node.

9. The DC-DC converter according to claim 8, wherein: The first transistor comprises a first n-channel transistor having: a drain connected to the supply voltage; a source connected to the first node; and a gate connected to the fourth node; The second transistor includes a second n-channel transistor having: a drain connected to the first node; a source connected to ground; and a gate connected to the second node; The third transistor includes a third n-channel transistor having: a drain connected to the second node; a source connected to ground; and a gate connected to the second node; The fourth transistor includes a first p-channel transistor having: a source connected to the supply voltage; a drain connected to the second node; and a gate connected to the third node; as well as The fifth transistor includes a fourth n-channel transistor having: a drain connected to the fourth node; a source connected to the ground; and a gate connected to the fourth node.

10. The DC-DC converter according to claim 9, Also included is a current mirror configured to mirror the distributed current generated by the current distributor to the root-finding circuit; and The current mirror comprises: a sixth transistor coupled to receive the distributed current; a seventh transistor coupled to the sixth transistor in a mirror relationship, thereby sinking a copy of the distributed current from the third node; an eighth transistor coupled to have a copy of the distributed current sunk by the eighth transistor; a ninth transistor coupled to the eighth transistor in a mirror relationship, thereby supplying the distributed current to the fourth node; and The tenth transistor is coupled to the ninth transistor in a mirror relationship.

11. The DC-DC converter according to claim 10, wherein: The sixth transistor includes a fifth n-channel transistor having: a drain coupled to receive the distributed current; a gate connected to the drain of the fifth n-channel transistor; and a source, connected to ground; The seventh transistor includes a sixth n-channel transistor having: a drain connected to the third node; The source, is connected to ground; A gate connected to the third node, the seventh transistor and the sixth transistor are in a mirror relationship; The eighth transistor includes a second p-channel transistor having: a source connected to the supply voltage; a drain connected to the third node; and a gate connected to the third node; The ninth transistor includes a third p-channel transistor, the third p-channel transistor having: a source connected to the supply voltage; a drain connected to the fourth node; and a gate connected to the third node; and The tenth transistor includes a fourth p-channel transistor MP3 having a source connected to the supply voltage, a drain connected to the ground, and a gate connected to the third node.

12. A method of operating a DC-DC converter, comprising: In response to each time the feedback voltage is equal to or lower than the reference voltage, turning off the low-side power switch and turning on the high-side power switch, thereby starting a charging cycle; as well as The on-time of the high-side power switch is set to maintain a constant amount of charge transferred from the input node to the output capacitor in cooperation with the inductor during each charging cycle regardless of changes in the input voltage at the input node.

13. The method of claim 12 , wherein setting the on-time of the high-side power switch to maintain the constant amount of the charge transferred from the input node to the output capacitor in cooperation with the inductor during each charging cycle regardless of the input voltage at the input node is performed by: generating a threshold voltage based on the input voltage and an output voltage at an output node, the threshold voltage being indicative of a desired peak current through the inductor; comparing the threshold voltage to a ramped voltage indicative of current through the inductor; as well as The low-side power switch is turned off while the high-side power switch is turned on until the peak voltage becomes equal to the threshold voltage, and then the high-side power switch is turned off while the low-side power switch is turned on, and then the low-side power switch is turned off when the current through the inductor passes through zero.

14. The method of claim 13, wherein generating the threshold voltage comprises: generating a distribution current based on a distribution operation performed on an output of a current indicative of the input voltage and a difference between the current indicative of the input voltage and a current indicative of the output voltage; as well as A square root operation is performed on the distributed current, and an output of the square root operation is generated as the threshold voltage.

15. A DC-DC converter, comprising: a high-side power switch coupled between the input voltage and a switch node; a low-side power switch coupled between the switch node and ground; an inductor coupled between the switch node and an output node; an output capacitor coupled between the output node and ground; as well as A control circuit, the control circuit comprising: a peak inductor current threshold generator configured to generate a threshold voltage based on the input voltage and an output voltage at the output node, the threshold voltage being indicative of a desired peak current through the inductor; a peak current control circuit configured to compare the threshold voltage to a ramp voltage indicative of a current through the inductor; and A controller is configured to turn off the low-side power switch while turning on the high-side power switch until the ramp voltage becomes equal to the threshold voltage, and then turn off the high-side power switch while turning on the low-side power switch.

16. The DC-DC converter according to claim 15, wherein the peak current control circuit comprises: a comparator configured to compare the ramp voltage indicative of the current through the inductor with the threshold voltage and to generate a control signal based on the comparison; a current subtractor configured to generate an output by subtracting a current indicative of the output voltage from a current indicative of the input voltage, the output comprising a ramp current; Peak current capacitor; as well as A switch is configured to couple the peak current capacitor to ground when the control signal is asserted, and to couple the peak current capacitor to receive the ramp current when the control signal is de-asserted.

17. The DC-DC converter of claim 16, wherein the peak inductor current threshold generator comprises: a current distributor configured to generate a distribution current based on a distribution operation performed on the current indicative of the input voltage and the output of the current subtractor; as well as The root finding circuit is configured to perform a square root operation on the distributed current and generate an output of the square root operation as the threshold voltage. 18 . The DC-DC converter according to claim 17 , further comprising a current mirror configured to mirror the distributed current generated by the current distributor to the root-finding circuit.

Images