Quadruple frequency circuit, signal processing method and communication chip

Abstract

The present application provides a quadruple frequency circuit, a signal processing method and a communication chip, wherein the circuit includes a first double frequency circuit, a second double frequency circuit and a calibration circuit, wherein the first double frequency circuit is used to receive the first clock signal output by the external circuit, and output a first calibration clock signal, and output a second clock signal with double frequency according to the first clock signal and the error control signal output by the calibration circuit, the second double frequency circuit is used to receive the second clock signal, and output a third clock signal with quadruple frequency, the calibration circuit is used to receive the first calibration clock signal and the second clock signal, and output the error control signal. The second clock signal generated by the first double frequency circuit is calibrated for duty cycle by the calibration circuit, thereby improving the frequency stability and noise performance of the third clock signal generated by the second double frequency circuit, the design is simple, the chip area is small, and the economic benefit is high.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a quadruple frequency circuit, a signal processing method and a communication chip. Background Art

[0002] With the development of the fifth-generation mobile communication technology (5G), 5G communication technology has higher and higher requirements for the local oscillator (LO). The LO signal is generally provided by a phase-locked loop (PLL). The higher the reference clock frequency, the better the jitter performance of the phase-locked loop.

[0003] The existing technology generally adopts a dual phase-locked loop structure to achieve a high-performance phase-locked loop. The output clock of the first-stage phase-locked loop is used as the input reference clock of the second-stage phase-locked loop. This solution can improve the performance of the second-stage phase-locked loop, but the design is complex, the circuit area and power consumption are large, and the overall economic benefit is poor. Summary of the invention

[0004] The object of the present invention is to provide a quadruple frequency circuit, a signal processing method and a communication chip to solve the technical problems in the prior art of complex dual phase-locked loop structure design, large circuit area and large power consumption.

[0005] In order to achieve the above objectives, the first aspect of the present application discloses a quadruple frequency circuit, comprising:

[0006] A first frequency doubling circuit connected to the output terminals of the external circuit and the calibration circuit, configured to receive a first clock signal output by the external circuit, output a first calibration clock signal, and output a second clock signal with a doubled frequency according to the first clock signal and the error control signal output by the calibration circuit;

[0007] a second frequency doubling circuit connected to the output end of the first frequency doubling circuit, configured to receive the second clock signal and output a third clock signal with a quadrupled frequency;

[0008] The calibration circuit is connected to the output end of the first double frequency circuit, and is configured to receive the first calibration clock signal and the second clock signal, and output the error control signal.

[0009] Optionally, the first double frequency circuit includes:

[0010] a first buffer circuit, wherein an input end of the first buffer circuit is connected to the external circuit and configured to output the first calibration clock signal and a first intermediate clock signal after performing amplitude shaping and / or phase calibration on the first clock signal;

[0011] a first digital-to-time converter circuit, wherein an input terminal of the first digital-to-time converter circuit is respectively connected to an output terminal of the first buffer circuit and an output terminal of the calibration circuit, and is configured to adjust a delay of the first intermediate clock signal according to the error control signal;

[0012] A first XOR circuit, wherein the input end of the first XOR circuit is respectively connected to the output end of the first buffer circuit and the output end of the first digital-to-time converter circuit, and is configured to output the second clock signal according to the adjusted first intermediate clock signal.

[0013] Optionally, the calibration circuit includes:

[0014] a duty cycle detection circuit, wherein an input end of the duty cycle detection circuit is connected to an output end of the first double frequency circuit, and is configured to detect a duty cycle of the second clock signal to obtain a duty cycle detection voltage;

[0015] a comparator circuit, wherein an input end of the comparator circuit is connected to an output end of the duty cycle detection circuit and is configured to compare and process the duty cycle detection voltage to obtain a state indication signal;

[0016] a second buffer circuit, wherein an input end of the second buffer circuit is connected to an output end of the first frequency doubling circuit, and is configured to receive the first calibration clock signal and output an intermediate calibration clock signal;

[0017] A frequency divider circuit, wherein an input end of the frequency divider circuit is connected to an output end of the second buffer circuit and is configured to perform frequency reduction processing on the intermediate calibration clock signal to obtain a second calibration clock signal with a low frequency;

[0018] A logic state machine circuit, wherein the input end of the logic state machine circuit is respectively connected to the output end of the comparator circuit and the output end of the frequency divider circuit, and is configured to generate the error control signal according to the second calibration clock signal and the state indication signal.

[0019] Optionally, the duty cycle detection circuit specifically includes:

[0020] a first duty cycle detection circuit connected to the output end of the first double frequency circuit and configured to detect the duty cycle of the first clock signal in the second clock signal to obtain a first duty cycle detection voltage;

[0021] a second duty cycle detection circuit connected to the output end of the first double frequency circuit and configured to detect the duty cycle of the second clock signal in the second clock signal to obtain a second duty cycle detection voltage;

[0022] The logic state machine circuit is specifically configured as follows:

[0023] determining a current calibration cycle according to the second calibration clock signal;

[0024] If the current calibration cycle is an initial cycle, then determine whether the duty cycle error is greater than a preset threshold value; if the duty cycle error is greater than the preset threshold value, then determine whether the state indication signal meets a preset calibration condition; if the state indication signal meets the preset calibration condition, then set the error control signal as a first control signal and output it; if the state indication signal does not meet the preset calibration condition, then generate an abnormal indication signal; if the duty cycle error is less than or equal to the preset threshold value, then generate a calibration end indication signal;

[0025] If the current calibration cycle is not an initial cycle, determining whether the status indication signal satisfies the preset calibration condition, if the preset calibration condition is satisfied, setting the error control signal to a second control signal and outputting it; if the preset calibration condition is not satisfied, setting the error control signal to a third control signal and outputting it;

[0026] The duty cycle error is determined based on the first duty cycle detection voltage and the second duty cycle detection voltage; and the preset calibration condition is determined based on an initial circuit state of the first digital-to-time converter circuit.

[0027] Optionally, the logic state machine circuit is further configured as follows:

[0028] If the current calibration cycle is not an initial cycle, determining whether the current circuit state satisfies a preset end condition, and if the preset end condition is satisfied, generating the calibration end indication signal;

[0029] If the preset end condition is not met, executing a process of determining whether the status indication signal meets the preset calibration condition;

[0030] The preset end condition is determined according to the preset calibration condition.

[0031] Optionally, if the preset calibration condition is that the first duty cycle detection voltage is greater than the second duty cycle detection voltage, the first control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an open state to be turned off, the second control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an open state to be turned off, and the third control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an open state to be turned on;

[0032] If the preset calibration condition is that the first duty cycle detection voltage is less than or equal to the second duty cycle detection voltage, the first control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an off state to turn on, the second control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an off state to turn on, and the third control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an on state to turn off.

[0033] Optionally, the first digital-to-time converter circuit includes:

[0034] a temperature decoder circuit connected to the output terminal of the calibration circuit and configured to convert the error control signal into an enable signal;

[0035] A plurality of delay units are connected to the output end of the temperature decoder circuit and are configured to control their own on and off according to the enable signal.

[0036] Optionally, the calibration circuit further includes:

[0037] The duty cycle real-time monitoring circuit is connected to the output end of the comparator circuit and is configured to receive the state indication signal and output a stable indication signal according to the change of the state indication signal. The stable indication signal is used to indicate the on and off of the logic state machine circuit, the second buffer circuit and the divider circuit.

[0038] In a second aspect, the present application discloses a signal processing method for a quadruple frequency circuit, wherein the quadruple frequency circuit comprises a first double frequency circuit, a second double frequency circuit and a calibration circuit; the method comprises:

[0039] The first double frequency circuit receives a first clock signal output by an external circuit and outputs a first calibration clock signal;

[0040] The first frequency doubling circuit outputs a second clock signal with a doubled frequency according to the first clock signal and the error control signal output by the calibration circuit;

[0041] The second frequency doubling circuit outputs a third clock signal with a quadrupled frequency according to the second clock signal;

[0042] The calibration circuit outputs the error control signal according to the first calibration clock signal and the second clock signal.

[0043] Optionally, the first frequency doubling circuit includes a first buffer circuit, a first digital-to-time converter circuit and a first XOR circuit; and the method specifically includes:

[0044] The first buffer circuit performs amplitude shaping and / or phase calibration on the first clock signal and then outputs the first calibration clock signal and a first intermediate clock signal;

[0045] The first digital-to-time converter circuit adjusts the delay of the first intermediate clock signal according to the error control signal;

[0046] The first XOR circuit outputs the second clock signal according to the adjusted first intermediate clock signal.

[0047] Optionally, the calibration circuit includes a duty cycle detection circuit, a comparator circuit, a second buffer circuit, a frequency divider circuit, and a logic state machine circuit; and the method specifically includes:

[0048] The duty cycle detection circuit detects the duty cycle of the second clock signal to obtain a duty cycle detection voltage;

[0049] The comparator circuit compares and processes the duty cycle detection voltage to obtain a state indication signal;

[0050] The second buffer circuit receives the first calibration clock signal and outputs an intermediate calibration clock signal;

[0051] The frequency divider circuit performs frequency reduction processing on the intermediate calibration clock signal to obtain a second calibration clock signal with a low frequency;

[0052] The logic state machine circuit generates the error control signal according to the second calibration clock signal and the state indication signal.

[0053] Optionally, the duty cycle detection circuit specifically includes a first duty cycle detection circuit and a second duty cycle detection circuit; and the method specifically includes:

[0054] The first duty cycle detection circuit detects the duty cycle of the first clock signal in the second clock signal to obtain a first duty cycle detection voltage;

[0055] The second duty cycle detection circuit detects the duty cycle of the second clock signal in the second clock signal to obtain a second duty cycle detection voltage;

[0056] The logic state machine circuit determines the current calibration cycle according to the second calibration clock signal; if the current calibration cycle is an initial cycle, it is determined whether the duty cycle error is greater than a preset threshold value; if the duty cycle error is greater than the preset threshold value, it is determined whether the state indication signal satisfies a preset calibration condition; if the state indication signal satisfies the preset calibration condition, the error control signal is set to a first control signal and outputted; if the state indication signal does not satisfy the preset calibration condition, an abnormality indication signal is generated; if the duty cycle error is less than or equal to the preset threshold value, a calibration end indication signal is generated; if the current calibration cycle is not an initial cycle, it is determined whether the state indication signal satisfies the preset calibration condition; if the preset calibration condition is satisfied, the error control signal is set to a second control signal and outputted; if the preset calibration condition is not satisfied, the error control signal is set to a third control signal and outputted;

[0057] The duty cycle error is determined based on the first duty cycle detection voltage and the second duty cycle detection voltage; and the preset calibration condition is determined based on an initial circuit state of the first digital-to-time converter circuit.

[0058] Optionally, the method further includes:

[0059] If the current calibration cycle is not an initial cycle, the logic state machine circuit determines whether the current circuit state meets a preset end condition, and if so, generates the calibration end indication signal; if not, executes a process of determining whether the state indication signal meets the preset calibration condition;

[0060] The preset end condition is determined according to the preset calibration condition.

[0061] Optionally, the method further includes:

[0062] If the preset calibration condition of the logic state machine circuit is that the first duty cycle detection voltage is greater than the second duty cycle detection voltage, the first control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an open state to be turned off, the second control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an open state to be turned off, and the third control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an off state to be turned on; if the preset calibration condition is that the first duty cycle detection voltage is less than or equal to the second duty cycle detection voltage, the first control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an off state to be turned on, the second control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an off state to be turned on, and the third control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an open state to be turned off.

[0063] Optionally, the first digital-to-time converter circuit includes a temperature decoder circuit and a plurality of delay units; and the method includes:

[0064] The temperature decoder circuit converts the error control signal into an enable signal;

[0065] The multiple delay units control their own on and off according to the enable signal.

[0066] Optionally, the calibration circuit further includes a duty cycle real-time monitoring circuit; the method specifically includes:

[0067] The duty cycle real-time monitoring circuit receives the state indication signal, and outputs a stability indication signal according to the change of the state indication signal, wherein the stability indication signal is used to indicate the on and off of the logic state machine circuit, the second buffer circuit and the divider circuit.

[0068] In a third aspect, the present application discloses a communication chip, wherein the communication chip includes the quadruple frequency circuit described above.

[0069] The beneficial effects of the present invention are as follows:

[0070] Compared with the prior art, the present application provides a quadruple frequency circuit, which includes a first double frequency circuit, a second double frequency circuit and a calibration circuit, wherein the first double frequency circuit is used to receive the first clock signal output by the external circuit, and output a first calibration clock signal, and output a second clock signal with double frequency according to the first clock signal and the error control signal output by the calibration circuit, the second double frequency circuit is used to receive the second clock signal, output a third clock signal with quadruple frequency, and the calibration circuit is used to receive the first calibration clock signal and the second clock signal, and output the error control signal. The second clock signal generated by the first double frequency circuit is calibrated for duty cycle by the calibration circuit, thereby improving the frequency stability and noise performance of the third clock signal generated by the second double frequency circuit. The quadruple frequency circuit is integrated in a high-performance phase-locked loop, with simple design, small chip area and high economic benefits. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0072] Figure 1 A schematic diagram of the structure of a quadruple frequency circuit provided in an embodiment of the present application;

[0073] Figure 2 A schematic diagram of the structure of a first double frequency circuit provided in an embodiment of the present application;

[0074] Figure 3 A schematic structural diagram of a first digital-to-time converter circuit provided in an embodiment of the present application;

[0075] Figure 4 A schematic diagram of the structure of a calibration circuit provided in an embodiment of the present application;

[0076] Figure 5 A schematic diagram of the structure of another quadruple frequency circuit provided in an embodiment of the present application.

[0077] The reference numerals are described as follows:

[0078] 100-first double frequency circuit; 110-first buffer circuit; 120-first digital time converter circuit; 121-temperature decoder circuit; 122-delay unit; 123-third buffer circuit; 124-resistor; 125-fourth buffer circuit; 130-first XOR circuit; 200-second double frequency circuit; 210-second digital time converter circuit; 220-second XOR circuit; 300-calibration circuit; 310-duty cycle detection circuit; 311-first duty cycle detection circuit; 312-second duty cycle detection circuit; 320-comparator circuit; 330-second buffer circuit; 340-divider circuit; 350-logic state machine circuit; 360-duty cycle real-time monitoring circuit. DETAILED DESCRIPTION

[0079] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0080] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0081] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0082] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0083] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0084] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0085] Figure 1 The schematic diagram of the structure of a quadruple frequency circuit provided by the embodiment of the present application is shown as an example. Figure 1 As can be seen from FIG. 1 , the quadruple frequency circuit includes a first double frequency circuit 100 , a second double frequency circuit 200 and a calibration circuit 300 .

[0086] The input end of the first double frequency circuit 100 can be connected to the output end of the external circuit and the calibration circuit 300, and the output end can be connected to the input end of the second double frequency circuit 200 and the calibration circuit 300. The external circuit is usually a crystal circuit, such as a digitally controlled crystal oscillator circuit (DCXO), or other types of crystal circuits.

[0087] The first double frequency circuit 100 is configured to receive the first clock signals clk_inp and clk_inn output by the external circuit, and output a first calibration clock signal clk_cali, and an error control signal dtc_code output by the calibration circuit 300 according to the first clock signals clk_inp and clk_inn. <n-1:0>, outputting second clock signals clk_x2_inp and clk_x2_inn with doubled frequency.

[0088] Among them, the first clock signals clk_inp and clk_inn output by the external circuit are usually differential clock signals. The differential clock circuit is a special circuit, and its main function is to generate two clock signals with opposite phases. When these two clock signals with opposite phases are transmitted in the circuit, the bit error rate in the data transmission process can be effectively reduced and the stability of data transmission can be improved.

[0089] Furthermore, the second clock signals clk_x2_inp and clk_x2_inn outputted by the first double frequency multiplication circuit 100 and the third clock signals clk_x4_inp and clk_x4_inn outputted by the second double frequency multiplication circuit 200 are also differential clock signals.

[0090] The input terminal of the second frequency doubling circuit 200 may be connected to the output terminal of the first frequency doubling circuit 100 , and is configured to receive the second clock signals clk_x2_inp and clk_x2_inn, and output third clock signals clk_x4_inp and clk_x4_inn with quadruple frequencies.

[0091] The input end of the calibration circuit 300 can be connected to the output end of the first double frequency circuit 100, and the output end can be connected to the input end of the first double frequency circuit 100, and is configured to receive the first calibration clock signal clk_cali and the second clock signals clk_x2_inp and clk_x2_inn, and output the error control signal dtc_code <n-1:0>.

[0092] The duty cycle of the second clock signal generated by the first double frequency circuit is calibrated by the calibration circuit, thereby improving the frequency stability and noise performance of the third clock signal generated by the second double frequency circuit. The quadruple frequency circuit is integrated in a high-performance phase-locked loop, has a simple design, a small chip area, and high economic benefits.

[0093] In order to more clearly describe the structure and signal processing flow of the first double frequency circuit 100, Figure 2 The first frequency doubling circuit 100 will be described in detail.

[0094] like Figure 2 , which is a schematic diagram of the structure of a first double frequency circuit provided by an embodiment of the present application. The first double frequency circuit 100 includes a first buffer circuit 110 , a first digital-to-time converter circuit 120 and a first XOR circuit 130 .

[0095] Specifically, the first buffer circuit 110 may also be referred to as a buffer circuit, an input end of which may be connected to an output end of an external circuit, and an output end of which may be connected to an input end of the first digital-to-time converter circuit 120, an input end of the first XOR circuit 130, and an input end of the calibration circuit 300. The first buffer circuit 110 is configured to output a first calibration clock signal clk_cali and a first intermediate clock signal after performing amplitude shaping and / or phase calibration on the first clock signals clk_inp and clk_inn.

[0096] The first digital-to-time converter circuit 120 may also be referred to as a DTC (digital-timing-converter) circuit, whose input terminal is respectively connected to the output terminal of the first buffer circuit 110 and the output terminal of the calibration circuit 300, and whose output terminal is connected to the input terminal of the first XOR circuit 130. The first digital-to-time converter circuit 120 is configured to generate a signal according to the error control signal DTC_code. <n-1:0>, adjust the delay of the first intermediate clock signal.

[0097] In order to more clearly describe the process of adjusting the delay of the first intermediate clock signal by the first digital-to-time converter circuit 120, Figure 3 The internal structure and signal processing process of the first digital-to-time converter circuit 120 are described in detail.

[0098] like Figure 3 , which is a schematic diagram of the structure of a first digital-to-time converter circuit provided in an embodiment of the present application. The first digital-to-time converter circuit 120 includes a temperature decoder circuit 121 and a plurality of delay units 122 .

[0099] The input end of the temperature decoder circuit 121 is connected to the output end of the calibration circuit 300 , specifically to the output end of the logic state machine circuit 350 in the calibration circuit 300 ; the output end of the temperature decoder circuit 121 is connected to each delay unit 122 .

[0100] The temperature decoder circuit 121 is configured to convert the error control signal dtc_code <n-1:0>The enable signal includes a row enable signal and a column enable signal. The row enable signal is used to control the on and off of the row delay unit in the plurality of delay units, and the column enable signal is used to control the on and off of the column delay unit in the plurality of delay units.

[0101] The plurality of delay units 122 are connected to the output end of the temperature decoder circuit 121 and are configured to control their own on and off according to the enable signal.

[0102] Specifically, the number of delay units 122 is 2 n , including 2 n -1 normal delay unit and 1 dummy delay unit. Where n is the error control signal dtc_code <n-1:0>The number of bits of the corresponding binary code, that is, the error control signal dtc_code <n-1:0>The delay unit 122 adopts row and column control, that is, the high bit [n:m] in the n-bit binary code passes through the temperature decoder circuit 121, and the converted temperature code is used as 2 n -1 normal delay unit row enable signal; the low bit [m-1:0] in the n-bit binary code passes through the temperature decoder circuit 121, and the converted temperature code is used as 2 n -1 column enable signal for normal delay unit.

[0103] Preferably, 2 n - The size of the delay units can be exactly the same, thus ensuring high linearity.

[0104] For example, if n=4, the error control signal dtc_code <n-1:0>If the error control signal dtc_code<3:0> is a 4-bit binary code, the first digital-to-time converter circuit 120 includes 16 delay units 122, which are arranged in 4 rows and 4 columns, and one of them is a dummy delay unit. If the high bit [3:2] of the error control signal dtc_code<3:0> is converted into a row enable signal row<2:0> by the temperature decoder circuit 121, the low bit [1:0] of the error control signal dtc_code<3:0> is converted into a column enable signal col<2:0> by the temperature decoder circuit 121. At this time, the four delay units 122 in the first row use col<2:0> to control the on and off of three of the delay units, and the remaining one is used as a dummy delay unit. The delay units 122 in the second to fourth rows use row<2:0> to control the on and off of the entire row of delay units.

[0105] As a further example, if the error control signal dtc_code<3:0> is 4'b1011, the high-order dtc_code<3:2> corresponds to the data of 2'b10, which is converted into the row enable signal row<2:0>, specifically 3'b011, through the temperature decoder circuit 121; the low-order dtc_code<1:0> corresponds to the data of 2'b11, which is converted into the column enable signal col<2:0>, specifically 3'b111, through the temperature decoder circuit 121. After the internal logic processing of the delay unit 122, the 3 delay units in the first row, the 4 delay units in the second row, and the 4 delay units in the third row are all turned on, and a total of 11 delay units are in the turned-on state.

[0106] For another example, dtc_code<3:0> is 4'b1101, the high-order dtc_code<3:2> corresponds to the data of 2'b11, which is converted into the row enable signal row<2:0> through the temperature decoder circuit 121, specifically 3'b111; the low-order dtc_code<1:0> corresponds to the data of 2'b01, which is converted into the column enable signal col<2:0> through the temperature decoder circuit 121, specifically 3'b001. After the internal logic processing of the delay unit 122, 1 delay unit in the first row, 4 delay units in the second row, 4 delay units in the third row and 4 delay units in the fourth row are all turned on, and a total of 13 delay units are in the turned-on state.

[0107] It should be noted that: (1) This application defines the error control signal dtc_code <n-1:0>The number of bits of the corresponding binary code is not specifically limited. In the above embodiment, the error control signal dtc_code is provided. <n-1:0>is an example of a 4-bit binary code. In other examples, the error control signal dtc_code <n-1:0>It may also be a binary code of other bits; (2) The present application does not make any specific limitation on the layout of the delay unit 122. The above embodiment provides 16 delay units 122 arranged in the form of 4 rows and 4 columns. In other examples, the 16 delay units 122 may also be arranged in the form of 2 rows and 8 columns or 8 rows and 2 columns. Those skilled in the art may adjust the layout of the delay unit 122 according to actual needs.

[0108] In addition, if Figure 3 As shown, the first digital-to-time converter circuit 120 may further include a third buffer circuit 123, a resistor 124 and a fourth buffer circuit 125. The resistor 124 is located between the third buffer circuit 123 and the fourth buffer circuit 125, and each delay unit 122 is also connected to the input end of the fourth buffer circuit 125.

[0109] The input end of the first XOR circuit 130 is respectively connected to the output end of the first buffer circuit 110 and the output end of the first digital-to-time converter circuit 120, and the output end is connected to the input end of the calibration circuit 300 and the input end of the second double frequency circuit 200. The first XOR circuit 130 is configured to output the second clock signals clk_x2_inp and clk_x2_inn according to the adjusted first intermediate clock signal.

[0110] Combination Figure 2 It can be seen that the first buffer circuit 110 has at least two output terminals, one output terminal is connected to the calibration circuit 300, and outputs the first calibration clock signal clk_cali to the calibration circuit 300 as a calibration clock; the other output terminal is connected to the first digital-to-time converter circuit 120 and the first XOR circuit 130, and generates second clock signals clk_x2_inp and clk_x2_inn with twice the frequency.

[0111] It should be noted that when the first buffer circuit 110 outputs the clock signal to the first digital-to-time converter circuit 120 and the first XOR circuit 130, it can be as follows: Figure 2 As shown in the figure, it is connected to the first digital-to-time converter circuit 120 and the first XOR circuit 130 through one output terminal; or, it can also be connected to the first digital-to-time converter circuit 120 and the first XOR circuit 130 respectively through two output terminals. Technical personnel in this field can set it according to their needs, and this application does not limit it.

[0112] In order to more clearly describe the structure and signal processing flow of the calibration circuit 300, Figure 4 The calibration circuit 300 is described in detail. Figure 4 The schematic diagram of the structure of a calibration circuit provided by an embodiment of the present application is shown as an example. Figure 4 As shown, the calibration circuit 300 includes a duty cycle detection circuit 310 , a comparator circuit 320 , a second buffer circuit 330 , a frequency divider circuit 340 , and a logic state machine circuit 350 .

[0113] The duty cycle detection circuit 310 may also be referred to as a dutycycle_detector circuit, and its input end may be connected to the output end of the first double frequency circuit 100, and its output end may be connected to the input end of the comparator circuit 320. Specifically, the input end of the duty cycle detection circuit 310 may be connected to the output end of the first XOR circuit 130 in the first double frequency circuit 100. The duty cycle detection circuit 310 may be configured to detect the duty cycle of the second clock signals clk_x2_inp and clk_x2_inn to obtain a duty cycle detection voltage.

[0114] Further, such as Figure 4 As shown, the duty cycle detection circuit 310 may specifically include a first duty cycle detection circuit 311 and a second duty cycle detection circuit 312 .

[0115] The input end of the first duty cycle detection circuit 311 is connected to the output end of the first double frequency circuit 100, specifically connected to an output end of the first XOR circuit 130 in the first double frequency circuit 100; the output end of the first duty cycle detection circuit 311 is connected to an input end of the comparator circuit 320. The first duty cycle detection circuit 311 can be configured to detect the duty cycle of the first clock signal (such as clk_x2_inp) in the second clock signals clk_x2_inp and clk_x2_inn to obtain a first duty cycle detection voltage Vp.

[0116] The input end of the second duty cycle detection circuit 312 is connected to the output end of the first double frequency circuit 100, specifically connected to the other output end of the first XOR circuit 130 in the first double frequency circuit 100; the output end of the second duty cycle detection circuit 312 is connected to the other input end of the comparator circuit 320. The second duty cycle detection circuit 312 can be configured to detect the duty cycle of the second clock signal (such as clk_x2_inn) in the second clock signals clk_x2_inp and clk_x2_inn to obtain a second duty cycle detection voltage Vn.

[0117] Exemplarily, the duty cycle detection circuit 310 may be an RC low-pass filter, which performs DC voltage duty cycle detection on the second clock signals clk_x2_inp and clk_x2_inn to obtain duty cycle detection voltages Vp and Vn.

[0118] In other examples, the duty cycle detection circuit 310 may also be other types of filters, and those skilled in the art may set them as needed, which is not limited in this application.

[0119] The comparator circuit 320 may also be referred to as a Comp circuit, and its input terminal may be connected to the output terminal of the duty cycle detection circuit 310, and its output terminal may be connected to the input terminal of the logic state machine circuit 350. By using the comparator circuit 320, the comparison process in the calibration circuit 300 may be simplified, and the circuit power consumption and layout area may be reduced.

[0120] Specifically, the comparator circuit 320 can have two input terminals, one input terminal can be connected to the output terminal of the first duty cycle detection circuit 311, and receive the first duty cycle detection voltage Vp output by the first duty cycle detection circuit 311; the other input terminal can be connected to the output terminal of the second duty cycle detection circuit 312, and receive the second duty cycle detection voltage Vn output by the second duty cycle detection circuit 312.

[0121] The comparator circuit 320 may be configured to perform comparison processing on the duty cycle detection voltage to obtain a state indication signal state_signal. Depending on the result of the comparison processing, the representation content of the obtained state indication signal state_signal may also be different.

[0122] If the first duty cycle detection voltage Vp is greater than the second duty cycle detection voltage Vn, the state indication signal state_signal can be characterized as a first indication signal; if the first duty cycle detection voltage Vp is less than or equal to the second duty cycle detection voltage Vn, the state indication signal state_signal can be characterized as a second indication signal.

[0123] Further, the first indication signal may be a high level signal, and the second indication signal may be a low level signal.

[0124] The specific characterization content of the state indication signal state_signal of the present application is not limited, and those skilled in the art can define the characterization content of the state indication signal state_signal according to actual conditions, as long as the results of the comparison processing can be distinguished through the state indication signal state_signal.

[0125] The second buffer circuit 330 may also be referred to as a buffer circuit, and its input end may be connected to the output end of the first double frequency circuit 100, and specifically may be connected to the output end of the first buffer circuit 110 in the first double frequency circuit 100; its output end may be connected to the input end of the frequency divider circuit 340. The second buffer circuit 330 is used to improve the driving capability of the first calibration clock signal clk_cali, and specifically may be configured to receive the first calibration clock signal clk_cali and output an intermediate calibration clock signal.

[0126] The frequency divider circuit 340 may also be referred to as a divider circuit, and its input end may be connected to the output end of the second buffer circuit 330, and its output end may be connected to the input end of the logic state machine circuit 350. The frequency divider circuit 340 may be configured to perform frequency reduction processing on the intermediate calibration clock signal to obtain a second calibration clock signal with a low frequency.

[0127] The period of the second calibration clock signal can be used as a calibration period. Each time a rising edge comes, the logic state machine circuit 350 is triggered to perform a judgment, that is, a calibration is completed for the first double frequency circuit 100 in each divided clock period.

[0128] The logic state machine circuit 350 may also be referred to as a logic_state_machine circuit, wherein the input end thereof is respectively connected to the output end of the comparator circuit 320 and the output end of the frequency divider circuit 340, and the output end thereof is connected to the input end of the first double frequency circuit 100, specifically, to the input end of the first digital-to-time converter circuit 120 in the first double frequency circuit 100. The logic state machine circuit 350 may be configured to generate an error control signal dtc_code according to the second calibration clock signal and the state indication signal state_signal. <n-1:0>.

[0129] Furthermore, the logic state machine circuit 350 is specifically configured to determine the current calibration cycle according to the second calibration clock signal. Depending on the current calibration cycle, the signal processing flow to be executed is also different.

[0130] If the current calibration cycle is the initial cycle, it is determined whether the duty cycle error is greater than the preset threshold. If the duty cycle error is greater than the preset threshold, it is determined whether the state indication signal state_signal meets the preset calibration condition. If the state indication signal state_signal meets the preset calibration condition, the error control signal dtc_code is set. <n-1:0>It is set as the first control signal and output. If the state indication signal state_signal does not meet the preset calibration condition, an abnormal indication signal overflow is generated; if the duty cycle error is less than or equal to the preset threshold, a calibration end indication signal dcc_cal_done is generated.

[0131] If the current calibration cycle is not the initial cycle, it is determined whether the state indication signal state_signal satisfies the preset calibration condition. If the preset calibration condition is satisfied, the error control signal dtc_code is set to <n-1:0>Set as the second control signal and output; if the preset calibration condition is not met, the error control signal dtc_code <n-1:0>Set as the third control signal and output.

[0132] The duty cycle error is determined according to the first duty cycle detection voltage Vp and the second duty cycle detection voltage Vn, for example, it may be the difference between the first duty cycle detection voltage Vp and the second duty cycle detection voltage Vn.

[0133] The preset calibration condition may be determined according to the initial circuit state of the first digital-to-time converter circuit 120. If the initial circuit state of the first digital-to-time converter circuit 120 is that all the delay units 122 are in the on state, that is, the duty cycle of the second clock signals clk_x2_inp and clk_x2_inn initially output by the first double frequency circuit 100 is the largest, then the preset calibration condition may be set to that the first duty cycle detection voltage Vp is greater than the second duty cycle detection voltage Vn; if the initial state of the first digital-to-time converter circuit 120 is that all the delay units 122 are in the off state, that is, the duty cycle of the second clock signals clk_x2_inp and clk_x2_inn initially output by the first double frequency circuit 100 is the smallest, then the preset calibration condition may be set to that the first duty cycle detection voltage Vp is less than or equal to the second duty cycle detection voltage Vn.

[0134] Further, if the preset calibration condition is that the first duty cycle detection voltage Vp is greater than the second duty cycle detection voltage Vn, the first control signal is used to control at least one of the delay units 122 in the first digital-to-time converter circuit 120 that are in an open state to be turned off, the second control signal is used to control at least one of the delay units 122 in the first digital-to-time converter circuit 120 that are in an open state to be turned off, and the third control signal is used to control at least one of the delay units 122 in the first digital-to-time converter circuit 120 that are in an open state to be turned on.

[0135] If the preset calibration condition is that the first duty cycle detection voltage is less than Vp or equal to the second duty cycle detection voltage Vn, the first control signal is used to control at least one of the delay units 122 in the off state in the first digital-to-time converter circuit 120 to turn on, the second control signal is used to control at least one of the delay units 122 in the off state in the first digital-to-time converter circuit 120 to turn on, and the third control signal is used to control at least one of the delay units 122 in the on state in the first digital-to-time converter circuit 120 to turn off.

[0136] In the embodiment of the present application, taking the preset calibration condition that the first duty cycle detection voltage Vp is greater than the second duty cycle detection voltage Vn as an example, if the current calibration cycle is the initial cycle, the logic state machine circuit 350 is specifically configured to, if the state indication signal state_signal satisfies the preset calibration condition, that is, the representation content of the state indication signal state_signal satisfies the first duty cycle detection voltage Vp is greater than the second duty cycle detection voltage Vn, then the error control signal dtc_code <n-1:0>The first control signal can be set to a first control signal and output. n-1 The control step length is 2, that is, the delay unit in the first digital-to-time converter circuit 120 in the open state is controlled. n-1 The delay unit is turned off.

[0137] by Figure 3 As an example, the first digital-to-time converter circuit 120 including 16 delay units 122 shown in FIG. 1 is arranged in 4×4 rows and columns (one of which is a dummy delay unit). The initial value of the error control signal dtc_code<3:0> is 4′b1111, which is reduced by 2. n-1 After a control step, the error control signal dtc_code<3:0> becomes 4'b0111, ie, the delay units 122 of the third and fourth rows are turned off, and the corresponding row enable signal row<2:0> changes from 3'b111 to 3'b001.

[0138] Furthermore, the logic state machine circuit 350 is specifically configured to generate an abnormal indication signal overflow if the state indication signal state_signal does not satisfy a preset calibration condition, that is, the representation content of the state indication signal state_signal does not satisfy that the first duty cycle detection voltage Vp is greater than the second duty cycle detection voltage Vn, that is, the representation content of the state indication signal state_signal is that the first duty cycle detection voltage Vp is less than or equal to the second duty cycle detection voltage Vn.

[0139] Exemplarily, the logic state machine circuit 350 can output the abnormal indication signal overflow_high through the state_error pin, and can also output the calibration end indication signal dcc_cal_done through the cal_done pin, wherein the calibration end indication signal dcc_cal_done is high level effective, and the calibration process is ended. <n-1:0>4'b1111, providing the second clock signals clk_x2_inp and clk_x2_inn with doubled frequency and maximum duty cycle.

[0140] In the initial cycle, if it is determined according to the condition that the state indication signal state_signal satisfies the preset calibration condition, it indicates that it is necessary to perform duty cycle calibration on the first double frequency circuit 100. In order to complete the duty cycle calibration more accurately, the embodiment of the present application can divide the calibration cycles other than the initial cycle into three categories, the first category is from the 2nd calibration cycle to the nth calibration cycle, the second category is from the n+1th calibration cycle to the 2n-1th calibration cycle, and the third category is the 2nth control cycle.

[0141] For the second calibration cycle to the nth calibration cycle, the logic state machine circuit 350 is specifically configured to set the error control signal to the second control signal and output it if the state indication signal meets the preset calibration condition; if the state indication signal does not meet the preset calibration condition, set the error control signal to the third control signal and output it. In the tth calibration cycle, the second control signal can specifically include a decrease of 2 n-t The control step length is 2, that is, the delay unit in the first digital-to-time converter circuit 120 in the open state is controlled. n-t The delay unit is turned off; the third control signal may specifically include increasing 2 n-t The control step length is 2, that is, the delay unit in the first digital-to-time converter circuit 120 in the off state is controlled. n-t The delay unit is turned on. t is an integer greater than or equal to 2 and less than or equal to n.

[0142] Still Figure 3 As an example, the first digital-to-time converter circuit 120 including 16 delay units 122 shown in FIG. 1 is arranged in 4×4 rows and columns (one of which is a dummy delay unit). In the second calibration cycle, the error control signal dtc_code<3:0> output in the previous calibration cycle is 4'b0111. If the representation content of the state indication signal state_signal at this time satisfies that the first duty cycle detection voltage Vp is greater than the second duty cycle detection voltage Vn, then after reducing the error control signal dtc_code<3:0> by 4 control steps, the error control signal dtc_code<3:0> becomes 4'b0011, that is, the delay unit 122 in the second row is turned off, and the corresponding row enable signal ro w<2:0> changes from 3'b001 to 3'b000; if at this time the representation content of the state indication signal state_signal satisfies that the first duty cycle detection voltage Vp is less than or equal to the second duty cycle detection voltage Vn, then after the error control signal dtc_code<3:0> is increased by 4 control steps, the error control signal dtc_code<3:0> becomes 4'b1011, that is, the delay unit 122 of the third row is turned on, and the corresponding row enable signal row<2:0> changes from 3'b001 to 3'b011.

[0143] In the third calibration cycle, the error control signal dtc_code<3:0> output in the previous calibration cycle is 4'b0011 or 4'b1011. If the representation content of the state indication signal state_signal satisfies that the first duty cycle detection voltage Vp is greater than the second duty cycle detection voltage Vn, the error control signal dtc_code<3:0> is reduced by 2 control steps, and the error control signal dtc_code<3:0> changes from 4'b0011 to 4'b0001, or from 4'b1 011 changes to 4'b1001, turning off the corresponding delay unit 122; if at this time the representation content of the state indication signal state_signal satisfies that the first duty cycle detection voltage Vp is less than or equal to the second duty cycle detection voltage Vn, then after increasing the error control signal dtc_code<3:0> by 2 control steps, the error control signal dtc_code<3:0> changes from 4'b0011 to 4'b0101, or from 4'b1011 to 4'b1101, turning on the corresponding delay unit 122.

[0144] The specific calibration process in the 4th calibration cycle can refer to the contents of the 2nd and 3rd calibration cycles described above, which will not be repeated here.

[0145] For the n+1th calibration cycle to the 2n-1th calibration cycle, the logic state machine circuit 350 is specifically configured to set the error control signal to the second control signal and output it if the state indication signal meets the preset calibration condition; if the state indication signal does not meet the preset calibration condition, set the error control signal to the third control signal and output it. The second control signal may specifically include reducing 1 control step, that is, controlling 1 delay unit in the open state of the first digital-to-time converter circuit 120 to be turned off; the third control signal may specifically include increasing 1 control step, that is, controlling 1 delay unit in the closed state of the first digital-to-time converter circuit 120 to be turned on.

[0146] Still Figure 3 As an example, the first digital-to-time converter circuit 120 including 16 delay units 122 is shown in FIG. 1 . The 16 delay units 122 are arranged in 4×4 rows and columns (one of which is a dummy delay unit). In the fifth calibration cycle, if the error control signal dtc_code<3:0> output in the previous calibration cycle is 4'b1010, if the representation content of the state indication signal state_signal at this time satisfies that the first duty cycle detection voltage Vp is greater than the second duty cycle detection voltage Vn, then the error control signal dtc_code<3:0> is reduced by 1 control step, and the error control signal dtc_code<3:0> is changed from 4'b1010 to 4'b1001, and the corresponding delay unit 122 is turned off; if the representation content of the state indication signal state_signal at this time satisfies that the first duty cycle detection voltage Vp is less than or equal to the second duty cycle detection voltage Vn, then the error control signal dtc_code<3:0> is increased by 1 control step, and the error control signal dtc_code<3:0> is changed from 4'b1010 to 4'b1011, and the corresponding delay unit 122 is turned on.

[0147] In the sixth calibration cycle, the error control signal dtc_code<3:0> output in the previous calibration cycle is 4'b1001 or 4'b1011. If the representation content of the state indication signal state_signal satisfies that the first duty cycle detection voltage Vp is greater than the second duty cycle detection voltage Vn, the error control signal dtc_code<3:0> is reduced by 1 control step, and the error control signal dtc_code<3:0> changes from 4'b1001 to 4'b1000, or from 4'b1 011 changes to 4'b1010, turning off the corresponding delay unit 122; if at this time the representation content of the state indication signal state_signal satisfies that the first duty cycle detection voltage Vp is less than or equal to the second duty cycle detection voltage Vn, then after the error control signal dtc_code<3:0> is increased by 1 control step, the error control signal dtc_code<3:0> changes from 4'b1001 to 4'b1010, or from 4'b1011 to 4'b1100, turning on the corresponding delay unit 122.

[0148] The specific calibration process in the 7th calibration cycle can refer to the contents of the 5th and 6th calibration cycles described above, which will not be repeated here.

[0149] For the 2nth calibration cycle, the logic state machine circuit 350 is specifically configured to set the error control signal to the second control signal and output it if the state indication signal meets the preset calibration condition; if the state indication signal does not meet the preset calibration condition, set the error control signal to the third control signal and output it. The second control signal remains unchanged; the third control signal may specifically include increasing one control step, that is, controlling one of the delay units in the off state in the first digital-to-time converter circuit 120 to turn on.

[0150] Still Figure 3 As an example, the first digital-to-time converter circuit 120 including 16 delay units 122 shown in FIG. 1 is arranged in 4×4 rows and columns (one of which is a dummy delay unit). In the 8th calibration cycle, if the error control signal dtc_code<3:0> output in the previous calibration cycle is 4′b1010, if the representation content of the state indication signal state_signal at this time satisfies that the first duty cycle detection voltage Vp is greater than the second duty cycle detection voltage Vn, then the error control signal dtc_code<3:0> is kept unchanged and is still 4′b1010; if the representation content of the state indication signal state_signal at this time satisfies that the first duty cycle detection voltage Vp is less than or equal to the second duty cycle detection voltage Vn, then after increasing the error control signal dtc_code<3:0> by 1 control step, the error control signal dtc_code<3:0> changes from 4′b1010 to 4′b1011, and the corresponding delay unit 122 is turned on.

[0151] In an embodiment of the present application, the logic state machine circuit 350 is specifically configured to determine whether the current circuit state meets the preset end condition if the current calibration cycle is not the initial cycle, and if so, generate a calibration end indication signal dcc_cal_done; if not, execute a process of determining whether the state indication signal state_signal meets the preset calibration condition.

[0152] The preset end condition may be determined according to a preset calibration condition. If the preset calibration condition is that the first duty cycle detection voltage Vp is greater than the second duty cycle detection voltage Vn, the preset end condition may be set to that all delay units 122 in the first digital-to-time converter circuit 120 are in an off state, or the preset calibration times are reached; if the preset calibration condition is that the first duty cycle detection voltage Vp is less than or equal to the second duty cycle detection voltage Vn, the preset end condition may be set to that all delay units 122 in the first digital-to-time converter circuit 120 are in an on state, or the preset calibration times are reached.

[0153] The number of calibrations can be recorded by the count field. In the initial cycle, the value of the count field is 1. After each calibration cycle, the value of the count field increases by 1. Furthermore, the preset number of calibrations can be set to 2n. When the number of calibrations reaches 2n, the preset end condition is met.

[0154] Exemplarily, after completing the calibration process of 2n calibration cycles, the logic state machine circuit 350 may output a calibration end indication signal dcc_cal_done, and simultaneously output a reverse indication signal dcc_en to the second buffer circuit 330 and the frequency divider circuit 340 .

[0155] Further, after each type of calibration cycle is completed, the logic state machine circuit 350 is specifically configured to determine whether the current circuit state meets the preset end condition, and if the preset end condition is met, a calibration end indication signal dcc_cal_done is generated; if the preset end condition is not met, the calibration process for the next type of calibration cycle is executed. Specifically, after the nth calibration cycle and the 2n-1th calibration cycle are completed, the logic state machine circuit 350 is specifically configured to determine whether the current circuit state meets the preset end condition, and if the preset end condition is met, a calibration end indication signal dcc_cal_done is generated; if the preset end condition is not met, the calibration process for the n+1th calibration cycle to the 2n-1th calibration cycle is executed, or the calibration process for the 2nth calibration cycle is executed.

[0156] In the present application embodiment, Figure 4 As shown, the calibration circuit 300 further includes a duty cycle real-time monitoring circuit 360, the input end of the duty cycle real-time monitoring circuit 360 is connected to the output end of the comparator circuit 320, and the output end is connected to the input end of the logic state machine circuit 350. The duty cycle real-time monitoring circuit 360 can be configured to receive the state indication signal state_signal, and output a stable indication signal stable_signal according to the change of the state indication signal state_signal.

[0157] The stable indication signal stable_signal is used to indicate the on / off of the logic state machine circuit 350 , the second buffer circuit 330 , and the frequency divider circuit 340 .

[0158] If it is determined that the duty cycles of the second clock signals clk_x2_inp and clk_x2_inn are in a stable state based on the change of the state indication signal state_signal, the stable indication signal stable_signal characterized as a high-level signal can be output to the logic state machine circuit 350, the second buffer circuit 330 and the divider circuit 340. After the logic state machine circuit 350, the second buffer circuit 330 and the divider circuit 340 receive the stable indication signal stable_signal characterized as a high-level signal, they generate a shutdown enable signal to shut down their own circuits, thereby reducing the overall power consumption of the quadruple frequency circuit and reducing circuit noise at the same time. On the contrary, if it is determined based on the change of the state indication signal state_signal that the duty cycle of the second clock signals clk_x2_inp and clk_x2_inn is not in a stable state, a stable indication signal stable_signal characterized as a low-level signal can be output to the logic state machine circuit 350, the second buffer circuit 330 and the divider circuit 340. After receiving the stable indication signal stable_signal, the logic state machine circuit 350, the second buffer circuit 330 and the divider circuit 340 continue to operate.

[0159] It should be noted that, according to the change of the state indication signal state_signal, the stable indication signal stable_signal can also be other representation contents. Those skilled in the art can set it according to actual conditions, and this application does not limit it. For example, when the duty cycle of the second clock signals clk_x2_inp and clk_x2_inn is in a stable state, the stable indication signal stable_signal represented by a low-level signal can also be output; when the duty cycle of the second clock signals clk_x2_inp and clk_x2_inn is not in a stable state, the stable indication signal stable_signal represented by a high-level signal can also be output; accordingly, after the logic state machine circuit 350, the second buffer circuit 330 and the divider circuit 340 receive the stable indication signal stable_signal of a low-level signal, they generate a shutdown enable signal, and after receiving the stable indication signal stable_signal of a high-level signal, they continue to run.

[0160] In addition, the duty cycle real-time monitoring circuit 360 is also configured to monitor whether the duty cycle error is greater than a preset threshold after the logic state machine circuit 350, the second buffer circuit 330 and the divider circuit 340 are turned off. If the duty cycle error is greater than the preset threshold due to temperature, power supply or other factors, a stable indication signal stable_signal represented by a low-level signal can be output to the logic state machine circuit 350, the second buffer circuit 330 and the divider circuit 340. After receiving the stable indication signal stable_signal, the logic state machine circuit 350, the second buffer circuit 330 and the divider circuit 340 generate an enable signal to start their own circuits.

[0161] The duty cycle real-time monitoring circuit 360 is further configured to perform falling edge detection on the state indication signal state_signal to generate a narrow pulse signal state_signal_pulse, wherein the narrow pulse signal state_signal_pulse can be used as a reset signal of an internal timer.

[0162] If the characterization content of the state indication signal state_signal does not change, the characterization content of the narrow pulse signal state_signal_pulse will not change. Exemplarily, if the state indication signal state_signal remains characterized as a high level signal or a low level signal, the narrow pulse signal state_signal_pulse will remain as a low level signal; if the state indication signal state_signal changes from being characterized as a high level to being characterized as a low level signal, or the state indication signal state_signal changes from being characterized as a low level to being characterized as a high level signal, the characterization content of the narrow pulse signal state_signal_pulse will change from a low level signal to a high level signal.

[0163] In this way, if the narrow pulse signal state_signal_pulse is preset to be characterized as a high-level signal as the reset signal of the timer, that is, the timer is reset to a high-level reset, and the highest bit of the counter is inverted as the stable indication signal stable_signal, then, if the narrow pulse signal state_signal_pulse remains a low-level signal, the counter counts normally; if the narrow pulse signal state_signal_pulse changes from a low-level signal to a high-level signal, the counter is reset.

[0164] The signal processing process of the duty cycle real-time monitoring circuit 360 is described below with reference to an example. The duty cycle real-time monitoring circuit 360 monitors the change of the state indication signal state_signal in real time. If the representation content of the state indication signal state_signal remains a high-level signal, it means that the duty cycle error is within the preset error range, and the representation content of the stable indication signal stable_signal output by the duty cycle real-time monitoring circuit 360 is a high-level signal, and the logic state machine circuit 350, the second buffer circuit 330 and the frequency divider circuit 340 generate a shutdown enable signal to shut down their own circuits; if the representation content of the state indication signal state_signal changes from a high-level signal to a low-level signal, it means that the duty cycle error exceeds the preset threshold, and the stable indication signal stable_signal represented as a low-level signal can be output to the logic state machine circuit 350, the second buffer circuit 330 and the frequency divider circuit 340, and the logic state machine circuit 350, the second buffer circuit 330 and the frequency divider circuit 340 generate an open enable signal to start their own circuits.

[0165] In this way, when the duty cycle of the second clock signal is greater than the preset threshold due to temperature, power supply voltage or other reasons, the calibration circuit is started again. After the calibration is completed, the calibration circuit is in sleep mode and only the duty cycle detection circuit works, thereby reducing overall power consumption.

[0166] like Figure 5 As shown, it is a structural schematic diagram of another quadruple frequency circuit provided in an embodiment of the present application, wherein the second double frequency circuit 200 includes a second digital-to-time converter circuit 210 and a second XOR circuit 220, and the second clock signals clk_x2_inp and clk_x2_inn are processed by the second digital-to-time converter circuit 210 and the second XOR circuit 220 to output third clock signals clk_x4_inp and clk_x4_inn.

[0167] Thus, the quadruple frequency circuit includes a first double frequency circuit, a second double frequency circuit and a calibration circuit, wherein the first double frequency circuit is used to receive the first clock signal output by the external circuit, and output a first calibration clock signal, and output a second clock signal with double frequency according to the first clock signal and the error control signal output by the calibration circuit, the second double frequency circuit is used to receive the second clock signal, and output a third clock signal with quadruple frequency, and the calibration circuit is used to receive the first calibration clock signal and the second clock signal, and output the error control signal. The second clock signal generated by the first double frequency circuit is calibrated for duty cycle by the calibration circuit, thereby improving the frequency stability and noise performance of the third clock signal generated by the second double frequency circuit. The quadruple frequency circuit is integrated in a high-performance phase-locked loop, with simple design, small chip area and high economic benefits.

[0168] Based on the same inventive concept, an embodiment of the present application further provides a signal processing method for a quadruple frequency circuit, wherein the quadruple frequency circuit includes a first double frequency circuit, a second double frequency circuit and a calibration circuit; the method includes:

[0169] The first double frequency circuit receives a first clock signal output by an external circuit and outputs a first calibration clock signal;

[0170] The first frequency doubling circuit outputs a second clock signal with a doubled frequency according to the first clock signal and the error control signal output by the calibration circuit;

[0171] The second frequency doubling circuit outputs a third clock signal with a quadrupled frequency according to the second clock signal;

[0172] The calibration circuit outputs the error control signal according to the first calibration clock signal and the second clock signal.

[0173] Optionally, the first frequency doubling circuit includes a first buffer circuit, a first digital-to-time converter circuit and a first XOR circuit; and the method specifically includes:

[0174] The first buffer circuit performs amplitude shaping and / or phase calibration on the first clock signal and then outputs the first calibration clock signal and a first intermediate clock signal;

[0175] The first digital-to-time converter circuit adjusts the delay of the first intermediate clock signal according to the error control signal;

[0176] The first XOR circuit outputs the second clock signal according to the adjusted first intermediate clock signal.

[0177] Optionally, the calibration circuit includes a duty cycle detection circuit, a comparator circuit, a second buffer circuit, a frequency divider circuit, and a logic state machine circuit; and the method specifically includes:

[0178] The duty cycle detection circuit detects the duty cycle of the second clock signal to obtain a duty cycle detection voltage;

[0179] The comparator circuit compares and processes the duty cycle detection voltage to obtain a state indication signal;

[0180] The second buffer circuit receives the first calibration clock signal and outputs an intermediate calibration clock signal;

[0181] The frequency divider circuit performs frequency reduction processing on the intermediate calibration clock signal to obtain a second calibration clock signal with a low frequency;

[0182] The logic state machine circuit generates the error control signal according to the second calibration clock signal and the state indication signal.

[0183] Optionally, the duty cycle detection circuit specifically includes a first duty cycle detection circuit and a second duty cycle detection circuit; and the method specifically includes:

[0184] The first duty cycle detection circuit detects the duty cycle of the first clock signal in the second clock signal to obtain a first duty cycle detection voltage;

[0185] The second duty cycle detection circuit detects the duty cycle of the second clock signal in the second clock signal to obtain a second duty cycle detection voltage;

[0186] The logic state machine circuit determines the current calibration cycle according to the second calibration clock signal; if the current calibration cycle is an initial cycle, it is determined whether the duty cycle error is greater than a preset threshold value; if the duty cycle error is greater than the preset threshold value, it is determined whether the state indication signal satisfies a preset calibration condition; if the state indication signal satisfies the preset calibration condition, the error control signal is set to a first control signal and outputted; if the state indication signal does not satisfy the preset calibration condition, an abnormality indication signal is generated; if the duty cycle error is less than or equal to the preset threshold value, a calibration end indication signal is generated; if the current calibration cycle is not an initial cycle, it is determined whether the state indication signal satisfies the preset calibration condition; if the preset calibration condition is satisfied, the error control signal is set to a second control signal and outputted; if the preset calibration condition is not satisfied, the error control signal is set to a third control signal and outputted;

[0187] The duty cycle error is determined based on the first duty cycle detection voltage and the second duty cycle detection voltage; and the preset calibration condition is determined based on an initial circuit state of the first digital-to-time converter circuit.

[0188] Optionally, the method further includes:

[0189] If the current calibration cycle is not an initial cycle, the logic state machine circuit determines whether the current circuit state meets a preset end condition, and if so, generates the calibration end indication signal; if not, executes a process of determining whether the state indication signal meets the preset calibration condition;

[0190] The preset end condition is determined according to the preset calibration condition.

[0191] Optionally, the method further includes:

[0192] If the preset calibration condition of the logic state machine circuit is that the first duty cycle detection voltage is greater than the second duty cycle detection voltage, the first control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an open state to be turned off, the second control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an open state to be turned off, and the third control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an off state to be turned on; if the preset calibration condition is that the first duty cycle detection voltage is less than or equal to the second duty cycle detection voltage, the first control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an off state to be turned on, the second control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an off state to be turned on, and the third control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an open state to be turned off.

[0193] Optionally, the first digital-to-time converter circuit includes a temperature decoder circuit and a plurality of delay units; and the method includes:

[0194] The temperature decoder circuit converts the error control signal into an enable signal;

[0195] The multiple delay units control their own on and off according to the enable signal.

[0196] Optionally, the calibration circuit further includes a duty cycle real-time monitoring circuit; the method specifically includes:

[0197] The duty cycle real-time monitoring circuit receives the state indication signal, and outputs a stability indication signal according to the change of the state indication signal, wherein the stability indication signal is used to indicate the on and off of the logic state machine circuit, the second buffer circuit and the divider circuit.

[0198] Based on the same inventive concept, an embodiment of the present application further provides a communication chip, which includes the quadruple frequency circuit described above.

[0199] Compared with the prior art, the present application provides a quadruple frequency circuit, which includes a first double frequency circuit, a second double frequency circuit and a calibration circuit, wherein the first double frequency circuit is used to receive the first clock signal output by the external circuit, and output a first calibration clock signal, and output a second clock signal with double frequency according to the first clock signal and the error control signal output by the calibration circuit, the second double frequency circuit is used to receive the second clock signal, output a third clock signal with quadruple frequency, and the calibration circuit is used to receive the first calibration clock signal and the second clock signal, and output the error control signal. The second clock signal generated by the first double frequency circuit is calibrated for duty cycle by the calibration circuit, thereby improving the frequency stability and noise performance of the third clock signal generated by the second double frequency circuit. The quadruple frequency circuit is integrated in a high-performance phase-locked loop, with simple design, small chip area and high economic benefits.

[0200] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A frequency quadrupling circuit, characterized in that: include: A first frequency doubling circuit connected to the output terminals of the external circuit and the calibration circuit, configured to receive a first clock signal output by the external circuit, output a first calibration clock signal, and output a second clock signal with a doubled frequency according to the first clock signal and the error control signal output by the calibration circuit; a second frequency doubling circuit connected to the output end of the first frequency doubling circuit, configured to receive the second clock signal and output a third clock signal with a quadrupled frequency; The calibration circuit is connected to the output end of the first double frequency circuit, and is configured to receive the first calibration clock signal and the second clock signal, and output the error control signal; The first double frequency circuit comprises: a first buffer circuit, wherein an input end of the first buffer circuit is connected to the external circuit and configured to output the first calibration clock signal and a first intermediate clock signal after performing amplitude shaping and / or phase calibration on the first clock signal; a first digital-to-time converter circuit, wherein an input terminal of the first digital-to-time converter circuit is respectively connected to an output terminal of the first buffer circuit and an output terminal of the calibration circuit, and is configured to adjust a delay of the first intermediate clock signal according to the error control signal; a first XOR circuit, wherein an input terminal of the first XOR circuit is respectively connected to an output terminal of the first buffer circuit and an output terminal of the first digital-to-time converter circuit, and is configured to output the second clock signal according to the adjusted first intermediate clock signal; The calibration circuit comprises: a duty cycle detection circuit, wherein an input end of the duty cycle detection circuit is connected to an output end of the first double frequency circuit, and is configured to detect a duty cycle of the second clock signal to obtain a duty cycle detection voltage; a comparator circuit, wherein an input end of the comparator circuit is connected to an output end of the duty cycle detection circuit and is configured to perform comparison processing on the duty cycle detection voltage to obtain a state indication signal; a second buffer circuit, wherein an input end of the second buffer circuit is connected to an output end of the first frequency doubling circuit, and is configured to receive the first calibration clock signal and output an intermediate calibration clock signal; A frequency divider circuit, wherein an input end of the frequency divider circuit is connected to an output end of the second buffer circuit and is configured to perform frequency reduction processing on the intermediate calibration clock signal to obtain a second calibration clock signal with a low frequency; A logic state machine circuit, wherein the input end of the logic state machine circuit is respectively connected to the output end of the comparator circuit and the output end of the frequency divider circuit, and is configured to generate the error control signal according to the second calibration clock signal and the state indication signal.

2. The quadruple frequency circuit according to claim 1, characterized in that: The duty cycle detection circuit specifically includes: a first duty cycle detection circuit connected to the output end of the first double frequency circuit and configured to detect the duty cycle of the first clock signal in the second clock signal to obtain a first duty cycle detection voltage; a second duty cycle detection circuit connected to the output end of the first double frequency circuit and configured to detect the duty cycle of the second clock signal in the second clock signal to obtain a second duty cycle detection voltage; The logic state machine circuit is specifically configured as follows: determining a current calibration cycle according to the second calibration clock signal; If the current calibration cycle is an initial cycle, then determine whether the duty cycle error is greater than a preset threshold value; if the duty cycle error is greater than the preset threshold value, then determine whether the state indication signal meets a preset calibration condition; if the state indication signal meets the preset calibration condition, then set the error control signal as a first control signal and output it; if the state indication signal does not meet the preset calibration condition, then generate an abnormal indication signal; if the duty cycle error is less than or equal to the preset threshold value, then generate a calibration end indication signal; If the current calibration cycle is not an initial cycle, determining whether the status indication signal satisfies the preset calibration condition, if the preset calibration condition is satisfied, setting the error control signal to a second control signal and outputting it; if the preset calibration condition is not satisfied, setting the error control signal to a third control signal and outputting it; The duty cycle error is determined based on the first duty cycle detection voltage and the second duty cycle detection voltage; and the preset calibration condition is determined based on an initial circuit state of the first digital-to-time converter circuit.

3. The quadruple frequency circuit according to claim 2, characterized in that: The logic state machine circuit is further specifically configured as: If the current calibration cycle is not an initial cycle, determining whether the current circuit state satisfies a preset end condition, and if the preset end condition is satisfied, generating the calibration end indication signal; If the preset end condition is not met, executing a process of determining whether the status indication signal meets the preset calibration condition; The preset end condition is determined according to the preset calibration condition.

4. The quadruple frequency circuit according to claim 2, characterized in that: If the preset calibration condition is that the first duty cycle detection voltage is greater than the second duty cycle detection voltage, the first control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an on state to be turned off, the second control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an on state to be turned off, and the third control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an off state to be turned on; If the preset calibration condition is that the first duty cycle detection voltage is less than or equal to the second duty cycle detection voltage, the first control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an off state to turn on, the second control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an off state to turn on, and the third control signal is used to control at least one of the delay units in the first digital-to-time converter circuit that are in an on state to turn off.

5. The quadruple frequency circuit according to claim 1, characterized in that: The first digital-to-time converter circuit comprises: a temperature decoder circuit connected to the output terminal of the calibration circuit and configured to convert the error control signal into an enable signal; A plurality of delay units are connected to the output end of the temperature decoder circuit and are configured to control their own on and off according to the enable signal.

6. The quadruple frequency circuit according to claim 1, characterized in that: The calibration circuit further comprises: The duty cycle real-time monitoring circuit is connected to the output end of the comparator circuit and is configured to receive the state indication signal and output a stable indication signal according to the change of the state indication signal. The stable indication signal is used to indicate the on and off of the logic state machine circuit, the second buffer circuit and the divider circuit.

7. A signal processing method for a quadruple frequency circuit, characterized in that: The quadruple frequency circuit includes a first double frequency circuit, a second double frequency circuit and a calibration circuit; the method includes: The first double frequency circuit receives a first clock signal output by an external circuit and outputs a first calibration clock signal; The first frequency doubling circuit outputs a second clock signal with a doubled frequency according to the first clock signal and the error control signal output by the calibration circuit; The second frequency doubling circuit outputs a third clock signal with a quadrupled frequency according to the second clock signal; The calibration circuit outputs the error control signal according to the first calibration clock signal and the second clock signal; Wherein, the first double frequency circuit comprises: a first buffer circuit, wherein an input end of the first buffer circuit is connected to the external circuit and configured to output the first calibration clock signal and a first intermediate clock signal after performing amplitude shaping and / or phase calibration on the first clock signal; a first digital-to-time converter circuit, wherein an input terminal of the first digital-to-time converter circuit is respectively connected to an output terminal of the first buffer circuit and an output terminal of the calibration circuit, and is configured to adjust a delay of the first intermediate clock signal according to the error control signal; a first XOR circuit, wherein an input terminal of the first XOR circuit is respectively connected to an output terminal of the first buffer circuit and an output terminal of the first digital-to-time converter circuit, and is configured to output the second clock signal according to the adjusted first intermediate clock signal; The calibration circuit comprises: a duty cycle detection circuit, wherein an input end of the duty cycle detection circuit is connected to an output end of the first double frequency circuit, and is configured to detect a duty cycle of the second clock signal to obtain a duty cycle detection voltage; a comparator circuit, wherein an input end of the comparator circuit is connected to an output end of the duty cycle detection circuit and is configured to perform comparison processing on the duty cycle detection voltage to obtain a state indication signal; a second buffer circuit, wherein an input end of the second buffer circuit is connected to an output end of the first frequency doubling circuit, and is configured to receive the first calibration clock signal and output an intermediate calibration clock signal; A frequency divider circuit, wherein an input end of the frequency divider circuit is connected to an output end of the second buffer circuit and is configured to perform frequency reduction processing on the intermediate calibration clock signal to obtain a second calibration clock signal with a low frequency; A logic state machine circuit, wherein the input end of the logic state machine circuit is respectively connected to the output end of the comparator circuit and the output end of the frequency divider circuit, and is configured to generate the error control signal according to the second calibration clock signal and the state indication signal.

8. A communication chip, characterized in that: The communication chip comprises the quadruple frequency circuit as claimed in any one of claims 1 to 6.

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