Delay phase-locked loop circuit, delay phase-locking method and memory

Abstract

The invention relates to a time-delay phase-locked loop circuit, a time-delay phase-locking method and a memory, and the time-delay phase-locked loop circuit comprises a comparator, a fine adjustment control circuit and a fine adjustment circuit. The comparator is configured to receive a reference clock signal and a clock signal to be finely adjusted and generate a first feedback signal; the jump of the first feedback signal represents that the phase relationship between the reference clock signal and the clock signal to be finely adjusted is changed. The fine tuning control circuit is connected with the comparator and is configured to generate a fine tuning control code based on a binary search algorithm; and receiving a first feedback signal, and adjusting the fine tuning control code based on a binary search algorithm in response to the first feedback signal. And the fine tuning circuit is configured to respond to the numerical value change of each bit of code in the fine tuning control code, and adjust a fine tuning delay value until the phase difference between the reference clock signal and the clock signal to be finely tuned is smaller than the unit delay amount of the fine tuning circuit. Therefore, the adjustment interval can be rapidly reduced, and fine adjustment locking is accelerated.

Description

Technical Field

[0001] The present disclosure relates to the semiconductor field, and in particular to a delay phase-locked loop circuit, a delay phase-locked loop method and a memory. Background Art

[0002] In order to meet the wide working range and high precision of DDR (Double Data Rate) memory, the delay line usually adopts a combination of coarse adjustment and fine adjustment. In order to produce high-precision delay, the fine adjustment process usually adopts phase interpolation technology. In order to reduce the jitter caused by the delay loop lock (DLL) during data transmission (tracking), shift registers are often used to control the fine adjustment process.

[0003] As the working range of DDR becomes wider and wider in the future, if the unit delay of the coarse delay unit is too small, the number of coarse delay units required for low frequency will increase greatly; if the unit delay of the coarse delay unit is too large, the number of fine delay units required for high frequency will increase greatly. In addition, in order to meet the resolution requirements of higher frequency conditions, the number of fine delay units will increase dramatically. Therefore, continuing to use traditional shift registers for control during the fine locking process will make the fine locking process take a long time. Summary of the invention

[0004] In view of this, the embodiments of the present disclosure provide a delay phase-locked loop circuit, a delay phase-locked method and a memory to speed up the fine-tuning locking process.

[0005] The technical solution of the present invention is achieved in this way:

[0006] The embodiment of the present disclosure provides a delay phase-locked loop circuit, including: a comparator, a fine-tuning control circuit, and a fine-tuning circuit; the comparator is configured to receive a reference clock signal and a clock signal to be fine-tuned, and compare the phases of the reference clock signal and the clock signal to be fine-tuned to generate a first feedback signal; the jump of the first feedback signal indicates that the phase relationship between the reference clock signal and the clock signal to be fine-tuned has changed; the fine-tuning control circuit is connected to the comparator and is configured to generate a fine-tuning control code; and, receives the first feedback signal, and adjusts the fine-tuning control code based on a binary search algorithm in response to the first feedback signal; the fine-tuning circuit is configured to receive the fine-tuning control code and a fine-tuning input clock signal, applies a fine-tuning delay value to the fine-tuning input clock signal, and generates the clock signal to be fine-tuned; and adjusts the fine-tuning delay value in response to the change in the numerical value of each bit encoded in the fine-tuning control code until the phase difference between the reference clock signal and the clock signal to be fine-tuned is less than the unit delay amount of the fine-tuning circuit.

[0007] The present disclosure provides a delay phase-locked method, comprising: receiving a reference clock signal and a clock signal to be fine-tuned, and comparing the phases of the reference clock signal and the clock signal to be fine-tuned to generate a first feedback signal; a jump of the first feedback signal indicates that the phase relationship between the reference clock signal and the clock signal to be fine-tuned has changed; generating a fine-tuning control code based on a binary search algorithm; and receiving the first feedback signal, and adjusting the fine-tuning control code based on a binary search algorithm in response to the first feedback signal; receiving the fine-tuning control code and the clock signal to be fine-tuned, applying a fine-tuning delay value to the clock signal to be fine-tuned, and generating the clock signal to be fine-tuned; and adjusting the fine-tuning delay value in response to a change in the numerical value of each bit encoded in the fine-tuning control code until the phase difference between the reference clock signal and the clock signal to be fine-tuned is less than a unit delay amount of the fine-tuning circuit.

[0008] The present disclosure also provides a memory, which includes the delay phase-locked loop circuit in the above solution, and the memory is a dynamic random access memory DRAM.

[0009] The embodiment of the present disclosure provides a delay phase-locked loop circuit, which includes: a comparator, a fine-tuning control circuit, and a fine-tuning circuit; the comparator is configured to receive a reference clock signal and a clock signal to be fine-tuned, and compare the phases of the reference clock signal and the clock signal to be fine-tuned to generate a first feedback signal; the jump of the first feedback signal indicates that the phase relationship between the reference clock signal and the clock signal to be fine-tuned has changed; the fine-tuning control circuit is connected to the comparator and configured to generate a fine-tuning control code; and, receives the first feedback signal, and adjusts the fine-tuning control code based on a binary search algorithm in response to the first feedback signal; the fine-tuning circuit is configured to receive the fine-tuning control code and the fine-tuning input clock signal, applies a fine-tuning delay value to the fine-tuning input clock signal, and generates the clock signal to be fine-tuned; and in response to the change in the value of each bit of the fine-tuning control code, adjusts the fine-tuning delay value until the phase difference between the reference clock signal and the clock signal to be fine-tuned is less than the unit delay amount of the fine-tuning circuit. In this way, the fine-tuning control circuit can generate and adjust the fine-tuning control code using a binary search algorithm. Each time the fine adjustment control circuit adjusts the fine adjustment control code, the fine adjustment circuit will adjust the corresponding fine adjustment delay value to the middle value of the current adjustment sub-interval. In addition, the next adjustment sub-interval can be determined in sequence based on the phase relationship between the clock signal to be fine-tuned and the reference clock signal. That is, the fine adjustment control circuit can use the binary method to quickly narrow the adjustment sub-interval. Thus, the number of comparisons between the clock signal to be fine-tuned and the reference clock signal can be reduced, further speeding up the fine adjustment locking process of the delay phase-locked loop circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 The circuit structure of the delay phase-locked loop circuit provided in the embodiment of the present disclosure is shown in FIG. Figure 1 ;

[0011] Figure 2Schematic diagram of the phase relationship of the clock signal provided in the embodiment of the present disclosure Figure 1 ;

[0012] Figure 3 A schematic diagram of the circuit structure of a fine-tuning delay line provided in an embodiment of the present disclosure;

[0013] Figure 4A Schematic diagram of the phase relationship of the clock signal provided in the embodiment of the present disclosure Figure 2 ;

[0014] Figure 4B Schematic diagram of the phase relationship of the clock signal provided in the embodiment of the present disclosure Figure 3 ;

[0015] Figure 4C Schematic diagram 4 of the phase relationship of the clock signal provided in the embodiment of the present disclosure;

[0016] Figure 5 A schematic diagram of the circuit structure of a fine-tuning control circuit provided in an embodiment of the present disclosure;

[0017] Figure 6 A control logic diagram of a fine-tuning control circuit provided in an embodiment of the present disclosure;

[0018] Fig. 7A Schematic diagram of the phase relationship of the clock signal provided in the embodiment of the present disclosure Figure 5 ;

[0019] Figure 7B Schematic diagram of the phase relationship of the clock signal provided in the embodiment of the present disclosure Figure 6 ;

[0020] Fig. 8A The circuit structure of the delay phase-locked loop circuit provided in the embodiment of the present disclosure is shown in FIG. Figure 2 ;

[0021] Figure 8B A schematic diagram of the circuit structure of a step register provided in an embodiment of the present disclosure;

[0022] Fig. 9A Schematic diagram 7 of the phase relationship of the clock signal provided in the embodiment of the present disclosure;

[0023] Fig. 9B Schematic diagram 8 of the phase relationship of the clock signal provided in the embodiment of the present disclosure;

[0024] Fig. 10A Schematic diagram 9 of the phase relationship of the clock signal provided in the embodiment of the present disclosure;

[0025] Fig. 10B Schematic diagram 10 of the phase relationship of the clock signal provided in the embodiment of the present disclosure;

[0026] Fig.11 A schematic diagram of the circuit structure of an edge detection circuit provided in an embodiment of the present disclosure;

[0027] Fig.12 A schematic diagram of the circuit structure of a sequence detection circuit provided in an embodiment of the present disclosure;

[0028] Fig.13 A schematic diagram of the circuit structure of a fine adjustment circuit provided in an embodiment of the present disclosure;

[0029] Fig.14 A schematic diagram of the circuit structure of the decoding circuit provided in the embodiment of the present disclosure Figure 1 ;

[0030] Fig.15 A schematic diagram of the circuit structure of the decoding circuit provided in the embodiment of the present disclosure Figure 2 ;

[0031] Fig.16 A schematic diagram of the circuit structure of a selection circuit provided in an embodiment of the present disclosure;

[0032] Fig.17 A schematic diagram of a flow chart of a time-delay phase-locking method provided in an embodiment of the present disclosure;

[0033] Fig.18 The circuit structure of the delay phase-locked loop circuit provided in the embodiment of the present disclosure is shown in FIG. Figure 3 ;

[0034] Fig.19 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0036] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0037] If similar descriptions of "first / second" appear in the application documents, the following description is added. In the following description, the terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0039] Figure 1 is a schematic diagram of the structure of an optional delay phase-locked loop circuit 100 provided in an embodiment of the present disclosure, such as Figure 1 As shown, the delay phase-locked loop circuit 100 includes: a comparator 10, a fine adjustment control circuit 20, and a fine adjustment circuit 30. The comparator 10 is configured to receive a reference clock signal RefClk and a clock signal to be fine-tuned, and compare the phases of the reference clock signal RefClk and the clock signal to be fine-tuned to generate a first feedback signal PdOut. The jump of the first feedback signal PdOut indicates that the phase relationship between the reference clock signal RefClk and the clock signal to be fine-tuned has changed. The fine adjustment control circuit 20, connected to the comparator 10, is configured to generate a fine adjustment control code SAR<3:0> based on a binary search algorithm, and to receive the first feedback signal PdOut, and adjust the fine adjustment control code SAR<3:0> based on a binary search algorithm in response to the first feedback signal PdOut. The fine adjustment circuit 30 is configured to receive the fine adjustment control code SAR<3:0> and a fine adjustment input clock signal, apply a fine adjustment delay value to the fine adjustment input clock signal, and generate a clock signal to be fine-tuned. Furthermore, the fine tuning circuit 30 adjusts the fine tuning delay value in response to the change in the value of each bit encoded in the fine tuning control code SAR<3:0> until the phase difference between the reference clock signal RefClk and the clock signal to be fine tuned is less than the unit delay of the fine tuning circuit 30 .

[0040] It should be noted that the reference Figure 1 The delay phase-locked loop circuit 100 adjusts the reference clock signal RefClk and outputs a feedback signal FBClk. In the process of coarse adjustment locking, the feedback signal FBClk is the clock signal to be coarsely adjusted. In the process of fine adjustment locking, the feedback signal FBClk is the clock signal to be finely adjusted.

[0041] It should also be noted that in the embodiments of the present disclosure, reference Figure 1The delay phase-locked loop circuit 100 may further include a coarse adjustment circuit 40. After the coarse adjustment circuit 40 completes the coarse adjustment locking, the coarse adjustment circuit 40 will input a fine adjustment input clock signal to the fine adjustment circuit 30. The coarse adjustment circuit 40 in the delay phase-locked loop circuit 100 may adopt a dual delay line structure. Therefore, the fine adjustment input clock signal may include a first fine adjustment input clock signal ODDIN and a second fine adjustment input clock signal EVENIN. The first fine adjustment input clock signal ODDIN and the second fine adjustment input clock signal EVENIN have different phases.

[0042] In the embodiments of the present disclosure, reference Figure 1 , the comparator 10 may be a phase detector (PD). During the fine tuning locking process, the comparator 10 may be configured to compare the phase relationship between the reference clock signal RefClk and the clock signal to be fine tuned. For example, if the first feedback signal PdOut output by the comparator 10 is at a high level, it indicates that the phase of the clock signal to be fine tuned lags behind the phase of the reference clock signal RefClk; conversely, if the first feedback signal PdOut output by the comparator 10 is at a low level, it indicates that the phase of the reference clock signal RefClk lags behind the phase of the clock signal to be fine tuned. Thus, the present disclosure can confirm whether the phase relationship between the reference clock signal RefClk and the clock signal to be fine tuned has changed based on whether the first feedback signal PdOut has a jump.

[0043] Figure 2 It is an optional phase relationship diagram between a clock signal to be fine-tuned and a fine-tuned input clock signal provided by an embodiment of the present disclosure.

[0044] In the present disclosure, in combination Figure 1 and Figure 2 The fine adjustment circuit 30 is configured to receive a fine adjustment input clock signal, apply a fine adjustment delay value to the fine adjustment input clock signal, and generate a clock signal to be fine adjusted. For example, the fine adjustment circuit 30 receives a first fine adjustment input clock signal ODDIN and a second fine adjustment input clock signal EVENIN. Then, the fine adjustment circuit 30 processes the first fine adjustment input clock signal ODDIN and the second fine adjustment input clock signal EVENIN using a phase interpolation technique, that is, applies a fine adjustment delay value to the first fine adjustment input clock signal ODDIN and the second fine adjustment input clock signal EVENIN. Thus, the fine adjustment circuit 30 can adjust the phase of the clock signal to be fine adjusted LCLAB, so that the phase of the clock signal to be fine adjusted LCLAB changes between the first fine adjustment input clock signal ODDIN and the second fine adjustment input clock signal EVENIN.

[0045] It should be noted that if the number of bits corresponding to the fine-tuning delay value is 2n, the number of bits of the fine-tuning control code is n; n is a positive integer. For example, the fine-tuning delay value can be 16 bits, and the fine-tuning control circuit 20 only needs to generate a 4-bit fine-tuning control code.

[0046] Figure 3 1 is a circuit diagram of an optional fine-tuning delay line 310 provided by an embodiment of the present disclosure. It should be noted that the number of inverters 311 included in the fine-tuning delay line 310 may correspond to the number of bits of the fine-tuning delay value. For example, DL_ODD_SELT<15:0> and DL_EVEN_SELT<15:0> may both be 16 bits, and the corresponding number of inverters 311 is 16 groups. Among them, the inverter 311 receiving C0 and D0 is a group with the inverter 311 receiving the first fine-tuning input clock signal ODDIN at the corresponding position; the inverter 311 receiving C1 and D1 is a group with the inverter 311 receiving the first fine-tuning input clock signal ODDIN at the corresponding position, and so on. DL_ODD_SELT<15:0> includes D15 to D0, and C15 to C0 are the inverted signals of DL_ODD_SELT<15:0>. Optionally, D0 and F0 are in-phase signals, C0 and E0 are in-phase signals, and so on, D15 and F15 are in-phase signals, and C15 and E15 are in-phase signals.

[0047] In the present disclosure, in combination Figure 1 and Figure 3 , the fine adjustment circuit 30 may include a fine adjustment delay line (FDL) 310. The fine adjustment control circuit 20 provides the fine adjustment control code SAR<3:0> to the fine adjustment circuit 30, and the fine adjustment circuit 30 inputs the corresponding fine adjustment delay value DL_ODD_SELT<15:0> and the fine adjustment delay value DL_EVEN_SELT<15:0> into the fine adjustment delay line 310 according to the code in the fine adjustment control code SAR<3:0>. Thus, the fine adjustment circuit 30 can adjust the fine adjustment delay value applied to the first fine adjustment input clock signal ODDIN and the second fine adjustment input clock signal EVENIN by controlling the on and off states of each inverter 311 in the fine adjustment delay line 310. Thus, the phase of the clock signal to be finely adjusted LCLAB is adjusted.

[0048] In the present disclosure, in combination Figure 2 and Figure 3, the level state of one bit in the fine adjustment delay value DL_ODD_SELT<15:0> and the fine adjustment delay value DL_EVEN_SELT<15:0> corresponds to the on or off state of one inverter 311 in the fine adjustment delay line 310. In this way, one bit in the fine adjustment delay value DL_ODD_SELT<15:0> and the fine adjustment delay value DL_EVEN_SELT<15:0> is the unit delay amount of the fine adjustment circuit 30, that is, the minimum adjustment range of the fine adjustment circuit 30. When DL_EVEN_SELT<15:0> remains unchanged, if the number of low-level bits in DL_ODD_SELT<15:0> is greater, the phase of the clock signal LCLAB to be fine-tuned will be closer to the phase of the first fine-tuning input clock signal ODDIN, and farther away from the phase of the second fine-tuning input clock signal EVENIN; conversely, if the number of low-level bits in DL_ODD_SELT<15:0> is smaller, the phase of the clock signal LCLAB to be fine-tuned will be closer to the phase of the second fine-tuning input clock signal EVENIN, and farther away from the phase of the first fine-tuning input clock signal ODDIN.

[0049] It should be noted that the unit delay amount can be the minimum amount of the fine-tuning delay value, and thus, the unit delay amount can be the minimum adjustment range of the fine-tuning circuit. Given that the size parameters such as the width-to-length ratio of each transistor in the inverter are adjustable, the delay amount caused by each transistor may not be the same, and thus, the delay amount caused by each inverter may not be uniform. Therefore, the unit delay amount can be the minimum amount of the fine-tuning delay value when the delay amount caused by the inverter is uneven.

[0050] It should also be noted that, given that the phases of the reference clock signal and the clock signal to be fine-tuned cannot be completely aligned, if the phase difference between the reference clock signal and the clock signal to be fine-tuned is less than the minimum adjustment range of the fine-tuning circuit, it can be considered that the phases of the reference clock signal and the clock signal to be fine-tuned are infinitely close, and the fine-tuning circuit has completed fine-tuning lock. Moreover, after the fine-tuning lock is completed, the phase difference between the reference clock signal and the clock signal to be fine-tuned is less than the unit delay of the fine-tuning circuit, that is, the phase difference between the reference clock signal and the clock signal to be fine-tuned is less than the delay of an inverter. Thus, it can be ensured that the delay between the clock signal to be fine-tuned and the reference clock signal is sub-gate, meeting the resolution requirements of the delay phase-locked loop circuit at higher frequencies.

[0051] Figure 4A , Figure 4B and Figure 4C is a schematic diagram of a phase relationship between an optional reference clock signal RefClk and a clock signal to be fine-tuned provided by an embodiment of the present disclosure; wherein, Figure 4A The phase relationship between the reference clock signal RefClk and the clock signal to be fine-tuned LCLAB during coarse-tuning locking is shown. Figure 4Band Figure 4C The phase relationship between the reference clock signal RefClk and the clock signal to be fine-tuned LCLAB during the fine-tuning locking process is shown; wherein, Figure 4B The fine adjustment control code SAR<3:0> corresponding to the clock signal to be finely adjusted LCLAB is a reset value, SAR<3:0>=0000.

[0052] It should be noted that Figure 4A , Figure 4B and Figure 4C The phase relationship between the reference clock signal and the clock signal to be fine-tuned is represented by the position relationship of the target transition edge. Figure 4A , Figure 4B and Figure 4C The target transition edges of the reference clock signal and the clock signal to be fine-tuned are shown as rising edges. Figure 4A The rising edge of the first fine adjustment input clock signal ODDIN is ahead of the rising edge of the reference clock signal RefClk, indicating that Figure 4A The phase of the first fine adjustment input clock signal ODDIN is ahead of the phase of the reference clock signal RefClk.

[0053] In the present disclosure, in combination Figure 1 and Figure 4A , during the coarse adjustment locking process, the fine adjustment delay line 310 receives the default delay code. For example, the adjustment unit of the fine adjustment delay line 310 receives the first default delay code and the second default delay code, the first default delay code is 1111_1111_1111_1111 and the second default delay code is 0000_0000_0000_0000. Accordingly, the applied fine adjustment delay value DL_ODD_SELT<15:0>=1111_1111_1111_1111, and the applied fine adjustment delay value DL_EVEN_SELT<15:0>=0000_0000_0000_0000. Thus, when the coarse adjustment locking is completed, the initial clock signal LCLAB to be finely adjusted is in the middle of the first fine adjustment input clock signal ODDIN and the second fine adjustment input clock signal EVENIN, that is, the rising edge of the clock signal LCLAB to be finely adjusted is at Figure 4A In the subsequent fine tuning locking process, the fine tuning control circuit 20 adjusts the fine tuning control code SAR<3:0> based on the binary search algorithm, and then the fine tuning circuit 30 adjusts the applied fine tuning delay value based on the change of each bit value of the fine tuning control code SAR<3:0>, so that the rising edge of the clock signal to be fine tuned at the initial time is Figure 4AThe MT position is close to the first fine adjustment input clock signal ODDIN or the second fine adjustment input clock signal EVENIN. In this way, one boundary of the maximum fine adjustment interval corresponding to the fine adjustment delay value is MT, and the other boundary is the first fine adjustment input clock signal ODDIN or the second fine adjustment input clock signal EVENIN. Thus, the adjustment interval of the fine adjustment circuit 30 is reduced, and the fine adjustment locking process of the delay phase-locked loop circuit 100 can be further accelerated.

[0054] In the present disclosure, in combination Figure 4A and Figure 4C After confirming that the reference clock signal RefClk is in the maximum fine adjustment interval of the fine adjustment delay value, the delay phase-locked loop circuit 100 can adjust the fine adjustment delay value DL_ODD_SELT<15:0> and the fine adjustment delay value DL_EVEN_SELT<15:0> to move the target transition edge of the clock signal to be fine-tuned LCLAB accordingly, that is, adjust the phase of the clock signal to be fine-tuned LCLAB. For example, Figure 4B The reference clock signal RefClk is within the maximum fine adjustment interval of DL_ODD_SELT<15:0>, that is, the rising edge of the reference clock signal RefClk is within Figure 4B If fine tuning locking is required, the rising edge of the clock signal LCLAB to be fine tuned needs to be adjusted close to the first fine tuning input clock signal ODDIN, and correspondingly, DL_ODD_SELT<15:0> needs to be gradually adjusted from 1111_1111_1111_1111 to 0000_0000_0000_0000. In addition, each time the fine tuning delay value DL_ODD_SELT<15:0> is adjusted, the phase of the corresponding clock signal LCLAB to be fine tuned is compared with the reference clock signal RefClk, so that the phase of the clock signal LCLAB to be fine tuned is continuously close to the phase of the reference clock signal RefClk, until the phase difference between the reference clock signal RefClk and the clock signal to be fine tuned is less than the unit delay of the fine tuning circuit 30. In this way, the present disclosure can continuously adjust the phase of the clock signal to be fine-tuned LCLAB through the fine-tuning control code SAR<3:0> generated by the fine-tuning control circuit 20 until the phase of the reference clock signal RefClk is aligned with the clock signal to be fine-tuned LCLAB, so that the delay phase-locked loop circuit 100 completes fine-tuning locking.

[0055] Figure 5 is a circuit diagram of an optional fine-tuning control circuit 20, Figure 6 This is a schematic diagram of an optional flow chart of the fine adjustment control circuit 20 generating a fine adjustment control code. It should be noted that: Figure 5 and Figure 6The following description takes the case where the fine adjustment control circuit 20 generates a 4-bit fine adjustment control code SAR<3:0> as an example.

[0056] In the present disclosure, in combination Figure 5 and Figure 6 In the fine tuning locking process, if the reference clock signal is within the maximum fine tuning interval of the fine tuning delay value, the fine tuning control circuit 20 can generate the fine tuning control code SAR<3:0> through a binary search algorithm. Therefore, the fine tuning circuit 30 can make the fine tuning delay value corresponding to the fine tuning control code SAR<3:0> be at the median value of the current adjustment interval based on the fine tuning control code SAR<3:0>, and then continuously reduce the range of the adjustment interval until the range of the adjustment interval is equal to the unit delay amount. For example, Figure 4C As shown in FIG. 1 , the rising edge of the reference clock signal RefClk is between the rising edge of the first fine tuning input clock signal ODDIN and MT, that is, the reference clock signal RefClk is within the maximum fine tuning interval of the fine tuning delay value DL_ODD_SELT<15:0>. The fine tuning circuit 30 can control the SAR in the code SAR<3:0> <3> Set to 1, that is, SAR<3:0>=1000, corresponding to the fine adjustment delay value DL_ODD_SELT<15:0>=1111_1111_0000_0000. At this time, if the first feedback signal PdOut jumps, it means that the phase of the clock signal LCLAB(1) to be finely adjusted corresponding to the fine adjustment control code SAR<3:0>=1000 changes from lagging behind the phase of the reference clock signal RefClk to leading the phase of the reference clock signal RefClk. Therefore, the rising edge of the reference clock signal RefClk is between the rising edge of the clock signal LCLAB(1) to be finely adjusted and MT. Then, the control code SAR<3:0> needs to be adjusted from 1000 to 0100, so that the fine adjustment delay value DL_ODD_SELT<15:0>=1111_0000_0000_0000. At this time, if the first feedback signal PdOut jumps, it means that the phase of the clock signal LCLAB(2) to be finely adjusted corresponding to the fine adjustment control code SAR<3:0>=0100 changes from being ahead of the phase of the reference clock signal RefClk to being behind the phase of the reference clock signal RefClk. Therefore, the rising edge of the reference clock signal RefClk is between the rising edge of the clock signal LCLAB(1) to be finely adjusted and the rising edge of the clock signal LCLAB(2) to be finely adjusted. Then, the clock signal LCLAB(3) to be finely adjusted corresponding to the control code SAR<3:0> needs to be between the clock signal LCLAB(1) to be finely adjusted and the clock signal LCLAB(2) to be finely adjusted until the adjustment interval is less than the unit delay of the fine adjustment circuit.

[0057] It should be noted that the subordinate relationship between the fine-tuning control circuit and the components in the fine-tuning circuit is artificially divided and does not change the actual circuit relationship. The fine-tuning control circuit may also include a decoding circuit, a first selection circuit, a second selection circuit and a fine-tuning shift register; correspondingly, the fine-tuning circuit may only include a fine-tuning delay line.

[0058] It is understandable that the fine-tuning control circuit of the present disclosure can generate and adjust the fine-tuning control code using a binary search algorithm. Each time the fine-tuning control circuit adjusts the fine-tuning control code, the corresponding fine-tuning delay value is adjusted to the middle value of the current adjustment sub-interval. Moreover, the next adjustment sub-interval can be determined in sequence based on the comparison of the phase relationship between the clock signal to be fine-tuned and the reference clock signal. In this way, the present disclosure can use the binary search method to quickly narrow the adjustment sub-interval, thereby reducing the number of comparisons between the clock signal to be fine-tuned and the reference clock signal, and further speeding up the fine-tuning locking process of the delay phase-locked loop circuit 100.

[0059] In some embodiments of the present disclosure, reference Figure 1 , the delay phase-locked loop circuit 100 also includes: a coarse adjustment circuit 40. The coarse adjustment circuit 40 is configured to perform coarse adjustment on the coarse adjustment clock signal; and after the coarse adjustment is completed, it is in a locked state and outputs a fine adjustment input clock signal. The coarse adjustment clock signal is generated based on the reference clock signal RefClk. The fine adjustment control circuit 20 is also configured to adjust the fine adjustment control code SAR<3:0> to a reset value when the coarse adjustment circuit 40 is in a locked state. The fine adjustment circuit 30 is also configured to adjust the fine adjustment delay value from one boundary value of the maximum fine adjustment interval to another boundary value in response to the fine adjustment control code SAR<3:0> of the reset value when the coarse adjustment circuit 40 is in a locked state. The coarse adjustment circuit 40 is also configured to advance or delay the fine adjustment input clock signal by one coarse adjustment interval when the fine adjustment control code SAR<3:0> is adjusted to the reset value.

[0060] It should be noted that, combined with Figure 1 and Figure 2 ,, during the actual operation of the delay phase-locked loop circuit 100, the phase relationship between the reference clock signal RefClk and the fine-tuning input clock signal cannot be known. At the same time, due to the limitation of the maximum fine-tuning interval of the fine-tuning delay value, the phase of the clock signal to be fine-tuned can only change between the first fine-tuning input clock signal ODDIN and the second fine-tuning input clock signal EVENIN. Therefore, it is necessary to confirm whether the phase of the reference clock signal is between the phase of the first fine-tuning input clock signal ODDIN and the phase of the second fine-tuning input clock signal EVENIN.

[0061] Further, in the embodiments of the present disclosure, reference is made to Figure 1, when the coarse adjustment circuit 40 is in the locked state, the fine adjustment control circuit 20 can reset the fine adjustment control code SAR<3:0>. For example, the fine adjustment control code SAR<3:0> is reset to 0000. The fine adjustment circuit 30 can adjust the fine adjustment delay value from one boundary value of the maximum fine adjustment interval to another boundary value in response to the fine adjustment control code SAR<3:0> of the reset value. For example, the default delay code received by the fine adjustment circuit 30 is as follows: Figure 4A As shown, it is 1111_1111_1111_1111, and the corresponding fine-tuning delay value DL_ODD_SELT<15:0>=1111_1111_1111_1111; after the fine-tuning control code SAR<3:0> is reset to 0000, the corresponding fine-tuning delay code is as follows Figure 4B As shown, it is 0000_0000_0000_0000, and the corresponding fine adjustment delay value DL_ODD_SELT<15:0>=0000_0000_0000_0000. Therefore, the rising edge of the clock signal LCLAB to be fine-tuned is Figure 4A At the MT position in Figure 4B At the position of the rising edge of the first fine adjustment input clock signal ODDIN.

[0062] Further, in the embodiments of the present disclosure, continue to refer to Figure 1 , when the fine adjustment control code SAR<3:0> is adjusted to the reset value, if the first feedback signal PdOut jumps, it means that when the clock signal to be fine-tuned is at two boundary values, the phase relationship between the clock signal to be fine-tuned and the reference clock signal RefClk changes. Figure 4A When the medium fine adjustment delay value DL_ODD_SELT<15:0>=1111_1111_1111_1111, the phase of the clock signal to be finely adjusted LCLAB lags behind the reference clock signal RefClk; Figure 4A The fine-tuning delay value in is adjusted to Figure 4B When DL_ODD_SELT<15:0>=0000_0000_0000_0000, the phase of the clock signal LCLAB to be fine-tuned is ahead of the reference clock signal RefClk. That is to say, the reference clock signal RefClk is within the maximum fine-tuning interval of the fine-tuning delay value DL_ODD_SELT<15:0>. In this way, the fine-tuning delay value is adjusted from one boundary value of the maximum fine-tuning interval to another boundary value. Therefore, when the clock signal to be fine-tuned is at two boundary values ​​respectively, whether the reference clock signal RefClk is within the maximum fine-tuning interval of the fine-tuning delay code can be confirmed by whether the first feedback signal PdOut jumps.

[0063] Accordingly, continue to refer to Figure 1, when the fine adjustment control code SAR<3:0> is adjusted to the reset value, if the first feedback signal PdOut does not jump, it means that when the clock signal to be fine-tuned is at two boundary values, the phase relationship between the clock signal to be fine-tuned and the reference clock signal RefClk does not change. In other words, the reference clock signal RefClk is not within the maximum fine adjustment interval of the fine adjustment delay code. For example, Fig. 7A The medium fine-tuning delay value DL_ODD_SELT<15:0> is adjusted from 1111_1111_1111_1111 to 0000_0000_0000_0000, the rising edge of the clock signal LCLAB to be fine-tuned moves from the MT position to the rising edge of the first fine-tuning input clock signal ODDIN, and the phase of the reference clock signal RefClk is still ahead of the clock signal LCLAB to be fine-tuned, that is, the reference clock signal RefClk is not within the maximum fine-tuning interval of the fine-tuning delay value DL_ODD_SELT<15:0>. Therefore, it is necessary to advance or delay the fine-tuning input clock signal by a coarse-tuning interval so that the reference clock signal RefClk is within the maximum fine-tuning interval of the fine-tuning delay code. For example, Figure 7B As shown, the coarse adjustment circuit 40 advances the fine adjustment input clock signal by a coarse adjustment interval, and the reference clock signal RefClk is between the first fine adjustment input clock signal ODDIN and the second fine adjustment input clock signal EVENIN'. In this way, during the fine adjustment locking process, the present disclosure can adjust the fine adjustment input clock signal through the coarse adjustment circuit so that the reference clock signal is within the maximum fine adjustment interval of the clock signal to be fine adjusted. Thus, the adjustment interval of the fine adjustment circuit 30 is reduced, and the fine adjustment locking process of the delay phase-locked loop circuit 100 can be further accelerated.

[0064] In some embodiments of the present disclosure, reference Figure 1 The fine-tuning control circuit 20 is configured to start adjusting from the highest bit of the fine-tuning control code SAR<3:0>, adjust the fine-tuning delay value to the middle value of the maximum fine-tuning interval, and determine the first adjustment sub-interval in response to the first feedback signal PdOut; and adjust the fine-tuning control code SAR<3:0> bit by bit, adjust the fine-tuning delay value to the middle value of the current adjustment sub-interval, and determine the next adjustment sub-interval in sequence in response to the first feedback signal PdOut, until the phase difference between the reference clock signal RefClk and the clock signal to be fine-tuned is less than the unit delay amount of the fine-tuning circuit 30.

[0065] It should be noted that the fine-tuning control code SAR<3:0> includes SAR <3> SAR <2> SAR <1> and SAR <0> . Figure 5 The 4 fine adjustment control sub-units 210 are included, and each fine adjustment control sub-unit 210 outputs one bit of the fine adjustment control code SAR<3:0>. Figure 5Comp is a pulse signal, VDD is a power signal, CLK is a clock signal, and the START signal is used to start the corresponding fine-tuning control subunit 210 .

[0066] In the present disclosure, in combination Figure 5 and Figure 6 , the fine adjustment control circuit 20 starts adjusting from the highest bit of the fine adjustment control code SAR<3:0>, adjusts the fine adjustment delay value to the middle value of the maximum fine adjustment interval, and determines the first adjustment sub-interval in response to the first feedback signal PdOut. For example, the fine adjustment control circuit 20 adjusts the fine adjustment control code SAR<3:0> to 1000, as shown in FIG. Figure 4C As shown, the rising edge of the clock signal to be fine-tuned is adjusted from the MT position to the LCLAB(1) position, and LCLAB(1) is located between the first fine-tuning input clock signal ODDIN and the MT position. The phase of the clock signal to be fine-tuned changes from lagging behind the reference clock signal RefClk to leading the reference clock signal RefClk, and the first feedback signal PdOut jumps. Therefore, it can be determined that the reference clock signal RefClk is between the LCLAB(1) position and the MT position.

[0067] Further, in the embodiments of the present disclosure, combined with Figure 5 and Figure 6 , the fine adjustment control circuit 20 adjusts the fine adjustment control code SAR<3:0> bit by bit, adjusts the fine adjustment delay value to the middle value of the current adjustment sub-interval, and determines the next adjustment sub-interval in sequence in response to the first feedback signal PdOut, until the phase difference between the reference clock signal RefClk and the clock signal to be fine-tuned is less than the unit delay amount of the fine adjustment circuit 30. For example, the fine adjustment control circuit 20 adjusts SAR <2> Set to 1, the fine-tuning control code SAR<3:0> is adjusted from 1000 to 0100, such as Figure 4C As shown, the rising edge of the clock signal to be fine-tuned is adjusted from the position of LCLAB(1) to the position of LCLAB(2), and LCLAB(2) is located in the middle of the position of LCLAB(1) and the position of MT. The phase of the clock signal to be fine-tuned changes from a phase ahead of the reference clock signal RefClk to a phase behind the reference clock signal RefClk, and the first feedback signal PdOut will jump. Therefore, it can be determined that the reference clock signal RefClk is between the position of LCLAB(1) and the position of LCLAB(2). In this way, the fine-tuning control circuit 20 of the present disclosure can generate and adjust the fine-tuning control code SAR<3:0> using a binary search algorithm. Therefore, the binary search algorithm can be used to quickly narrow the fine-tuning interval, and the number of comparisons between the clock signal to be fine-tuned and the reference clock signal is reduced, further accelerating the fine-tuning locking process.

[0068] Fig. 8AIt is a schematic diagram of the structure of an optional delay phase-locked loop circuit 100 provided in an embodiment of the present disclosure. It should be noted that the delay phase-locked loop circuit 100 can also generate a corresponding fine-tuning delay value through the fine-tuning control code Q<15:0> generated by the stepping register 50, so that the delay phase-locked loop circuit 100 can complete fine-tuning locking.

[0069] Figure 8B 1 is a schematic diagram of the structure of an optional step register 50 provided in an embodiment of the present disclosure. It should be noted that the step register 50 may include 16 triggers 510, and each trigger 510 generates one bit of the fine-tuning control code Q<15:0>. Figure 8B The step register 50 in FIG. 5 is only used for example. The step register 50 may be any type of step register capable of generating the fine-tuning control code Q<15:0>, and is not limited here.

[0070] In the present disclosure, in combination Fig. 8A and Figure 8B The step register 50 is configured to adjust the fine-tuning control code Q<15:0> so as to adjust the fine-tuning delay value from one boundary value of the maximum fine-tuning interval to another boundary value in accordance with the unit delay amount of the fine-tuning circuit 30; and in response to the jump of the first feedback signal PdOut, terminate the adjustment of the fine-tuning control code Q<15:0>.

[0071] Fig. 9A and Fig. 9B is another optional phase relationship diagram of the reference clock signal RefClk and the clock signal to be fine-tuned provided by an embodiment of the present disclosure; wherein, Fig. 9A The phase relationship between the reference clock signal RefClk and the clock signal to be fine-tuned during coarse-tuning locking is shown. Fig. 9B The phase relationship between the reference clock signal RefClk and the clock signal to be fine-tuned during the fine-tuning locking process is shown.

[0072] In the present disclosure, in combination Fig. 9A and Fig. 9B When the fine adjustment control code Q<15:0> is adjusted to the reset value, the fine adjustment delay value DL_EVEN_SELT<15:0> is Fig. 9A The fine-tuning delay value DL_EVEN_SELT<15:0> in is adjusted from 0000_0000_0000_0000 to 1111_1111_1111_1111, and the rising edge of the fine-tuning clock signal LCLAB is Fig. 9A At the MT position in Fig. 9AAt the rising edge of the second fine-tuning input clock signal EVENIN. At this time, the phase of the first clock signal to be fine-tuned LCLAB is ahead of the reference clock signal RefClk. That is to say, the reference clock signal RefClk is in the maximum fine-tuning interval of the fine-tuning delay value DL_ODD_SELT<15:0>. The step register 50 adjusts the fine-tuning control code Q<15:0> so that the fine-tuning delay value DL_EVEN_SELT<15:0> changes to 1 bit by bit starting from the 0th bit and toward the 15th bit. In this way, the step register 50 adjusts the fine-tuning delay value DL_EVEN_SELT<15:0> from one boundary value of the maximum fine-tuning interval to another boundary value according to the unit delay amount of the fine-tuning circuit. That is, Figure 2 The inverters 311 receiving the second fine adjustment input clock signal EVENIN are closed one by one, and the rising edge of the fine adjustment clock signal LCLAB is turned off according to Fig. 9B The direction indicated by the middle arrow gradually approaches the rising edge of the second fine tuning input clock signal EVENIN from the MT position until it is aligned with the reference clock signal RefClk. Thus, the delay phase-locked loop circuit completes fine tuning locking.

[0073] Fig. 10A and Fig. 10B is another optional phase relationship diagram of the reference clock signal RefClk and the clock signal to be fine-tuned provided by an embodiment of the present disclosure; wherein, Fig. 10A The phase relationship between the reference clock signal RefClk and the clock signal to be fine-tuned during coarse-tuning locking is shown. Fig. 10B The phase relationship between the reference clock signal RefClk and the clock signal to be fine-tuned during the fine-tuning locking process is shown.

[0074] In the present disclosure, in combination Fig. 10A and Fig. 10B , when the fine adjustment control code Q<15:0> is adjusted to the reset value, if the first feedback signal does not jump, it means that when the clock signal to be fine-tuned LCLAB is at two boundary values, the phase relationship between the clock signal to be fine-tuned and the reference clock signal does not change. For example, Fig. 10A In the fine-tuning delay value DL_EVEN_SELT<15:0>0000_0000_0000_0000 is adjusted to 1111_1111_1111_1111, and the rising edge of the fine-tuning clock signal LCLAB is Fig. 10A At the MT position in Fig. 10AAt the rising edge of the second fine adjustment input clock signal EVENIN in the PWM signal. At this time, the phase of the first clock signal to be fine-tuned LCLAB still lags behind the reference clock signal RefClk. Therefore, it is necessary to advance or delay the fine adjustment input clock signal by a coarse adjustment interval so that the reference clock signal RefClk is within the maximum fine adjustment interval of the fine adjustment delay code. For example, Fig. 10B As shown in FIG. 1 , the coarse adjustment circuit advances the fine adjustment input clock signal by one coarse adjustment interval, and the reference clock signal RefClk is between MT' and the second fine adjustment input clock signal EVENIN. In this way, the step register 50 adjusts the fine adjustment delay value DL_EVEN_SELT<15:0> from one boundary value of the maximum fine adjustment interval to another boundary value according to the unit delay amount of the fine adjustment circuit. That is, the rising edge of the clock signal to be fine-tuned LCLAB is adjusted according to Fig. 10B The direction indicated by the middle arrow is from the rising edge of the second fine tuning input clock signal EVENIN gradually approaching the position of MT' until it is aligned with the reference clock signal RefClk. Thus, the delay phase-locked loop circuit completes fine tuning locking.

[0075] Fig.11 Schematic diagram of a circuit structure of an optional edge detection circuit 610 provided in an embodiment of the present disclosure. Fig.12 is a schematic diagram of a circuit structure of an optional sequence detection circuit 620 provided in an embodiment of the present disclosure. It should be noted that TdcOut<N:0> is the coarse adjustment control code generated by the coarse adjustment circuit 40, the coarse adjustment control code TdcOut<N:0> It can be generated by a time to digital converter (TDC). N is used to represent the coarse control code TdcOut<N:0> The number of bits, for example, when N is 7, the coarse adjustment control code TdcOut<7:0> is an 8-bit code.

[0076] In some embodiments of the present disclosure, Fig.11 and Fig.12The fine adjustment circuit further includes a sequence detection circuit 620, a pulse update circuit 630, a sequence detection register 640 and an edge detection circuit 610. The sequence detection circuit 620 is connected to the coarse adjustment circuit 40 and is configured to generate a corresponding verification signal SeqOut based on the sequence of the phases of the first fine adjustment input clock signal and the second fine adjustment input clock signal. The pulse update circuit 630 is configured to generate a corresponding pulse signal when the coarse adjustment circuit 40 is in a locked state. The sequence detection register 640 is connected to the sequence detection circuit 620 and the pulse update circuit 630, and is configured to receive the verification signal SeqOut and the pulse signal, and generate a second feedback signal SeqOutIni in response to the verification signal and the pulse signal. The edge detection circuit 610 is connected to the comparator 10 and is configured to monitor the jump of the first feedback signal PdOut and generate a third feedback signal EdgeOut.

[0077] It should be noted that, in the embodiments of the present disclosure, reference Figure 1 , since it is impossible to know whether the reference clock signal RefClk is within the maximum fine adjustment interval of the fine adjustment delay value during the actual operation of the delay phase-locked loop circuit 100. For example, after the coarse adjustment circuit 40 completes the coarse adjustment lock, the fine adjustment control circuit 20 will Figure 1 The fine adjustment control code SAR<3:0> in the reset value is reset to 0000. The fine adjustment circuit 30 can adjust the fine adjustment delay value from one boundary value of the maximum fine adjustment interval to another boundary value in response to the fine adjustment control code SAR<3:0> of the reset value. Correspondingly, Figure 4A and Fig. 7A As shown, the rising edge of the clock signal to be fine-tuned LCLAB is adjusted from the MT position to the rising edge position of the first fine-tuning input clock signal ODDIN. Figure 4A The phase of the clock signal LCLAB to be fine-tuned is adjusted from lagging behind the reference clock signal RefClk to being ahead of the reference clock signal RefClk, that is, the reference clock signal RefClk is within the maximum fine-tuning interval of the fine-tuning delay value. Fig. 7A The phase of the clock signal LCLAB to be fine-tuned always lags behind the phase of the reference clock signal RefClk, that is, the reference clock signal RefClk is not within the maximum fine-tuning interval of the fine-tuning delay value. In this way, in the subsequent fine-tuning locking process, it is necessary to determine whether the clock signal LCLAB to be fine-tuned needs to cross the boundary where the first fine-tuning input clock signal ODD is located, that is, to determine whether the reference clock signal RefClk is within the maximum fine-tuning interval of the fine-tuning delay value. In addition, when the reference clock signal RefClk is not within the maximum fine-tuning interval of the fine-tuning delay value, the coarse-tuning circuit is required to advance or delay the fine-tuning input clock signal by one coarse-tuning interval, so that the reference clock signal RefClk is within the maximum fine-tuning interval of the fine-tuning delay value.

[0078] Further, in the embodiments of the present disclosure, continue to refer to Fig.11 , the edge detection circuit 610 receives the first feedback signal PdOut output by the comparator 10, and detects whether the first feedback signal PdOut output by the comparator 10 has a jump. In this way, when the fine-tuning control code is adjusted to the reset value, if the first feedback signal PdOut jumps, it means that the reference clock signal RefClk is in the maximum fine-tuning interval of the fine-tuning delay value. Therefore, if Figure 4A As shown, the rising edge of the clock signal to be fine-tuned LCLAB does not need to cross the boundary where the first fine-tuning input clock signal ODD is located. On the contrary, if the first feedback signal PdOut does not jump, it means that the reference clock signal RefClk is not in the maximum fine-tuning interval of the fine-tuning delay value. Fig. 7A As shown, the rising edge of the fine-tuning clock signal LCLAB needs to cross the boundary where the first fine-tuning input clock signal ODD is located. Then, the edge detection circuit 610 needs to send a third feedback signal EdgeOut to the coarse-tuning circuit 40, and the coarse-tuning circuit 40 delays or advances the fine-tuning input clock signal by a coarse-tuning interval based on the received third feedback signal EdgeOut. For example, Figure 7B In the embodiment, the coarse adjustment circuit 40 is advanced by a coarse adjustment interval, and the phase of the reference clock signal RefClk is between the phase of the second fine adjustment input clock signal EVENIN′ and the phase of the first fine adjustment input clock signal ODDIN.

[0079] It should also be noted that in the embodiments of the present disclosure, reference Figure 2 , the phase sequence of the first fine tuning input clock signal ODDIN and the second fine tuning input clock signal EVENIN is different. Thus, in the fine tuning locking process, the fine tuning delay value applied to the clock signal to be fine tuned LCLAB is also different. For example, Figure 4A The phase of the first fine tuning input clock signal ODDIN is ahead of the phase of the second fine tuning input clock signal EVENIN; in the fine tuning locking process, if Figure 4B As shown, the rising edge of the clock signal to be fine-tuned needs to be adjusted to be close to the first fine-tuning input clock signal ODDIN. Therefore, the applied fine-tuning delay value DL_EVEN_SELT<15:0> always remains at 0000_0000_0000_0000, and the applied fine-tuning delay value DL_ODD_SELT<15:0> will be gradually adjusted from 1 to 0 from 1111_1111_1111_1111. Fig. 9A The phase of the second fine tuning input clock signal EVENIN is ahead of the phase of the first fine tuning input clock signal ODDIN; in the fine tuning locking process, if Fig. 9BAs shown, the rising edge of the clock signal to be fine-tuned needs to be adjusted to be close to the second fine-tuning input clock signal EVENIN, so the applied fine-tuning delay value DL_ODD_SELT<15:0> is always kept as 1111_1111_1111_1111, and the applied fine-tuning delay value DL_EVEN_SELT<15:0> is gradually adjusted from 0000_0000_0000_0000 from 0 to 1. Therefore, before fine-tuning locking is performed using the fine-tuning control code, the order of the phases of the first fine-tuning input clock signal ODDIN and the second fine-tuning input clock signal EVENIN needs to be determined.

[0080] Further, in the embodiments of the present disclosure, continue to refer to Fig.12 , the coarse adjustment circuit 40 can adjust the coarse adjustment control code TdcOut<N:0> The sequence detection circuit 620 receives the coarse adjustment control code TdcOut.<N:0> For example, for TdcOut<N:0> Perform odd check, if TdcOut<N:0> =11110000, the number of "1" is 4 (even number), which means that the phase of the first fine adjustment input clock signal ODDIN is ahead of the phase of the second fine adjustment input clock signal EVENIN, and the sequence detection circuit 620 outputs the verification signal SeqOut as a low level. On the contrary, if TdcOut<N:0> =11111000, the number of "1" is 5 (odd number), which means that the phase of the first fine adjustment input clock signal ODDIN lags behind the phase of the second fine adjustment input clock signal EVENIN, and the sequence detection circuit 620 outputs the verification signal SeqOut as a high level. After the coarse adjustment circuit 40 completes the coarse adjustment lock, the pulse update circuit 630 generates a pulse to generate a pulse signal. The sequence detection register 640 records the initial phase relationship between the first fine adjustment input clock signal ODDIN and the second fine adjustment input clock signal EVENIN based on the received pulse signal and the verification signal SeqOut, and outputs the corresponding second feedback signal SeqOutIni. For example, the phase of the first fine adjustment input clock signal ODDIN leads the phase of the second fine adjustment input clock signal EVENIN, the verification signal SeqOut is a high level, and the second feedback signal SeqOutIni is a high level. The phase of the first fine adjustment input clock signal ODDIN lags behind the phase of the second fine adjustment input clock signal EVENIN, the verification signal SeqOut is a low level, and the second feedback signal SeqOutIni is a low level.

[0081] Fig.13 It is a schematic diagram of the structure of an optional fine adjustment circuit 30 provided by the present disclosure. It should be noted that the value of each bit in the fine adjustment delay code is the same as the value of the corresponding bit of the generated fine adjustment delay value.

[0082] In some embodiments of the present disclosure, reference Fig.13 , the fine adjustment circuit 30 includes a decoding circuit 320. The decoding circuit 320 is configured to receive the fine adjustment control code SAR<3:0> and generate a plurality of fine adjustment delay codes based on the fine adjustment control code SAR<3:0>. The decoding circuit 320 is also configured to select a corresponding fine adjustment delay code output from the plurality of fine adjustment delay codes in response to the second feedback signal and the third feedback signal EdgeOut. The second feedback signal represents the order of the phases of the first fine adjustment input clock signal ODDIN and the second fine adjustment input clock signal EVENIN; the third feedback signal EdgeOut represents the order of the phases of the clock signal to be fine-tuned and the fine adjustment input clock signal.

[0083] It should be noted that, in the embodiments of the present disclosure, Figure 1 and Fig.13 , the fine adjustment delay value corresponding to the same fine adjustment control code SAR<3:0> output by the fine adjustment control circuit 20 is different for the different phase sequences of the first fine adjustment input clock signal ODDIN and the second fine adjustment input clock signal EVENIN, and whether the clock signal to be fine-tuned needs to cross the boundary where the first fine adjustment input clock signal ODDIN or the second fine adjustment input clock signal EVENIN is located. For example, after the coarse adjustment circuit 40 completes the coarse adjustment lock, if the second feedback signal SeqOutIni is at a high level, it means that the phase of the first fine adjustment input clock signal ODDIN is ahead of the phase of the second fine adjustment input clock signal EVENIN, and the fine adjustment circuit 30 needs to be based on the reset value of the fine adjustment control code SAR<3:0>=0000, according to Figure 4B As shown, the fine adjustment delay value DL_ODD_SELT<15:0> is adjusted from 1111_1111_1111_1111 corresponding to the default delay code to 0000_0000_0000_0000. If the second feedback signal SeqOutIni is at a low level, it means that the phase of the second fine adjustment input clock signal EVENIN is ahead of the phase of the first fine adjustment input clock signal ODDIN, and the fine adjustment circuit 30 needs to adjust the fine adjustment control code SAR<3:0>=0000 based on the reset value, according to Fig. 9A As shown in the figure, the fine adjustment delay value DL_EVEN_SELT<15:0> is adjusted from 0000_0000_0000_0000 corresponding to the default delay code to 1111_1111_1111_1111. And, when the fine adjustment control code SAR<3:0> is adjusted from 1000 to 1100, as shown in the figure, Figure 4CAs shown, the clock signal to be fine-tuned LCLAB does not need to cross the boundary where the first fine-tuning input clock signal ODDIN is located, the fine-tuning delay value DL_ODD_SELT<15:0> is adjusted from 1111_1111_0000_0000 to 1111_0000_0000_0000, and the rising edge of the clock signal to be fine-tuned is Figure 4C The LCLAB(1) position in is adjusted to the LCLAB(2) position; however, Figure 7B In the process, the clock signal to be fine-tuned LCLAB needs to cross the boundary where the first fine-tuning input clock signal ODDIN is located. When the fine-tuning control code SAR<3:0> is adjusted from 1000 to 1100, the fine-tuning delay value DL_ODD_SELT<15:0> is adjusted from 1111_1111_0000_0000 to 1111_1111_1111_0000, and the rising edge of the clock signal to be fine-tuned is Figure 4C Therefore, the decoding circuit needs to decode the fine adjustment control code SAR<3:0> into a corresponding fine adjustment delay code and generate a corresponding fine adjustment delay value according to the different phase sequences of the first fine adjustment input clock signal ODDIN and the second fine adjustment input clock signal EVENIN and whether the clock signal to be fine adjusted needs to cross the boundary between the first fine adjustment input clock signal ODDIN and the second fine adjustment input clock signal EVENIN.

[0084] In the present disclosure, continue to refer to Fig.13 , the decoding circuit 320 decodes the fine adjustment control code SAR<3:0> into a plurality of fine adjustment delay codes, and in response to the second feedback signal SeqOutIni and the third feedback signal EdgeOut, selects a corresponding fine adjustment delay code from the plurality of fine adjustment delay codes for output. In the process of fine adjustment locking, the second feedback signal SeqOutIni can represent the phase sequence of the first fine adjustment input clock signal ODDIN and the second fine adjustment input clock signal EVENIN. When the fine adjustment control code SAR<3:0> is adjusted to the reset value, the third feedback signal EdgeOut is generated based on detecting the jump of the first feedback signal. At this time, the jump of the first feedback signal can represent whether the clock signal to be fine-tuned crosses the boundary where the first fine adjustment input clock signal ODDIN or the second fine adjustment input clock signal EVENIN is located. In this way, when the reference clock signal and the fine adjustment input clock signal have multiple phase relationships, the decoding circuit 320 can ensure that the fine adjustment delay codes selected for output all generate corresponding fine adjustment delay values. Thereby, the compatibility of the fine adjustment circuit 30 is further improved.

[0085] Fig.14 is a schematic diagram of an optional decoding circuit 320. In some embodiments of the present disclosure, reference Fig.14 , the decoding circuit 320 decodes the fine adjustment control code SAR<3:0> to generate a plurality of fine adjustment delay codes Decoder<15:0>. For example, the fine adjustment delay code Decoder<15:0> includes a first fine adjustment delay code Decoder0<15:0>, a second fine adjustment delay code Decoder1<15:0>, a third fine adjustment delay code Decoder2<15:0> and a fourth fine adjustment delay code Decoder3<15:0>.

[0086] SAR<3:0> Decoder2<15:0> SAR<3:0> Decoder3<15:0> 0000 (reset value) 0000000000000000 0000 (reset value) 0000000000000000 0001 1111111111111110 0001 1000000000000000 0010 1111111111111100 0010 1100000000000000 0011 1111111111111000 0011 1110000000000000 0100 1111111111110000 0100 1111000000000000 0101 1111111111100000 0101 1111100000000000 0110 1111111111000000 0110 1111110000000000 0111 1111111110000000 0111 1111111000000000 1000 1111111100000000 1000 1111111100000000 1001 1111111000000000 1001 1111111110000000 1010 1111110000000000 1010 1111111111000000 1011 1111100000000000 1011 1111111111100000 1100 1111000000000000 1100 1111111111110000 1101 1110000000000000 1101 1111111111111000 1110 1100000000000000 1110 1111111111111100 1111 1000000000000000 1111 1111111111111110 SAR<3:0> Decoder1<15:0> SAR<3:0> Decoder0<15:0> 0000 (reset value) 1111111111111111 0000 (reset value) 1111111111111111 0001 0111111111111111 0001 0000000000000001 0010 0011111111111111 0010 0000000000000011 0011 0001111111111111 0011 0000000000000111 0100 0000111111111111 0100 0000000000001111 0101 0000011111111111 0101 0000000000011111 0110 0000001111111111 0110 0000000000111111 0111 0000000111111111 0111 0000000001111111 1000 0000000011111111 1000 0000000011111111 1001 0000000001111111 1001 0000000111111111 1010 0000000000111111 1010 0000001111111111 1011 0000000000011111 1011 0000011111111111 1100 0000000000001111 1100 0000111111111111 1101 0000000000000111 1101 0001111111111111 1110 0000000000000011 1110 0011111111111111 1111 0000000000000001 1111 0111111111111111

[0087] Table 1

[0088] It should be noted that Table 1 is a truth table of the fine adjustment delay code Decoder<15:0> and the fine adjustment control code SAR<3:0>.

[0089] In the embodiment of the present disclosure, combined with Table 1 and Fig.14 The decoding circuit 320 can decode the fine adjustment control code SAR<3:0> into the corresponding fine adjustment delay code Decoder<15:0> according to the different order of the phases of the first fine adjustment input clock signal and the second fine adjustment input clock signal, and whether the clock signal to be fine adjusted needs to cross the boundary where the first fine adjustment input clock signal and the second fine adjustment input clock signal are located, and generate the corresponding fine adjustment delay value according to the truth table in Table 1. For example, when the phase of the first fine adjustment input clock signal is ahead of the phase of the second fine adjustment input clock signal EVENIN, and the clock signal to be fine adjusted needs to cross the boundary where the first fine adjustment input clock signal is located, the first selector Mux1 selects to output the fine adjustment delay code Decoder2<15:0> decoded by the third decoder Decoder2 based on the second feedback signal SeqOutIni, and the third selector Mux3 selects to output the fine adjustment delay code Decoder2<15:0> decoded by the third decoder Decoder2 based on the third feedback signal EdgeOut. Therefore, in the case where the reference clock signal and the fine-tuning input clock signal have various phase relationships, the decoding circuit 320 can ensure that the fine-tuning delay codes selected for output all generate corresponding fine-tuning delay values.

[0090] Fig.15 is another optional structural diagram of the decoding circuit 320. In some embodiments of the present disclosure, reference Fig.15, the fine adjustment delay code Decoder<15:0> includes a first fine adjustment delay code Decoder0<15:0>, a second fine adjustment delay code Decoder1<15:0>, a third fine adjustment delay code Decoder0N<15:0> and a fourth fine adjustment delay code Decoder1N<15:0>. The decoding circuit 320 includes a first decoder Decoder0, a first inverter 321, a second decoder Decoder1 and a second inverter 322. The first decoder Decoder0 is connected to the fine adjustment control circuit and is configured to decode the fine adjustment control code SAR<3:0> into the first fine adjustment delay code Decoder0<15:0>. The first inverter 321 is connected to the first decoder Decoder0, and is configured to receive the first fine-tuning delay code Decoder0<15:0>, and convert the first fine-tuning delay code Decoder0<15:0> into the third fine-tuning delay code Decoder0N<15:0>. The first fine-tuning delay code Decoder0<15:0> and the third fine-tuning delay code Decoder0N<15:0> are used to control the target transition edge of the clock signal to be fine-tuned to be close to the target transition edge of the first fine-tuning input clock signal or the second fine-tuning input clock signal. The value of each bit of the third fine-tuning delay code Decoder0N<15:0> is opposite to the value of the first fine-tuning delay code Decoder0<15:0>. The second decoder Decoder1 is connected to the fine-tuning control circuit, and is configured to decode the fine-tuning control code into the second fine-tuning delay code. The second inverter 322 is connected to the second decoder Decoder1 and is configured to receive the second fine adjustment delay code Decoder1<15:0> and convert the second fine adjustment delay code Decoder1<15:0> into the fourth fine adjustment delay code Decoder1N<15:0>. The second fine adjustment delay code Decoder1<15:0> and the fourth fine adjustment delay code Decoder1N<15:0> are used to control the target transition edge of the clock signal to be fine-tuned to be close to the target transition edge of the first fine adjustment input clock signal or the second fine adjustment input clock signal. The value of each bit of the fourth fine adjustment delay code Decoder1N<15:0> is opposite to the value of the second fine adjustment delay code Decoder1<15:0>.

[0091] SAR<3:0> Decoder1<15:0> SAR<3:0> Decoder0<15:0> 0000 (reset value) 1111111111111111 0000 (reset value) 1111111111111111 0001 0111111111111111 0001 0000000000000001 0010 0011111111111111 0010 0000000000000011 0011 0001111111111111 0011 0000000000000111 0100 0000111111111111 0100 0000000000001111 0101 0000011111111111 0101 0000000000011111 0110 0000001111111111 0110 0000000000111111 0111 0000000111111111 0111 0000000001111111 1000 0000000011111111 1000 0000000011111111 1001 0000000001111111 1001 0000000111111111 1010 0000000000111111 1010 0000001111111111 1011 0000000000011111 1011 0000011111111111 1100 0000000000001111 1100 0000111111111111 1101 0000000000000111 1101 0001111111111111 1110 0000000000000011 1110 0011111111111111 1111 0000000000000001 1111 0111111111111111

[0092] Table 2

[0093] It should be noted that Table 2 shows Fig.15The truth table corresponding to the first decoder Decoder0 and the second decoder Decoder1 in Table 1. The first fine-tuning delay code Decoder0<15:0> and the third fine-tuning delay code Decoder2<15:0> in Table 1 are inverted, and the second fine-tuning delay code Decoder1<15:0> and the fourth fine-tuning delay code Decoder4<15:0> are inverted. Therefore, the first fine-tuning delay code Decoder0<15:0> and the second fine-tuning delay code Decoder1<15:0> in Table 2 can be inverted to obtain all the fine-tuning delay codes in Table 1.

[0094] EdgeOut SeqOutIni Decoder<15:0> 0 0 Decoder0<15:0> 0 1 Decoder0N<15:0> 1 0 Decoder1<15:0> 1 1 Decoder1N<15:0>

[0095] Table 3

[0096] It should be noted that Table 3 shows the fine-tuning delay code Decoder<15:0> decoded and output by the decoding circuit when the second feedback signal SeqOutIni and the third feedback signal EdgeOut are in different level states.

[0097] In the embodiment of the present disclosure, combined with Table 3 and Fig.15 , the decoding circuit 320 can decode the fine adjustment control code SAR<3:0> into the corresponding fine adjustment delay code Decoder<15:0> and generate the corresponding fine adjustment delay value according to the different level states of the second feedback signal SeqOutIni and the third feedback signal EdgeOut in Table 3. For example, when the second feedback signal SeqOutIni is 0 (low level) and the third feedback signal EdgeOut is 0 (low level), the phase of the first fine adjustment input clock signal lags behind the phase of the second fine adjustment input clock signal, and the clock signal to be fine-tuned needs to cross the boundary where the second fine adjustment input clock signal is located, the first decoder Decoder0 decodes the fine adjustment control code SAR<3:0> into the corresponding first fine adjustment delay code Decoder0<15:0>. Then, the first selector Mux1 selects to output the first fine adjustment delay code Decoder0<15:0> decoded by the first decoder Decoder0 based on the second feedback signal SeqOutIni, and the third selector Mux3 selects to output the first fine adjustment delay code Decoder0<15:0> based on the third feedback signal EdgeOut. Thus, in the case where the reference clock signal and the fine adjustment input clock signal have a variety of phase relationships, the decoding circuit 320 can ensure that the selected output fine adjustment delay codes all generate corresponding fine adjustment delay values.

[0098] It can be understood that the present disclosure can decode the fine-tuning control code by a decoder and an inverter. In this way, while ensuring that the decoding circuit can ensure that the selected output fine-tuning delay code generates the corresponding fine-tuning delay value, the number of decoders is reduced, thereby further simplifying the circuit structure of the decoding circuit and reducing the area of ​​the delay phase-locked loop circuit.

[0099] In some embodiments of the present disclosure, reference Fig.15 The decoding circuit 320 includes a first selector Mux1, a second selector Mux2, and a third selector Mux3. The first selector Mux1 is connected to the first decoder Decoder0 and the first inverter 321, and is configured to receive the second feedback signal SeqOutIni, the first fine-tuning delay code Decoder0<15:0>, and the third fine-tuning delay code Decoder0N<15:0>; and in response to the second feedback signal SeqOutIni, selects an output from the first fine-tuning delay code Decoder0<15:0> and the third fine-tuning delay code Decoder0N<15:0>. The second selector Mux2 is connected to the second decoder Decoder1 and the second inverter 322, and is configured to receive the second feedback signal SeqOutIni, the second fine-tuning delay code Decoder1<15:0> and the fourth fine-tuning delay code Decoder1N<15:0>; and in response to the second feedback signal SeqOutIni, selects one output from the second fine-tuning delay code Decoder1<15:0> and the fourth fine-tuning delay code Decoder1N<15:0>. The third selector Mux3 is connected to the first selector Mux1 and the second selector Mux2, and is configured to select a corresponding one of the two fine-tuning delay codes output by the first selector Mux1 and the second selector Mux2 for output in response to the third feedback signal EdgeOut.

[0100] In the embodiment of the present disclosure, combined with Table 3 and Fig.15, the first selector Mux1 and the second selector Mux2 can output the corresponding fine adjustment delay code Decoder<15:0> according to the level state of the second feedback signal SeqOutIni. For example, when the second feedback signal SeqOutIni is 0 (low level), the phase of the first fine adjustment input clock signal lags behind the phase of the second fine adjustment input clock signal EVENIN, and the first selector Mux1 selects to output the first fine adjustment delay code Decoder0<15:0> and the third fine adjustment delay code Decoder0N<15:0> based on the low level second feedback signal SeqOutIni; the second selector Mux2 selects to output the second fine adjustment delay code Decoder1<15:0> and the fourth fine adjustment delay code Decoder1N<15:0> based on the low level second feedback signal SeqOutIni. When the third feedback signal EdgeOut is 0 (low level), the third selector Mux3 selects and outputs the first fine delay code Decoder0<15:0> and the second fine delay code Decoder1<15:0> based on the low level third feedback signal EdgeOut.

[0101] In some embodiments of the present disclosure, reference Fig.13 , the fine adjustment circuit 30 also includes a first selection circuit 330 and a second selection circuit 340. The first selection circuit 330 is connected to the decoding circuit 320 and is configured to receive the fine adjustment delay code and the default delay code; wherein, when the target transition edge of the first fine adjustment input clock signal ODDIN is used as the boundary value for adjustment, the fine adjustment delay code is selected to be output from the fine adjustment delay code and the default delay code; when the target transition edge of the second fine adjustment input clock signal EVENIN is used as the boundary value for adjustment, the default delay code is selected to be output from the fine adjustment delay code and the default delay code. The second selection circuit 340 is connected to the decoding circuit 320 and is configured to receive the fine adjustment delay code and the default delay code; wherein, when the target transition edge of the second fine adjustment input clock signal EVENIN is used as the boundary value for adjustment, the fine adjustment delay code is selected to be output from the fine adjustment delay code and the default delay code; when the target transition edge of the first fine adjustment input clock signal ODDIN is used as the boundary value for adjustment, the default delay code is selected to be output from the fine adjustment delay code and the default delay code.

[0102] That is, the fine-tuning delay line 310 receives the first fine-tuning input clock signal ODDIN and the second fine-tuning input clock signal EVENIN, and when adjusting with the target transition edge of the first fine-tuning input clock signal ODDIN as the boundary value, through the selection of the first selection circuit 330 and the second selection circuit 340, the fine-tuning delay line 310 applies the fine-tuning delay value corresponding to the fine-tuning delay code to the first fine-tuning input clock signal ODDIN, and applies the fine-tuning delay value corresponding to the default delay code to the second fine-tuning input clock signal EVENIN, to generate the clock signal to be fine-tuned; when adjusting with the target transition edge of the second fine-tuning input clock signal EVENIN as the boundary value, the adjustment unit of the fine-tuning delay line 310 applies the fine-tuning delay value corresponding to the fine-tuning delay code to the second fine-tuning input clock signal EVENIN, and applies the fine-tuning delay value corresponding to the default delay code to the first fine-tuning input clock signal ODDIN, to generate the clock signal to be fine-tuned.

[0103] In the embodiments of the present disclosure, reference Fig.13 , the fine-tuning circuit 30 also includes a first selection circuit 330 and a second selection circuit 340. The first selection circuit 330 is connected to the decoding circuit 320, and is configured to receive the fine-tuning delay code Decoder<15:0> and the default delay code. Moreover, when adjusting with the target transition edge of the first fine-tuning input clock signal as the boundary value, the first selection circuit 330 selects the fine-tuning delay code Decoder<15:0> and the default delay code to output; when adjusting with the target transition edge of the second fine-tuning input clock signal as the boundary value, the default delay code is selected to output from the fine-tuning delay code Decoder<15:0> and the default delay code. For example, Fig. 9B As shown, during the fine tuning locking process, the first selection circuit 330 needs to output the fine tuning delay code Decoder<15:0>, and the applied fine tuning delay value DL_EVEN_SELT<15:0> will be gradually adjusted from 1111_1111_1111_1111, from 1 to 0. Thus, the rising edge of the clock signal LCLAB to be fine tuned can be gradually adjusted to be close to the second fine tuning input clock signal EVENIN.

[0104] Accordingly, continue to refer to Fig.13The second selection circuit 340 is connected to the decoding circuit 320 and is configured to receive the fine-tuning delay code Decoder<15:0> and the default delay code. When adjusting with the target transition edge of the second fine-tuning input clock signal as the boundary value, the second selection circuit 340 selects the fine-tuning delay code Decoder<15:0> and the default delay code to output; when adjusting with the target transition edge of the first fine-tuning input clock signal as the boundary value, the default delay code is selected to output from the fine-tuning delay code Decoder<15:0> and the default delay code. For example, Figure 4C As shown, in the fine tuning locking process, the first selection circuit 330 needs to output the fine tuning delay code Decoder<15:0>, and the applied fine tuning delay value DL_ODD_SELT<15:0> will be gradually adjusted from 111_1111_1111_1111, from 1 to 0. Thus, the rising edge of the fine tuning clock signal LCLAB can be gradually adjusted to be close to the first fine tuning input clock signal ODDIN.

[0105] In some embodiments of the present disclosure, reference Fig.13 , the default delay code includes a first default delay code and a second default delay code. The first selection circuit 330 is further configured to receive the first default delay code and the fine-tuning delay code; and, when the coarse-tuning circuit is in a locked state and the phase of the first fine-tuning input clock signal leads the phase of the second fine-tuning input clock signal, the fine-tuning delay code is selected to be output from the first default delay code and the fine-tuning delay code. The second selection circuit 340 is further configured to receive the second default delay code and the fine-tuning delay code; and, when the coarse-tuning circuit is in a locked state and the phase of the second fine-tuning input clock signal leads the phase of the first fine-tuning input clock signal, the fine-tuning delay code is selected to be output from the second default delay code and the fine-tuning delay code.

[0106] In the embodiments of the present disclosure, reference Fig.13 , the delay value corresponding to the first default delay code may be the minimum value of the fine-tuning delay value; the delay value corresponding to the second default delay code may be the maximum value of the fine-tuning delay value. For example, the first default delay code may be 1111_1111_1111_1111, and the corresponding fine-tuning delay value DL_ODD_SELT<15:0> may be 1111_1111_1111_1111. The second default delay code may be 0000_0000_0000_0000, and the corresponding fine-tuning delay value DL_EVEN_SELT<15:0> may be 0000_0000_0000_0000. Thus, the target transition edge of the clock signal to be fine-tuned at the initial time can be set at the MT position in the figure, that is, the phase of the clock signal to be fine-tuned at the initial time can be set to the middle phase of the first fine-tuning input clock signal and the second fine-tuning input clock signal.

[0107] In the present disclosure, continue to refer to Fig.13 , the coarse adjustment lock signal DL_CDL_LOCK is used to characterize the lock state of the coarse adjustment circuit. For example, when the coarse adjustment circuit is in the lock state, the coarse adjustment lock signal DL_CDL_LOCK is at a low level. The second feedback signal SeqOutIni is used to characterize the order of the phases of the first fine adjustment input clock signal and the second fine adjustment input clock signal. The second feedback signal SeqOutIniN is an inverted signal of the second feedback signal SeqOutIni. For example, the phase of the second fine adjustment input clock signal EVENIN is ahead of the phase of the first fine adjustment input clock signal ODDIN, the second feedback signal SeqOutIni is at a high level, and the second feedback signal SeqOutIniN is at a low level.

[0108] In the present disclosure, continue to refer to Fig.13 , when the coarse adjustment circuit is in a locked state and the phase of the first fine adjustment input clock signal ODDIN is ahead of the phase of the second fine adjustment input clock signal EVENIN, the fine adjustment delay code is used to adjust the fine adjustment delay value DL_ODD_SELT<15:0>, and the fine adjustment delay value DL_EVEN_SELT<15:0> remains unchanged. In this way, the first selection circuit 330 needs to select the fine adjustment delay code output from the first default delay code and the fine adjustment delay code, thereby adjusting the fine adjustment delay value DL_ODD_SELT<15:0>. When the coarse adjustment circuit is in a locked state and the phase of the second fine adjustment input clock signal EVENIN is ahead of the phase of the first fine adjustment input clock signal ODDIN, the fine adjustment delay code is used to adjust the fine adjustment delay value DL_EVEN_SELT<15:0>, and the fine adjustment delay value DL_ODD_SELT<15:0> remains unchanged. In this way, the second selection circuit 340 needs to select the fine-adjustment delay code output from the second default delay code and the fine-adjustment delay code, thereby adjusting the fine-adjustment delay value DL_EVEN_SELT<15:0>.

[0109] Fig.16 It is a circuit structure diagram of an optional selection circuit provided in an embodiment of the present disclosure.

[0110] In some embodiments of the present disclosure, reference Fig.16, the first selection circuit 330 includes a first AND gate 331 and a fourth selector Mux4. The second selection circuit 340 includes a second AND gate 341 and a fifth selector Mux5. Among them, the first AND gate 331 is configured to receive the coarse adjustment lock signal DL_CDL_LOCK and the second feedback signal SeqOutIniN, and in response to the second feedback signal SeqOutIniN and the coarse adjustment lock signal DL_CDL_LOCK, output the corresponding first selection signal to the fourth selector Mux4. The coarse adjustment lock signal DL_CDL_LOCK is used to characterize the locking state of the coarse adjustment circuit. The fourth selector Mux4, connected to the first AND gate 331 and the decoding circuit, is configured to receive the first selection signal, the fine adjustment delay code Decoder<15:0> and the first default delay code; and in response to the first selection signal, select a corresponding output from the fine adjustment delay code Decoder<15:0> and the first default delay code. The second AND gate 341 is configured to receive the coarse adjustment lock signal DL_CDL_LOCK and the second feedback signal SeqOutIni, and in response to the coarse adjustment lock signal DL_CDL_LOCK and the second feedback signal, output a corresponding second selection signal to the fifth selector Mux5. The fifth selector Mux5 is connected to the second AND gate 341 and the decoding circuit, and is configured to receive the second selection signal, the fine adjustment delay code Decoder<15:0> and the second default delay code; and in response to the second selection signal, select a corresponding output from the fine adjustment delay code Decoder<15:0> and the second default delay code.

[0111] In the embodiments of the present disclosure, reference Fig.16, when the coarse adjustment circuit is in the locked state, the coarse adjustment lock signal DL_CDL_LOCK is at a low level. If the phase of the second fine adjustment input clock signal EVENIN is ahead of the phase of the first fine adjustment input clock signal ODDIN, the second feedback signal SeqOutIni is at a high level, and the second feedback signal SeqOutIniN is at a low level. At this time, the first AND gate 331 is in a closed state, the second AND gate 332 is in an open state, the first selection signal is at a low level, and the second selection signal is at a high level. Then, the fourth selector Mux4 selects the first default delay code output from the fine adjustment delay code Decoder<15:0> and the first default delay code based on the first selection signal of the first AND gate 331. The fifth selector Mux5 selects the fine adjustment delay code Decoder<15:0> output from the fine adjustment delay code Decoder<15:0> and the second default delay code based on the second selection signal of the second AND gate 332. On the contrary, the phase of the first fine adjustment input clock signal ODDIN is ahead of the phase of the second fine adjustment input clock signal EVENIN, the first AND gate 331 is in the open state, the second AND gate 332 is in the closed state, the first selection signal is at a high level, and the second selection signal is at a low level. Then, the fourth selector Mux4 selects the fine adjustment delay code Decoder<15:0> to be output from the fine adjustment delay code Decoder<15:0> and the first default delay code based on the first selection signal of the first AND gate 331. The fifth selector Mux5 selects the second default delay code to be output from the fine adjustment delay code Decoder<15:0> and the second default delay code based on the second selection signal of the second AND gate 332.

[0112] In some embodiments of the present disclosure, reference Fig.13 The fine adjustment circuit 30 further includes a fine adjustment shift register 350. The fine adjustment shift register 350 is configured to receive and store the fine adjustment delay code when the delay phase-locked loop circuit performs fine adjustment locking; and, when the delay phase-locked loop circuit completes fine adjustment locking, adjust the phase of the clock signal to be fine-tuned based on the stored fine adjustment delay code.

[0113] In the embodiments of the present disclosure, reference Fig.13 After the fine tuning lock is completed, the delay phase-locked loop circuit can adjust the phase of the clock signal to be fine-tuned using the fine tuning shift register 350 based on the fine tuning delay code stored when the fine tuning lock is completed. In this way, the competition problem caused by the transmission of the fine tuning control word can be avoided, thereby avoiding the jitter of the clock signal caused by the competition.

[0114] Fig.17 is an optional flow chart of the delay phase locking method provided by the embodiment of the present disclosure, which is combined with Figure 1 The steps shown are explained.

[0115] S101, receiving a reference clock signal and a clock signal to be fine-tuned, and comparing the phases of the reference clock signal and the clock signal to be fine-tuned to generate a first feedback signal; a jump of the first feedback signal indicates that the phase relationship between the reference clock signal and the clock signal to be fine-tuned has changed.

[0116] Fig.18 is a schematic diagram of the circuit structure of an optional delay phase-locked circuit. It should be noted that the embodiment of the present disclosure can be Fig.18 The delay phase-locked circuit shown in the figure is realized Fig.17 The delay locking method shown. Fig.18 In the embodiment, the first duty cycle correction circuit DCC0 and the second duty cycle correction circuit DCC1 are used to adjust the duty cycle of the clock; the DCD (Duty Cycle Detection) is used to monitor the duty cycle information of the input signal (such as the clock signal), thereby controlling the duty cycle correction circuit to adjust the duty cycle of the clock signal through the control circuit DCC_Ctrl. The data strobe signal DQS (Data Strobe Signal) receives the clock signal to be fine-tuned after the fine-tuning lock is completed, and outputs it in the form of a DQS signal for data alignment; the replica delay circuit Replica is used to simulate the delay of the DQS signal on the path outside the delay phase-locked circuit, and output the corresponding clock signal to compare the phase with the reference clock signal in the comparator 10.

[0117] In the embodiments of the present disclosure, reference Fig.18 The comparator 10 compares the received reference clock signal and the clock signal to be fine-tuned, and compares the phases of the reference clock signal and the clock signal to be fine-tuned to generate a first feedback signal. Thus, it is possible to confirm whether the phase relationship between the reference clock signal and the clock signal to be fine-tuned has changed based on the jump of the first feedback signal.

[0118] S102 , generating a fine-tuning control code based on a binary search algorithm; and receiving a first feedback signal, and adjusting the fine-tuning control code based on the binary search algorithm in response to the first feedback signal.

[0119] S103, receiving the fine-tuning control code and the fine-tuning input clock signal, applying the fine-tuning delay value to the fine-tuning input clock signal, and generating the clock signal to be fine-tuned; and adjusting the fine-tuning delay value in response to the numerical change of each bit encoded in the fine-tuning control code, until the phase difference between the reference clock signal and the clock signal to be fine-tuned is less than the unit delay of the fine-tuning circuit.

[0120] In the embodiments of the present disclosure, reference Fig.18, the fine-tuning control circuit 20 generates a fine-tuning control code based on a binary search algorithm. The fine-tuning circuit may include a fine-tuning delay line 310. The fine-tuning delay line 310 receives a fine-tuning input clock signal, and applies a fine-tuning delay value corresponding to the fine-tuning delay code or the default delay code to the fine-tuning input clock signal based on a fine-tuning delay code generated by a default delay code or a fine-tuning control code, and generates a clock signal to be fine-tuned. The fine-tuning control circuit 20 receives a first feedback signal, and adjusts the fine-tuning control code based on a binary search algorithm in response to the first feedback signal. In addition, the fine-tuning circuit 30 adjusts the fine-tuning delay value in response to the numerical change of each bit of the fine-tuning control code, until the phase difference between the reference clock signal and the clock signal to be fine-tuned is less than the unit delay amount of the fine-tuning circuit 30. In this way, the fine-tuning control circuit 20 of the present disclosure can generate a fine-tuning control code using a binary search algorithm. Thus, the fine-tuning interval can be quickly narrowed using the binary search method, and the number of comparisons between the clock signal to be fine-tuned and the reference clock signal is small, further accelerating the fine-tuning locking process.

[0121] In some embodiments of the present disclosure, S201 to S202 can be used to implement Fig.17 S103 shown will be described in conjunction with each step.

[0122] S201, coarsely adjust the clock signal to be coarsely adjusted; and after the coarse adjustment is completed, the clock signal is in a locked state and a fine adjustment input clock signal is output; the clock signal to be coarsely adjusted is generated based on the reference clock signal.

[0123] In the embodiments of the present disclosure, reference Fig.18 The coarse adjustment circuit may include a time-to-digital converter 410 and a coarse adjustment delay line (CDL) 420. The time-to-digital converter 410 generates a coarse adjustment control code, and then the coarse adjustment delay line 420 generates a corresponding fine adjustment input clock signal based on the coarse adjustment control code and the reference clock signal RefClk.

[0124] S202. When the coarse adjustment circuit is in a locked state, the fine adjustment control code is adjusted to a reset value. When the coarse adjustment circuit is in a locked state, the fine adjustment delay value is adjusted from one boundary value of the maximum fine adjustment interval to another boundary value in response to the fine adjustment control code of the reset value. When the fine adjustment control code is adjusted to the reset value, if the first feedback signal jumps, the fine adjustment input clock signal is advanced by a coarse adjustment interval.

[0125] In the embodiments of the present disclosure, reference Fig.18 When the coarse adjustment circuit is in a locked state, the fine adjustment control circuit 20 adjusts the fine adjustment control code to a reset value. When the coarse adjustment circuit is in a locked state, the fine adjustment circuit adjusts the fine adjustment delay value from one boundary value of the maximum fine adjustment interval to another boundary value in response to the fine adjustment control code of the reset value. For example, Figure 4AWhen the medium fine adjustment delay value DL_ODD_SELT<15:0>=1111_1111_1111_1111, the phase of the clock signal to be finely adjusted LCLAB lags behind the reference clock signal RefClk; Figure 4A The fine-tuning delay value in is adjusted to Figure 4B When DL_ODD_SELT<15:0>=0000_0000_0000_0000, the phase of the clock signal to be fine-tuned LCLAB is ahead of the reference clock signal RefClk. If the first feedback signal jumps, it means that when the clock signal to be fine-tuned is at two boundary values, the phase relationship between the clock signal to be fine-tuned and the reference clock signal changes, that is, the clock signal to be fine-tuned is in the maximum fine-tuning interval of the fine-tuning delay value. Therefore, when the clock signal to be fine-tuned is at two boundary values, whether the first feedback signal jumps can be used to confirm whether the reference clock signal is in the maximum fine-tuning interval of the fine-tuning delay code.

[0126] It can be understood that in the process of fine-tuning locking, the present invention first resets the fine-tuning control code so that the clock signal to be fine-tuned can be adjusted to the boundary of its corresponding maximum fine-tuning interval, thereby confirming whether the fine-tuning input clock signal is within the adjustment range of the fine-tuning circuit based on whether the phase relationship between the clock signal to be fine-tuned and the reference clock signal changes.

[0127] In some embodiments of the present disclosure, S301 to S302 can be used to implement Fig.17 S103 shown will be described in conjunction with each step.

[0128] S301 , starting from the highest bit of the fine adjustment control code, adjusting the fine adjustment delay value to the middle value of the maximum fine adjustment interval, and determining a first adjustment sub-interval in response to a first feedback signal.

[0129] In the embodiments of the present disclosure, reference Fig.18 , the fine adjustment control circuit 20 starts adjusting from the highest bit of the fine adjustment control code, adjusts the fine adjustment delay value to the middle value of the maximum fine adjustment interval, and determines the first adjustment sub-interval in response to the first feedback signal. For example, the fine adjustment control circuit 20 adjusts the fine adjustment control code to 1000, so that the rising edge of the clock signal to be fine-tuned can be adjusted to Figure 4CWherein, if the first feedback signal jumps, it means that the phase relationship between the reference clock signal RefClk and the clock signal to be fine-tuned has changed, and the rising edges corresponding to the two boundary values ​​of the next adjustment sub-interval are LCLAB(1) and MT respectively; if the first feedback signal does not jump, it means that the phase relationship between the reference clock signal RefClk and the clock signal to be fine-tuned has not changed, and the rising edges corresponding to the two boundary values ​​of the next adjustment sub-interval are LCLAB(1) and the rising edge of the first fine-tuning input clock signal ODDIN respectively.

[0130] S302, adjust the fine-tuning control code bit by bit, adjust the fine-tuning delay value to the middle value of the current adjustment sub-interval, and determine the next adjustment sub-interval in sequence in response to the first feedback signal, until the phase difference between the reference clock signal and the clock signal to be fine-tuned is less than the unit delay of the fine-tuning circuit.

[0131] In the embodiments of the present disclosure, reference Fig.18 , the fine-tuning control circuit 20 can adjust the fine-tuning control code bit by bit, and determine the next adjustment sub-interval in sequence in response to the first feedback signal. Thus, the range of the adjustment sub-interval is continuously reduced, so that the phase difference between the reference clock signal RefClk and the clock signal to be fine-tuned is less than the unit delay of the fine-tuning circuit, and the fine-tuning lock is completed. In this way, the fine-tuning control circuit disclosed in the present invention can use the binary method to quickly reduce the fine-tuning interval, reduce the number of comparisons between the clock signal to be fine-tuned and the reference clock signal, and can further speed up the fine-tuning locking process.

[0132] Fig.19 is a schematic diagram of the structure of a memory 200 provided in an embodiment of the present disclosure, such as Fig.19 As shown, the memory 200 includes the delay phase locked loop circuit 100 .

[0133] In some embodiments of the present disclosure, Fig.19 As shown, the memory 200 is a DRAM.

[0134] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0135] The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0136] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A delay phase-locked loop circuit, characterized in that: include: Comparator, fine-tuning control circuit and fine-tuning circuit; The comparator is configured to receive a reference clock signal and a clock signal to be finely adjusted, and compare the phases of the reference clock signal and the clock signal to be finely adjusted to generate a first feedback signal; The jump of the first feedback signal indicates that the phase relationship between the reference clock signal and the clock signal to be fine-tuned has changed; The fine adjustment control circuit is connected to the comparator and is configured to generate a fine adjustment control code based on a binary search algorithm; and, receiving the first feedback signal, and adjusting the fine-tuning control code based on a binary search algorithm in response to the first feedback signal; The fine adjustment circuit is configured to receive the fine adjustment control code and the fine adjustment input clock signal, apply a fine adjustment delay value to the fine adjustment input clock signal, and generate the clock signal to be fine adjusted; In response to the change in the value of each bit encoded in the fine-tuning control code, the fine-tuning delay value is adjusted until the phase difference between the reference clock signal and the clock signal to be fine-tuned is less than the unit delay of the fine-tuning circuit.

2. The delay phase-locked loop circuit according to claim 1, characterized in that: The delay phase-locked loop circuit also includes: a coarse adjustment circuit; The coarse adjustment circuit is configured to perform coarse adjustment on the clock signal to be coarsely adjusted; and is in a locked state after the coarse adjustment is completed, outputting the fine adjustment input clock signal; the clock signal to be coarsely adjusted is generated based on the reference clock signal; The fine adjustment control circuit is further configured to adjust the fine adjustment control code to a reset value when the coarse adjustment circuit is in a locked state; The fine adjustment circuit is further configured to adjust the fine adjustment delay value from one boundary value of the maximum fine adjustment interval to another boundary value in response to the fine adjustment control code of the reset value when the coarse adjustment circuit is in a locked state; The coarse adjustment circuit is further configured to advance or delay the fine adjustment input clock signal by a coarse adjustment interval if the first feedback signal does not jump when the fine adjustment control code is adjusted to a reset value.

3. The delay phase-locked loop circuit according to claim 2, characterized in that: The fine adjustment control circuit is configured to adjust the fine adjustment delay value to a middle value of the maximum fine adjustment interval starting from the highest bit of the fine adjustment control code, and determine a first adjustment sub-interval in response to the first feedback signal; as well as, The fine-tuning control code is adjusted bit by bit to adjust the fine-tuning delay value to the middle value of the current adjustment sub-interval, and in response to the first feedback signal, the next adjustment sub-interval is determined in sequence until the phase difference between the reference clock signal and the clock signal to be fine-tuned is less than the unit delay of the fine-tuning circuit.

4. The delay phase-locked loop circuit according to claim 2, characterized in that: The fine-tuning input clock signal includes: a first fine-tuning input clock signal and a second fine-tuning input clock signal; the target transition edge of the first fine-tuning input clock signal and the target transition edge of the second fine-tuning input clock signal both correspond to the boundary value of the maximum fine-tuning interval.

5. The delay phase-locked loop circuit according to claim 4, characterized in that: The fine adjustment circuit comprises: a decoding circuit; The decoding circuit is configured to receive the fine-tuning control code and generate multiple fine-tuning delay codes based on the fine-tuning control code; and, in response to a second feedback signal and a third feedback signal, select a corresponding one of the multiple fine-tuning delay codes to output; the second feedback signal represents the order of the phases of the first fine-tuning input clock signal and the second fine-tuning input clock signal; the third feedback signal represents the order of the phases of the clock signal to be fine-tuned and the fine-tuning input clock signal.

6. The delay phase-locked loop circuit according to claim 5, characterized in that: The fine-tuning delay code includes: a first fine-tuning delay code, a second fine-tuning delay code, a third fine-tuning delay code and a fourth fine-tuning delay code; The decoding circuit comprises: a first decoder, a first inverter, a second decoder and a second inverter; The first decoder is connected to the fine adjustment control circuit and is configured to decode the fine adjustment control code into the first fine adjustment delay code; The first inverter is connected to the first decoder and is configured to receive the first fine-tuning delay code and convert the first fine-tuning delay code into the third fine-tuning delay code; wherein, The first fine adjustment delay code and the third fine adjustment delay code are used to control the target transition edge of the clock signal to be fine adjusted to be close to the target transition edge of the first fine adjustment input clock signal or the second fine adjustment input clock signal; the value of each bit of the third fine adjustment delay code is opposite to the value of the first fine adjustment delay code; The second decoder is connected to the fine adjustment control circuit and is configured to decode the fine adjustment control code into the second fine adjustment delay code; The second inverter is connected to the second decoder and is configured to receive the first fine-tuning delay code and convert the second fine-tuning delay code into the fourth fine-tuning delay code; wherein, The second fine-tuning delay code and the fourth fine-tuning delay code are used to control the target transition edge of the clock signal to be fine-tuned to be close to the target transition edge of the first fine-tuning input clock signal or the second fine-tuning input clock signal; the value of each bit of the fourth fine-tuning delay code is opposite to the value of the second fine-tuning delay code.

7. The delay phase-locked loop circuit according to claim 6, characterized in that: The decoding circuit further includes: a first selector, a second selector and a third selector; The first selector is connected to the first decoder and the first inverter, and is configured to receive the second feedback signal, the first fine-adjustment delay code, and the third fine-adjustment delay code; and select an output from the first fine-adjustment delay code and the third fine-adjustment delay code in response to the second feedback signal; The second selector is connected to the second decoder and the second inverter, and is configured to receive the second feedback signal, the second fine-adjustment delay code, and the fourth fine-adjustment delay code; and select an output from the second fine-adjustment delay code and the fourth fine-adjustment delay code in response to the second feedback signal; The third selector is connected to the first selector and the second selector, and is configured to select a corresponding one of the two fine-tuning delay codes output by the first selector and the second selector to output in response to the third feedback signal.

8. The delay phase-locked loop circuit according to claim 5, characterized in that: The fine adjustment circuit further includes: a first selection circuit and a second selection circuit; The first selection circuit is connected to the decoding circuit and is configured to receive the fine adjustment delay code and the default delay code; and when adjusting with the target transition edge of the first fine adjustment input clock signal as the boundary value, the fine adjustment delay code is selected to be output between the fine adjustment delay code and the default delay code; when adjusting with the target transition edge of the second fine adjustment input clock signal as the boundary value, the default delay code is selected to be output between the fine adjustment delay code and the default delay code; The second selection circuit is connected to the decoding circuit and is configured to receive the fine-tuning delay code and the default delay code; wherein, when adjusting with the target transition edge of the second fine-tuning input clock signal as the boundary value, the fine-tuning delay code output is selected between the fine-tuning delay code and the default delay code; and when adjusting with the target transition edge of the first fine-tuning input clock signal as the boundary value, the default delay code output is selected between the fine-tuning delay code and the default delay code.

9. The delay phase-locked loop circuit according to claim 8, characterized in that: The default delay code includes: a first default delay code and a second default delay code; The first selection circuit is further configured to receive the first default delay code and the fine adjustment delay code; and, when the coarse adjustment circuit is in a locked state and the phase of the first fine adjustment input clock signal is ahead of the phase of the second fine adjustment input clock signal, select the fine adjustment delay code to output from the first default delay code and the fine adjustment delay code; The second selection circuit is also configured to receive the second default delay code and the fine-tuning delay code; and, when the coarse-tuning circuit is in a locked state and the phase of the second fine-tuning input clock signal is ahead of the phase of the first fine-tuning input clock signal, the fine-tuning delay code output is selected from the second default delay code and the fine-tuning delay code.

10. The delay phase-locked loop circuit according to claim 9, characterized in that: The first selection circuit includes: a first AND gate and a fourth selector; the second selection circuit includes: a second AND gate and a fifth selector; wherein, The first AND gate is configured to receive a coarse adjustment locking signal and the second feedback signal, and output a corresponding first selection signal to the fourth selector in response to the second feedback signal and the coarse adjustment locking signal; the coarse adjustment locking signal is used to indicate a locking state of the coarse adjustment circuit; The fourth selector is connected to the first AND gate and the decoding circuit, and is configured to receive the first selection signal, the fine adjustment delay code and the first default delay code; and in response to the first selection signal, select a corresponding output from the fine adjustment delay code and the first default delay code; The second AND gate is configured to receive the coarse adjustment locking signal and the second feedback signal, and output a corresponding second selection signal to the fifth selector in response to the coarse adjustment locking signal and the second feedback signal; The fifth selector is connected to the second AND gate and the decoding circuit, and is configured to receive the second selection signal, the fine-tuning delay code and the second default delay code; and in response to the second selection signal, select a corresponding output from the fine-tuning delay code and the second default delay code.

11. The delay phase-locked loop circuit according to claim 5, characterized in that: The fine adjustment circuit also includes: a fine adjustment shift register; The fine adjustment shift register is configured to receive and store the fine adjustment delay code when the delay phase locked loop circuit performs fine adjustment locking; and When the delay phase-locked loop circuit completes fine-tuning locking, the phase of the clock signal to be fine-tuned is adjusted based on the stored fine-tuning delay code.

12. The delay phase-locked loop circuit according to claim 5, characterized in that: The fine adjustment circuit also includes: a sequence detection circuit, a pulse update circuit, a sequence detection register and an edge detection circuit; wherein, The sequence detection circuit is connected to the coarse adjustment circuit and is configured to generate a corresponding check signal based on the sequence of the phases of the first fine adjustment input clock signal and the second fine adjustment input clock signal; The pulse update circuit is configured to generate a corresponding pulse signal when the coarse adjustment circuit is in the locked state; The sequence detection register is connected to the sequence detection circuit and the pulse update circuit, and is configured to receive the verification signal and the pulse signal, and generate the second feedback signal in response to the verification signal and the pulse signal; The edge detection circuit is connected to the comparator, and is configured to monitor the transition of the first feedback signal to generate the third feedback signal.

13. A time-delay phase-locking method, characterized in that: include: Receiving a reference clock signal and a clock signal to be fine-tuned, and comparing the phases of the reference clock signal and the clock signal to be fine-tuned to generate a first feedback signal; The jump of the first feedback signal indicates that the phase relationship between the reference clock signal and the clock signal to be fine-tuned has changed; Generate fine-tuning control codes based on a binary search algorithm; and, receiving the first feedback signal, and adjusting the fine-tuning control code based on a binary search algorithm in response to the first feedback signal; Receiving the fine adjustment control code and the fine adjustment input clock signal, applying a fine adjustment delay value to the fine adjustment input clock signal, and generating the clock signal to be fine adjusted; In response to the change in the value of each bit encoded in the fine-tuning control code, the fine-tuning delay value is adjusted until the phase difference between the reference clock signal and the clock signal to be fine-tuned is less than the unit delay of the fine-tuning circuit.

14. The delay phase locking method according to claim 13, characterized in that: The time-delay phase-locking method further comprises: The coarse adjustment clock signal to be adjusted is performed coarsely; and after the coarse adjustment is completed, the coarse adjustment clock signal is locked and a fine adjustment input clock signal is output; the coarse adjustment clock signal to be adjusted is generated based on the reference clock signal; When the coarse adjustment circuit is in a locked state, adjusting the fine adjustment control code to a reset value; When the coarse adjustment circuit is in a locked state, in response to the fine adjustment control code of the reset value, adjusting the fine adjustment delay value from one boundary value of the maximum fine adjustment interval to another boundary value; In the case where the fine adjustment control code is adjusted to a reset value, if the first feedback signal changes, the fine adjustment input clock signal is advanced or delayed by a coarse adjustment interval.

15. The delay phase locking method according to claim 14, characterized in that: The time-delay phase-locking method further comprises: Starting from the highest bit of the fine adjustment control code, adjusting the fine adjustment delay value to the middle value of the maximum fine adjustment interval, and determining a first adjustment sub-interval in response to the first feedback signal; and The fine-tuning control code is adjusted bit by bit, the fine-tuning delay value is adjusted to the middle value of the current adjustment sub-interval, and in response to the first feedback signal, the next adjustment sub-interval is determined in sequence until the phase difference between the reference clock signal and the clock signal to be fine-tuned is less than the unit delay of the fine-tuning circuit.

16. A memory, characterized in that: The memory comprises the delay phase-locked loop circuit according to any one of claims 1 to 12, and the memory is a dynamic random access memory DRAM.

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