High-speed RF analog-to-digital converter calibration method based on reference channel

Abstract

The present invention discloses a high-speed radio frequency analog-to-digital converter calibration method based on a reference channel, comprising: performing gain error correction on the reference channel; sampling the input signal through the output channel, sampling the inverse signal of the input signal through the reference channel, injecting a pseudo-random signal into the MDACs of the two channels to obtain a first output code and a second output code, and performing gain error correction accordingly; injecting a constant differential voltage into the input end of the reference channel to cause a lateral shift of the residual transfer curve; and simultaneously sampling the input signal using the output channel and the reference channel to obtain a third output code and a fourth output code, and performing capacitance mismatch correction accordingly. The present invention uses the reference channel to quickly correct the inter-stage gain error of the output channel, and the capacitance mismatch correction object does not include the capacitance mismatch of the reference channel, thereby reducing the area and power consumption of the correction circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a high-speed radio frequency analog-to-digital converter calibration method based on a reference channel. Background Art

[0002] High-speed, high-precision analog-to-digital converters (ADCs) are widely used in communication base stations, satellite remote sensing, and other applications, playing a vital role in aerospace, defense, and military industries. However, factors such as capacitor mismatch and interstage gain error caused by process variations during the manufacturing process can severely impact ADC performance and exacerbate nonlinearities in the ADC quantization process. Therefore, ADC calibration is necessary.

[0003] In the related art, the ADC can be calibrated by using a pseudo-random signal correction method, which is to add a PN*V dither signal, where the pseudo-random signal PN is a sequence of 1 and -1, and its mathematical expectation is 0, V dither The error value is extracted by allowing the signal to follow the sampled signal through the same quantization path as the constant value. This method has become a hot topic in academia due to its minimal modification of the original ADC and its excellent correction effect. However, the PN-based correction method contains natural digital noise, which reduces its correction speed and accuracy. This digital noise mainly comes from the limited number of bits in the averager. Specifically, in the pseudo-random signal correction algorithm, the gain error ε is estimated using the following formula:

[0004]

[0005] In the above formula, D is the output of the averager, G is the ideal gain of the MDAC (multiplying digital-to-analog converter), ε is the gain error, and V res is the residual signal, N is the number of sampling points, LSB BE is the minimum quantization step size of the subsequent ADC. PN(i) represents the i-th bit of the pseudo-random signal PN. Since the mathematical expectation of PN is 0, the first term on the right side of the above equation should be 0. However, since N cannot approach ∞ in practice, the first term is not 0, resulting in the estimated value ε calculated by the circuit. e ≠ε, so the correction effect is not ideal.

[0006] In related technologies, ADC calibration can also refer to ADC method, such as Figure 1 As shown in FIG, this method calibrates the main ADC by adding a low-speed, high-precision reference ADC. This method has a fast correction effect, but it has high requirements on the accuracy of the ADC. If there is a capacitance mismatch in the ADC itself, it will affect the capacitance mismatch calibration, and the ADC itself also has non-ideal factors. Summary of the Invention

[0007] In order to solve the above problems existing in the prior art, the present invention provides a high-speed radio frequency analog-to-digital converter calibration method based on a reference channel.

[0008] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0009] A high-speed radio frequency analog-to-digital converter calibration method based on a reference channel, wherein the output channel of the analog-to-digital converter includes a pre-stage ADC, an MDAC, and a post-stage ADC cascaded in sequence; the method comprises:

[0010] Providing a reference channel and performing gain error correction on the reference channel; the reference channel and the output channel have the same structure and are clock synchronized;

[0011] Performing output channel gain error correction, comprising: sampling an input signal using the output channel and simultaneously sampling an inverse signal of the input signal using the reference channel, injecting the same pseudo-random signal into the input terminals of the two MDACs during the sampling process, and obtaining a first output code and a second output code at the output terminals of the two subsequent ADCs, respectively; and performing gain error correction on the output channel according to the first output code and the second output code;

[0012] Performing output channel capacitance mismatch correction includes: injecting a constant differential voltage into the input end of the reference channel to cause a horizontal shift of the margin transfer curve of the reference channel; using the output channel and the reference channel to simultaneously sample the input signal, and obtaining a third output code and a fourth output code at the output ends of the two subsequent ADCs, respectively; and performing capacitance mismatch correction on the output channel according to the third output code and the fourth output code.

[0013] Optionally, performing gain error correction on the reference channel includes:

[0014] injecting a constant voltage into an input terminal of the MDAC of the reference channel, sampling the constant voltage using the MDAC of the reference channel and a subsequent ADC, and obtaining a fifth output code at an output terminal of the subsequent ADC of the reference channel;

[0015] Performing gain error correction on the reference channel according to the fifth output code.

[0016] Optionally, performing gain error correction on the reference channel according to the fifth output code includes:

[0017] Subtract each bit of the fifth output code from the corresponding expected value, and divide the difference by the corresponding first attenuation factor to obtain the gain error coefficient of the reference channel at that bit; wherein the first attenuation factor is equal to the expected value minus 2N-1 , N is the number of quantization bits of the subsequent ADC;

[0018] Gain error correction is performed on the reference channel according to the gain error coefficient of each bit of the reference channel.

[0019] Optionally, the constant voltage is greater than 0V and less than or equal to 1*LSB volt; LSB is the minimum quantization step of the subsequent ADC.

[0020] Optionally, the amplitude of the constant differential voltage is -0.5*LSB volts; LSB is the minimum quantization step of the subsequent ADC.

[0021] Optionally, performing gain error correction on the output channel according to the first output code and the second output code includes:

[0022] Adding the first output code and the second output code to obtain an added code;

[0023] Multiplying the added code by the pseudo-random signal at the corresponding moment to obtain a multiplied code;

[0024] Accumulating the plurality of multiplied codes, and averaging the accumulated codes when the accumulated codes reach a preset number to obtain a cumulative average code;

[0025] Dividing each bit of the accumulated average code by the corresponding second attenuation factor and then subtracting 2 to obtain a gain error coefficient of the output channel at that bit; wherein the second attenuation factor is obtained by a digital code obtained by amplifying the pseudo-random signal by an ideal amplifier and then quantizing it by an ideal quantizer;

[0026] Gain error correction is performed on the output channel according to the gain error coefficient of each bit of the output channel.

[0027] Optionally, the third output code and the fourth output code are both composed of a pre-stage code and a post-stage code; the pre-stage code is output by the pre-stage ADC, each pre-stage code corresponds to an MSB region, and multiple MSB regions are sorted according to the pre-stage code; the post-stage code is a code following the pre-stage code;

[0028] The performing capacitance mismatch correction on the output channel according to the third output code and the fourth output code includes:

[0029] Obtaining third output codes corresponding to various MSB regions, and obtaining fourth output codes corresponding to various MSB regions;

[0030] Subtracting the subsequent codes of the third output code and the fourth output code corresponding to the same MSB region to obtain a plurality of error codes, each error code corresponding to an MSB region;

[0031] The error codes corresponding to the same MSB region are averaged to obtain multiple average error codes, each of which corresponds to an MSB region;

[0032] Subtracting the average error codes of adjacent MSB regions to obtain a first shift value of a subsequent MSB region relative to a previous MSB region;

[0033] Determine the second translation value of the 2nd to nth MSB regions relative to the margin transfer curve according to each of the first translation values; wherein the first MSB region has no corresponding second translation value; n=2 N1 , N1 is the number of bits of the previous ADC;

[0034] Capacitance mismatch correction is performed on the output channels according to each of the second shift values.

[0035] Optionally, after performing the output channel gain error correction and before performing the output channel capacitance mismatch correction, the method further includes:

[0036] Determine whether output channel capacitance mismatch correction has been performed;

[0037] If output channel capacitance mismatch correction has been performed, obtaining each second translation value obtained when performing output channel capacitance mismatch correction, and directly performing capacitance mismatch correction on the output channel according to each second translation value;

[0038] If the output channel capacitance mismatch correction has not been performed, the step of performing the output channel capacitance mismatch correction is continued, and the obtained second shift values ​​are stored for future use.

[0039] The present invention provides a high-speed RF analog-to-digital converter calibration method based on a reference channel. This method utilizes the reference channel to rapidly calibrate the inter-stage gain error of the output channel, significantly improving the ADC calibration speed. A constant differential voltage is then injected into the input of the reference channel to cause a horizontal shift in the reference channel's margin transfer curve. This not only provides a calibration reference for the output channel's transfer curve but also ensures that capacitance mismatch in the reference channel has no impact on the calibration effect. This eliminates the capacitance mismatch in the reference channel from the target of capacitance mismatch correction, reducing the area and power consumption of the digital correction circuit.

[0040] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is a schematic diagram of the existing reference ADC method for calibrating the ADC;

[0042] Figure 2Flowchart of a high-speed RF analog-to-digital converter calibration method based on a reference channel provided by an embodiment of the present invention;

[0043] Figure 3 yes Figure 2 Schematic diagram of gain error correction for a reference channel in the illustrated method;

[0044] Figure 4 yes Figure 2 Schematic diagram of output channel gain error correction in the method shown;

[0045] Figure 5 yes Figure 2 Schematic diagram of output channel capacitance mismatch correction in the method shown;

[0046] Figure 6 The margin transfer curve between the output channel and the reference channel under ideal conditions is shown as an example.

[0047] Figure 7 The input transfer curves of the output channel and the reference channel are shown exemplarily;

[0048] Figure 8 The input transfer curves of the output channel and the reference channel under capacitance mismatch are shown as an example. DETAILED DESCRIPTION

[0049] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0050] In order to effectively improve the correction effect of ADC, the embodiment of the present invention provides a high-speed RF analog-to-digital converter correction method based on a reference channel, which can quickly correct the inter-stage gain error and capacitor mismatch in the pipeline analog-to-digital converter, such as Figure 2 As shown, the method includes the following steps:

[0051] S10. Provide a reference channel and perform gain error correction on the reference channel. The reference channel and the output channel of the analog-to-digital converter have the same structure and are clock-synchronized.

[0052] See also Figure 3 As shown, the output channel includes a pre-stage ADC, MDAC and post-stage ADC cascaded in sequence. The reference channel and the output channel have the same structure and are clock synchronized. Figure 3 The entire circuit structure of the reference channel is not shown.

[0053] In step S10, gain error correction is performed on the reference channel, including:

[0054] (1) To the MDAC of the reference channel ( Figure 3A constant voltage is injected into the input terminal of the MDAC2 in the reference channel, and the constant voltage is sampled by the MDAC of the reference channel and the subsequent ADC, thereby obtaining a fifth output code Dout5 at the output terminal of the subsequent ADC of the reference channel.

[0055] The constant voltage is greater than 0V and less than or equal to 1*LSB volt. For example, the constant voltage may be 0.5*LSB volt. Here, LSB is the minimum quantization step size of the subsequent ADC.

[0056] In addition, while the MDAC of the reference channel and the subsequent ADC are sampling the constant voltage, the output channel can sample the input signal normally. Figure 3 As shown in the figure, the positive input terminal of the front-stage ADC of the output channel is connected to the positive voltage VIP of the input signal, and the negative input terminal is connected to the negative voltage VIN of the input signal, so that the output channel is used to sample the input signal; at the same time, the MDAC ( Figure 3 The input of MDAC1 in the DAC is injected with a pseudo-random signal PN to keep the output channel in normal quantization output. Figure 3 As shown, an adder is used to add the residual signal output by the front-stage ADC of the output channel to the pseudo-random signal PN to realize the injection of the pseudo-random signal.

[0057] (2) Perform gain error correction on the reference channel according to the fifth output code.

[0058] Specifically, performing gain error correction on the reference channel according to the fifth output code includes:

[0059] (2-a) Subtract each bit of the fifth output code from the corresponding expected value, and divide the difference by the corresponding first attenuation factor to obtain the gain error coefficient of the reference channel at that bit; where the first attenuation factor is equal to the expected value minus 2 N-1 , N is the number of quantization bits of the subsequent ADC;

[0060] (2-b) Perform gain error correction on the reference channel according to the gain error coefficient of each bit of the reference channel.

[0061] Specifically, the output code of the reference channel is subtracted by 2 through a subtractor. N-1 , and then divided by (1+ε e ), and then add 2 through the adder N-1 The gain error correction can be completed. Here, ε e This is the gain error coefficient obtained in step S10.

[0062] Furthermore, to ensure the accuracy of the error estimate, the step of performing gain error correction on the reference channel may be repeated multiple times, thereby averaging the gain error coefficients obtained over the multiple cycles as the final gain error coefficient obtained in step S10. Gain error correction is then performed on the reference channel based on the final gain error coefficient.

[0063] In actual calibration, the aforementioned gain error correction steps for the reference channel can be implemented in a GEC (Gain Error Correction) circuit. This gain error correction circuit includes built-in modules such as a subtractor, a divider, and a shift operation unit, allowing for convenient subtraction and division operations. Furthermore, the first attenuation factor and the expected value can also be pre-stored in the GEC circuit.

[0064] In step S10 , a deterministic input is injected into the reference channel, and then the actual error of the circuit is obtained by comparing the difference between the actual output and the ideal output, thereby quickly completing the gain error correction of the reference channel.

[0065] S20, performing output channel gain error correction, including: sampling an input signal using the output channel and simultaneously sampling an inverse signal of the input signal using the reference channel, injecting the same pseudo-random signal into the input ends of the MDACs of the two channels during the sampling process, thereby obtaining a first output code and a second output code at the output ends of the subsequent ADCs of the two channels, respectively; and performing gain error correction on the output channel according to the first output code and the second output code.

[0066] See also Figure 4 The positive input terminal of the front-stage ADC of the output channel is connected to the positive voltage VIP of the input signal, and the negative input terminal is connected to the negative voltage VIN of the input signal; at the same time, the positive input terminal of the front-stage ADC of the reference channel is connected to the negative voltage VIN of the input signal, and the negative input terminal is connected to the positive voltage VIPN of the input signal; the residual signals output by the front-stage ADCs of the two channels are respectively added to the same pseudo-random signal PN by using an adder, so that the same pseudo-random signal PN is injected into the input terminals of the MDACs of the two channels, thereby obtaining the first output code Dout1 and the second output code Dout2 at the output terminals of the post-stage ADCs of the two channels respectively.

[0067] Then, the output channel is subjected to gain error correction according to the first output code and the second output code, specifically comprising:

[0068] (1) Adding the first output code and the second output code to obtain an added code;

[0069] (2) multiplying the addition code by the pseudo-random signal at the corresponding moment to obtain the multiplication code;

[0070] (3) Accumulating the multiple multiplied codes, averaging them when the accumulated number reaches a preset number, and obtaining a cumulative average code; the number of accumulated multiplied codes may be predetermined and is not limited in the embodiment of the present invention;

[0071] (4) Dividing each bit of the accumulated average code by the corresponding second attenuation factor and then subtracting 2 to obtain the gain error coefficient of the output channel at that bit; wherein the second attenuation factor is obtained by amplifying the pseudo-random signal by an ideal amplifier and then quantizing it by an ideal quantizer;

[0072] (5) Perform gain error correction on the output channel according to the gain error coefficient of each bit of the output channel.

[0073] Specifically, the output code of the output channel is subtracted by 2 through the subtractor N-1 , then divide it by (1+ε) through the divider, and then add 2 through the adder N-1 Here, ε is the gain error coefficient obtained in step S20.

[0074] Furthermore, to ensure the accuracy of the error estimate, the step of performing gain error correction on the output channel can be repeated multiple times, thereby averaging the gain error coefficients obtained over the multiple cycles to form the final gain error coefficients. Then, gain error correction is performed on the output channel based on the final gain error coefficients.

[0075] It can be understood that since the quantization objects of the output channel and the reference channel are analog signals of the same magnitude and opposite directions, step S20 can quickly reduce the PN-independent quantities in the pseudo-random signal algorithm to zero, greatly accelerating the correction speed of the PN algorithm. This principle can be expressed by the following formula:

[0076]

[0077] In the above formula, PN(i) represents the i-th bit of the pseudo-random signal, D is the output of the averager used in calculating the cumulative average code in step (4), G is the ideal gain of the MDAC of the output channel, and V res is the margin signal of the output channel, which is output by the pre-ADC of the output channel. dither It is a constant voltage superimposed on the pseudo-random signals 1 and -1. The meanings of the remaining parameters are as described above.

[0078] Based on the above formula, it can be seen that although there is still an inter-stage gain error in the output channel, after adding it with the corresponding term of the reference channel, the numerator of the first term on the right side of the above formula decreases, so the first term is much smaller than the existing pseudo-random signal correction method, thereby improving the correction accuracy and speed.

[0079] In actual calibration, the above-mentioned steps for correcting the gain error of the output channel can also be implemented in a GEC (Gain Error Correction) circuit. This gain error correction circuit has built-in modules such as an adder, a multiplier, an accumulator, a divider, an averager, a subtractor, and a shift operation unit, thereby conveniently implementing the various operations required for the correction operation. The second attenuation factor can also be pre-stored in the GEC circuit.

[0080] S30, performing output channel capacitance mismatch correction, including: injecting a constant differential voltage into the input end of the reference channel to cause a horizontal shift of the margin transfer curve of the reference channel; using the output channel and the reference channel to simultaneously sample the input signal, thereby obtaining a third output code and a fourth output code at the output ends of the subsequent ADCs of the two channels, respectively; and performing capacitance mismatch correction on the output channel according to the third output code and the fourth output code.

[0081] After the gain calibration of the two channels is completed, the capacitance mismatch of the output channel is corrected. When the sampling clock becomes low, the sampling of the output channel and the reference channel ends. At the same time, see Figure 5 As shown, a constant differential voltage is additionally injected into the reference channel input terminal, and its amplitude is preferably set to -0.5*LSB volts (but not limited to this), thereby causing the margin transfer curve of the reference channel to shift horizontally. Figure 5 The voltages applied to the positive and negative input terminals of the reference channel are 0.25*LSB volts and -0.25*LSB volts respectively.

[0082] Figure 6 The margin transfer curve of the output channel and the reference channel under ideal conditions is shown as an example, and the corresponding ADC quantization curve is shown as follows: Figure 7 When there is a capacitance mismatch in the channel, for a multi-stage pipeline ADC, its quantization curve will shift up and down in each MSB (big endian) and LSB (little endian) region corresponding to the previous ADC. The direction and magnitude of the shift are determined by the capacitance mismatch encountered when the previous ADC generates the margin. The corresponding quantization curve is shown in Figure 8 Therefore, this feature can be used to correct the capacitance mismatch of the output channel.

[0083] Specifically, in practice, the third output code Dout3 and the fourth output code Dout4 obtained from the output ends of the two post-stage ADCs are both composed of a previous-stage code and a post-stage code; the previous-stage code is output by the previous-stage ADC, each previous-stage code corresponds to an MSB area, and multiple MSB areas are sorted according to the previous-stage code; the post-stage code is the code after the previous-stage code.

[0084] Therefore, capacitance mismatch correction is performed on the output channel according to the third output code and the fourth output code, specifically including:

[0085] (1) obtaining a third output code corresponding to various MSB regions, and obtaining a fourth output code corresponding to various MSB regions;

[0086] (2) Subtracting the subsequent codes of the third output code and the fourth output code corresponding to the same MSB region to obtain multiple error codes, each error code corresponding to an MSB region;

[0087] (3) averaging the error codes corresponding to the same MSB region to obtain multiple average error codes, each average error code corresponding to one MSB region; the number of average error codes can be preset;

[0088] (4) Subtracting the average error codes of adjacent MSB regions to obtain a first shift value of the subsequent MSB region relative to the preceding MSB region;

[0089] (5) Determine the second shift values ​​of the 2nd to nth MSB regions relative to the margin transfer curve based on the first shift values; wherein the first MSB region has no corresponding second shift value; n is the number of MSB regions, n=2 N1 , N1 is the number of bits of the previous ADC;

[0090] Specifically, the operation in step (5) can be expressed by the following formula:

[0091]

[0092] In the above formula, error i～i-1 Indicates the first translation value of the i-th MSB region relative to the i-1-th MSB region, E i represents the second shift value of the i-th MSB region relative to the margin transfer curve.

[0093] (6) Perform capacitance mismatch correction on the output channel according to each second shift value.

[0094] Specifically, the corresponding MSB area is determined according to the previous code in the output code of the output channel, and then the second translation value of the MSB area relative to the margin transfer curve is subtracted from the subsequent code of the output channel to complete the capacitance mismatch correction of the output channel.

[0095] from Figure 8 It can also be seen that even if there is a capacitance mismatch in the reference channel, it will not affect the correction of the output channel.

[0096] In one embodiment, after performing output channel gain error correction and before performing output channel capacitance mismatch correction, the method of the embodiment of the present invention may further include the following steps:

[0097] (a) Determine whether output channel capacitance mismatch correction has been performed;

[0098] (b) If the output channel capacitance mismatch correction has been performed, then the respective second shift values ​​obtained when the output channel capacitance mismatch correction is performed are obtained, and the capacitance mismatch correction is performed on the output channel directly according to the respective second shift values; and if the output channel capacitance mismatch correction has not been performed, then the steps of performing the output channel capacitance mismatch correction are continued, and the respective second shift values ​​obtained are stored for future use.

[0099] In practice, since capacitance mismatch is determined solely by process mismatch, after the initial capacitance mismatch correction for the output channel is completed, it is only necessary to record the second shift value of each MSB region relative to the margin transfer curve. Subsequent capacitance mismatch correction for the ADC can be performed directly based on each second shift value, thereby achieving rapid capacitance mismatch correction. Furthermore, since the capacitance mismatch of the reference channel does not need to be corrected, a significant amount of area and power consumption of the capacitance mismatch correction circuit can be saved.

[0100] In summary, the reference channel-based high-speed RF analog-to-digital converter calibration method provided by the embodiment of the present invention utilizes the reference channel to quickly calibrate the inter-stage gain error of the output channel, thereby greatly improving the calibration speed of the ADC. Subsequently, a constant differential voltage is injected into the input end of the reference channel to cause the margin transfer curve of the reference channel to shift laterally. This not only provides a correction reference for the transfer curve of the output channel, but also ensures that the capacitance mismatch of the reference channel does not have any impact on the calibration effect. Therefore, the calibration object of the correction circuit does not include the capacitance mismatch of the reference channel, thereby reducing the area and power consumption of the digital correction circuit.

[0101] It should be noted that the terms "first," "second," and the like are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure.

[0102] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0103] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings and the disclosed content. In the description of the present invention, the word "comprising" does not exclude other components or steps, "one" or "a" does not exclude multiple situations, and "multiple" means two or more, unless otherwise clearly and specifically limited. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0104] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A high-speed radio frequency analog-to-digital converter calibration method based on a reference channel, characterized in that: The output channel of the analog-to-digital converter includes a pre-stage ADC, an MDAC, and a post-stage ADC connected in cascade sequence; the method includes: Providing a reference channel and performing gain error correction on the reference channel; the reference channel and the output channel have the same structure and are clock synchronized; Performing output channel gain error correction, comprising: sampling an input signal using the output channel and simultaneously sampling an inverse signal of the input signal using the reference channel, injecting the same pseudo-random signal into the input terminals of the two MDACs during the sampling process, and obtaining a first output code and a second output code at the output terminals of the two subsequent ADCs, respectively; and performing gain error correction on the output channel according to the first output code and the second output code; Performing output channel capacitance mismatch correction includes: injecting a constant differential voltage into the input end of the reference channel to cause a horizontal shift of the margin transfer curve of the reference channel; using the output channel and the reference channel to simultaneously sample the input signal, and obtaining a third output code and a fourth output code at the output ends of the two subsequent ADCs, respectively; and performing capacitance mismatch correction on the output channel according to the third output code and the fourth output code.

2. The method according to claim 1, characterized in that The performing gain error correction on the reference channel includes: injecting a constant voltage into an input terminal of the MDAC of the reference channel, sampling the constant voltage using the MDAC of the reference channel and a subsequent ADC, and obtaining a fifth output code at an output terminal of the subsequent ADC of the reference channel; Performing gain error correction on the reference channel according to the fifth output code.

3. The method according to claim 2, characterized in that The performing gain error correction on the reference channel according to the fifth output code includes: Subtract each bit of the fifth output code from the corresponding expected value, and divide the difference by the corresponding first attenuation factor to obtain the gain error coefficient of the reference channel at that bit; wherein the first attenuation factor is equal to the expected value minus 2 N-1 , N is the number of quantization bits of the subsequent ADC; Gain error correction is performed on the reference channel according to the gain error coefficient of each bit of the reference channel.

4. The method according to claim 2, characterized in that The constant voltage is greater than 0V and less than or equal to 1*LSB volt; LSB is the minimum quantization step of the subsequent ADC.

5. The method according to claim 1, wherein The amplitude of the constant differential voltage is -0.5*LSB volts; LSB is the minimum quantization step size of the subsequent ADC.

6. The method according to claim 1, characterized in that The performing gain error correction on the output channel according to the first output code and the second output code includes: Adding the first output code and the second output code to obtain an added code; Multiplying the added code by the pseudo-random signal at the corresponding moment to obtain a multiplied code; Accumulating the plurality of multiplied codes, and averaging the accumulated codes when the accumulated codes reach a preset number to obtain a cumulative average code; Dividing each bit of the accumulated average code by the corresponding second attenuation factor and then subtracting 2 to obtain a gain error coefficient of the output channel at that bit; wherein the second attenuation factor is obtained by a digital code obtained by amplifying the pseudo-random signal by an ideal amplifier and then quantizing it by an ideal quantizer; Gain error correction is performed on the output channel according to the gain error coefficient of each bit of the output channel.

7. The method according to claim 1, characterized in that The third output code and the fourth output code are both composed of a pre-stage code and a post-stage code; the pre-stage code is output by the pre-stage ADC, each pre-stage code corresponds to an MSB region, and the multiple MSB regions are sorted according to the pre-stage code; The latter code is the code following the former code; The performing capacitance mismatch correction on the output channel according to the third output code and the fourth output code includes: Obtaining third output codes corresponding to various MSB regions, and obtaining fourth output codes corresponding to various MSB regions; Subtracting the subsequent codes of the third output code and the fourth output code corresponding to the same MSB region to obtain a plurality of error codes, each error code corresponding to an MSB region; The error codes corresponding to the same MSB region are averaged to obtain multiple average error codes, each of which corresponds to an MSB region; Subtracting the average error codes of adjacent MSB regions to obtain a first shift value of a subsequent MSB region relative to a previous MSB region; Determine the second translation value of the 2nd to nth MSB regions relative to the margin transfer curve according to each of the first translation values; wherein the first MSB region has no corresponding second translation value; n=2 N1 , N1 is the number of bits of the previous ADC; Capacitance mismatch correction is performed on the output channels according to each of the second shift values.

8. The method according to claim 7, characterized in that After performing output channel gain error correction and before performing output channel capacitance mismatch correction, the method further includes: Determine whether output channel capacitance mismatch correction has been performed; If output channel capacitance mismatch correction has been performed, obtaining each second translation value obtained when performing output channel capacitance mismatch correction, and directly performing capacitance mismatch correction on the output channel according to each second translation value; If the output channel capacitance mismatch correction has not been performed, the step of performing the output channel capacitance mismatch correction is continued, and the obtained second shift values ​​are stored for future use.

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